AT6005-2AC [ATMEL]
Coprocessor Field Programmable Gate Arrays; 协处理器，现场可编程门阵列
| 型号： | AT6005-2AC |
| 厂家： | 
ATMEL |
| 描述： | Coprocessor Field Programmable Gate Arrays |
| 文件： | 总28页 (文件大小：789K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High-performance
– System Speeds > 100 MHz
– Flip-flop Toggle Rates > 250 MHz
– 1.2 ns/1.5 ns Input Delay
– 3.0 ns/6.0 ns Output Delay
• Up to 204 User I/Os
• Thousands of Registers
• Cache Logic® Design
– Complete/Partial In-System Reconfiguration
– No Loss of Data or Machine State
– Adaptive Hardware
Coprocessor
Field
• Low Voltage and Standard Voltage Operation
– 5.0 (VCC = 4.75V to 5.25V)
– 3.3 (VCC = 3.0V to 3.6V)
Programmable
Gate Arrays
• Automatic Component Generators
– Reusable Custom Hard Macro Functions
• Very Low-power Consumption
– Standby Current of 500 µA/ 200 µA
– Typical Operating Current of 15 to 170 mA
• Programmable Clock Options
AT6000(LV)
Series
– Independently Controlled Column Clocks
– Independently Controlled Column Resets
– Clock Skew Less Than 1 ns Across Chip
• Independently Configurable I/O (PCI Compatible)
– TTL/CMOS Input Thresholds
– Open Collector/Tristate Outputs
– Programmable Slew-rate Control
– I/O Drive of 16 mA (combinable to 64 mA)
• Easy Migration to Atmel Gate Arrays for High Volume Production
Description
AT6000 Series SRAM-based Field Programmable Gate Arrays (FPGAs) are ideal for
use as reconfigurable coprocessors and implementing compute-intensive logic.
Supporting system speeds greater than 100 MHz and using a typical operating current
of 15 to 170 mA, AT6000 Series devices are ideal for high-speed, compute-intensive
designs. These FPGAs are designed to implement Cache Logic®, which provides the
user with the ability to implement adaptive hardware and perform hardware
acceleration.
The patented AT6000 Series architecture employs a symmetrical grid of small yet
powerful cells connected to a flexible busing network. Independently controlled clocks
and resets govern every column of cells. The array is surrounded by programmable
I/O.
(continued)
AT6000 Series Field Programmable Gate Arrays
Device
AT6002
6,000
1,024
1,024
96
AT6003
9,000
1,600
1,600
120
AT6005
15,000
3,136
AT6010
30,000
6,400
Usable Gates
Cells
Registers (maximum)
I/O (maximum)
Typ. Operating Current (mA)
Cell Rows x Columns
3,136
6,400
108
204
Rev. 0264F–10/99
15 - 30
32 x 32
25 - 45
40 x 40
40 - 80
56 x 56
85 - 170
80 x 80
Devices range in size from 4,000 to 30,000 usable gates,
and 1024 to 6400 registers. Pin locations are consistent
throughout the AT6000 Series for easy design migration.
High-I/O versions are available for the lower gate count
devices.
The Symmetrical Array
At the heart of the Atmel architecture is a symmetrical array
of identical cells (Figure 1). The array is continuous and
completely uninterrupted from one edge to the other,
except for bus repeaters spaced every eight cells
(Figure 2).
AT6000 Series FPGAs utilize a reliable 0.6 µm single-poly,
double-metal CMOS process and are 100% factory-tested.
In addition to logic and storage, cells can also be used as
wires to connect functions together over short distances
and are useful for routing in tight spaces.
Atmel's PC- and workstation-based Integrated Develop-
ment System is used to create AT6000 Series designs.
Multiple design entry methods are supported.
The Atmel architecture was developed to provide the high-
est levels of performance, functional density and design
flexibility in an FPGA. The cells in the Atmel array are
small, very efficient and contain the most important and
most commonly used logic and wiring functions. The cell’s
small size leads to arrays with large numbers of cells,
greatly multiplying the functionality in each cell. A simple,
high-speed busing network provides fast, efficient commu-
nication over medium and long distances.
The Busing Network
There are two kinds of buses: local and express (see
Figures 2 and 3).
Local buses are the link between the array of cells and the
busing network. There are two local buses – North-South 1
and 2 (NS1 and NS2) – for every column of cells, and two
local buses – East-West 1 and 2 (EW1 and EW2) – for
every row of cells. In a sector (an 8 x 8 array of cells
enclosed by repeaters) each local bus is connected to
every cell in its column or row, thus providing every cell in
the array with read/write access to two North-South and
two East-West buses.
Figure 1. Symmetrical Array Surrounded by I/O
AT6000(LV) Series
2
AT6000(LV) Series
Figure 2. Busing Network (one sector)
CELL
REPEATER
Figure 3. Cell-to-cell and Bus-to-bus Connections
3
Each cell, in addition, provides the ability to route a signal
on a 90° turn between the NS1 bus and EW1 bus and
between the NS2 bus and EW2 bus.
In all of these cases, each connection provides signal
regeneration and is thus unidirectional. For bidirectional
connections, the basic repeater function for the NS2 and
EW2 repeaters is augmented with a special programmable
connection allowing bidirectional communication between
local-bus segments. This option is primarily used to imple-
ment long, tristate buses.
Express buses are not connected directly to cells, and thus
provide higher speeds. They are the fastest way to cover
long, straight-line distances within the array.
Each express bus is paired with a local bus, so there are
two express buses for every column and two express
buses for every row of cells.
The Cell Structure
The Atmel cell (Figure 4) is simple and small and yet
can be programmed to perform all the logic and wiring
functions needed to implement any digital circuit. Its four
sides are functionally identical, so each cell is completely
symmetrical.
Connective units, called repeaters, spaced every eight
cells, divide each bus, both local and express, into
segments spanning eight cells. Repeaters are aligned in
rows and columns thereby partitioning the array into 8 x 8
sectors of cells. Each repeater is associated with a
local/express pair, and on each side of the repeater are
connections to a local-bus segment and an express-bus
segment. The repeater can be programmed to provide any
one of twenty-one connecting functions. These functions
are symmetric with respect to both the two repeater sides
and the two types of buses.
Read/write access to the four local buses – NS1, EW1,
NS2 and EW2 – is controlled, in part, by four bidirectional
pass gates connected directly to the buses. To read a local
bus, the pass gate for that bus is turned on and the three-
input multiplexer is set accordingly. To write to a local bus,
the pass gate for that bus and the pass gate for the associ-
ated tristate driver are both turned on. The two-input
multiplexer supplying the control signal to the drivers per-
mits either: (1) active drive, or (2) dynamic tristating
controlled by the B input. Turning between LNS1 and LEW1 or
between LNS2 and LEW2 is accomplished by turning on the
two associated pass gates. The operations of reading, writ-
ing and turning are subject to the restriction that each bus
can be involved in no more than a single operation.
Among the functions provided are the ability to:
• Isolate bus segments from one another
• Connect two local-bus segments
• Connect two express-bus segments
• Implement a local/express transfer
Figure 4. Cell Structure
AT6000(LV) Series
4
AT6000(LV) Series
In addition to the four local-bus connections, a cell receives
two inputs and provides two outputs to each of its
North (N), South (S), East (E) and West (W) neighbors.
These inputs and outputs are divided into two classes: “A”
and “B”. There is an A input and a B input from each neigh-
boring cell and an A output and a B output driving all four
neighbors. Between cells, an A output is always connected
to an A input and a B output to a B input.
• In State 3 – corresponding to the “3” inputs of the
multiplexers – the XOR function of State 2 is provided to
the D input of a D-type flip-flop, the Q output of which is
connected to the cell’s A output. Clock and
asynchronous reset signals are supplied externally as
described later. The AND of the outputs from the two
upstream AND gates is provided to the cell's B output.
Within the cell, the four A inputs and the four B inputs enter
two separate, independently configurable multiplexers. Cell
flexibility is enhanced by allowing each multiplexer to select
also the logical constant “1”. The two multiplexer outputs
enter the two upstream AND gates.
Logic States
The Atmel cell implements a rich and powerful set of logic
functions, stemming from 44 logical cell states which per-
mutate into 72 physical states. Some states use both A and
B inputs. Other states are created by selecting the “1” input
on either or both of the input multiplexers.
Downstream from these two AND gates are an Exclusive-
OR (XOR) gate, a register, an AND gate, an inverter and
two four-input multiplexers producing the A and B outputs.
These multiplexers are controlled in tandem (unlike the
A and B input multiplexers) and determine the function of
the cell.
• In State 0 – corresponding to the “0” inputs of the
multiplexers – the output of the left-hand upstream AND
gate is connected to the cell’s A output, and the output of
the right-hand upstream AND gate is connected to the
cell’s B output.
There are 28 combinatorial primitives created from the
cell’s tristate capabilities and the 20 physical states repre-
sented in Figure 5. Five logical primitives are derived from
the physical constants shown in Figure 7. More complex
functions are created by using cells in combination.
A two-input AND feeding an XOR (Figure 8) is produced
using a single cell (Figure 9). A two-to-one multiplexer
selects the logical constant “0” and feeds it to the right-
hand AND gate. The AND gate acts as a feed-through, let-
ting the B input pass through to the XOR. The three-to-one
multiplexer on the right side selects the local-bus input,
LNS1, and passes it to the left-hand AND gate. The A and
LNS1 signals are the inputs to the AND gate. The output of
the AND gate feeds into the XOR, producing the logic state
(A L) XOR B.
• In State 1 – corresponding to the “1” inputs of the
multiplexers – the output of the left-hand upstream AND
gate is connected to the cell’s B output, the output of the
right-hand upstream AND gate is connected to the cell’s
A output.
• In State 2 – corresponding to the “2” inputs of the
multiplexers – the XOR of the outputs from the two
upstream AND gates is provided to the cell’s A output,
while the NAND of these two outputs is provided to the
cell’s B output.
5
Figure 5. Combinatorial Physical States
Figure 7. Physical Constants
L
L
A
L
B
B
i
i
i
"0"
"0"
"0"
"1"
"1"
"0"
B
"1"
"1"
B
A, L
B
A, L
B
A, L
A, L
o
o
o
o
A, L
B
B
A, L
B
A, L
A
B
B
A, L
A
B
A, L
o
o
o
o
o
A L
A L
B
L
L
A L
i
i
i
i
i
A, L
B
B
o
A, L
A, L
B
B
o
o
Figure 8. Two-input AND Feeding XOR
A
L
B
i
A, L
B
B
o
A, L
B
o
L
L
L B
i
A L
A
L
i
i
i
i
A, L
A, L
o
o
A, L
B
A, L
B
o
o
A, L
B
o
A
A
L
B
A
B
L
B
A L
B
A L
i
B
i
i
i
1
0
A, L
o
A, L
B
A, L
B
o
o
A, L
B
o
A, L
B
o
Figure 9. Cell Configuration (A L) XOR B
Figure 6. Register States
A
A
L
B
B
i
D
Q
"0"
B
D
Q
D
Q
D
Q
A, L
o
A, L
B
A, L
A
B
A, L
o
o
o
A L
L
B
L
i
i
i
D
Q
D
Q
D
Q
A, L
A, L
o
o
A, L
A
B
B
o
L
B
A L
B
A
1
L
i
B
i
i
0
D
Q
D
Q
D
Q
D
Q
A, L
o
A, L
B
A, L
B
o
o
A, L
B
o
AT6000(LV) Series
6
AT6000(LV) Series
Clock Distribution
Asynchronous Reset
Along the top edge of the array is logic for distributing clock
signals to the D flip-flop in each logic cell (Figure 10). The
distribution network is organized by column and permits
columns of cells to be independently clocked. At the head
of each column is a user-configurable multiplexer providing
the clock signal for that column. It has four inputs:
Along the bottom edge of the array is logic for asynchro-
nously resetting the D flip-flops in the logic cells
(Figure 10). Like the clock network, the asynchronous reset
network is organized by column and permits columns to be
independently reset. At the bottom of each column is a
user-configurable multiplexer providing the reset signal for
that column. It has four inputs:
• Global clock supplied through the CLOCK pin
• Global asynchronous reset supplied through the
RESET pin
• Express bus adjacent to the distribution logic
• “A” output of the cell at the head of the column
• Logical constant “1” to conserve power (no clock)
• Express bus adjacent to the distribution logic
• “A” output of the cell at the foot of the column
• Logical constant “1” to conserve power
Through the global clock, the network provides low-skew
distribution of an externally supplied clock to any or all of
the columns of the array. The global clock pin is also con-
nected directly to the array via the A input of the upper left
and right corner cells (AW on the left, and AN on the right).
The express bus is useful in distributing a secondary clock
to multiple columns when the global clock line is used as a
primary clock. The A output of a cell is useful in providing a
clock signal to a single column. The constant “1” is used to
reduce power dissipation in columns using no registers.
The asynchronous reset logic uses these four inputs in the
same way that the clock distribution logic does. Through
the global asynchronous reset, any or all columns can be
reset by an externally supplied signal. The global asynchro-
nous reset pin is also connected directly to the array via the
A input of the lower left and right corner cells (AS on the
left, and AE on the right). The express bus can be used to
distribute a secondary reset to multiple columns when the
global reset line is used as a primary reset, the A output of
a cell can also provide an asynchronous reset signal to a
single column, and the constant “1” is used by columns
with registers requiring no reset. All registers are reset dur-
ing power-up.
Figure 10. Column Clock and Column Reset
GLOBAL
CLOCK
GLOBAL
CLOCK
"1"
A
D
Q
Input/Output
CELL
The Atmel architecture provides a flexible interface
between the logic array, the configuration control logic and
the I/O pins.
EXPRESS
BUS
EXPRESS
BUS
D
Q
Two adjacent cells – an “exit” and an “entrance” cell – on
the perimeter of the logic array are associated with each
I/O pin.
CELL
D
E
D
I
C
A
T
E
D
R
B
U
R
I
E
D
O
U
T
I
N
G
There are two types of I/Os: A-type (Figure 11) and B-type
(Figure 12). For A-type I/Os, the edge-facing A output of an
exit cell is connected to an output driver, and the edge-
facing A input of the adjacent entrance cell is connected to
an input buffer. The output of the output driver and the input
of the input buffer are connected to a common pin.
CELL
CELL
D
Q
EXPRESS
BUS
EXPRESS
BUS
B-type I/Os are the same as A-type I/Os, but use the B
inputs and outputs of their respective entrance and exit
cells. A- and B-type I/Os alternate around the array Control
of the I/O logic is provided by user-configurable memory
bits.
D
Q
A
"1"
GLOBAL
RESET
GLOBAL
RESET
7
Figure 11. A-type I/O Logic
Slew Rate Control
A user-configurable bit controls the slew rate – fast or slow
– of the output buffer. A slow slew rate, which reduces
noise and ground bounce, is recommended for outputs that
are not speed-critical. Fast and slow slew rates have the
same DC-current sinking capabilities, but the rate at which
each allows the output devices to reach full drive differs.
Pull-up
A user-configurable bit controls the pull-up transistor in the
I/O pin. It’s primary function is to provide a logical “1” to
unused input pins. When on, it is approximately equivalent
to a 25K resistor to VCC
.
Enable Select
User-configurable bits determine the output-enable for the
output driver. The output driver can be static – always on or
always off – or dynamically controlled by a signal gener-
ated in the array. Four options are available from the array:
(1) the control is low and always driving; (2) the control is
high and never driving; (3) the control is connected to a ver-
tical local bus associated with the output cell; or (4) the
control is connected to a horizontal local bus associated
with the output cell. On power-up, the user I/Os are config-
ured as inputs with pull-up resistors.
Figure 12. B-type I/O Logic
In addition to the functionality provided by the I/O logic, the
entrance and exit cells provide the ability to register both
inputs and outputs. Also, these perimeter cells (unlike inte-
rior cells) are connected directly to express buses: the
edge-facing A and B outputs of the entrance cell are con-
nected to express buses, as are the edge-facing A and B
inputs of the exit cell. These buses are perpendicular to the
edge, and provide a rapid means of bringing I/O signals to
and from the array interior and the opposite edge of the
chip.
Chip Configuration
The Integrated Development System generates the SRAM
bit pattern required to configure a AT6000 Series device. A
PC parallel port, microprocessor, EPROM or serial configu-
ration memory can be used to download configuration
patterns.
TTL/CMOS Inputs
A user-configurable bit determines the threshold level –
TTL or CMOS – of the input buffer.
Users select from several configuration modes. Many fac-
tors, including board area, configuration speed and the
number of designs implemented in parallel can influence
the user’s final choice.
Open Collector/Tristate Outputs
A user-configurable bit which enables or disables the active
pull-up of the output device.
Configuration is controlled by dedicated configuration pins
and dual-function pins that double as I/O pins when the
device is in operation. The number of dual-function pins
required for each mode varies.
AT6000(LV) Series
8
AT6000(LV) Series
The devices can be partially reconfigured while in opera-
tion. Portions of the device not being modified remain
operational during reconfiguration. Simultaneous configu-
ration of more than one device is also possible. Full
configuration takes as little as a millisecond, partial configu-
ration is even faster.
M0, M1, M2
Configuration mode pins are used to determine the config-
uration mode. All three are TTL input pins.
CCLK
Configuration clock pin. CCLK is a TTL input or a CMOS
output depending on the mode of operation. In modes 1, 2,
3, and 6 it is an input. In modes 4 and 5 it is an output with
a typical frequency of 1 MHz. In all modes, the rising edge
of the CCLK signal is used to sample inputs and change
outputs.
Refer to the Pin Function Description section following for a
brief summary of the pins used in configuration. For more
information about configuration, refer to the AT6000 Series
Configuration data sheet.
Pin Function Description
CLOCK
This section provides abbreviated descriptions of the vari-
ous AT6000 Series pins. For more complete descriptions,
refer to the AT6000 Series Configuration data sheet.
External logic source used to drive the internal global clock
line. Registers toggle on the rising edge of CLOCK. The
CLOCK signal is neither used nor affected by the configu-
ration modes. It is always a TTL input.
Pinout tables for the AT6000 series of devices follow.
RESET
Power Pins
Array register asynchronous reset. RESET drives the inter-
nal global reset. The RESET signal is neither used nor
affected by the configuration modes. It is always a TTL
input.
VCC, VDD, GND, VSS
VCC and GND are the I/O supply pins, VDD and VSS are the
internal logic supply pins. VCC and VDD should be tied to the
same trace on the printed circuit board. GND and VSS
should be tied to the same trace on the printed circuit
board.
Dual-function Pins
When CON is high, dual-function I/O pins act as device
I/Os; when CON is low, dual-function pins are used as con-
figuration control or data signals as determined by the
configuration modes. Care must be taken when using
these pins to ensure that configuration activity does not
interfere with other circuitry connected to these pins in the
application.
Input/Output Pins
All I/O pins can be used in the same way (refer to the I/O
section of the architecture description). Some I/O pins are
dual-function pins used during configuration of the array.
When not being used for configuration, dual-function I/Os
are fully functional as normal I/O pins. On initial power-up,
all I/Os are configured as TTL inputs with a pull-up.
D0 or I/O
Serial configuration modes use D0 as the serial data input
pin. Parallel configuration modes use D0 as the least-sig-
nificant bit. Input data must meet setup and hold
requirements with respect to the rising edge of CCLK. D0 is
a TTL input during configuration.
Dedicated Timing and Control Pins
CON
Configuration-in-process pin. After power-up, CON stay-
sLow until power-up initialization is complete, at which time
CON is then released. CON is an open collector signal.
After power-up initialization, forcing CON low begins the
configuration process.
D1 to D7 or I/O
Parallel configuration modes use these pins as inputs.
Serial configuration modes do not use them. Data must
meet setup and hold requirements with respect to the rising
edge of CCLK. D1 - D7 are TTL inputs during configuration.
CS
Configuration enable pin. All configuration pins are ignored
if CS is high. CS must be held low throughout the configu-
ration process. CS is a TTL input pin.
A0 to A16 or I/O
During configuration in modes 1, 2 and 5, these pins are
CMOS outputs and act as the address pins for a parallel
EPROM. A0 - A16 eliminates the need for an external
address counter when using an external parallel nonvolatile
9
memory to configure the FPGA. Addresses change after
the rising edge of the CCLK signal.
current contents of the internal configuration RAM. If a mis-
match is detected between the data being loaded and the
data already in the RAM, the ERR pin goes low. The
CHECK function is optional and can be disabled during ini-
tial programming.
CSOUT or I/O
When cascading devices, CSOUT is an output used to
enable other devices. CSOUT should be connected to the
CS input of the downstream device. The CSOUT function is
optional and can be disabled during initial programming
when cascading is not used. When cascading devices,
CSOUT should be dedicated to configuration and not used
as a configurable I/O.
ERR or I/O
During configuration, ERR is an output. When the CHECK
function is activated and a mismatch is detected between
the current configuration data stream and the data already
loaded in the configuration RAM, ERR goes low. The ERR
ouput is a registered signal. Once a mismatch is found, the
signal is set and is only reset after the configuration cycle is
restarted. ERR is also asserted for configuration file errors.
The ERR function is optional and can be disabled during
initial programming.
CHECK or I/O
During configuration, CHECK is a TTL input that can be
used to enable the data check function at the beginning of
a configuration cycle. No data is written to the device while
CHECK is low. Instead, the configuration file being applied
to D0 (or D0 - D7, in parallel mode) is compared with the
Device Pinout Selection (Max. Number of User I/O)
AT6002
64 I/O
80 I/O
96 I/O
95 I/O
-
AT6003
64 I/O
80 I/O
108 I/O
120 I/O
-
AT6005
64 I/O
80 I/O
108 I/O
108 I/O
-
AT6010
-
84 PLCC
100 VQFP
132 PQFP
144 TQFP
208 PQFP
240 PQFP
-
108 I/O
120 I/O
172 I/O
204 I/O
-
-
-
Bit-stream Sizes
Mode(s)
Type
Beginning Sequence
Preamble
AT6002
AT6003
4153
4153
4154
4154
4153
4154
AT6005
8077
8077
8078
8078
8077
8078
AT6010
1
2
3
4
5
6
Parallel
Parallel
Serial
2677
2677
2678
2678
2677
2678
16393
16393
16394
16394
16393
16394
Preamble
Null Byte/Preamble
Null Byte/Preamble
Preamble
Serial
Parallel
Parallel
Preamble/Preamble
AT6000(LV) Series
10
AT6000(LV) Series
Pinout Assignment
Left Side (Top to Bottom)
84
100
132
144
180
208
240
AT6002
AT6003
AT6005
AT6010
PLCC
VQFP
PQFP
TQFP
CPGA
PQFP
PQFP
-
-
-
I/O51(A)
-
12
-
-
1
-
-
18
-
-
1
B1
C1
1
2
1
I/O24(A) or A7
I/O30(A) or A7
I/O27(A) or A7
I/O50(A) or A7
I/O49(A)
2
-
I/O29(B)
-
2
D1
3
3
-
-
-
I/O48(B)
-
-
-
-
-
-
4
-
-
-
VCC
-
-
-
-
PWR(1)
E1
4
5
-
-
-
I/O47(A)
-
-
-
-
5
6
-
-
-
GND
-
-
-
-
GND(2)
G1
H1
6
7
-
I/O28(A)
I/O26(A)
I/O46(A)
-
-
19
20
-
3
7
8
I/O23(A) or A6
I/O27(A) or A6
I/O25(A) or A6
I/O45(A) or A6
I/O44(B)
13
-
2
-
4
8
9
-
-
-
-
-
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
-
-
-
I/O43(A)
-
-
-
-
C2
9
I/O22(B)
I/O26(A)
I/O24(A)
I/O42(A)
-
-
21
22
-
5
D2
10
11
-
I/O21(A) or A5
I/O25(A) or A5
I/O23(A) or A5
I/O41(A) or A5
I/O40(B)
14
-
3
-
6
E2
-
-
-
-
-
-
-
-
I/O39(A)
-
-
-
-
F2
12
13
14
-
I/O20(B)
I/O24(B)
I/O23(A) or A4
-
I/O22(A)
I/O38(A)
-
4
5
-
23
24
-
7
G2
H2
I/O19(A) or A4
I/O21(A) or A4
I/O37(A) or A4
I/O36(B)
15
-
8
-
-
-
-
I/O18(B)
I/O22(B)
I/O21(A) or A3
I/O20(B)
-
I/O20(A)
I/O35(A)
-
-
25
26
27
-
9
D3
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
I/O17(A) or A3
I/O19(A) or A3
I/O34(A) or A3
I/O33(A)
16
-
6
7
-
10
11
-
E3
I/O16(B)
I/O18(A)
F3
-
-
I/O32(B)
-
-
I/O15(A) or A2
I/O19(A) or A2
I/O18(B)
GND
I/O17(A) or A2
I/O31(A) or A2
I/O30(A)
17
-
8
-
28
29
30
31
32
-
12
13
14
15
16
-
G3
H3
-
I/O16(A)
GND
GND
GND
18
19
20
-
9
10
11
-
GND(2)
GND(2)
F4
VSS
VSS
VSS
VSS
I/O14(A) or A1
I/O17(A) or A1
-
I/O15(A) or A1
I/O29(A) or A1
I/O28(B)
-
-
-
-
I/O16(B)
I/O15(A) or A0
I/O14(A) or D7
-
-
I/O27(A)
-
-
-
17
18
19
-
G4
H4
I/O13(A) or A0
I/O12(B) or D7
-
I/O14(A) or A0
I/O13(A) or D7
-
I/O26(A) or A0
I/O25(B) or D7
I/O24(B)
21
22
-
12
13
-
33
34
-
H5
-
I/O11(A) or D6
I/O10(A) or D5
VDD
I/O13(A) or D6
I/O12(A) or D5
VDD
I/O12(A) or D6
I/O11(A) or D5
VDD
I/O23(A) or D6
I/O22(A) or D5
VDD
23
24
25
26
14
15
16
17
35
36
37
38
20
21
22
23
J4
K4
PWR(1)
PWR(1)
VCC
VCC
VCC
VCC
11
Pinout Assignment (Continued)
Left Side (Top to Bottom)
84
100
132
144
180
208
240
AT6002
AT6003
AT6005
AT6010
PLCC
VQFP
PQFP
TQFP
CPGA
PQFP
PQFP
I/O9(B)
I/O11(B)
I/O10(A)
I/O21(A)
I/O20(B)
I/O19(A) or D4
I/O18(A)
I/O17(A)
I/O16(B)
I/O15(A) or D3
I/O14(A)
I/O13(A)
GND
-
-
-
-
39
-
24
-
J3
-
33
34
35
36
37
-
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
-
-
-
I/O8(A) or D4
I/O10(A) or D4
I/O9(A) or D4
27
-
18
19
-
40
41
-
25
26
-
K3
L3
I/O7(B)
I/O9(B)
I/O8(A)
-
-
-
-
M3
-
-
-
-
-
-
-
-
I/O6(A) or D3
I/O8(A) or D3
I/O7(A) or D3
28
-
20
-
42
43
-
27
28
-
N3
J2
38
39
40
41
42
-
-
I/O7(B)
I/O6(A)
-
-
-
-
-
K2
GND(2)
GND(2)
-
GND
GND
GND
-
-
44
-
29
-
-
-
-
VSS
-
-
-
-
-
I/O12(B)
I/O11(A) or D2
I/O10(A)
I/O9(A)
-
-
-
-
I/O5(A) or D2
I/O6(A) or D2
I/O5(A) or D2
29
-
21
22
-
45
46
-
30
31
-
M2
N2
P2
-
43
44
45
-
I/O4(B)
I/O5(B)
I/O4(A)
-
-
-
-
-
-
-
I/O8(B)
-
-
-
-
I/O3(A) or D1
I/O4(A) or D1
I/O3(A) or D1
I/O7(A) or D1
I/O6(A)
30
-
23
-
47
48
-
32
33
-
J1
46
47
48
-
I/O2(B)
I/O3(A)
I/O2(A)
K1
L1
-
-
-
I/O5(A)
-
-
-
-
-
I/O4(B)
-
-
-
-
-
-
I/O2(B)
-
I/O3(A)
-
-
-
34
35
-
M1
N1
P1
R1
49
50
51
52
I/O1(A) or D0
I/O1(A) or D0
I/O1(A) or D0
I/O2(A) or D0
I/O1(A)
31
-
24
-
49
-
-
-
-
CCLK
CCLK
CCLK
CCLK
32
25
50
36
Notes: 1. PWR = Pins connected to power plane = F1, E4/E5, L2, R4, K15, L12, E14, A12.
2. GND = Pins connected to ground plane = L4, M4, N9, N10, E12, D12, C7, C6.
AT6000(LV) Series
12
AT6000(LV) Series
Pinout Assignment
Bottom Side (Left to Right)
84
100
132
144
180
208
240
AT6002
AT6003
AT6005
AT6010
PLCC
VQFP
PQFP
TQFP
CPGA
PQFP
PQFP
CON
CON
CON
CON
33
-
26
-
51
-
37
-
M5
M6
53
54
55
56
-
61
62
63
64
65
66
67
68
69
-
-
-
I/O204(A)
I/O203(A)
I/O202(A)
I/O201(B)
VCC
I/O96(A)
I/O120(A)
I/O108(A)
34
-
27
-
52
-
38
39
-
M7
-
-
-
-
-
-
I/O119(B)
-
R2
-
-
-
-
-
-
-
-
-
-
-
-
PWR(1)
R3
57
58
59
60
-
-
I/O200(A)
GND
-
-
-
-
-
-
-
-
-
-
GND(2)
R5
I/O118(A)
I/O107(A)
I/O199(A)
-
-
53
40
I/O95(A) or
CSOUT
I/O117(A) or
CSOUT
I/O106(A) or
CSOUT
I/O198(A) or
CSOUT
35
28
54
41
R6
61
70
-
-
-
I/O197(B)
I/O196(A)
I/O195(A)
I/O194(A)
I/O193(B)
I/O192(A)
I/O191(A)
-
-
-
-
-
-
-
-
-
-
71
72
73
74
75
76
77
-
-
-
R7
P3
P4
-
62
63
64
-
I/O94(B)
I/O116(A)
I/O105(A)
-
-
55
56
-
42
43
-
I/O93(A)
I/O115(A)
I/O104(A)
36
-
29
-
-
-
-
-
-
-
-
-
-
-
P5
P6
65
66
I/O92(B)
I/O114(B)
I/O103(A)
-
30
57
44
I/O91(A) or
CHECK
I/O113(A) or
CHECK
I/O102(A) or
CHECK
I/O190(A) or
CHECK
37
31
58
45
P7
67
78
-
-
-
I/O189(B)
I/O188(A)
-
-
-
-
-
-
-
-
79
80
I/O90(B)
I/O112(B)
I/O101(A)
59
46
N4
68
I/O89(A) or
ERR
I/O111(A) or
ERR
I/O100(A) or
ERR
I/O187(A) or
ERR
38
32
60
47
N5
69
81
I/O88(B)
I/O110(B)
-
I/O99(A)
-
I/O186(A)
I/O185(B)
I/O184(A)
I/O183(A)
GND
-
-
33
-
61
-
48
-
N6
-
70
71
72
73
74
75
76
77
78
79
80
81
82
82
83
84
85
86
87
88
89
90
91
92
93
94
-
I/O87(A)
I/O109(A)
I/O108(B)
GND
I/O98(A)
I/O97(A)
GND
I/O96(A)
-
39
-
34
-
62
63
64
65
-
49
50
51
52
-
N7
-
M8
GND(2)
M9
-
GND
40
41
-
35
36
-
I/O86(A)
I/O107(A)
-
I/O182(A)
I/O181(B)
I/O180(A)
I/O179(A)
CS
-
-
I/O106(B)
I/O105(A)
CS
-
-
-
-
53
54
55
56
-
M10
M11
L8
I/O85(A)
CS
I/O95(A)
CS
42
43
44
-
37
38
39
-
66
67
68
-
I/O84(B)
-
I/O104(A)
-
I/O94(A)
-
I/O178(A)
I/O177(B)
I/O176(A)
M12
-
I/O83(A)
I/O103(A)
I/O93(A)
45
40
69
57
N8
13
Pinout Assignment (Continued)
Bottom Side (Left to Right)
84
100
132
144
180
208
240
AT6002
AT6003
AT6005
AT6010
PLCC
VQFP
PQFP
TQFP
CPGA
PQFP
PQFP
-
-
-
VDD
-
46
47
-
-
41
42
-
-
70
71
72
-
-
58
59
60
-
PWR(1)
PWR(1)
N11
N12
-
83
84
85
86
87
88
89
90
-
95
VCC
VCC
VCC
VCC
96
I/O82(A)
I/O102(A)
I/O92(A)
I/O175(A)
I/O174(A)
I/O173(B)
I/O172(A)
I/O171(A)
I/O170(A)
I/O169(B)
I/O168(A)
I/O167(A)
I/O166(A)
GND
97
I/O81(B)
I/O101(B)
I/O91(A)
98
-
-
-
-
-
99
I/O80(A)
I/O100(A)
I/O90(A)
48
-
43
44
-
73
74
-
61
62
-
N13
P8
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
I/O79(B)
I/O99(B)
I/O89(A)
-
-
-
-
P9
-
-
-
-
-
-
-
-
I/O78(A)
I/O98(A)
I/O88(A)
49
-
45
-
75
76
-
63
64
-
P10
P11
P12
GND(2)
-
91
92
93
94
-
-
I/O97(B)
I/O87(A)
-
-
-
-
-
GND
GND
GND
-
-
77
-
65
-
-
-
-
I/O165(B)
I/O164(A)
I/O163(A)
I/O162(A)
I/O161(B)
I/O160(A)
I/O159(A)
I/O158(A)
I/O157(B)
I/O156(A)
I/O155(A)
I/O154(A)
RESET
-
-
I/O77(A)
I/O96(A)
I/O86(A)
50
-
46
47
-
78
79
-
66
67
-
P13
P14
P8
95
96
97
-
I/O76(B)
I/O95(B)
I/O85(A)
-
-
-
-
-
-
-
-
-
-
-
-
I/O75(A)
I/O94(A)
I/O84(A)
51
-
48
-
80
81
-
68
69
-
R9
98
99
100
-
I/O74(B)
I/O93(A)
I/O83(A)
R10
R11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O92(B)
I/O91(A)
-
-
-
-
-
70
71
-
R12
R13
R14
R15
101
102
103
104
I/O73(A)
-
I/O82(A)
-
52
-
49
-
82
-
RESET
RESET
RESET
53
50
83
72
Notes: 1. PWR = Pins connected to power plane = F1, E4/E5, L2, R4, K15, L12, E14, A12.
2. GND = Pins connected to ground plane = L4, M4, N9, N10, E12, D12, C7, C6.
AT6000(LV) Series
14
AT6000(LV) Series
Pinout Assignment
Right Side (Bottom to Top)
84
100
132
144
180
208
240
AT6002
AT6003
AT6005
AT6010
PLCC
VQFP
PQFP
TQFP
CPGA
PQFP
PQFP
-
-
-
I/O153(A)
I/O152(A)
I/O151(A)
I/O150(B)
VCC
-
54
-
-
51
-
-
84
85(3)
-
-
P15
N15
M15
-
105
106
107
-
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
I/O72(A)
I/O90(A)
I/O81(A)
73
74
-
-
I/O89(B)
I/O80(A)
-
-
-
-
-
-
-
-
-
-
-
-
PWR(1)
L15
GND(2)
J15
H15
-
108
109
110
111
112
-
-
-
-
I/O149(A)
GND
-
-
-
-
-
-
-
-
-
-
-
-
I/O88(A)
I/O87(A)
-
-
I/O148(A)
I/O147(A)
I/O146(B)
I/O145(A)
I/O144(A)
I/O143(A)
I/O142(B)
I/O141(A)
I/O140(A)
I/O139(A)
I/O138B
I/O137(A)
I/O136(A)
I/O135(A)
I/O134(B)
I/O133(A)
I/O132(A)
GND
-
-
85(4)
86
-
75
76
-
I/O71(A)
I/O79(A)
-
55
-
52
-
-
-
-
-
-
-
-
-
N14
M14
L14
-
113
114
115
-
I/O70(B)
I/O69(A)
-
I/O86(A)
I/O85(A)
-
I/O78(A)
I/O77(A)
-
-
-
87
88
-
77
78
-
56
-
53
-
-
-
-
-
-
-
-
K14
J14
H14
-
116
117
118
-
I/O68(B)
I/O67(A)
-
I/O84(B)
I/O83(A)
-
I/O76(A)
I/O75(A)
-
-
54
55
-
89
90
-
79
80
-
57
-
I/O66(B)
I/O65(A)
I/O64(B)
-
I/O82(B)
I/O81(A)
I/O80(B)
-
I/O74(A)
I/O73(A)
I/O72(A)
-
-
-
91
92
93
-
81
82
83
-
M13
L13
K13
-
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
58
-
56
57
-
-
I/O63(A)
-
I/O79(A)
I/O78(B)
GND
I/O71(A
I/O70(A)
GND
VSS
59
-
58
-
94
95
96
97
98
-
84
85
86
87
88
-
J13
H13
GND(2)
GND(2)
K12
-
GND
VSS
60
61
62
-
59
60
61
-
VSS
VSS
I/O62(A)
-
I/O77(A)
-
I/O69(A)
-
I/O131(A)
I/O130(B)
I/O129(A)
I/O128(A)
I/O127(A)
I/O126(B)
I/O125(A)
I/O124(A)
VDD
-
I/O76(B)
I/O75(A)
I/O74(A)
-
-
-
-
-
89
90
91
-
J12
H12
H11
-
I/O61(A)
I/O60(B)
-
I/O68(A)
I/O67(A)
-
63
64
-
62
63
-
99
100
-
I/O59(A)
I/O58(A)
VDD
I/O73(A)
I/O72(A)
VDD
I/O66(A)
I/O65(A)
VDD
65
66
67
68
64
65
66
67
101
102
103
104
92
93
94
95
G12
F12
PWR(1)
PWR(1)
VCC
VCC
VCC
VCC
15
Pinout Assignment (Continued)
Right Side (Bottom to Top)
84
100
132
144
180
208
240
AT6002
AT6003
AT6005
AT6010
PLCC
VQFP
PQFP
TQFP
CPGA
PQFP
PQFP
I/O57(B)
I/O71(B)
I/O64(A)
I/O123(A)
I/O122(B)
I/O121(A)
I/O120(A)
I/O119(A)
I/O118(B)
I/O117(A)
I/O116(A)
I/O115(A)
GND
-
-
-
-
105
96
-
G13
-
137
138
139
140
141
-
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178‘
179
180
-
-
-
-
I/O56(A)
I/O70(A)
I/O63(A)
69
-
68
69
-
106
97
98
-
F13
E13
D13
-
I/O55(B)
I/O69(B)
I/O62(A)
107
-
-
-
-
-
-
-
-
-
-
-
-
I/O54(A)
I/O68(A)
I/O61(A)
70
-
70
-
108
99
100
-
C13
G14
F14
GND(2)
GND(2)
-
142
143
144
145
146
-
-
I/O67(B)
I/O60(A)
109
-
-
-
-
-
-
GND
GND
GND
-
-
110
101
-
-
-
-
VSS
-
-
-
-
-
-
I/O114(B)
I/O113(A)
I/O112(A)
I/O111(A)
I/O110(B)
I/O109(A)
I/O108(A)
I/O107(A)
I/O106(B)
I/O105(A)
I/O104(A)
I/O103(A)
M2
-
-
-
111
112
-
-
I/O53(A)
I/O66(A)
I/O59(A)
71
-
71
72
-
102
103
-
D14
C14
B14
-
147
148
149
-
I/O52(B)
I/O65(B)
I/O58(A)
-
-
-
-
-
-
-
-
-
-
-
I/O51(A)
I/O64(A)
I/O57(A)
72
-
73
-
113
114
-
104
105
-
G15
F15
E15
-
150
151
152
-
I/O50(B)
I/O63(A)
I/O56(A)
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O62(B)
-
-
-
-
106
107
-
D15
C15
B15
A15
153
154
155
156
I/O49(A)
I/O61(A)
I/O55(A)
73
-
74
-
115
-
-
-
-
M2
M2
M2
74
75
116
108
Notes: 1. PWR = Pins connected to power plane = F1, E4/E5, L2, R4, K15, L12, E14, A12.
2. GND = Pins connected to ground plane = L4, M4, N9, N10, E12, D12, C7, C6.
3. 85 = Pin 85 on AT6005.
4. 85 = Pin 85 on AT6003 and AT6010.
AT6000(LV) Series
16
AT6000(LV) Series
Pinout Assignment
Top Side (Right to Left)
84
100
132
144
180
208
240
AT6002
AT6003
AT6005
AT6010
PLCC
VQFP
PQFP
TQFP
CPGA
PQFP
PQFP
M1
M1
M1
M1
75
-
76
-
117
109
-
D11
D10
D9
157
158
159
160
-
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
-
-
-
I/O102(A)
I/O101(A)
I/O100(A)
I/O99(B)
VCC
-
I/O48(A)
I/O60(A)
I/O54(A)
76
-
77
-
118
110
111
-
-
I/O59(B)
-
-
A14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PWR(1)
A13
GND(2)
A11
A10
-
161
162
163
164
165
-
-
-
-
I/O98(A)
GND
-
-
-
-
-
-
-
-
-
-
-
I/O58(A)
I/O53(A)
I/O97(A)
I/O96(A)
I/O95(B)
I/O94(A)
I/O93(A)
I/O92(A)
I/O91(B)
I/O90(A)
I/O89(A)
I/O88(A)
I/O87(B)
I/O86(A)
I/O85(A)
I/O84(A)
I/O83(B)
I/O82(A)
I/O81(A)
GND
-
-
119
120
-
112
113
-
I/O47(A)
I/O57(A)
I/O52(A)
77
-
78
-
-
-
-
-
-
-
-
-
-
-
A9
166
167
168
-
I/O46(B)
I/O56(A)
I/O51(A)
-
-
121
122
-
114
115
-
B13
B12
-
I/O45(A)
I/O55(A)
I/O50(A)
78
-
79
-
-
-
-
-
-
-
-
-
-
-
B11
B10
B9
169
170
171
-
I/O44(B)
I/O54(B)
I/O49(A)
-
80
81
-
123
124
-
116
117
-
I/O43(A)
I/O53(A)
I/O48(A)
79
-
-
-
-
-
I/O42(B)
I/O52(B)
I/O47(A)
-
-
125
126
127
-
118
119
120
-
C12
C11
C10
-
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
I/O41(A)
I/O51(A)
I/O46(A)
80
-
82
83
-
I/O40(B)
I/O50(B)
I/O45(A)
-
-
-
-
I/O39(A)
I/O49(A)
I/O44(A)
81
-
84
-
128
129
130
131
-
121
122
123
124
-
C9
-
I/O48(B)
I/O43(A)
D8
GND
GND
GND
82
83
-
85
86
-
GND(2)
D7
I/O38(A)
I/O47(A)
I/O42(A)
I/O80(A)
I/O79(B)
I/O78(A)
I/O77(A) or A16
CLOCK
I/O76(A) or A15
I/O75(B)
I/O74(A) or A14
VDD
-
-
-
-
-
I/O46(B)
-
-
-
-
125
126
127
128
-
D6
I/O37(A) or A16
I/O45(A) or A16
I/O41(A) or A16
84
1
2
-
87
88
89
-
132
1
D5
CLOCK
CLOCK
CLOCK
E8
I/O36(B) or A15
I/O44(B) or A15
I/O40(A) or A15
2
D4
-
-
-
-
-
I/O35(A) or A14
I/O43(A) or A14
I/O39(A) or A14
3
-
90
-
3
129
-
C8
-
-
-
-
PWR(1)
PWR(1)
VCC
VCC
VCC
VCC
4
91
4
130
17
Pinout Assignment (Continued)
Top Side (Right to Left)
84
100
132
144
180
208
240
AT6002
AT6003
AT6005
AT6010
PLCC
VQFP
PQFP
TQFP
CPGA
PQFP
PQFP
I/O34(A) or A13
I/O42(A) or A13
I/O38(A) or A13
I/O73(A) or A13
I/O72(A)
5
-
92
5
6
131
132
-
C5
C4
-
189
190
191
192
193
194
-
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
I/O33(B)
I/O41(B)
I/O37(A)
-
-
-
-
-
I/O71(B)
-
-
I/O32(A) or A12
I/O40(A) or A12
I/O36(A) or A12
I/O70(A) or A12
I/O69(A)
6
-
93
94
-
7
133
134
-
C3
B8
B7
-
I/O31(B)
I/O39(B)
I/O35(A)
8
-
-
-
I/O68(A)
-
-
-
-
-
I/O67(B)
-
-
-
-
I/O30(A) or A11
I/O38(A) or A11
I/O34(A) or A11
I/O66(A) or A11
I/O65(A)
7
-
95
-
9
135
136
-
B6
B5
B4
GND(2)
-
195
196
197
198
-
-
I/O37(B)
I/O33(A)
10
-
-
-
-
I/O64(A)
-
-
GND
GND
GND
GND
-
-
11
-
137
-
-
-
-
I/O63(B)
-
-
I/O29(A) or A10
I/O36(A) or A10
I/O32(A) or A10
I/O62(A) or A10
I/O61(A)
8
-
96
97
-
12
13
-
138
139
-
B3
B2
A8
-
199
200
201
-
I/O28(B)
I/O35(B)
I/O31(A)
-
-
-
I/O60(A)
-
-
-
-
I/O59(B)
-
-
-
-
I/O27(A) or A9
I/O34(A) or A9
I/O30(A) or A9
I/O58(A) or A9
I/O57(A)
9
-
98
-
14
15
-
140
141
-
A7
A6
A5
-
202
203
204
-
I/O26(B)
I/O33(A)
I/O29(A)
-
-
-
I/O56(A)
-
-
-
-
-
I/O55(B)
-
-
-
-
-
I/O32(B)
-
I/O54(A)
-
-
-
142
143
-
A4
A3
A2
A1
205
206
-207
208
I/O25(A) or A8
I/O31(A) or A8
I/O28(A) or A8
I/O53(A) or A8
I/O52(A)
10
-
99
-
16
-
-
-
-
M0
M0
M0
M0
11
100
17
144
Notes: 1. PWR = Pins connected to power plane = F1, E4/E5, L2, R4, K15, L12, E14, A12.
2. GND = Pins connected to ground plane = L4, M4, N9, N10, E12, D12, C7, C6.
AT6000(LV) Series
18
AT6000(LV) Series
AC Timing Characteristics – 5V Operation
Delays are based on fixed load. Loads for each type of device are described in the notes. Delays are in nanoseconds.
Worst case: VCC = 4.75V to 5.25V. Temperature = 0°C to 70°C.
Load
Cell Function
Wire(4)
Parameter
From
To
A, B
B
Definition(7)
-1
-2
-4
1.8
3.2
4.0
3.2
4.0
4.9
3.0
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPD (max)(4)
A, B, L
1
1
1
1
1
1
-
0.8
1.6
1.8
1.7
1.7
2.1
1.5
0
1.2
2.2
2.4
2.2
2.3
3.0
2.0
0
NAND
t
t
t
PD (max)
PD (max)
PD (max)
A, B, L
XOR
A, B, L
A
AND
A, B, L
B
A, B
A
MUX
t
PD (max)
L
A
D-Flip-flop(5)
D-Flip-flop(5)
D-Flip-flop
Bus Driver
tsetup (min)
thold (min)
A, B, L
CLK
A, B, L
A
CLK
-
t
PD (max)
CLK
1
2
3
2
3
3
-
1.5
2.0
1.3
1.7
1.8
1.8
1.6
1.5
1.0
1.3
3.3
7.5
3.1
3.8
8.2
2.0
2.6
1.6
2.1
2.4
2.4
2.0
1.9
1.2
1.4
3.5
8.0
3.3
4.0
8.5
3.0
4.0
2.3
3.0
3.0
3.0
2.9
2.8
1.5
2.3
6.0
12.0
5.5
6.5
12.5
tPD (max)
tPD (max)
tPD (max)
A
L
L, E
E
Repeater
L, E
L
Column Clock
Column Reset
Clock Buffer(5)
Reset Buffer(5)
TTL Input(1)
GCLK, A, ES
CLK
RES
GCLK
GRES
A
t
PD (max)
GRES, A, EN
tPD (max)
tPD (max)
tPD (max)
tPD (max)
tPD (max)
tPD (max)
tPXZ (max)
tPXZ (max)
tPXZ (max)
CLOCK PIN
RESET PIN
-
I/O
I/O
A
3
3
4
4
4
4
4
CMOS Input(2)
Fast Output(3)
Slow Output(3)
Output Disable(5)
Fast Enable(3)(5)
Slow Enable(3)(5)
A
I/O PIN
I/O PIN
I/O PIN
I/O PIN
I/O PIN
A
L
L
L
Device
Cell Types
Wire, XWire, Half-adder, Flip-flop
Outputs
A, B
L
ICC (max)
Cell(6)
4.5 µA/MHz
2.5 µA/MHz
40 µA/MHz
Bus(6)
Wire, XWire, Half-adder, Flip-flop, Repeater
Column Clock Driver
Column Clock(6)
CLK
Notes: 1. TTL buffer delays are measured from a VIH of 1.5V at the pad to the internal VIH at A. The input buffer load is constant.
2. CMOS buffer delays are measured from a VIH of 1/2 VCC at the apd to the internal VIH at A. The input buffer load is constant.
3. Buffer delay is to a pad voltage of 1.5V with one output switching.
4. Max specifications are the average of mas tPDLH and tPDHL
.
5. Parameter based on characterization and simulation; not tested in production
6. Exact power calculation is available in an Atmel application note.
7. Load Definition: 1 = Load of one A or B input; 2 = Load of one L input; 3 = Constant Load; 4 = Tester Load of 50 pF.
= Preliminary Information
19
AC Timing Characteristics – 3.3V Operation
Delays are based on fixed load. Loads for each type of device are described in the notes. Delays are in nanoseconds.
Worst case: VCC = 3.0V to 3.6V. Temperature = 0°C to 70°C.
Load
Cell Function
Wire(4)
Parameter
From
To
A, B
B
Definition(7)
-4
1.8
3.2
4.0
3.2
4.0
4.9
3.0
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPD (max)(4)
A, B, L
1
1
1
1
1
1
-
NAND
tPD (max)
tPD (max)
tPD (max)
A, B, L
XOR
A, B, L
A
AND
A, B, L
B
A, B
A
MUX
tPD (max)
L
A
D-Flip-flop(5)
D-Flip-flop(5)
D-Flip-flop
Bus Driver
tsetup (min)
thold (min)
tPD (max)
A, B, L
CLK
A, B, L
A
CLK
-
CLK
1
2
3
2
3
3
4
5
3
3
6
6
6
6
6
3.0
4.0
2.3
3.0
3.0
3.0
2.9
2.8
1.5
2.3
6.0
12.0
5.5
6.5
12.5
tPD (max)
A
L
L, E
E
Repeater
tPD (max)
L, E
L
Column Clock
Column Reset
Clock Buffer(5)
Reset Buffer(5)
TTL Input(1)
tPD (max)
GCLK, A, ES
CLK
RES
GCLK
GRES
A
tPD (max)
GRES, A, EN
tPD (max)
tPD (max)
tPD (max)
tPD (max)
tPD (max)
tPD (max)
tPXZ (max)
tPXZ (max)
tPXZ (max)
CLOCK PIN
RESET PIN
I/O
I/O
A
CMOS Input(2)
Fast Output(3)
Slow Output(3)
Output Disable(5)
Fast Enable(3)(5)
Slow Enable(3)(5)
A
I/O PIN
I/O PIN
I/O PIN
I/O PIN
I/O PIN
A
L
L
L
Device
Cell Types
Outputs
ICC (max)
Cell(6)
Wire, XWire, Half-adder, Flip-flop
Wire, XWire, Half-adder, Flip-flop, Repeater
Column Clock Driver
A, B
L
2.3 µA/MHz
1.3 µA/MHz
20 µA/MHz
Bus(6)
Column Clock(6)
CLK
Notes: 1. TTL buffer delays are measured from a VIH of 1.5V at the pad to the internal VIH at A. The input buffer load is constant.
2. CMOS buffer delays are measured from a VIH of 1/2 VCC at the apd to the internal VIH at A. The input buffer load is constant.
3. Buffer delay is to a pad voltage of 1.5V with one output switching.
4. Max specifications are the average of mas tPDLH and tPDHL
.
5. Parameter based on characterization and simulation; not tested in production
6. Exact power calculation is available in an Atmel application note.
7. Load Definition: 1 = Load of one A or B input; 2 = Load of one L input; 3 = Constant Load; 4 = Load of 28 Clock Columns; 5
= Load of 28 Reset Columns; 6 = Tester Load of 50 pF.
AT6000(LV) Series
20
AT6000(LV) Series
Absolute Maximum Ratings*
Supply Voltage (VCC) ........................................-0.5V to + 7.0V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. These are stress rating only
and functional operation of the device at these or
any other conditions beyond those listed under
operating conditions is not implied. Exposure to
Absolute Maximum Rating conditions for
extended periods of time may affect device reli-
ability.
DC Input Voltage (VIN) ...............................-0.5V to VCC + 0.5V
DC Output Voltage (VON) ...........................-0.5V to VCC + 0.5V
Storage Temperature Range
(TSTG)........................................................... -65°C to +150°C
Power Dissipation (PD)............................................. 1500 mW
Lead Temperature (TL)
(Soldering, 10 sec.) ........................................................260°C
ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V
DC and AC Operating Rage – 5V Operation
AT6002-2/4
AT6003-2/4
AT6005-2/4
AT6010-2/4
Commercial
AT6002-2/4
AT6003-2/4
AT6005-2/4
AT6010-2/4
Industrial
AT6002-2/4
AT6003-2/4
AT6005-2/4
AT6010-2/4
Military
Operating Temperature (Case)
CC Power Supply
0°C - 70°C
5V ± 5%
-40°C - 85°C
5V ± 10%
-55°C - 125°C
5V ± 10%
V
High (VIHT
Low (VILT
High (VIHC
Low (VILC
)
2.0V - VCC
2.0V - VCC
2.0V - VCC
Input Voltage Level
(TTL)
)
0V - 0.8V
0V - 0.8V
0V - 0.8V
)
70% - 100% VCC
0 - 30% VCC
50 ns (max)
70% - 100% VCC
0 - 30% VCC
50 ns (max)
70% - 100% VCC
0 - 30% VCC
50 ns (max)
Input Voltage Level
(CMOS)
)
Input Signal Transition Time (TIN)
DC and AC Operating Rage – 3.3V Operation
AT6002-2/4, AT6003-2/4
AT6005-2/4, AT6010-2/4
Commercial
Operating Temperature (Case)
0°C - 70°C
3.3V ± 5%
VCC Power Supply
High (VIHT
Low (VILT
High (VIHC
Low (VILC
)
2.0V - VCC
Input Voltage Level
(TTL)
)
0V - 0.8V
)
70% - 100% VCC
0 - 30% VCC
50 ns (max)
Input Voltage Level
(CMOS)
)
Input Signal Transition Time (TIN)
21
DC Characteristics – 5V Operation
Symbol
Parameter
Conditions
Min
Max
VCC
Units
CMOS
70% VCC
V
V
V
V
V
V
V
V
VIH
High-level Input Voltage
Commercial
TTL
2.0
0
VCC
CMOS
30% VCC
0.8
VIL
Low-level Input Voltage
High-level Output Voltage
Low-level Output Voltage
Commercial
Commercial
Commercial
VO = VCC (max)
TTL
0
IOH = -4 mA, VCC min
3.9
3.0
VOH
VOL
IOZH
I
I
I
OH = -16 mA, VCC min
OL = 4 mA, VCC min
OL = 16 mA, VCC min
0.4
0.5
High-level Tristate
10
µA
Output Leakage Current
High-level Tristate
Without Pull-up, VO = VSS
With Pull-up, VO = VSS
VIN = VCC (max)
-10
µA
µA
µA
µA
µA
µA
pF
IOZL
IIH
Output Leakage Current
High-level Input Current
-500
10
Without Pull-up, VIN = VSS
With Pull-up, VIN = VSS
Without Internal Oscillator (Standby)
All Pins
-10
IIL
Low-level Input Current
-500
ICC
Power Consumption
Input Capacitance
500
10
CIN
AT6000(LV) Series
22
AT6000(LV) Series
DC Characteristics – 3.3V Operation
Symbol
Parameter
Conditions
Min
Max
VCC
Units
CMOS
TTL
70% VCC
V
V
V
V
V
V
V
V
VIH
High-level Input Voltage
Commercial
2.0
0
VCC
CMOS
TTL
30% VCC
0.8
VIL
Low-level Input Voltage
High-level Output Voltage
Low-level Output Voltage
Commercial
Commercial
Commercial
VO = VCC (max)
0
I
I
I
I
OH = -2 mA, VCC min
OH = -6 mA, VCC min
OL = +2 mA, VCC min
OL = +6 mA, VCC min
2.4
2.0
VOH
VOL
IOZH
0.4
0.5
High-level Tristate
10
µA
Output Leakage Current
High-level Tristate
Without Pull-up, VO = VSS
With Pull-up, VO = VSS
VIN = VCC (max)
-10
µA
µA
µA
µA
µA
µA
pF
IOZL
IIH
Output Leakage Current
High-level Input Current
-500
10
Without Pull-up, VIN = VSS
With Pull-up, VIN = VSS
Without Internal Oscillator (Standby)
All Pins
-10
IIL
Low-level Input Current
-500
ICC
Power Consumption
Input Capacitance
200
10
(1)
CIN
Note:
1. Parameter based on characterization and simulation; it is not tested in production.
Device Timing: During Operation
23
Ordering Information – AT6002
Usable
Gates
Speed
Grade (ns)
Ordering Code
Package
Operation Range
6,000
2
AT6002-2AC
AT6002A-2AC
AT6002-2JC
AT6002-2QC
100A
144A
84J
5V Commercial
(0°C to 70°C)
132Q
AT6002-2AI
AT6002A-2AI
AT6002-2JI
AT6002-2QI
100A
144A
84J
5V Industrial
(-40°C to 85°C)
132Q
6,000
4
AT6002-4AC
AT6002A-4AC
AT6002-4JC
AT6002-4QC
100A
144A
84J
5V Commercial
(0°C to 70°C)
132Q
AT6002LV-4AC
AT6002ALV-4AC
AT6002LV-4JC
AT6002LV-4QC
100A
144A
84J
3.3V Commercial
(0°C to 70°C)
132Q
AT6002-4AI
AT6002A-4AI
AT6002-4JI
AT6002-4QI
100A
144A
84J
5V Industrial
(-40°C to 85°C)
132Q
Package Type
84-lead, Plastic J-leaded Chip Carrier (PLCC)
84J
100A
132Q
144A
208Q
240Q
100-lead, Very Thin (1.0 mm) Plastic Gull-Wing Quad Flat Package (VQFP)
132-lead, Bumpered Plastic Gull-Wing Quad Flat Package (BQFP)
144-lead, Thin (1.4 mm) Plastic Gull-Wing Quad Flat Package (TQFP)
208-lead, Plastic Gull-Wing Quad Flat Package (PQFP)
240-lead, Plastic Gull-Wing Quad Flat Package (PQFP)
AT6000(LV) Series
24
AT6000(LV) Series
Ordering Information – AT6003
Usable
Gates
Speed
Grade (ns)
Ordering Code
Package
Operation Range
9,000
2
AT6003-2AC
AT6003A-2AC
AT6003-2JC
AT6003-2QC
100A
144A
84J
5V Commercial
(0°C to 70°C)
132Q
AT6003-2AI
AT6003A-2AI
AT6003-2JI
AT6003-2QI
100A
144A
84J
Industrial
(-40°C to 85°C)
132Q
9,000
4
AT6003-4AC
AT6003A-4AC
AT6003-4JC
AT6003-4QC
100A
144A
84J
5V Commercial
(0°C to 70°C)
132Q
AT6003LV-4AC
AT6003ALV-4AC
AT6003LV-4JC
AT6003LV-4QC
100A
144A
84J
3.3V Commercial
(0°C to 70°C)
132Q
AT6003-4AI
AT6003A-4AI
AT6003-4JI
AT6003-4QI
100A
144A
84J
5V Industrial
(-40°C to 85°C)
132Q
Package Type
84-lead, Plastic J-leaded Chip Carrier (PLCC)
84J
100A
132Q
144A
208Q
240Q
100-lead, Very Thin (1.0 mm) Plastic Gull-Wing Quad Flat Package (VQFP)
132-lead, Bumpered Plastic Gull-Wing Quad Flat Package (BQFP)
144-lead, Thin (1.4 mm) Plastic Gull-Wing Quad Flat Package (TQFP)
208-lead, Plastic Gull-Wing Quad Flat Package (PQFP)
240-lead, Plastic Gull-Wing Quad Flat Package (PQFP)
25
Ordering Information – AT6005
Usable
Gates
Speed
Grade (ns)
Ordering Code
Package
Operation Range
15,000
2
AT6005-2AC
AT6005A-2AC
AT6005-2JC
AT6005-2QC
AT6005A-2QC
100A
144A
84J
5V Commercial
(0°C to 70°C)
132Q
208Q
AT6005-2AI
AT6005A-2AI
AT6005-2JI
AT6005-2QI
AT6005A-2QI
100A
144A
84J
Industrial
(-40°C to 85°C)
132Q
208Q
15,000
4
AT6005-4AC
AT6005A-4AC
AT6005-4JC
AT6005-4QC
AT6005A-4QC
100A
144A
84J
5V Commercial
(0°C to 70°C)
132Q
208Q
AT6005LV-4AC
AT6005ALV-4AC
AT6005LV-4JC
AT6005LV-4QC
AT6005ALV-4QC
100A
144A
84J
3.3V Commercial
(0°C to 70°C)
132Q
208Q
AT6005-4AI
AT6005A-4AI
AT6005-4JI
AT6005-4QI
AT6005A-4QI
100A
144A
84J
5V Commercial
(-40°C to 85°C)
132Q
208Q
Package Type
84-lead, Plastic J-leaded Chip Carrier (PLCC)
84J
100A
132Q
144A
208Q
240Q
100-lead, Very Thin (1.0 mm) Plastic Gull-Wing Quad Flat Package (VQFP)
132-lead, Bumpered Plastic Gull-Wing Quad Flat Package (BQFP)
144-lead, Thin (1.4 mm) Plastic Gull-Wing Quad Flat Package (TQFP)
208-lead, Plastic Gull-Wing Quad Flat Package (PQFP)
240-lead, Plastic Gull-Wing Quad Flat Package (PQFP)
AT6000(LV) Series
26
AT6000(LV) Series
Ordering Information – AT6010
Usable
Gates
Speed
Grade (ns)
Ordering Code
Package
Operation Range
30,000
2
AT6010-2JC
84J
5V Commercial
AT6010A-2AC
AT6010-2QC
AT6010A-2QC
AT6010H-2QC
144A
132Q
208Q
240Q
(0°C to 70°C)
AT6010-2JI
84J
Industrial
AT6010A-2AI
AT6010-2QI
AT6010A-2QI
AT6010H-2QI
144A
132Q
208Q
240Q
(-40°C to 85°C)
30,000
4
AT6010A-4AC
AT6010-4QC
AT6010-4JC
144A
132Q
84J
5V Commercial
(0°C to 70°C)
AT6010A-4QC
AT6010H-4QC
208Q
240Q
AT6010ALV-4AC
AT6010LV-4QC
AT6010LV-4JC
AT6010ALV-4QC
AT6010HLV-4QC
144A
132Q
84J
3.3V Commercial
(0°C to 70°C)
208Q
240Q
AT6010A-4AI
AT6010-4QI
AT6010-4JI
144A
132Q
84J
5V Industrial
(-40°C to 85°C)
AT6010A-4QI
AT6010H-4QI
208Q
240Q
Package Type
84-lead, Plastic J-leaded Chip Carrier (PLCC)
84J
100A
132Q
144A
208Q
240Q
100-lead, Very Thin (1.0 mm) Plastic Gull-Wing Quad Flat Package (VQFP)
132-lead, Bumpered Plastic Gull-Wing Quad Flat Package (BQFP)
144-lead, Thin (1.4 mm) Plastic Gull-Wing Quad Flat Package (TQFP)
208-lead, Plastic Gull-Wing Quad Flat Package (PQFP)
240-lead, Plastic Gull-Wing Quad Flat Package (PQFP)
27
Atmel Headquarters
Atmel Operations
Corporate Headquarters
2325 Orchard Parkway
San Jose, CA 95131
TEL (408) 441-0311
FAX (408) 487-2600
Atmel Colorado Springs
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL (719) 576-3300
FAX (719) 540-1759
Europe
Atmel Rousset
Zone Industrielle
13106 Rousset Cedex
France
Atmel U.K., Ltd.
Coliseum Business Centre
Riverside Way
Camberley, Surrey GU15 3YL
England
TEL (33) 4-4253-6000
FAX (33) 4-4253-6001
TEL (44) 1276-686-677
FAX (44) 1276-686-697
Asia
Atmel Asia, Ltd.
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimhatsui
East Kowloon
Hong Kong
TEL (852) 2721-9778
FAX (852) 2722-1369
Japan
Atmel Japan K.K.
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
Fax-on-Demand
North America:
1-(800) 292-8635
International:
1-(408) 441-0732
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
BBS
1-(408) 436-4309
© Atmel Corporation 1999.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-
ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-
erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are
not authorized for use as critical components in life support devices or systems.
®
™
Marks bearing and/or are registered trademarks and trademarks of Atmel Corporation.
Terms and product names in this document may be trademarks of others.
Printed on recycled paper.
0264F–10/99/xM
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