AT7910EKB-E_技术文档

Features

• SpaceWire Router

– Logical to Physical addressing translation

– Priority Management

– Header Deletion Capability

• Eight Bidirectional SpaceWire links

– Full duplex communication

– Data rate from 2 up to 200 Mbit/s in each direction

• Two External Interfaces

SpW-10X

SpaceWire

Router

– Dedicated Input and Output FIFOs

– 9-bit wide Interface

• Configuration Port

– Read/Write Accesses to internal registers

– Accessible from both the spacewire links (8 channels) and the external interfaces

– Remote Memory Access Protocol (RMAP) support

• Time Code Interface

AT7910E

– Master/Slave Capability

• Error/Status Interface

• Operating range

– Voltages

• 3V to 3.6V

– Temperature

• - 55°C to +125°C

• Maximum Power consumption

– All spacewire links active at 200Mbit/s : 4W -TBC

• Radiation Performance

– Total dose tested successfully up to 300 Krad (Si)

– No single event latchup below a LET of 80 MeV/mg/cm2

• ESD better than 2000V

• Quality Grades

– QML-Q or V with SMD

• Package: 196pins MQFPF

• Mass: 12grams

7796B–AERO–08/08

1. Description

The SpW-10X SpaceWire routing switch is capable of connecting many nodes, providing a

means of routing packets between the nodes connected to it. It comprises eight SpaceWire link

interfaces and a routing matrix. The routing matrix enables packets arriving at one link interface

to be transferred to and sent out of another link interface on the routing switch.

The AT7910E was designed by Austrian Aerospace (Austria) and the University of Dundee

(Scotland). It is manufactured using the SEU hardened cell library from Atmel MH1RT CMOS

0.35µm radiation hardened sea of gates technology.

For any technical question relative to the functionality of the AT7910E please contact Atmel tech-

nical support at assp-applab.hotline@nto.atmel.com.

This document must be read in conjunction with the University of Dundee “SpaceWire Router

SpW-10X User Manual” available at www.atmel.com.

The SpaceWire router comprises the following functional logic blocks:

• Eight SpaceWire bi-directional serial ports.

• Two external parallel input/output ports each comprising an input FIFO and an output FIFO.

• A non-blocking crossbar switch connecting any input port to any output port.

• An internal configuration port accessible via the crossbar switch from the external parallel

input/output port or the SpaceWire input/output ports.

• A routing table accessible via the configuration port which holds the logical address to output

port mapping.

• Control logic to control the operation of the switch, performing arbitration and group adaptive

routing.

• Control registers than can be written and read by the configuration port and which hold

control information e.g. link operating speed.

• An external time-code interface comprising tick_in, tick_out and current tick count value

• Internal status/error registers accessible via the configuration port

• External status/error signals

A block diagram of the routing switch is given in the following figure:

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AT7910E

Figure 1-1. SpaceWire Router Block Diagram

Control

Logic

Routing

Table

SpaceWire

Port 1

SpaceWire

Port 2

SpaceWire

Port 3

Status/Error

Registers

Status

Outputs

SpaceWire

Port 4

SpaceWire

Interfaces

SpaceWire

Port 5

SpaceWire

Port 6

SpaceWire

Port 7

SpaceWire

Port 8

Control

Registers

Non-blocking

Crossbar

Configuration

Port

Switch

External

Input FIFO

Input/Output

Output FIFO

External Port

External

Input/Output

Input FIFO

Time-Code

Inputs /

Outputs

Time-Code

Interface

Output FIFO

External Port

1.1

SpaceWire Ports

The SpaceWire router has eight bi-directional SpaceWire links each conformant to the

SpaceWire standard.

Each SpaceWire link is controlled by an associated link register and routing control logic. Pack-

ets received on SpaceWire links are routed by the routing control logic to the configuration port,

other SpaceWire link ports or the external FIFO ports depending on the packet address.

Packets with invalid addresses are discarded by the SpaceWire router. The SpaceWire link sta-

tus is recorded in the associated link register and error status is held by the router until cleared

by a configuration command.

1.2

External Ports

The SpaceWire router has two bi-directional parallel FIFO interfaces that can be used to connect

the router to an external host system. The external port FIFO is two data characters deep.

Each FIFO is written to or read from synchronously with the 30MHz system clock. An eight-bit

data interface and an extra control bit for end of packet markers are provided by each external

port FIFO. Packets received by the external port are routed by the routing control logic to the

configuration port, SpaceWire link ports or the other external port depending on the packet

address.

Packets with invalid addresses are discarded by the SpaceWire router.

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1.3

Configuration Port

The SpaceWire router has one configuration port which performs read and write operations to

internal router registers.

Packets are routed to the configuration port when a packet with a leading address byte equal to

zero is received. The Remote Memory Access Protocol (RMAP) is used to access the configura-

tion port.

If an invalid command packet is received then the error is flagged to an associated status regis-

ter and the packet is discarded.

1.4

Routing table

The SpaceWire router routing table is set by the router command packets to assign logical

addresses to physical destination ports on the router.

A group of destination ports can be set, in each routing table location, to enable group adaptive

routing. When a packet is received with a logical address the routing table is checked by the

routing control logic and the packet is routed to the destination port when the port is ready. Rout-

ing table locations are set to invalid at power on or at reset.

The routing table logical addresses can also be set to support high priority and header deletion.

High priority packets are routed before low priority packets and header deletion of logical

addresses can be used to support regional logical addressing.

An invalid routing address will cause the packet to be spilled by the control logic.

1.5

Routing control logic and crossbar

The routing control logic is responsible for arbitration of output ports, group adaptive routing and

the crossbar switching. Arbitration is performed when two or more source ports are requesting

to use the same destination port.

A priority based arbitration scheme with two priority levels, high and low, is used where high pri-

ority packets are routed before low priority packets. Fair arbitration is performed on packets

which have the same priority levels to ensure each packet gets equal access to the output port.

Group adaptive routing control selects one of a number of output ports for sending out the

source packet.

1.6

Time Code Processing

An internal time-code register is used in the router to allow the router to be a time-code master

or a time-code slave.

In master mode the time-code interface is used to provide a tick-in to the SpaceWire routing

causing time-codes to be propagated through the network. Two modes of time master operation

are supported, an automatic mode where a time-code is propagated on each external tick-in and

a normal mode where the time-code is propagated dependent on the external time-in signal.

In time-code slave mode a valid received time-code, one plus the value of the router time-code

register, causes a tick-out to be sent to the SpaceWire links and the external time-code inter-

face. The time-code is propagated to all time-code ports except the port on which the time-code

was received. If the time-code received is not one plus the value of the time-code register then

the time-code register is updated but the tick-out is not performed.

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AT7910E

1.7

Control/Status Registers

The control and status registers in the SpaceWire router provide the means to control the opera-

tion of the router, set the router configuration and parameters or monitor the status of the device.

The registers are accessed using RMAP command packets received by the configuration port.

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2. Pin Configuration

Table 1. Pin assignment

Name

Number

1

VDDB

CLK

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

VSSB

VSSA

81

82

SIN-7

SOUT-7

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

EXTINDATA9_6

EXTINDATA9_7

EXTINDATA9_8

EXTINFULL9

VSSB

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

EXTTIMEIN2

EXTTIMEIN3

EXTTIMEIN4

EXTTIMEIN5

EXTTIMEIN6

EXTTIMEIN7

SELEXTTIME

TIMECTRRST

EXTTICKOUT

EXTTIMEOUT0

EXTTIMEOUT1

EXTTIMEOUT2

EXTTIMEOUT3

VSSB

2

3

RST

VDDA

83

SOUT+7

4

TESTIOE

TESTE

FEEDBDIV0

VSSA

VDDB

84

VSSB

5

DOUT-3

DOUT+3

DIN+4

85

VDDB

6

86

DOUT-7

VDDB

7

87

DOUT+7

EXTINWRITE9

EXTOUTDATA10_0

EXTOUTDATA10_1

EXTOUTDATA10_2

EXTOUTDATA10_3

EXTOUTDATA10_4

EXTOUTDATA10_5

VSSB

8

VDDA

DIN-4

88

DIN+8

9

FEEDBDIV1

FEEDBDIV2

VSSB

LVDS_REF

SIN+4

89

DIN-8

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

90

SIN+8

SIN-4

91

VSSA

VDDPLL

VCOBias

LOOPFILTER

VSSPLL

VDDB

SOUT-4

SOUT+4

DOUT-4

DOUT+4

VSSA

92

VDDA

93

SIN-8

94

SOUT-8

95

SOUT+8

VDDB

96

DOUT-8

EXTOUTDATA10_6

EXTOUTDATA10_7

EXTOUTDATA10_8

EXTOUTEMPTY10

VSSA

EXTTIMEOUT4

EXTTIMEOUT5

EXTTIMEOUT6

EXTTIMEOUT7

STATMUXADDR0

STATMUXADDR1

STATMUXADDR2

STATMUXADDR3

VSSB

DIN+1

VDDA

97

DOUT+8

DIN-1

VSSB

98

VSSB

SIN+1

VDDB

99

VDDB

SIN-1

DIN+5

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

EXTOUTDATA9_0

EXTOUTDATA9_1

EXTOUTDATA9_2

EXTOUTDATA9_3

EXTOUTDATA9_4

VSSA

SOUT-1

SOUT+1

DOUT-1

DOUT+1

DIN+2

DIN-5

VDDA

SIN+5

EXTOUTREAD10

EXTINDATA10_0

EXTINDATA10_1

EXTINDATA10_2

EXTINDATA10_3

EXTINDATA10_4

EXTINDATA10_5

EXTINDATA10_6

EXTINDATA10_7

EXTINDATA10_8

EXTINFULL10

EXTINWRITE10

VSSA

SIN-5

SOUT-5

SOUT+5

DOUT-5

DOUT+5

DIN+6

VDDB

DIN-2

VDDA

STATMUXOUT0

STATMUXOUT1

STATMUXOUT2

VSSA

SIN+2

EXTOUTDATA9_5

VSSB

SIN-2

VSSB

DIN-6

VDDB

SIN+6

EXTOUTDATA9_6

EXTOUTDATA9_7

EXTOUTDATA9_8

EXTOUTEMPTY9

EXTOUTREAD9

EXTINDATA9_0

EXTINDATA9_1

EXTINDATA9_2

EXTINDATA9_3

EXTINDATA9_4

EXTINDATA9_5

VDDA

SOUT-2

SOUT+2

DOUT-2

DOUT+2

DIN+3

SIN-6

STATMUXOUT3

STATMUXOUT4

STATMUXOUT5

STATMUXOUT6

STATMUXOUT7

VSSB

VDDB

SOUT-6

SOUT+6

DOUT-6

DOUT+6

DIN+7

VDDA

DIN-3

VSSB

SIN+3

VDDB

SIN-3

EXTTICKIN

SOUT-3

SOUT+3

DIN-7

EXTTIMEIN0

SIN+7

EXTTIMEIN1

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AT7910E

3. Pin Description

Table 2. Pin description

Signal Name⁽¹⁾⁽³⁾

Type⁽²⁾

Function

Buffer type

POWER

VDDA

VDDB

3.3V Power for the device

Ground for the device

VDDPLL

VSSA

VSSB

POWER

VSSPLL

LVDSRef

VCOBias

LoopFilter

LVDS Power reference for the device

Bias for the PLL VCO (Rvco)

Internal PLL filter

System Clock - Provides the reference clock for all the AT7910E modules

except the SpaceWire interface receivers

CLK

I

CMOS3V3

RST

I

Asynchronous active low system reset

CMOS3V3

FEEDBDIV[2:0]

PLL feedback divider configuration - Set the internal PLL output clock rate

DOUT+[1:8]

DOUT-[1:8]

O

I

LVDS+ LVDS-

Differential output pair - Data part of Data-Strobe SpaceWire link 1 to 8.

Differential output pair - Strobe part of Data-Strobe SpaceWire link 1 to 8.

Differential input pair - Data part of Data-Strobe SpaceWire link 1 to 8.

Differential input pair - Strobe part of Data-Strobe SpaceWire link 1 to 8.

SOUT+[1:8]

SOUT-[1:8]

DIN+[1:8]

DIN-[1:8]

SIN+[1:8]

SIN-[1:8]

I

Output data from external port zero FIFO.

Bit eight determines the data type data, EOP or EEP

EXTOUTDATA9[8:0]

EXTINDATA9[8:0]

O

I

CMOS3V3

Input data from external port zero FIFO.

Bit eight determines the data type data, EOP or EEP

FIFO ready signal for external output port zero. When high the FIFO has

data. When low the FIFO is empty

EXTOUTEMPTY9

EXTOUTREAD9

EXTINFULL9

O

I

CMOS3V3

Asserted Low to read from the external output port zero FIFO.

FIFO ready signal for external input port zero. When high there is space in

the FIFO so it can be written to. When low the FIFO is full.

O

I

EXTINWRITE9

Asserted Low to write to the external input port zero FIFO.

Output data from external port one FIFO.

Bit eight determines the data type data, EOP or EEP

EXTOUTDATA10[8:0]

O

Input data from external port one FIFO.

Bit eight determines the data type data, EOP or EEP

EXTINDATA10[8:0]

EXTOUTEMPTY10

I

CMOS3V3

FIFO ready signal for external output port one. When high the FIFO has

data. When low the FIFO is empty

O

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Signal Name⁽¹⁾⁽³⁾

EXTOUTREAD10

Type⁽²⁾

I

Function

Buffer type

CMOS3V3

Asserted Low to read from the external output port one FIFO.

FIFO ready signal for external input port one. When high there is space in

the FIFO so it can be written to. When low the FIFO is full.

EXTINFULL10

O

I

CMOS3V3

EXTINWRITE10

Asserted Low to write to the external input port one FIFO.

The rising edge of the EXT_TICK_IN signal is used to indicate when a time-

code is to be sent

EXTTICKIN

I

CMOS3V3

EXT_TIME_IN(7:0) provides the value of the time-code to be distributed by

the router

EXTTIMEIN[7:0]

If SEL_EXT_TIME is high on the rising edge of EXT_TICK_IN the value on

EXT_TIME_IN(7:0) is loaded into the internal time-code register and

propagated by the router.

SELEXTTIME

I

CMOS3V3

TIMECTRRST

EXTTICKOUT

I

This signal causes the internal time-code counter to be reset to zero.

CMOS3V3

The falling edge of EXT_TICK_OUT is used to indicated the reception of a

time-code.

O

EXTTIMEOUT[7:0]

Received time-code value which is valid when EXT_TICK_OUT is asserted.

STATMUXADDR[3:0]

STATMUXOUT[7:0]

I

Select the error indication status signals to be output on STAT_MUX_OUT

CMOS3V3

After reset the STAT_MUX_OUT pins are inputs which define the power on

configuration status of the router.

I/O

After the power on reset configuration of the router has been read from

STAT_MUX_OUT the pins are driven as outputs by the router.

TESTEN

I

Shall be tied to ground

CMOS3V3

TESTIOEN

Notes: 1. Groups of pins represent busses where the highest number is the MSB.

2. O = Output; I = Input; I/O = Input/Output

3. XXX = active low signal

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AT7910E

4. Interfaces

The AT7910E provides a routing capability between eight SpaceWire links according to the

SpaceWire Standard ECSS-E-50-12A. In addition for use as a node interface, the AT7910E

integrates other interfaces such as:

• External ports

• Configuration port

• Time-code interface

• Control/Status interface

4.1

Spacewire ports

The SpaceWire router has eight bi-directional SpaceWire links each compliant with the

SpaceWire standard ECSS-E-50-12A.

Each SpaceWire link is controlled by an associated link register and routing control logic. Net-

work level error recovery is performed when an error is detected on the SpaceWire link as

defined in the SpaceWire standard. Packets received on SpaceWire links are routed by the

routing control logic to the configuration port, other SpaceWire link ports or the external FIFO

ports.

Packets with invalid addresses are discarded by the SpaceWire router dependent on the packet

address. The SpaceWire link status is recorded in the associated link register and error status is

held by the router until cleared by a configuration command.

4.2

External ports

The SpaceWire router has two bi-directional parallel FIFO interfaces to an external host system.

Each FIFO is written to or read from synchronously to the 30MHz system clock. An eight-bit

data interface and an extra control bit for end of packet markers are provided by each external

port FIFO.

Packets received by the external port are routed by the routing control logic to the configuration

port, SpaceWire link ports or the other external port dependent on the packet address.

Packets with invalid addresses are discarded by the SpaceWire router.

4.3

Configuration port

The SpaceWire router has one configuration port which performs read and write operations to

internal router registers. Packets are routed to the configuration port when a packet with a lead-

ing address byte of zero is received.

The SpaceWire Router supports the Remote Memory Access Protocol (RMAP) as command

packet format.

If an invalid command packet is received then the error is flagged to the associated status regis-

ter and the packet is discarded.

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4.4

Time-code interface