AT7912EKF-E [ATMEL]
Single SpaceWire link High Speed Controller; 单SpaceWire的链路高速控制器
| 型号： | AT7912EKF-E |
| 厂家： | 
ATMEL |
| 描述： | Single SpaceWire link High Speed Controller |
| 文件： | 总21页 (文件大小：340K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
Also known as SMCS116SpW
•
• Single Bidirectional SpaceWire link allowing
– Full duplex communication
– Transmit rate from 1.25 up to 200 Mbit/s in each direction
– Supports Serial Transfer Universal Protocol (STUP)
•
•
Derived from the T7906 Single Point to Point IEEE 1355 High Speed Controller
– Known anomalies of the T7906 chip corrected
Host interface
Single
– Gives read/write accesses to the AT7912E configuration registers
– Gives read/write accesses to the SpaceWire channel
ADC/ DAC interface
SpaceWire link
High Speed
Controller
•
– Allows direct connection of an ADC with a width of up to 16 bits
– Allows direct connection of a DAC with up to 16 data lines and the required control
signals
•
•
FIFO interface
RAM interface
– 16-bit data bus and 16-bit address bus
– Four chip selects to address 4 different memory partitions
Two independent UART interfaces
24 Bidirectional General Purpose I/Os
Two 32-Bit Timers / Event Counters
SpaceWire Link Performance
AT7912E
•
•
•
•
– At 3.3V : 100Mbit/s full duplex communication
– At 5V : 200Mbit/s full duplex communication
Operating range
•
– Voltages
• 3V to 3.6V
• 4.5V to 5.5V
– Temperature
• - 55°C to +125°C
•
•
Maximum Power consumption
– At 3.6V with a 5MHz clock: 150mW
– At 5.5V with a 5MHz clock: 700mW
Radiation Performance
– Total dose tested successfully up to 50 Krad (Si)
– No single event latchup below a LET of 80 MeV/mg/cm2
ESD better than 2000V
•
•
Quality Grades
– QML-Q or V with SMD
•
•
Package: 100pins MQFPF
Mass: 3grams
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1
1. Description
The AT7912E provides an interface between a SpaceWire link according to the
SpaceWire Standard ECSS-E-50-12A and several different interfaces.
The AT7912E was designed by EADS Astrium in Germany under the name
'SMCS116SpW" for "Scalable Multi-channel Communication Subsystem for
SpaceWire". It is manufactured using the SEU hardened cell library from Atmel MG2RT
CMOS 0.5µm radiation tolerant sea of gates technology.
For any technical question relative to the functionality of the AT7912E please contact
Atmel technical support at assp-applab.hotline@nto.atmel.com.
This document should be read in conjunction with EADS Astrium 'SMCS116SpW User
Manual'. This user manual is available at www.atmel.com.
A block diagram of the AT7912E is given in figure 1.
Figure 1. AT7912E Block Diagram
The AT7912E provides one SpaceWire serial communication link with up to 200 Mbit/s
data transmit rate. It features a link disconnect detection and parity check at character
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level as well as an additional checksum generation/check at packet level. The AT7912E
supports both the standard SpaceWire link protocol (transparent mode) and the STUP
(Serial Transfer Universal Protocol) for efficient packet oriented data transfer.
In addition to the serial SpaceWire link, the AT7912E provides several different
interfaces:
• Host interface
• ADC interface
• DAC interface
• RAM interface
• FIFO interface
• General purpose I/O
• UART interfaces
• Timers / Event Counters
• JTAG (IEEE 1149.1)
2. Pin Configuration
Table 1. Pin assignment
Pin
Pin
Pin
Pin
Name
Name
IOB9
Name
DATA4
Name
Number
Number
Number
Number
1
PLLOUT
GND
VCC
VCC
LDO
LSO
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
TMR2_CLK
RxD1
2
VCC
DATA5
DATA6
DATA7
DATA8
VCC
3
GND
TMR1_EXP
TMR2_EXP
TxD1
4
IOB10
IOB11
IOB12
IOB13
IOB14
IOB15
IOB16
IOB17
IOB18
IOB19
IOB20
IOB21
IOB22
IOB23
IOB24
IOB25
IOB26
IOB27
DATA0
DATA1
DATA2
DATA3
5
6
HDATA0
HDATA1
HDATA2
HDATA3
HDATA4
HDATA5
HDATA6
VCC
7
LDI
GND
8
LSI
DATA9
DATA10
DATA11
VCC
9
GND
TCK
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
TMS
TDI
GND
TRST*
TDO
GND
VCC
IOB0
IOB1
IOB2
IOB3
IOB4
IOB5
IOB6
IOB7
IOB8
DATA12
DATA13
DATA14
DATA15
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
TMR1_CLK
GND
HDATA7
HDATNADR*
HSEL*
HWRNRD
HINTR*
RESET*
CLK
VCC_3VOLT
GND
GND
VCC
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3. Pin Description
Table 2. Pin description
5V 0.5V
max. output
current [mA]
3.3V 0.3V
max. output
current [mA]
Signal Name(1)(3) Type(2)(4)
Function
load [pF]
When low, the external host selects the AT7912E host
interface
HSEL*
I
Host interface write/read signal
if HWRnRD is high during HSEL* low, the host writes data to
the address register or to the AT7912E registers.
HWRnRD
I
if HWRnRD is low during HSEL* low, the host reads data
from the address register or the AT7912E registers.
Host interface data/address signal
if HDATnADR is high during read, the host reads/writes data
from/to the internal AT7912E (data) registers.
HDATnADR
HDATA(7:0)
I
if HDATnADR is low during read, the host
reads/writes address from/to the address register.
AT7912E data bus.
I/O/Z
3
3
1.5
1.5
50
50
HDATA(7:0) can be used as GPIO(2), if the Host interface is
disabled
HINTR*
O
I
Host interrupt request line
TMR1_CLK
Timer1 clock (max. 12.5 MHz)
Timer1 expired. Asserted for one cycle if the value of
TMR1_EXP
TMR2_CLK
TMR2_EXP
O
I
3
1.5
50
counter1 is equal to the content of register TPERIOD1(3:0).
Timer2 clock (max. 12.5 MHz)
Timer2 expired. Asserted for one cycle if the value of
counter2 is equal to the content of register TPERIOD2(3:0).
O
3
3
1.5
1.5
50
50
RxD1
TxD1
I
Receive data to UART1
Transmit data from UART1
Link Data Input
O
LDI
I
I
LSI
Link Strobe Input
LDO
O
Link Data Output
12
12
3
6
6
25
25
25
LSO
O
Link Strobe Output
DATA(15:0)
I/O/Z
Common AT7912E data bus
General purpose input/output lines
1.5
GPIO(7:0)
IOB(21:0)
I/O
I/O
3
6
1.5
3
25
25
IOB(24:22)
IOB27
Control bus.
I/O
I
3
1.5
25
The AT7912E controls the connected interface via these
lines.
IOB(26:25)
TRST*
TCK
I
I
Test Reset. Resets the test state machine
Test Clock. Provides an asynchronous clock for JTAG
boundary scan
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5V 0.5V
max. output
current [mA]
3.3V 0.3V
max. output
current [mA]
Signal Name(1)(3) Type(2)(4)
Function
load [pF]
Test Mode Select.
TMS
I
Used to control the test state machine. This input should be
left unconnected or tied to ground during normal operation
Test Data Input.
TDI
I
Provides serial data for the boundary scan logic
Test Data Output.
TDO
O/Z
3
1.5
50
Serial scan output of the boundary scan path
AT7912E Reset.
Sets the AT7912E to a known state. This input must be
asserted (low) at power-up. The minimum width of RESET
low is 2 cycles when CLK is running
RESET*
I
CLK
I
External clock input to AT7912E (max. 5 MHz)
Output of internal PLL.
PLLOUT
O
Used to connect a network of external RC filter devices.
PLL Control signal
Configure PLL for 3.3V or 5V operation
VCC = 5 Volt: connect this signal with GND
VCC = 3.3 Volt: connect this signal with VCC
VCC_3VOLT
I
VCC
GND
Power Supply
Ground
Notes: 1. Groups of pins represent busses where the highest number is the MSB.
2. O = Output; I = Input; Z = High Impedance
3. (*) = active low signal
4. O/Z = if using a configuration with two AT7912Es these signals can directly be con-
nected together (WIROR)
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3.1
Signals Organization
This section describes the signals of the AT7912E. Groups of signals represent buses
where the highest number is the MSB.
Figure 3-1. Signals Organization
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3.2
Shared I/O
Some of the functions of the AT7912E share the same I/O pins. This means that some
functions are mutually exclusive. As an example, the GPIO port shares some of its I/O
pins with the host interface. If the host interface is not used, these pins are available for
GPIO; otherwise they are used as the host address and data bus. The selection of
which functions are being used is made by programming the appropriate registers after
a chip reset.
A short overview of the signals allocation for the various functions is given in the table
below.
Table 3-1.
Shared I/Os description
Functions
RAM
FIFO
DAC/ADC
Interface
UART &
Signal
HDATA[7:0]
GPIO
I/O
Interface
I/O
Interface
I/O
I/O
Interrupts
I/O
GPIO2[7:0] I/O
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
IOB[7:0]
IOB8
GPIO0_0
GPIO0_1
GPIO0_2
GPIO0_3
GPIO0_4
GPIO0_5
GPIO0_6
GPIO0_7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
RTS1*
CTS1*
I
I
EXT_IRQ0*
EXT_IRQ1*
TxD2
I
I
O
I
RxD2
RTS2*
O
I
RTS2*
GPIO1[7:0] I/O
RAM_ADDR[7:0]
RAM_ADDR8
RAM_ADDR9
RAM_ADDR10
RAM_ADDR11
RAM_ADDR12
RAM_ADDR13
RAM_ADDR14
O
O
O
O
O
O
O
O
ADC_ADDR[7:0]
ADC_CS*
O
O
O
O
O
O
O
IOB9
ADC_R/C*
IOB10
IOB11
IOB12
IOB13
IOB14
DAC_WR*
DAC_ADDR0
DAC_ADDR1
DAC_ADDR2
FIFO_TRM_EOP_ACK
O
FIFO_RCV_PAR
FIFO_EOPL
IOB15
RAM_ADDR15
O
I/O
IOB16
IOB17
IOB18
IOB19
IOB20
IOB21
RAM_WR*
RAM_RD*
RAM_CS0*
RAM_CS1*
RAM_CS2*
RAM_CS3*
O
O
O
O
O
O
FIFO_RCVEOP
FIFO_RCVEEP
FIFO_RD*
O
O
I/O
I/O
I/O
I/O
FIFO_WR*
FIFO_EMPTY*
FIFO_FULL*
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Functions
FIFO
RAM
DAC/ADC
Interface
UART &
Signal
IOB22
IOB23
IOB24
IOB25
IOB26
GPIO
I/O
Interface
I/O
O
O
O
I
Interface
I/O
I/O
Interrupts
I/O
RAM_TEST
ADC_RDY
ADC_TRIG
I
I
RAM_TMR_RDY
RAM_RCV_RDY
RAM_BUS_REQ*
RAM_START_TRM
FIFO_TRMEOP
FIFO_TRMEEP
I
I
I
I
FIFO_RCV_EOP_ACK
FIFO_TRM_PAR
FIFO_EOPH
IOB27
RAM_START_RCV
I
I/O
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4. Interfaces
The AT7912E provides an interface between a SpaceWire link according to the
SpaceWire Standard ECSS-E-50-12A and several different interfaces:
• Host interface
• ADC/DAC interface
• RAM interface
• FIFO interface
• General purpose I/O
• UART interfaces
• Timers / Event Counters
4.1
4.2
Host Interface
Although the AT7912E is primarily designed to be remotely controlled, it can neverthe-
less be programmed and controlled by a local host if required. For that purpose the host
interface provides 8 multiplexed data and address lines.
ADC/DAC interface
The ADC interface allows connecting an ADC with a width of up to 16 bits directly to the
AT7912E. The AD conversion can be started by request via link or in a cyclic manner
triggered by the on chip timers. When the AD conversion is ready, this is recognized by
an external signal like "ready" or by an internal trigger, for example from the on chip
timer. After reading the sample from the ADC it is then sent over the link. An 8-bit
address generator is provided to allow multiplexing of analog signals. The address gen-
erator will start at a pre-programmed start address and will be incremented after each
conversion.
The DAC interface is very similar to the ADC interface. It provides up to 16 data lines
and the required control signals. The data to be sent to the DAC is received from the link
and is stored in a register until the command "start DAC" is received. After that com-
mand the register values will be put to the DAC.
4.3
RAM Interface
The RAM interface provides a 16-bit data bus and 16-bit address bus. Four chip select
lines allow addressing four different memory partitions (banks). This partitioning into dif-
ferent banks is done using 4 internal address boundary registers. These are 8 bit wide
and provide a minimum page size of 1024 words. The memory interface can be pro-
grammed to use 0 to 7 wait states.
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4.4
FIFO interface
The FIFO (8-bit or 16-bit data width) interface provides the control signals full, write,
empty and read, depending on the direction of the data flow (receive/transmit).
Data received from the FIFO interface is sent over the SpaceWire link grouped in pack-
ets. The length of a packet (in bytes) can be specified either by setting an internal
counter or by external signals. This interface can be programmed to use 0 to 7 wait
states.
The FIFO interface handles two operating modes:
• An active mode where the AT7912E FIFO controller reads and writes from/to an
external FIFO
• A passive mode where an external controller reads and writes from/to the AT7912E
internal FIFO.
4.5
GPIO Interface
The general purpose I/O (GPIO Interface) provides up to 24 bidirectional signal lines.
The direction (input or output) of each GPIO line can be set individually via register.
Data to/from the GPIO lines is written / read via the GPIO data register. The GPIO pro-
vides 8 dedicated I/O lines, the remaining 16 lines of the port are shared with the ADC
address and host data bus. These GPIO lines are available when the corresponding unit
(e.g. the host data bus) of the AT7912E is not being used (disabled).
4.6
UART interface
Two independent UARTs are included in the AT7912E as well. One UART uses dedi-
cated I/O lines whereas the second UART is sharing its pins with the GPIO port. The
transmit rate of the UARTs in bps can be programmed via a 12-bit wide register with a
maximum bit rate of about 780 kbit/s.
Each UART has a 4-byte FIFO in transmit, and a 4-byte FIFO in receive direction.
The UARTs can optionally use hardware handshake (rts/cts).
4.7
Timers / Event Counter
Two 32-bit on-chip timers are available on the AT7912E.
Each timer provides a 32-bit counter and a 32-bit reload register. The two timers can be
operated independently or cascaded.
The timers can be used to set an external signal when the timeout value is reached.
Each timer can generate periodic interrupts or only one interrupt, depending on configu-
ration. An external output, TMR_EXP, signals to other devices that the timer count has
expired. An external input, TMR_CLK, is provided which can be used as trigger source
for the timer.
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5. Operating Modes
5.1
Configuration of the AT7912E
The AT7912E provides registers and ports for configuration. Each register contains
exactly one byte (read / write), whereas a port (e.g. a FIFO interface) behaves like a
FIFO, meaning that multiple data bytes can be read or written from/to the port.
The ports of the AT7912E such as the FIFO, UART, ADC and RAM interfaces are
accessed by a read/write command to the corresponding port address. In the case of
FIFO, Host, UART and memory interfaces, a packet oriented access is also possible
(meaning transferring multiple data bytes with a single command). The read/write selec-
tion of a command is done by setting bit 7 (MSB) of the first byte to one (read) or zero
(write).
All internal registers are 8-bit wide addressable. Two simple commands, read and write,
suffice to access all registers of the AT7912E.
Configuration/Programming of the AT7912E internal registers is done via either a simple
protocol over the SpaceWire link or STUP over the SpaceWire link or directly via the
host interface.
• The simple protocol over the SpaceWire, compatible with the T7906 (SCMCS116)
link requires a command byte and, if necessary, one or more data bytes. The simple
protocol ignores following bytes, if more bytes are sent.
• The STUP over the SpaceWire link uses 4 bytes for commands. It also supports
logical addressing.
• The host interface provides a direct access to the internal registers through a 8-bit
multiplexed address/data bus. After reset, the host interface is enabled.
After a chip reset the AT7912E is configured via the internal controller. This can be
either by receiving the configuration data from the SpaceWire link or by an external con-
troller connected to the host port of the AT7912E.
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6. Test Interface
6.1
JTAG
This represents the boundary scan testing provisions specified by IEEE Standard
1149.1 of the Joint Testing Action Group (JTAG). The AT7912E test access port and on-
chip circuitry is fully compliant with the IEEE 1149.1 specification. The test access port
enables boundary scan testing of circuitry connected to the AT7912E I/O pins.
7. AT7912E differences with theT7906E
A few differences between the AT7912E and the T7906E exist in the registers, the sig-
nals and the pinout. These differences are detailed in the section 15 of the
‘SMCS116SpW User Manual”.
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8. Typical Applications
Many applications require a SpaceWire link front end, however, no controller is required
on the unit. Thanks to its communication memory interface, the AT7912E satisfies the
requirements of these applications. Due to its small package and low power consump-
tion it is an excellent alternative to FPGA based solutions.
A system using the AT7912E as a communication front-end for a microcontroller is
shown in the following figure:
Figure 8-1. Processor Interface
Additional application targets of the AT7912E are modules and units without any built-in
communication features, such as special image compression chips, application specific
programmable logic or mass memory. The AT7912E is perfectly suited to be used on
"non intelligent" modules such as A/D converter or sensor interfaces, due to its "control
by link" feature and system control facilities. In addition, its fault tolerance feature makes
the device very interesting for many critical industrial measurement and control systems.
Example applications of the AT7912E as communication and system controller on an
interface node consisting of an ADC and DAC is given in the figure below:
Figure 8-2. ADC/DAC Interface
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9. PLL Filter
The AT7912E embeds a PLL to generate its internal clock reference. The PLLOUT pin
of the PLL is the output of the AT7912E that allows connection of the external filter of the
PLL. The following figure presents the connection of the PLL filter.
Figure 9-1. PLL filter
AT7912E
Table 9-1.
PLL filter recommended components
R1
C1
C2
1,5 kΩ 5%, ¼W
22pF, 5%
1.8nF, 5%
10. Power Supply
To achieve its fast cycle time, the AT7912E is designed with high speed drivers on out-
put pins. Large peak currents may pass through a circuit board's ground and power
lines, especially when many output drivers are simultaneously charging or discharging
their load capacitances. These transient currents can cause disturbances on the power
and ground lines. To minimize these effects, the AT7912E provides separate supply
pins for its internal logic and for its external drivers.
All GND pins should have a low impedance path to ground. A ground plane is required
in AT7912E systems to reduce this impedance, minimizing noise.
The VCC pins should be bypassed to the ground plane using 8 high-frequency capaci-
tors (0.1 µF ceramic). Keep each capacitor's lead and trace length to the pins as short
as possible. This low inductive path provides the AT7912E with the peak currents
required when its output drivers switch. The capacitors' ground leads should also be
short and connect directly to the ground plane. This provides a low impedance return
path for the load capacitance of the AT7912E output drivers.
The following pins must have a capacitor: 3, 4, 16, 27, 56, 61, 88 and 100.
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11. Electrical Characteristics
11.1 Absolute Maximum Ratings
Table 11-1. Absolute Maximum Ratings
Parameter
Supply Voltage
Symbol
Value
Unit
VCC
-0.5 to +7
V
I/O Voltage
-0.5 to VCC + 0.5
-55 to +125
V
Operating Temperature
Range (Ambient)
TA
TJ
°C
Junction Temperature
TJ < TA +20
-65 to +150
°C
Storage Temperature
Range
Tstg
°C
Thermal resistance
Junction to case
RThJC
5
°C/W
Stresses above those listed may cause permanent damage to the device.
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11.2 DC Electrical Characteristics
The AT7912E can work with VCC = + 5 V 0.5 V and VCC = + 3.3V 0.3V. Although
specified for TTL outputs, all AT7912E outputs are CMOS compatible and will drive to
VCC and GND assuming no DC loads.
Table 11-2. 5V operating range DC Characteristics.
Parameter
Operating Voltage
Symbol
VCC
VIH
Min.
4.5
Max.
5.5
Unit
Conditions
V
Input HIGH Voltage
2.2
V
V
V
V
Input LOW Voltage
VIL
0.8
0.4
Output HIGH Voltage
Output LOW Voltage
Output Short circuit current
VOH
VOL
IOS
2.4
IOL = 1.5, 3, 6mA / VCC = VCC(min)
IOH = 1, 2, 4mA / VCC = VCC(min)
90(1)
180(2)
270(3)
mA
mA
mA
VOUT = VCC
VOUT = GND
Notes: 1. Applicable for HDATA[7:0], HINTR*, TMR1_EXP, TMR2_EXP, TxD1, DATA[15:0],
GPIO[7:0], IOB[24:22], IOB27 and TDO pins
2. Applicable for IOB[21:0] pins
3. Applicable for LDO and LSO pins
Table 11-3. 3.3V operating range DC Characteristics.
Parameter
Operating Voltage
Symbol
VCC
VIH
Min.
3.0
Max.
3.6
Unit
Conditions
V
Input HIGH Voltage
2.0
V
V
V
V
Input LOW Voltage
VIL
0.8
0.4
Output HIGH Voltage
Output LOW Voltage
Output Short circuit current
VOH
VOL
IOS
2.4
IOL = 3, 6, 12mA / VCC = VCC(min)
IOH = 3, 6, 12mA / VCC = VCC(min)
50(1)
100(2)
155(3
mA
mA
mA
VOUT = VCC
VOUT = GND
Notes: 1. Applicable for HDATA[7:0], HINTR*, TMR1_EXP, TMR2_EXP, TxD1, DATA[15:0],
GPIO[7:0], IOB[24:22], IOB27 and TDO pins
2. Applicable for IOB[21:0] pins
3. Applicable for LDO and LSO pins
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11.3 Power consumption
Maximum power consumption figures at Vcc = 5.5V; -55°C; CLK = 5 MHz are presented
in the following table.
Table 11-4. 5V Power Consumption
Operation Mode
Power consumption [mA]
not clocked
2
AT7912E in RESET
22
75
AT7912E in IDLE (1)
Maximum
120
1.
IDLE means clk = 5 MHz, link started and running at 10Mbit/s, no activity on the other
interfaces.
Maximum power consumption figures at Vcc = 3.6V; -55°C; CLK = 5 MHz are presented
in the following table.
Table 11-5. 3.3V Power Consumption
Operation Mode
Power consumption [mA]
not clocked
1
AT7912E in RESET
10
23
40
AT7912E in IDLE (1)
Maximum
1.
IDLE means clk = 5 MHz, link started and running at 10Mbit/s, no activity on the other
interfaces.
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11.4 AC Electrical Characteristics
The following table gives the worst case timings measured by Atmel on the 4.5V to 5.5V
operating range
Table 11-6. 5V operating range timings.
Parameter
Symbol
Min.
Max.
Unit
Propagation delay TCK Low to TDO Low
Tp1
20
ns
Propagation delay CLK High to TMR1_EXP Low
Propagation delay CLK High to LDO Low
Propagation delay CLK High to HINTR* Low
Propagation delay CLK High to IOB18 Low
Tp2
Tp3
Tp4
Tp5
23
16
25
16
ns
ns
ns
ns
The following table gives the worst case timings measured by Atmel on the 3.0V to 3.6V
operating range
Table 11-7. 3.3V operating range timings
Parameter
Symbol
Min.
Max.
Unit
Propagation delay TCK Low to TDO Low
Tp1
33
ns
Propagation delay CLK High to TMR1_EXP Low
Propagation delay CLK High to LDO Low
Propagation delay CLK High to HINTR* Low
Propagation delay CLK High to IOB18 Low
Tp2
Tp3
Tp4
Tp5
38
27
41
27
ns
ns
ns
ns
For guaranteed timings on the two operating voltage ranges, refer to the section 12 of
the ‘SMCS116SpW User Manual’
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12. Package Drawings
12.1 MQFPF100
100 pins Ceramic Quad Flat Pack (MQFPF 100)
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13. Ordering Information
Part-number
Temperature Range
Package
Quality Flow
AT7912EKF-E
25°C
MQFPF100
Engineering sample
AT7912EKF-MQ
AT7912EKF-SV
-55°C to +125°C
-55°C to +125°C
MQFPF100
MQFPF100
Mil Level B (*)
Space Level B (*)
(*) according to Atmel Quality flow document 4288, see Atmel web site.
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