AT7913E-YC-MQ [ATMEL]
Microprocessor Circuit, CMOS, CQFP352, CERAMIC, QFP-352;
| 型号： | AT7913E-YC-MQ |
| 厂家： | 
ATMEL |
| 描述： | Microprocessor Circuit, CMOS, CQFP352, CERAMIC, QFP-352 外围集成电路 |
| 文件： | 总26页 (文件大小：1108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ATMEL AT7913E
SpaceWire Remote Terminal Controller (RTC)
DATASHEET
Features
• LEON2-FT Sparc V8 Processor
•
•
•
•
•
•
•
•
•
5 stage pipeline
4K instruction caches / 4K data caches
Meiko FPU
Interrupt Controller
Uart serial links
32-bit Timers
Memory interface
General purpose IO
Debug Support Unit (DSU)
• FIFO interface
• ADC/DAC interface
•
•
24 channels
8bit/16bit wide data bus
• Two CAN interface
•
CAN interface supporting nominal and redundant bus connection
• Two Bidirectional SpaceWire links
•
•
•
RMAP support
Full duplex communication
Transmit rate from 1.25 up to 200 Mbit/s in each direction
• SpaceWire Link Performance
•
At 3.3V : 200Mbit/s full duplex communication
• JTAG Interface
• Operating range
•
Voltages
•
•
1.65V to 1.95V - core
3V to 3.6V - I/O
•
Temperature
•
- 55°C to +125°C
• Power consumption : 1W at 50MHz
• Radiation Performance
•
Tested up to a total dose of 300 Krad (Si) according to the MIL-STD883 method
1019
•
No single event latchup below a LET of 80 MeV/mg/cm2
• ESD better than 1000V
• Quality Grades
• QML-Q or V with SMD
7833G−AERO−01/12
• Package:
•
•
349 pins MCGA, MLGA
352 pins CQFP
Description
The SpaceWire Remote Terminal Controller (SpW-RTC) ASIC is a single chip embedded
system that includes a general purpose LEON2-FT SPARC V8 core with a MEIKO FP unit
(IEEE-754). This architecture provides the mixed capability to effectively perform data
handling at platform level and powerful data processing at payload level. The SpW-RTC
includes both CAN and SpaceWire interfaces which allows bridging traffic from sensor
networks onto a high data rate SpaceWire network. Its EDAC protected FIFO and memory
interfaces allows interfacing towards peripheral I/O that may perform specialised data
processing tasks.
The SpaceWire-RTC device includes an embedded microprocessor, a CAN bus controller,
ADC/DAC interfaces for analogue acquisition/conversion, standard interfaces and
resources (UARTs, timers, general purpose input output).
The SpaceWire-RTC device can be operated stand-alone or with a number of external
devices such as SRAM, PROM and FIFO memories, ADC and DAC converters. The
device can be managed locally by the on-chip processor, or remotely via its SpaceWire
link interfaces. SpaceWire-RTC device can operate as a single-chip system, with software
being uploaded to its on-chip memory via the SpaceWire link interface, forming a compact
solution for remotely controlled applications. Or it can operate in a full-size system, with
software being decompressed from local PROM and executed from multiple fast and wide
SRAM memory banks. The device provides scalability in terms of use of external devices
and operating frequency.
Figure 1.
AT7913E SpaceWre RTC Block Diagram
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Table of Contents
1. Pin Description.....................................................................................4
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
System.............................................................................................................. 4
CAN Interface.................................................................................................... 4
ADC/DAC Interface........................................................................................... 5
Memory Interface .............................................................................................. 5
FIFO Interface................................................................................................... 6
SpaceWire Interface.......................................................................................... 6
JTAG 7
Power Supply.................................................................................................... 7
2. Architecture..........................................................................................9
2.1
2.2
LEON2-FT processor........................................................................................ 9
Debug Support Unit......................................................................................... 10
2.2.1
2.2.2
Debug Support Unit .......................................................................... 10
Debug communication link................................................................ 10
2.3
LEON2-FT Peripherals.................................................................................... 10
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
Interrupt Controller............................................................................ 10
32-bit Timer....................................................................................... 10
UART Serial Links ............................................................................ 10
16-bit General Purpose Input Output................................................ 11
Memory Interface.............................................................................. 11
2.4
2.5
2.6
2.7
2.8
2.9
On-Chip Memory............................................................................................. 11
FIFO Interface................................................................................................. 11
ADC/DAC Interface......................................................................................... 11
32-bit Timers................................................................................................... 12
24-bit General Purpose Input Output .............................................................. 12
CAN Interface.................................................................................................. 12
2.10 SpaceWire Link Interface................................................................................ 12
2.11 JTAG Interface................................................................................................ 13
3. Typical Applications ...........................................................................14
3.1
3.2
3.3
AT7913E in ICU .............................................................................................. 14
AT7913E in OBC............................................................................................. 14
AT7913E on payload....................................................................................... 14
4. Package Information..........................................................................15
4.1
Packages Outline............................................................................................ 15
4.1.1
4.1.2
MCGA 349 outline ............................................................................ 15
QFP 352 outline................................................................................ 16
4.2
Pin Assignment ............................................................................................... 17
4.2.1
4.2.2
4.2.3
Power and Ground............................................................................ 17
System and Peripherals.................................................................... 18
Unconnected Pins............................................................................. 21
5. Electrical Characteristics....................................................................22
5.1
5.2
5.3
5.4
5.5
Absolute Maximum Ratings ............................................................................ 22
Operating Range............................................................................................. 22
DC characteristics........................................................................................... 23
AC characteristics ........................................................................................... 23
Timing Diagrams............................................................................................. 24
6. Ordering Information..........................................................................25
6.1
AT7913E Ordering Codes............................................................................... 25
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1.
Pin Description
1.1
System
SysClk – Input
System Clock
SysResetN - Input
System Reset
LeonErrorN - IO, open-drain, output
LEON Error - This active low output is asserted when the processor has entered error state and is halted. This happens
when traps are disabled and an synchronous (un-maskable) trap occurs.
LeonWDN - IO, open-drain, output
LEON watchdog - This active low output is asserted when the watchdog times-out.
LeonDsuEn - Input
DSU enable - The active high input enables the DSU unit. If de-asserted, the DSU trace buffer will continue to operate
but the processor will not enter debug mode.
LeonDsuTx – Output
DSU UART transmit - This active high output provides the data from the DSU communication link transmitter
LeonDsuRx - Input
DSU UART receive - This active high input provides the data to the DSU communication link receiver.
LeonDsuBre - Input
DSU break - A low-to-high transition on this active high input will generate break condition and put the processor in
debug mode
LeonDsuAct – Output
DSU active - This active high output is asserted when the processor is in debug mode and controlled by the DSU.
LeonPio[15:0] - IO
LEON Parallel Input / Output - These bi-directional signals can be used as inputs or outputs to control external devices.
Gpio[23:0] - IO
General Purpose Input / Output
TimeClk - Input
External timer clock
TimeTrig[2:1] – Output
External timer trigger - Asserted for 8 system clock periods
1.2
CAN Interface
CanTx[1:0] – Output
CAN transmit
CanRx[1:0] - Input
CAN receive
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CanEn[1:0] – Output
CAN transmit enable
1.3
ADC/DAC Interface
ADData[15:0] - IO
ADC/DAC data
ADAddr[7:0] - IO
ADC/DAC address
ADWr - Output
DAC write strobe
ADCs - Output
ADC chip select
ADRc - Output
ADC read/convert
ADRdy - Input
ADC ready
ADTrig - Input
ADC trigger
1.4
Memory Interface
MemA[22:0] – Output
Memory interface address - These active high outputs carry the address during accesses on the memory bus. When no
access is performed, the address of the last access is driven (also internal cycles).
MemD[31:0] - IO
Memory interface data - MemD[31:0] carries the data during transfers on the memory bus. The processor only drives
the bus during write cycles. During accesses to 8-bit areas, only MemD[31:24] are used.
MemCB[7:0] - IO
Memory interface checkbits MemCB[6:0] carries the EDAC checkbits, MemCB[7] takes the value of TB[7] in the error
control register. The processor only drive MemCB[7:0] during write cycles to areas programmed to be EDAC protected
MemCsN[3:0] – Output
SRAM chip select - These active low signals provide an individual output enable for each SRAM bank.
MemOeN[3:0] – Output
SRAM output enable -These active low outputs provide the chip-select signals for each SRAM bank.
MemWrN[3:0] – Output
SRAM byte write strobe - These active low outputs provide individual write strobes for each byte lane. MemWrN[0]
controls MemD[31:24], MemWrN[1] controls MemD[23:16], etc.
RomCsN[1:0] – Output
PROM chip select - These active low outputs provide the chip-select signal for the PROM area. RomCsN[0] is asserted
when the lower half of the PROM area is accessed (0 - 0x10000000), while RomCsN[1] is asserted for the upper half.
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IoCsN – Output
I/O area chip select - This active low output is the chip-select signal for the memory mapped I/O area.
IoOeN – Output
I/O area output enable - This active low output is asserted during read cycles on the memory bus.
IoRead – Output
I/O area read - This active high output is asserted during read cycles on the memory bus.
IoWrN – Output
I/O area write - This active low output provides a write strobe during write cycles on the memory bus.
IoBrdyN - Input
I/O area ready - This active low input indicates that the access to a memory mapped I/O area can be terminated on the
next rising clock edge.
MemBExcN -Input
Memory exception - This active low input is sampled simultaneously with the data during accesses on the memory bus.
If asserted, a memory error will be generated.
1.5
FIFO Interface
FifoD[15:0] - IO
FIFO data
FifoP[1:0] - IO
FIFO parity
FifoRdN - Output
FIFO read strobe
FifoWrN – Output
FIFO write strobe
FifoFullN - Input
FIFO full
FifoEmpN - Input
FIFO empty
FifoHalfN - Input
FIFO half-full, half-empty
1.6
SpaceWire Interface
SpwClkSrc - Input
SpaceWire transmitter clock source
SpwClkMult[1:0] - Input
SpaceWire clock configuration
SpwClk10Mbit[2:0] - Input
SpaceWire clock configuration
SpwClkPllCnfg[2:0] - Input
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SpaceWire clock configuration
SpwClkMuxSel - Input
SpaceWire clock configuration - configuration External clock when 1, internal PLL when 0.
SpwDIn_P[1:0] - Input, LVDS positive
SpaceWire Data input, positive
SpwDIn_N[1:0] - Input, LVDS negative
SpaceWire Data input, negative
SpwSIn_P[1:0] - Input, LVDS positive
SpaceWire Strobe input, positive
SpwSIn_N[1:0] - Input, LVDS negative
SpaceWire Strobe input, negative
SpwDOut_P[1:0] - Output, LVDS positive
SpaceWire Data output, positive
SpwDOut_N[1:0] - Output, LVDS negative
SpaceWire Data output, negative
SpwSOut_P[1:0] - Output, LVDS positive
SpaceWire Strobe output, positive
SpwSOut_N[1:0] - Output, LVDS negative
SpaceWire Strobe output, negative
LvdsRef[0:1] - Power
LVDS reference voltage for SpaceWire channels
1.7
JTAG
TAPTRST - Test Reset
Tap Reset - Resets the test state machine. Can be asynchronous with TCK. Shall be grounded for end application
TAPTCK - Test Clock
TAP clock - Used to clock serial data into boundary scan latches and control sequence of the test state machine. TCK
can be asynchronous with CLK
TAPTMS - Test Mode select
Tap Mode select - Resets the test state machine. Can be asynchronous with TCK. Shall be grounded for end
application.
TAPTDI - Test data input
TAP data input - Serial input data to the boundary scan latches. Synchronous with TCK.
TAPTDO - Test data output
Tap data output - Serial output data from the boundary scan latches. Synchronous with TCK
1.8
Power Supply
VDA – 1.8V Power Supply
VDA is the power supply input for the AT7913E Core.
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PVDDPLL – 1.8V PLL Power Supply
VDA is the power supply input for the AT7913E PLL.
VDB – 3.3V Power Supply
VDB is the power supply input for the AT7913E IOs.
VSA, VSB, PVSSPLL - Ground
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2.
Architecture
The AT7913E SpaceWire Remote Terminal Controller (RTC) is a bridge between the SpaceWire network and the CAN
bus. The AT7913E is based on a LEON2-FT SPARC v8 processor core together with a wide range of interfaces
including :
•
•
Debug Support Unit
LEON2-FT Peripherals
•
•
•
•
•
Interrupt Controller
32-bit Timer
UART Serial Links
16-bit General Purpose Input Output
Memory Interface
•
•
•
•
•
•
•
•
On-Chip Memory
FIFO Interface
ADC/DAC Interface.
32-bit Timers
24-bit General Purpose Input Output
CAN Interface
SpaceWire Link Interface
JTAG Interface
2.1
LEON2-FT processor
The SpaceWire-RTC ASIC includes the LEON2-FT Integer Unit (IU) and the MEIKO Floating Point Unit (FPU). The
LEON2-FT IU implements the SPARC integer instruction set as defined in the SPARC Architecture Manual Version 8.
The LEON2-FT IU has the following features:
•
•
•
•
•
5-stage instruction pipeline
Separate instruction and data cache interface
Support for 8 register windows
Multiplier 16x16
Radix-2 divider (non-restoring)
To allow for software compatibility with existing devices such as the AT697E from Atmel, the AT7913E SpaceWire-RTC
includes all standard LEON2-FT peripherals and the debug support unit.
The programming model of the SpaceWire-RTC device is thus compatible with the existing devices, only requiring
support for the additional functions and interfaces to be added to the existing software development tools and operating
systems.
The SpaceWire-RTC includes a LEON2-FT core with 4kbyte Instruction and Data caches. It also includes a MEIKO
FPU (the same one as included in the Atmel AT697device).
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2.2
Debug Support Unit
The AT7913E SpaceWire RTC includes a hardware debug support to aid software debugging on target hardware. The
support is provided through two modules:
•
•
a debug support unit (DSU)
a debug communication link
2.2.1 Debug Support Unit
The DSU can put the processor in debug mode, allowing read/write access to all processor registers and cache
memories. The DSU also contains a trace buffer which stores executed instructions and/or data transfers on the AMBA
AHB bus.
The debug support unit is used to control the trace buffer and the processor debug mode. The DSU is attached to the
AHB bus as slave, occupying a 2 Mbyte address space. Through this address space, any AHB master can access the
processor registers and the contents of the trace buffer.
The DSU control registers can be accessed at any time, while the processor registers and caches can only be accessed
when the processor has entered debug mode. The trace buffer can be accessed only when tracing is
disabled/completed. In debug mode, the processor pipeline is held and the processor state can be accessed by the
DSU.
2.2.2 Debug communication link
The SpaceWire-RTC device includes a debug support unit communication link that consists of a UART connected to the
AHB bus as a master. The debug communications link implements a simple read/write protocol and uses standard
asynchronous UART communications. The simple communication protocol is supported to transmit access parameters
and data.
A link command consists of a control byte, followed by a 32-bit address, followed by optional write data.
2.3
LEON2-FT Peripherals
The AT7913E SpaceWire-RTC includes all the standard LEON2-FT peripherals.
2.3.1 Interrupt Controller
The Interrupt Controller is used to priorities and propagate interrupt requests from internal or external devices to the
integer unit. 15 interrupts are handled, divided on two priority levels.
A Secondary Interrupt Controller is included to support the 32 additional interrupts used by the additional on-chip
peripherals of the AT7913E device.
2.3.2 32-bit Timer
The timer unit implements two 32-bit timers, one 32-bit watchdog and one 10-bit shared prescaler. The functionality of
the timers has not been modified with respect to existing implementations, to allow for software compatibility.
The watchdog functionality is used for overall software timeout handling and is the basis for error management.
2.3.3 UART Serial Links
Two identical UARTs are provided for serial communications. The UARTs support data frames with 8 data bits, one
optional parity bit and one stop bit. To generate the bit-rate, each UART has a programmable 12-bits clock divider.
Hardware flow-control is supported through handshake signals.
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2.3.4 16-bit General Purpose Input Output
The 16-bit general purpose input output port can be individually programmed as output or input. Two registers are
associated with the operation of the port; the combined input/output register, and direction register. When read, the
input/output register will return the current value of the port; when written, the value will be driven on the port signals.
The direction register defines the direction for each individual port.
2.3.5 Memory Interface
The SpaceWire-RTC memory interface is implemented using the LEON2-FT Memory Controller that supports the
following:
•
•
•
•
•
8-bit PROM with sequential EDAC,
8-bit SRAM with sequential EDAC
32-bit PROM/SRAM with parallel-EDAC
8, 16, 32 bit I/O without-EDAC (wait-state and/or ready handshake)
16 bit GPIO (byte-wise) when less than 32 bit memory used
2.4
On-Chip Memory
The SpaceWire-RTC device includes a fault tolerant on-chip SRAM with embedded Error Detection And Correction
(EDAC) and AMBA AHB slave interface.
One error is corrected and two errors are detected, which is done by using a (32, 7) BCH code. Some of the features
available are single error counter, diagnostic reads and writes and auto-scrubbing (automatic correction of single errors
during reads).
The on-chip memory comprises a 32-bit wide memory bank of 64 kbytes of data.
2.5
2.6
FIFO Interface
This FIFO memory can be accessed as an on-chip memory or as an external interface of the chip via the Memory
Interface.
The FIFO interface supports transmission and reception of blocks of data by use of circular buffers located in memory
external to the core. Separate transmit and receive buffers are assumed. Reception and transmission of data can be
ongoing simultaneously.
ADC/DAC Interface
The SpaceWire-RTC includes a combined analogue-to-digital converter (ADC) and digital-to-analogue converter (DAC)
interface.
The ADC/DAC interface provides a combined signal interface to parallel ADC and DAC devices. The two interfaces are
merged both at the pin/pad level as well as at the interface towards the AMBA bus. The interface supports
simultaneously one ADC device and one DAC device in parallel. Address and data signals unused by the ADC and the
DAC can be use for general purpose input output, providing 0, 8, 16 or 24 channels.
The ADC interface supports 8 and 16 bit data widths. It provides chip select, read/convert and ready signals. The timing
is programmable. It also provides an 8-bit address output. The ADC conversion can be initiated either via the AMBA
interface or by internal or external triggers. An interrupt is generated when a conversion is completed.
The DAC interface supports 8 and 16 bit data widths. It provides a write strobe signal. The timing is programmable. It
also provides an 8-bit address output.
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2.7
2.8
32-bit Timers
The SpaceWire-RTC includes a General Purpose Timer Unit that implements one prescaler and two 32-bit
decrementing timers.
24-bit General Purpose Input Output
The SpaceWire-RTC includes a 24-bit General Purpose Input Output core. The AMBA APB bus is used for control and
status handling.
The core provides 24 channels. Each channel is individually programmed as input or output. Additionally, 8 of the
channels are also programmable as pulse command outputs. The default reset configuration for each channel is as
input. The default reset value each channel is logical zero.
The pulse command outputs have a common 20-bit counter for establishing the pulse command length. The pulse
command length defines the logical one (active) part of the pulse. It is possible to select which of the channels shall
generate a pulse command. The pulse command outputs are generated simultaneously in phase with each other, and
with the same length (or duration). It is not possible to generate pulse commands out of phase with each other.
2.9
CAN Interface
The SpaceWire-RTC includes a CAN controller. The CAN protocol is based on the ESA HurriCANe CAN Controller
VHDL core.
The controller uses the AMBA APB bus for configuration, control and status handling. The AMBA AHB bus is used for
retrieving and storing CAN messages in memory external to the CAN controller. This memory can be located on-chip or
external to the chip.
The CAN controller supports transmission and reception of sets of messages by use of circular buffers located in
memory external to the core. Separate transmit and receive buffers are assumed. Reception and transmission of sets of
messages can be ongoing simultaneously.
2.10 SpaceWire Link Interface
The SpaceWire (SPW2) Module is used for transmitting and receiving data over a SpaceWire link. It provides support
for transmitting any type of protocol or data structure using SpaceWire packets.
It provides hardware support for receiving two types of SpaceWire Transfer Protocols, and can relay packets of other
protocols to software. The SpaceWire Virtual Channel Transfer Protocol (VCTP) implements multiple virtual channels
(only one implemented in SpaceWire-RTC) on a single SpaceWire link. The Remote Memory Access Protocol (RMAP)
implements remote memory access to resources in the node via the SpaceWire link.
Data received over the link by the SpaceWire CODEC are temporarily stored in an RxFIFO. Data are then stored to
memory by the SpaceWire Module via direct memoryaccess. Multiple Virtual Receive Channels (RxVC) can be used,
each with its private memory area to which data are written. In SpaceWire-RTC one channel (RxVC(1)) is used for
storing VCTP packets, and one channel (RxVC(0)) is used for storing RMAP responses, RMAP commands not
supported by hardware and packets of other types of Transfer Protocols.
All RxVC share the same link. The SpaceWire Module implements hardware support for the RMAP. RMAP is used for
remotely accessing resources on the local AMBA bus. The RMAP implementation can receive commands and generate
responses, utilizing the aforementioned RxFIFO and the TxFIFO.
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Data to be sent are read by the SpaceWire Module from memory via direct memory access. Data are then temporarily
stored in a TxFIFO when forwarded to the SpaceWire CODEC for transmission over the link. Multiple Virtual Transmit
Channels (TxVC) can be used, each with its private send list stored in memory from which data are read. In SpaceWire-
RTC one channel (TxVC(0)) is used for automatic RMAP responses, and another channel (TxVC(1)) is used for
transmissions set up by the user. All TxVC share the same link. RMAP responses have priority over transmissions set
up by the user. The arbitration is performed for each packet sent.
2.11 JTAG Interface
The JTAG interface (compliant with IEEE-Std-1149.1) is used for the purpose of boundary scan testing during
manufacture and test of printed circuit boards hosting the ASIC.
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3.
Typical Applications
The capabilities of the SpaceWire-RTC device are not limited to support the CAN bus in the instrument controller unit
(ICU), but also allows it to be used in an on-board computer (OBC).
The AT7913E SpaceWire RTC is perfectly suited for application requiring cost optimizations as it can be used in both
payload and avionics.
3.1
3.2
3.3
AT7913E in ICU
The SpaceWire-RTC device can be integrated in the instrument controller Unit (ICU) that acts as the payload data
processor and mainly receives payload data from instruments and produces processed data to be down linked. The
main data communication is performed via the SpaceWire network. The ICU is however controlled and monitored via
the CAN network from the On-Board Computer (OBC).
AT7913E in OBC
The CAN controller in the SpaceWire-RTC device acts as a remote terminal that is being managed by the OBC.
Alternatively, the SpaceWire-RTC device can be integrated in the On-Board Computer (OBC). Since the OBC acts as
the network manager on the CAN network, the CAN controller carters capability such as node management and time
distribution. The OBC also communicates or manages the SpaceWire network via SpaceWire links.
AT7913E on payload
The main application of the SpaceWire-RTC device is however in instruments or individual experiments of the payload.
It provides an abundance of interfaces, each with a high degree of programmability and configurability. It is able to
acquire analogue and digital data, generated by connected peripherals and to generate discrete commands towards the
same peripherals.
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4.
Package Information
4.1
Packages Outline
4.1.1 MCGA 349 outline
Figure 4-1. Mechanical description
Package lid is connected to ground
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4.1.2 QFP 352 outline
Table 4-1. Mechanical description
Package lid is connected to ground
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4.2
Pin Assignment
4.2.1 Power and Ground
Table 4-2. Power and Ground pin assignement
Pin
Name
Pin
Name
Pin
Name
Pin Name
Packages
Packages
Packages
Packages
QFP352 MCGA349
QFP352 MCGA349
QFP352 MCGA349
QFP352 MCGA349
VDA
VDA
VDA
VDA
VDA
VDA
VDA
VDA
VDA
VDA
VDA
VDA
VDA
VDA
VDA
VDA
VDA
VDA
8
V17
V16
C18
C19
U1
VSA
7
V18
V4
VDB 16
VDB 24
VDB 31
VDB 41
VDB 63
VDB 91
VDB 118
VDB 127
VDB 134
VDB 141
VDB 150
VDB 157
VDB 165
VDB 175
VDB 200
VDB 215
VDB 223
VDB 231
VDB 239
VDB 249
VDB 256
VDB 267
VDB 288
VDB 303
VDB 349
VDB 187
VDB 324
VDB 194
G12
F10
W8
W9
U10
V11
M11
W13
T14
N13
P18
M12
A8
VSB 17
VSB 25
VSB 32
VSB 42
VSB 64
VSB 92
VSB 119
VSB 128
VSB 135
VSB 142
VSB 151
VSB 158
VSB 166
VSB 179
VSB 188
VSB 195
VSB 202
VSB 217
VSB 224
VSB 233
VSB 240
VSB 250
VSB 259
VSB 268
VSB 290
VSB 305
VSB 325
VSB 351
VSB
D12
H10
P8
82
VSA 81
VSA 95
VSA 169
VSA 183
VSA 257
VSA 271
VSA 345
VSA
96
D1
170
184
272
346
258
D19
T1
U8
R10
U11
V12
R14
U15
R18
P14
N18
H9
U2
T19
U3
U18
U19
V3
U17
V2
W17
W3
B17
A3
VSA
W16
W4
B18
A4
VSA
VSA
VSA
A17
B3
VSA
A16
B2
M13
K14
J15
J16
G15
F17
F18
G7
M16
K12
K18
J14
H16
G16
G14
B5
VSA
B4
VSA
B16
C3
C1
VSA
C2
VSA
C17
PVDDPLL 279
PVSSPLL 280
A14
F14
D17
F1
F13
H8
J8
H3
H6
D2
K6
H7
M2
J6
V5
K8
N5
VSB
T3
ATMEL AT7913E [DATASHEET]
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4.2.2 System and Peripherals
Table 4-3. System and SpaceWire
Pin Name
Packages
Pin Name
Packages
Pin Name
Packages
QFP352
MCGA349
R1
QFP352
MCGA349
A10
QFP352
MCGA349
C11
L17
SysClk
SysResetN
TapTck
83
84
SpwClk10Mbit_0
SpwClk10Mbit_1
SpwClk10Mbit_2
SpwClkMult_0
SpwClkMult_1
SpwClkMuxSel
SpwClkPllCnfg_0
SpwClkPllCnfg_1
SpwClkPllCnfg_2
SpwClkSrc
306
307
308
281
282
287
284
285
286
283
SpwDIn_N_0
SpwDIn_N_1
SpwDIn_P_0
SpwDIn_P_1
SpwDOut_N_0
SpwDOut_N_1
SpwDOut_P_0
SpwDOut_P_1
SpwSIn_N_0
SpwSIn_N_1
SpwSIn_P_0
SpwSIn_P_1
SpwSOut_N_0
SpwSOut_N_1
SpwSOut_P_0
SpwSOut_P_1
300
212
299
211
293
205
291
203
302
214
301
213
296
208
294
206
R4
E11
310
313
312
309
311
19
E10
G10
B10
C10
E9
D10
D13
H12
H11
C14
A13
B11
L18
TapTdi
TapTdo
E13
N15
B12
M18
C12
M17
A11
L19
TapTms
TapTrstN
TestMode
TestSE
40
E14
TimeClk
44
J5
K4
K3
R7
V8
N8
U7
T8
M7
N7
B13
TimeTrig_1
TimeTrig_2
LeonDsuAct
LeonDsuBre
LeonDsuEn
LeonDsuRx
LeonDsuTx
LeonErrorN
LeonWDN
45
46
LvdsRef0
LvdsRef1
298
210
D11
L16
117
116
113
115
114
85
F12
M14
A12
M19
87
ATMEL AT7913E [DATASHEET]
18
7833G−AERO−04/12
Table 4-4. Memory Interface
Pin Name
Packages
Pin Name
Packages
Pin Name
Packages
Pin Name
Packages
QFP352 MCGA349
QFP352 MCGA349
QFP352 MCGA349
QFP352 MCGA349
MemA_0
MemA_1
MemA_2
MemA_3
MemA_4
MemA_5
MemA_6
MemA_7
MemA_8
MemA_9
MemA_10
MemA_11
MemA_12
MemA_13
MemA_14
MemA_15
MemA_16
MemA_17
MemA_18
MemA_19
MemA_20
MemA_21
MemA_22
120
121
124
125
126
129
130
131
132
133
136
137
138
139
140
145
146
147
148
149
152
153
154
P9
R8
MemD_0
MemD_1
MemD_2
MemD_3
MemD_4
MemD_5
MemD_6
MemD_7
MemD_8
MemD_9
MemD_10
MemD_11
MemD_12
MemD_13
MemD_14
MemD_15
MemD_16
MemD_17
MemD_18
MemD_19
MemD_20
MemD_21
MemD_22
182
185
186
189
191
192
193
196
197
198
199
218
219
220
221
222
225
226
227
228
230
234
235
T17
R19
R16
P16
P19
T18
N16
P17
N19
P15
L12
K19
L15
K16
K17
K15
K13
J19
H17
J18
J17
K11
H15
MemD_23
MemD_24
MemD_25
MemD_26
MemD_27
MemD_28
MemD_29
MemD_30
MemD_31
236
237
238
241
242
243
247
248
251
H19
J12
H18
G17
J13
H14
F15
G18
J11
RomCsN_0
RomCsN_1
MemCsN_0
MemCsN_1
MemCsN_2
MemCsN_3
MemOeN_0
MemOeN_1
MemOeN_2
MemOeN_3
MemWrN_0
MemWrN_1
MemWrN_2
MemWrN_3
MemBExcN
IoBrdyN
155
156
172
173
180
181
164
167
168
171
159
160
161
162
276
269
275
274
273
270
N11
P12
T15
N12
T16
N14
P13
V14
U16
W15
V13
U14
T13
L11
D14
D16
C16
B14
D15
A15
N9
V9
U9
P10
M10
W10
R9
T10
R11
V10
N10
W11
U12
T11
P11
L10
R12
W12
R13
T12
U13
MemCB_0
MemCB_1
MemCB_2
MemCB_3
MemCB_4
MemCB_5
MemCB_6
MemCB_7
252
253
254
255
260
261
262
263
F19
D18
F16
E17
E19
E16
H13
G13
IoCsN
IoOeN
IoRead
IoWrN
ATMEL AT7913E [DATASHEET]
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7833G−AERO−04/12
Table 4-5. Other Peripherals
Pin
Name
Pin Name
Packages
Pin Name
Packages
Packages
Pin Name
Packages
QFP352 MCGA349
QFP352 MCGA349
QFP352 MCGA349
QFP352 MCGA349
ADAddr_0
ADAddr_1
ADAddr_2
ADAddr_3
ADAddr_4
ADAddr_5
ADAddr_6
ADAddr_7
ADCs
47
48
49
50
51
52
53
54
79
59
60
71
72
73
74
76
77
61
62
65
66
67
68
69
70
80
57
58
78
K5
L5
FifoD_0
FifoD_1
FifoD_10
FifoD_11
FifoD_12
FifoD_13
FifoD_14
FifoD_15
FifoD_2
FifoD_3
FifoD_4
FifoD_5
FifoD_6
FifoD_7
FifoD_8
FifoD_9
FifoEmpN
FifoFullN
FifoHalfN
FifoP_0
FifoP_1
FifoRdN
FifoWrN
18
20
33
36
37
38
39
43
21
22
23
26
27
28
29
30
6
G4
G2
H5
J7
Gpio_0
Gpio_1
Gpio_2
Gpio_3
Gpio_4
Gpio_5
Gpio_6
Gpio_7
Gpio_8
Gpio_9
Gpio_10
Gpio_11
Gpio_12
Gpio_13
Gpio_14
Gpio_15
Gpio_16
Gpio_17
Gpio_18
Gpio_19
Gpio_20
Gpio_21
Gpio_22
Gpio_23
314
317
318
319
320
322
323
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
A9
B9
C9
D9
F9
J10
E8
B8
E7
D8
C7
G9
F8
A7
E6
B7
C6
D7
J9
LeonPio_0
LeonPio_1
LeonPio_2
LeonPio_3
LeonPio_4
LeonPio_5
LeonPio_6
LeonPio_7
LeonPio_8
LeonPio_9
LeonPio_10
LeonPio_11
LeonPio_12
LeonPio_13
LeonPio_14
LeonPio_15
93
94
P7
T4
K2
K7
L1
97
W5
T5
98
J2
99
V6
U4
T6
M3
L2
J3
100
101
104
105
106
107
108
109
110
111
112
J1
L3
K1
F3
G1
F5
H4
G3
H2
G5
H1
D3
G6
E1
F6
F4
F2
E4
W6
P6
T7
P2
K9
M5
N2
P3
N4
L9
ADData_0
ADData_1
ADData_10
ADData_11
ADData_12
ADData_13
ADData_14
ADData_15
ADData_2
ADData_3
ADData_4
ADData_5
ADData_6
ADData_7
ADData_8
ADData_9
ADRc
M8
V7
U6
W7
R6
M9
T2
P4
M1
L8
5
CanEn_0
CanEn_1
CanRx_0
CanRx_1
CanTx_0
CanTx_1
3
E2
D4
D5
G8
C4
A5
9
4
M4
N3
L7
12
13
11
10
A6
F7
D6
C5
B6
347
348
343
344
M6
N1
P5
N6
L4
ADRdy
ADTrig
L6
ADWr
R3
ATMEL AT7913E [DATASHEET]
20
7833G−AERO−04/12
4.2.3
Unconnected Pins
Table 4-6. Unconnected Pins
Pin
Name
Pin Name Packages
QFP352 MCGA349
Pin Name Packages
QFP352 MCGA349
Packages
Pin Name
Packages
QFP352 MCGA349
QFP352 MCGA349
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
B15
C8
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
102
103
143
144
163
174
176
177
178
190
201
204
207
K10
L13
L14
M15
P1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
209
216
229
232
244
245
246
264
265
266
277
278
289
W14
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
292
295
297
304
315
316
321
350
352
122
123
2
14
15
34
35
55
56
75
86
88
89
90
C13
C15
E3
E5
N17
R2
E12
E15
E18
F11
G11
G19
J4
R5
R15
R17
T9
U5
V15
ATMEL AT7913E [DATASHEET]
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7833G−AERO−04/12
5.
Electrical Characteristics
5.1
Absolute Maximum Ratings
*Notice:
Stresses at or above those listed under
"Absolute Maximum Ratings” may cause
permanent damage to the device. This is
Table: Absolute rating ltside
Supply Voltage I/Os (VDB buffers)……............................ -0.3V to +4V
Supply Voltage Core (VDA array)..............………….........-0.3V to +2V
Storage Temperature.................................................. -65°C to +150°C
Input/ Output Voltages with respect to Ground...... ............. -0.3V to 4V
Power Dissipation ..........................................................................2W
ESD for I/O ..............................................................................> 2000V
ESD for Pll …..........................................................................> 1000V
a
stress rating only and functional
operation of the device at these or any
other conditions beyond those indicated
in the operational sections of this
specification are not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect device
reliability
5.2
Operating Range
Table 5-1. Operating Range
Operating Temperature
VDB – IO Power Supply
VDA - Core Power Supply
-55°C to +125°C
3.3V ± 0.3V
1.8V ± 0.15V
ATMEL AT7913E [DATASHEET]
22
7833G−AERO−04/12
5.3
DC characteristics
Table 5-2. DC characteristics
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
VCA
VCB
VIH
Operating Voltage
1.65
3
1.8
3.3
1.95
3.6
V
V
Input HIGH Voltage
2
V
VIL
Input LOW Voltage
0.8
1
V
IIL
Low Level Input current
Vin = GND
-1
µA
µA
µA
µA
µA
µA
µA
µA
IILPD
IILPU
IIH
Low Level Input Pull-down Current
Low Level Input Pull-up Current
High Level Input Current
Vin = GND
-5
5
Vin = GND
-110
-1
Vin = VCB (max)
Vin = VCB (max)
Vin = VCB (max)
VOUT = GND
VOUT = VCB (max)
1
IIHPU
IIHPD
IOZL
IOZH
VOH
High Level Input Pull-up Current
High Level Input Pull-down Current
Output Leakage low current
Output Leakage high current
Output HIGH Voltage
-5
5
600
-1
1
IOL = 2, 4, 8, 12, 16mA / VCC =
VCB(min)
VCC-0.4
V
VOL
Output LOW Voltage
IOH = 2, 4, 8, 12, 16mA / VCC =
VCB(min)
0.4
V
IOS
Output Short circuit current
Differential Output Delay
VOUT = VCB
23
mA
mV
mV
Vod
247
454
1375
Vos
Common mode output voltage
1125
ICCSBa
Supply current for array when not
clocked
VCA(max)
VCA(max)
3.5
52
mA
mA
ICCOPa
Operating supply current for array
5.4
AC characteristics
The following table gives the worst case timings measured by Atmel on the 3.0V to 3.6V operating range
Table 5-3. 3.3V operating range timings
Parameter
Symbol
Min.
Max.
Unit
Propagation delay, SysClk rising to MemCsN falling
Propagation delay, SysClk rising to CanTx rising
Propagation delay, SysClk rising to Gpio rising
Propagation delay, SysClk rising to FifoD rising
Propagation delay, SpwClkSrc rising to SpwDout_P falling
Propagation delay, SpwClkSrc rising to SpwDout_N_0 rising
Tp0
Tp1
Tp2
Tp3
Tp4
Tp5
18 ns
29 ns
25 ns
16 ns
14 ns
14 ns
ATMEL AT7913E [DATASHEET]
23
7833G−AERO−04/12
5.5
Timing Diagrams
Figure 5-1. Static Ram read cycle (0 waitsate)
Figure 5-2. FifoD, GPIO and Can_Tx clock delay
Figure 5-3. Clock to SpaceWire Data Out delay
ATMEL AT7913E [DATASHEET]
24
7833G−AERO−04/12
6.
Ordering Information
6.1
AT7913E Ordering Codes
Atmel Ordering Code
Package Type
MCGA349
MCGA349
MCGA349
MCGA349
LGA349
LGA349
LGA349
LGA349
Temperature Range
25°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
25°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
25°C
-55°C to +125°C
-55°C to +125°C
Quality Level
Engineering sample
QMLQ
AT7913E-2H-E
5962-10A0301QXB
5962-10A0301VXB
5962R10A0301VXB
AT7913E-2U-E
5962-10A0301QYC
5962-10A0301VYC
5962R10A0301VYC
AT7913E-YC-E
QMLV
QMLV-RHA
Engineering sample
QMLQ
QMLV
QMLV-RHA
Engineering sample
QMLQ
CQFP352
CQFP352
CQFP352
AT7913E-YC-MQ*
AT7913E-YC-SV*
QMLV
(1) Preliminary ordering code waiting for SMD reference
ATMEL AT7913E [DATASHEET]
25
7833G−AERO−04/12
Atmel Corporation
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© 2012 Atmel Corporation. All rights reserved. / Rev.: 7833G−AERO−01/12
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