AT88SC1608-09ET-00 [ATMEL]
8 x 256 x 8 Secure Memory with Authentication; 8 ×256× 8安全存储器与认证
| 型号： | AT88SC1608-09ET-00 |
| 厂家： | 
ATMEL |
| 描述： | 8 x 256 x 8 Secure Memory with Authentication |
| 文件： | 总25页 (文件大小：246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• One 128 x 8 (1K bit) Configuration Zone
• Eight 256 x 8 (16K bits) User Zones
• Low Voltage Operation: 2.7V to 5.5V
• Two-wire Serial Interface
• 16-byte Page Write Mode
• Self-timed Write Cycle (10 ms max)
• Answer-to-Reset Register
• High Security Memory Including Anti-wiretapping
– 64-bit Authentication Protocol (under exclusive patent license from ELVA)
– Authentication Attempts Counter
– Eight Sets of Two 24-bit Passwords
– Specific Passwords for Read and Write
– Sixteen Password Attempts Counters
– Selectable Access Rights by Zone
• ISO Compliant Packaging
8 x 256 x 8
Secure Memory
with
• High Reliability
Authentication
– Endurance: 100,000 Cycles
– Data Retention: 100 Years
– ESD Protection: 4,000V (min)
• Low-power CMOS
AT88SC1608
Table 1. Pin Configuration
Name
VCC
GND
SCL
Description
ISO Module Contact
Standard Package Pin
Supply Voltage
Ground
C1
C5
C3
C7
C2
8
1
6
3
7
Serial Clock Input
Serial Data Input/Output
Reset Input
SDA
RST
Card Module Contact
8-pin SOIC, PDIP, or LAP
GND VCC
VCC
NC
1
8
NC
SDA
NC
2
7
RST
SCL
NC
3
4
6
5
0971G–SMEM–04/04
Description
The AT88SC1608 provides 17,408 bits of serial EEPROM memory organized as one
configuration zone of 128 bytes and eight user zones of 256 bytes each. This device is
optimized as a “secure memory” for the smart card market, secure identification for elec-
tronic data transfer, or components in a system, without the requirement of an internal
microprocessor.
The embedded authentication protocol allows the memory and the host to authenticate
each other. When this device is used with a host which incorporates a microcontroller
(e.g., AT89C51, AT89C2051, AT90S1200), the system provides an “anti-wiretapping”
configuration. The device and the host exchange “challenges” issued from a random
generator and verify their values through a specific cryptographic function included in
each part. When both agree on the same result, the access to the memory is permitted.
Figure 1. Security Methodology
Device
Card Number
Host (Reader)
COMPUTE Challenge A
Challenge A
Verify A
COMPUTE Challenge B
Challenge B
VERIFY B
VERIFY (RPW)
DATA
Read Password (RPW)
VERIFY (WPW)
Write 0 or 1
Write Password (WPW)
DATA
2
AT88SC1608
0971G–SMEM–04/04
AT88SC1608
Memory Access
Depending on the device configuration, the host might carry out the authentication pro-
tocol and/or present different passwords for each operation, read or write. Each user
zone may be configured for free access for read and write or for password-restricted
access. To insure security between the different user zones (multiapplication card),
each zone can use a different set of passwords. A specific AAC for each password and
for the authentication provides protection against “systematic attacks.” When the mem-
ory is unlocked, the two-wire serial protocol is effective, using SDA and SCL. The
memory includes a specific register providing a 32-bit data stream conforming to the
ISO 7816-10 synchronous answer-to-reset.
Figure 2. Block Diagram
VCC
Power
Mgt.
Authentication
Unit
Random
Generator
GND
Data
Transfer
SCL
SDA
Password
Verification
ISO
Interface
EEPROM
Answer
To Reset
RST
Pin Descriptions
Supply Voltage (VCC)
Serial Clock (SCL)
The VCC input is a 2.7V-to-5.5V positive voltage, supplied by the host.
The SCL input is used to positive edge clock data into the device and negative edge
clock data out of the device.
Serial Data (SDA)
The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and
may be wire-ORed with any number of other open drain or open collector devices. An
external pull-up resistor should be connected between SDA and VCC. The value of this
resistor and the system capacitance loading the SDA bus will determine the rise time of
SDA. This rise time will determine the maximum frequency during read operations. Low
value pull-up resistors will allow higher frequency operations while drawing higher aver-
age power supply current.
Reset (RST)
When the RST input is pulsed high, the device will output the data programmed into the
32-bit answer-to-reset register. All password and authentication access will be reset.
Following a reset, device authentication and password verification sequences must be
presented to re-establish user access.
3
0971G–SMEM–04/04
Memory Mapping
Table 1. Memory Map
Zone
The first 16K bits of the memory are divided into eight user zones of 256 bytes each.
$0
$1
$2
$3
$4
$5
$6
$7
$000
256 bytes
-
User 0
-
$0F8
$000
User 1
-
-
-
-
-
-
User 6
$0F8
$000
-
256 bytes
User 7
-
$0F8
Note:
“$” = hexadecimal value
4
AT88SC1608
0971G–SMEM–04/04
AT88SC1608
The last 1K bit of the memory is a configuration zone with specific system data, access
rights, and read/write commands; it is divided into six subzones.
Table 2. Configuration Zone
Configuration
$0
$1
Answer-to-Reset
Fab Code Reserved
AR0 AR1
$2
$3
$4
$5
$6
$7
Lot History Code
$00
$08
$10
$18
$20
$28
$30
$38
$40
$48
$50
$58
$60
$68
$70
$78
Fabrication
Card Manufacturer Code
AR2
AR3
AR4
AR5
AR6
AR7
Access
Reserved for Future Use
AAC
Identification Number (Nc)
Authentication
Cryptogram (Ci)
Secret
Test
Secret Seed (Gc)
Reserved for Memory Test
PAC
PAC
PAC
PAC
PAC
PAC
PAC
PAC
Write 0
Write 1
Write 2
Write 3
Write 4
Write 5
Write 6
PAC
PAC
PAC
PAC
PAC
PAC
PAC
Read 0
Read 1
Read 2
Read 3
Read 4
Read 5
Read 6
Read 7
Passwords
Secure Code/Write 7
PAC
Note:
AAC: Authentication Attempts Counter
PAC: Password Attempts Counter
AR0−7: Access Register for User Zone 0 to 7
Fuses
FAB, CMA, and PER are nonvolatile fuses blown at the end of each card life step. Once
blown, these EEPROM fuses can not be reset.
•
•
The FAB fuse is blown by Atmel prior to shipping wafers to the card manufacturer.
The CMA fuse is blown by the card manufacturer prior to shipping cards to the
issuer.
•
The PER fuse is blown by the issuer prior to shipping cards to the end user.
The fuses are read and written in the configuration zone using the address $80.
Table 3. Fuse Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
PER
CMA
FAB
$80
5
0971G–SMEM–04/04
When the fuses are all “1”s, read and write are allowed in the entire memory. Before
blowing the FAB fuse, Atmel writes the entire memory to “1”, except the fabrication sub-
zone and the secure code.
Figure 3. Access Rights
Zone
Access
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
FAB = 0
Free
CMA = 0
Free
PER = 0
Free
Fabrication
(Except CMC)
Forbidden
Free
Forbidden
Free
Forbidden
Free
Fabrication
(Only CMC)
Secure Code
Free
Forbidden
Free
Forbidden
Free
Access
Secure Code
Free
Secure Code
Free
Forbidden
Free
Authentication
Secret
Secure Code
Secure Code
Secure Code
Free
Secure Code
Secure Code
Secure Code
Free
Forbidden
Forbidden
Forbidden
Free
Test
Free
Free
Free
Secure Code
Secure Code
Free
Secure Code
Secure Code
Free
Write PW
Write PW
Free
Passwords
PAC
Secure Code
AR
Secure Code
AR
Write PW
AR
User Zones
AR
AR
AR
Note:
CMC = Card Manufacturer Code
AR = Access Rights as defined by the access register
PW = Password
6
AT88SC1608
0971G–SMEM–04/04
AT88SC1608
Configuration Zone
•
•
•
•
Answer-to-reset: 32-bit register defined by Atmel
Lot History Code: 32-bit register defined by Atmel
Fab Code: 16-bit register defined by Atmel
Card Manufacturer Code: 32-bit register defined by the card manufacturer
•
Access Registers
Eight 8-bit access registers defined by the issuer (enable if “0”). The access register for
each user zone will specify the privileges and requirements for access to that zone.
Table 4. Access Registers
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPE
RPE
ATE
PW2
PW1
PW0
MDF
PGO
•
Write Password Enable (WPE)
If enabled (WPE = “0”), the user is required to verify the write password to allow write
operations in the user zone. If disabled (WPE = “1”), all write operations are allowed
within the zone. Verification of the write password also allows the read and write pass-
words to be changed. During personalization (PER = “1”) the WPE bit is forced active
even if set to “1”. This forces the issuer to verify the write password in order to write data
to the user zone. This allows the security code (Write 7 password) to lock write functions
during transportation.
•
Read Password Enable (RPE)
If enabled (RPE = “0”), the user is required to verify either the read password or write
password to allow read operations in the user zone. Read operations initiated without a
verified password will return the status of the fuse bits ($00). Verification of the write
password will always allow read access to the zone. RPE = “0” and WPE = “1” is
allowed but is not recommended.
•
Authentication Enable (ATE)
If enabled (ATE = “0”), a valid authentication sequence must be completed before
access is allowed to the user zone. If disabled (ATE = “1”), authentication is not required
for access.
•
Password Set Select (PW2, PW1, PW0)
These three bits define which of the eight password sets must be presented to allow
access to the user zone. Each access register may point to a unique password set, or
access registers for multiple zones may point to the same password set. In this case,
verification of a single password will open several zones, combining the zones into a
single larger zone.
•
Modify Forbidden (MDF)
If enabled (MDF = “0”), no write access is allowed in the zone at any time.
Program Only (PGO)
•
If enabled (PGO = “0”), data within the zone may be changed from “1” to “0” but never
from “0” to “1”.
Identification Number
(Nc)
An identification number with up to 56 bits is defined by the issuer and should be unique
for each card.
7
0971G–SMEM–04/04
Cryptogram (Ci)
Secret Seed (Gc)
The 64-bit cryptogram is generated by the internal random generator and modified after
each successful verification of the cryptogram by the chip, on host request. The initial
value, defined by the issuer, is diversified as a function of the identification number.
The 64-bit secret seed, defined by the issuer, is diversified as a function of the identifica-
tion number.
Memory Test Zone
Password Sets
The memory test zone is a 64-bit free access zone for memory test.
The password sets are eight sets of two 24-bit passwords for read and write operations,
defined by the issuer. The write password allows the user to modify the read and write
passwords of the same set. By default, the eighth set of passwords (Write 7/Read 7) is
active for all user zones.
•
Secure Code
A 24-bit password, defined by Atmel, that is different for each card manufacturer. The
Write Password 7 is used as the secure code until the personalization is over (PER = 0).
•
Attempts Counters
There are 16 8-bit password attempts counters (PACs), one for each password, and one
other 8-bit attempts counter for the authentication protocol (AAC). The attempts
counters limit the number of consecutive incorrect code presentations allowed (currently
eight).
User Zones
These zones are dedicated to user data. The access rights of each zone are program-
mable separately via the access registers. If several zones share the same password
set, the set will be entered only once (after the part is powered up). Therefore, several
zones can be combined into one larger zone. The user zone address should be
changed each time a new zone is being reached.
Security Operations
Password Verification
Compare the operation password presented with the stored one and write a new bit in
the corresponding attempts counter for each wrong attempt. A valid attempt before the
limit erases the attempts counter, and allows the operation to be carried out as long as
the chip is powered.
Only one password is active at a time. When a new password is presented, access priv-
ileges defined by the previous password become invalid.
If the trials limit has been reached (i.e., the 8 bits of the attempts counter have been writ-
ten), the password verification process will not be taken into account.
Authentication Protocol
The access to a user zone may be protected by an authentication protocol in addition to
password-dependent rights.
The authentication success is memorized and active as long as the chip is powered,
unless a new authentication is initialized or RST becomes active. If the new authentica-
tion request is not validated, the card has lost its previous authentication and it should
be presented again. Only the last request is memorized.
The authentication verification protocol requires the host to perform an Initialize Authen-
tication command, followed by a Verify Authentication command.
8
AT88SC1608
0971G–SMEM–04/04
AT88SC1608
The password and authentication may be presented at any time and in any order. If the
trials limit has been reached, i.e., the 8 bits of the attempts counter have been written,
the password verification or authentication process will not be taken into account.
Command Definitions and Protocols
The communications protocol is based on the popular two-wire serial interface. Note
that the most significant bit is transmitted first.
Table 5. Device Commands
Command
Description
Code HEX
Chip Select
Instruction
b7
1
b6
0
b5
1
b4
1
b3
0
b2
0
b1
0
b0
0
Write User Zone
Read User Zone
$B0
$B1
$B4
$B5
$B2
$B3
$B6
$B7
1
0
1
1
0
0
0
1
Write Configuration Zone
Read Configuration Zone
Set User Zone Address
Verify Password
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
1
1
0
1
1
0
0
1
0
1
0
1
1
0
0
1
1
Initialize Authentication
Verify Authentication
1
0
1
1
0
1
1
0
1
0
1
1
0
1
1
1
Set User Zone Address
Figure 4. Set User Zone Address
S
T
A
R
S
T
O
P
Command
T
Fuses Index
A10 A9 A8
* * * * *
A
C
K
A
C
K
Note:
* = Don’t care bit
At power-on, no access to the user zones is allowed until the Set User Zone Address
command occurs. This command sets the three most significant bits of the byte
address, corresponding to the user zone address. This address stays valid until the host
sends a new one and as long as the chip is powered.
9
0971G–SMEM–04/04
Read Zone
Figure 5. Read Zone
S
T
A
R
N
A
C
K
S
T
O
P
A
C
K
Data (n+x)
T
Command
0
Byte Add (n)
Data (n)
–
–
–
A7
A0
D7
D0
D7
D0
A
C
K
A
C
K
Note:
z = 0: Read user zone
z = 1: Read configuration zone
The data byte address is internally incremented following the transmission of each data
byte. As long as the AT88SC1608 receives an acknowledge from the host, it will con-
tinue to increment the data byte address and serially clock out sequential data bytes.
During a read operation, the address will “roll over” from the last byte of the current zone
to the first byte of the same zone. If the host is not allowed to read at the specified
address, the device will transmit the data byte with all bits equal to “0”.
Write Zone
Figure 6. Write Zone
S
S
T
O
P
T
A
R
T
Data (n+x)
Command
Byte Add (n)
Data (n)
–
–
–
A7
A0
1 0 1 1 0 z 0 0
D7
D0
D7
D0
A
C
K
A
C
K
A
C
K
A
C
K
Note:
z = 0: Write user zone
z = 1: Write configuration zone
The lower four bits of the data byte address are internally incremented following the
receipt of each data byte. The higher data byte address bits are not incremented, retain-
ing the 16-byte write-page address. Each data byte within a page must only be loaded
once. Once a stop condition is issued to indicate the end of the host’s write command,
the device initiates the internally timed nonvolatile write cycle. An ACK polling sequence
can be initiated immediately. After a write command, if the host is not allowed to write to
some address locations, a nonvolatile write cycle will still be initiated. However, the
device will only modify data at the allowed addresses.
Read Fuses
Figure 7. Read Fuses
S
T
A
R
T
N S
A
T
C O
Command
Fuses Add
K
P
1 0 1 1 0 1 0 1
1 0 0 0 0 0 0 0
0 0 0 0 0 F2 F1 F0
A
C
K
A
C
K
Note:
Fx = 1: fuse is not blown
Fx = 0: fuse is blown
10
AT88SC1608
0971G–SMEM–04/04
AT88SC1608
The read fuses operation is always allowed. The device only transmits one data byte
and waits for a new command.
Write Fuses
Figure 8. Write Fuses
S
T
A
R
T
S
T
O
P
Command
Fuses Add
1 0 0 0 0 0 0 0
1 0 1 1 0 1 0 0
A
C
K
A
C
K
The write fuses operation is only allowed under secure code control and no data byte is
transmitted by the host. The fuses are blown sequentially: CMA is blown if FAB is equal
to “0”, and PER is blown if CMA is equal to “0”. If the fuses are all “0”s, the operation is
canceled and the device waits for a new command.
Once a stop condition is issued to indicate the end of the host’s write operation, the
device initiates the internal nonvolatile write cycle. An ACK polling sequence can be ini-
tiated immediately. Once blown, these fuses cannot be reset.
11
0971G–SMEM–04/04
Answer-to-reset
If RST is high during SCL clock pulse, the reset operation occurs according to the ISO
7816-10 synchronous answer-to-reset. The four bytes of the answer-to-reset register
are transmitted least significant bit (LSB) first on the 32 clock pulses provided on SCL.
Following a RST assertion, all password and authentication access privileges are reset.
The values programmed by Atmel are shown in Figure 9 below.
Figure 9. Answer-to-reset
R
E
S
E
$AA
$A0
1 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1
T
$55
$2C
0 0 1 1 0 1 0 0
0 1 0 1 0 1 0 1
–
–
–
–
D0
D7
D24
D23
D31
D8
D15 D16
Verify Password
Figure 10. Verify Password
S
T
A
R
S
T
O
P
Index
Pw(0)
–
T
Command
Pw(1)
–
Pw(2)
–
r p2 p1 p0
D23
D16
D7
D0
D15
D8
1 0 1 1 0 1 0 0
* * * *
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
1. Pw: Password, 3 bytes
2. The four bits “rppp” indicate the password to compare:
r = 0: Write password
r = 1: Read password
ppp: Password set number
(rppp = 0111 for the secure code)
Once the sequence is completed and a stop condition is issued, there is a nonvolatile
write cycle to update the associated attempts counter. In order to know whether or not
the inserted password was correct, the device requires the host to perform an ACK poll-
ing sequence with the specific device address of $B5. When the write cycle has been
completed, the ACK polling command ($B5, Read Configuration Zone) will return a valid
ACK. This command should be followed by the byte address of the respective PAC. If
the password presented is valid, the PAC will be set to $FF. If the password was not
valid, the PAC will have one additional bit written to “0”.
12
AT88SC1608
0971G–SMEM–04/04
AT88SC1608
Initialize Authentication
Figure 11. Initialize Authentication
S
T
A
R
S
T
O
Q0(0)
Q0(1)
P
T
Command
Q0(7)
D63
–
D
56
1 0 1 1 0 1 1 0 D7
–
D0 D15
–
D8
. . .
A
C
K
A
C
K
A
C
K
A
C
K
Note:
Q0: Host random number, 8 bytes
The initialize authentication command sets up the random generator with the crypto-
gram (Ci), the secret seed (Gc), and the host random number (Q0). Once the sequence
is completed and a stop condition is issued, there is a nonvolatile write cycle to write a
new bit of the 8-bit AAC to “0”. In order to complete the authentication protocol, the
device requires the host to perform an ACK polling sequence with the specific device
address of $B7, corresponding to the verify authentication command.
Verify Authentication
Figure 12. Verify Authentication
S
T
A
R
S
T
O
P
T
Q1(0)
Command
Q1(1)
Q1(7)
D
63
–
D
56
1 0 1 1 0 1 1 0
D
7
–
D
D
15
–
D
8
0
. . .
A
C
K
A
C
K
A
C
K
A
C
K
Note:
Q1: Host challenge, 8 bytes
If Q1 is equal to Ci + 1, then the device writes Ci + 2 in memory in place of Ci; this must
be preceded by the initialize authentication command. Once the sequence is completed
and a stop condition is issued, there is a nonvolatile write cycle to update the associated
attempts counter. In order to know whether or not the authentication was correct, the
device requires the host to perform an ACK polling sequence with the specific device
address of $B5 to read the AAC in the configuration zone. A valid authentication will
result in the AAC cleared to $FF. An invalid authentication attempt will initiate a nonvol-
atile write cycle, but no clear operation will be performed on the AAC.
Device Operation
Clock and Data
Transitions
The SDA pin is normally pulled high with an external device. Data on the SDA pin may
change only during SCL-low time periods (see Figure 14). Data changes during SCL-
high time periods will indicate a start or stop condition as defined below.
Start Condition
A high-to-low transition of SDA with SCL high is a start condition which must precede
any other command (see Figure 13).
13
0971G–SMEM–04/04
Stop Condition
Acknowledge
A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence,
the stop command will place the device in a standby power mode (see Figure 13).
All addresses and data are serially transmitted to and from the device in 8-bit words.
The device sends a zero to acknowledge that it has received each byte. This happens
during the ninth clock cycle. During read operations, the host must pull the SDA line low
during the ninth clock cycle to acknowledge that it has received the data byte. Failure to
transmit this ACK bit will terminate the read operation.
Standby Mode
The AT88SC1608 features a low-power standby mode that is enabled upon power-up
and after the receipt of the stop bit and the completion of any internal operations.
Acknowledge Polling
Once the internally-timed write cycle has started and the device inputs are disabled,
acknowledge polling can be initiated. This involves sending a start condition followed by
the device address representative of the operation desired. Only if the internal write
cycle has completed will the device respond with a “0”, allowing the sequence to
continue.
Figure 13. Start and Stop Definition
Note:
The SCL input should be low when the device is idle. Therefore, SCL is low before a start
condition and after a stop condition.
Figure 14. Data Validity
SDA
SCL
DATA STABLE
DATA STABLE
DATA
CHANGE
14
AT88SC1608
0971G–SMEM–04/04
AT88SC1608
Figure 15. Output Acknowledge
1
8
9
SCL
DATA IN
DATA OUT
START
ACKNOWLEDGE
Absolute Maximum Ratings
Note:
Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only; functional opera-
tion of the device at these or any other conditions
beyond those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
Operating Temperature . . . . . . . . . . . . . −55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . .−65°C to +150°C
Voltage on Any Pin with Respect
to Ground . . . . . . . . . . . . . . . . . . . . . −0.7V to VCC + 0.7V
Maximum Operating Voltage . . . . . . . . . . . . . . . . . .6.25V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . 5.0 mA
15
0971G–SMEM–04/04
DC Characteristics
Table 6. DC Characteristics
Applicable over recommended operating range from: VCC = +2.7V to 5.5V, TAC = 0°C to +70°C. (unless otherwise noted).
Symbol
Parameter
Test Condition
Min
Typ
Max
5.5
Units
V
(1)
VCC
Supply Voltage
2.7
ICC
ICC
Supply Current VCC = 5.0V
Supply Current VCC = 5.0V
Standby Current VCC = 2.7V
Standby Current VCC = 5.0V
Input Leakage Current
RST Input Leakage Current
Output Leakage Current
Input Low Level (2)
Read at 1 MHz
5.0
mA
mA
µA
µA
µA
µA
µA
V
Write at 1 MHz
5.0
(1)
ISB1
VIN = VCC or GND
VIN = VCC or GND
VIN = VCC or GND
VIN = VCC or GND
VOUT = VCC or GND
1.0
ISB2
ILI
20.0
1.0
ILI
20.0
1.0
ILO
VIL
VIH
VOL2
−0.3
VCC x 0.3
VCC + 0.5
0.4
Input High Level (2)
VCC x 0.7
V
Output Low Level VCC = 2.7V
IOL = 2.1 mA
V
Notes: 1. This parameter is preliminary; Atmel may change the specifications upon further characterization.
2. VIL min and VIH max are reference only and are not tested.
16
AT88SC1608
0971G–SMEM–04/04
AT88SC1608
Power Management
If VCC falls below 1.9V, the chip stops working until it rises above 2.7V.
AC Characteristics
Table 7. AC Characteristics(1)
5.0-volt
Symbol
fSCL
Parameter
Min
Max
Units
MHz
ns
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Clock Low to Data Out Valid
Start Hold Time
1.0
tLOW
400
400
tHIGH
tAA
ns
550
ns
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
200
200
10
ns
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time (2)
Inputs Fall Time (2)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
ns
ns
100
ns
100
30
ns
tF
ns
tSU.STO
tDH
200
20
ns
ns
tWR
10
ms
ns
tRST
Reset Width High
Reset Set-up Time
Reset Hold Time
600
50
tSU.RST
tHD.RST
tVCC-RST
ns
50
ns
Power-on Reset Time
2.0
ms
Note:
1. Applicable over recommended operating range fromTA = 0°C to +70°C, VCC = +2.7V to +5.5V, CL = 1 TTL Gate
and 100 pF (unless otherwise noted)
2. This parameter is characterized and is not 100% tested.
Pin Capacitance
Table 8. Pin Capacitance(1)
Symbol
CI/O
Test Condition
Max
8
Units
pF
Conditions
VI/O = 0V
VIN = 0V
Input/Output Capacitance (SDA)(2)
Input Capacitance (RST, SCL)(2)
CIN
6
pF
Notes: 1. Applicable over recommended operating conditionsTA = 25°C, f = 1.0 MHz, VCC = +2.7V
2. This parameter is characterized and is not 100% tested.
17
0971G–SMEM–04/04
Timing Diagrams
Figure 16. Bus Timing
Note:
SCL: Serial Clock; SDA: Serial Data I/O
Figure 17. Synchronous Answer-to-reset Timing
tRST
RST
tAA
DO
SDA
D2
D1
tSU.RST
tAA
tHD.RST
SCL
tHIGH
tLOW
18
AT88SC1608
0971G–SMEM–04/04
AT88SC1608
Figure 18. Write Cycle Timing
SCL
8th BIT
ACK
SDA
WORDn
tWR
STOP
START
CONDITION
CONDITION
Note:
The write cycle Time tWR is the time from valid stop condition of a write sequence to the end of the internal clear/write cycle.
SCL: Serial Clock
SDA: Serial Data I/O
19
0971G–SMEM–04/04
Ordering Information
Ordering Code
Package
Voltage Range
2.7V–5.5V
2.7V–5.5V
2.7V–5.5V
2.7V–5.5V
2.7V–5.5V
2.7V–5.5V
Temperature Range
AT88SC1608-09ET-00
AT88SC1608-09PT-00
AT88SC1608-10PI-00
AT88SC1608-10SI-00
AT88SC1608-10CI-00
AT88SC1608-10WI-00
M2 – E Module
M2 – P Module
8P3
Commerical (0°C–70°C)
Commerical (0°C–70°C)
Industrial (−40°C–85°C)
Industrial (−40°C–85°C)
Industrial (−40°C–85°C)
Industrial (−40°C–85°C)
8SI
8C
7 mil Wafer
Package Type(1)
M4 – E Module
M4 – P Module
8S1
Description
M4 ISO 7816 Smart Card Module
M4 ISO 7816 Smart Card Module with Atmel Logo
8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.230” Wide, Leadless Array Package (LAP)
8P3
8C
Note:
1. Formal drawings may be obtained from an Atmel sales office.
20
AT88SC1608
0971G–SMEM–04/04
AT88SC1608
Smart Card Modules
Ordering Code: 09ET-00
Ordering Code: 09PT-00
Module Size: M2
Module Size: M2
Dimension*: 12.6 x 11.4 [mm]
Dimension*: 12.6 x 11.4 [mm]
Glob Top: Square: 8.8 x 8.8 [mm]
Thickness: 0.58 [mm]
8.0 [mm] max
Glob Top: Round:
Thickness: 0.58 [mm] max
Pitch: 14.25 [mm]
Pitch: 14.25 [mm]
*Note: The module dimensions listed refer to the dimensions of the exposed metal contact area. The actual dimensions
of the module after excise or punching from the carrier tape are generally 0.4 mm greater in both directions
(i.e., a punched M2 module will yield 13.0 x 11.8 mm).
21
0971G–SMEM–04/04
Packaging Information
Ordering Code: 10SI-00
8-lead SOIC
1
3
2
H
N
Top View
e
B
A
D
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
MIN
–
MAX
1.75
0.51
0.25
5.00
4.00
NOM
NOTE
SYMBOL
A
B
C
D
E
e
–
A2
–
–
–
–
–
–
–
–
L
1.27 BSC
E
H
L
–
–
–
–
6.20
1.27
End View
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.
10/10/01
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
A
Small Outline (JEDEC SOIC)
R
22
AT88SC1608
0971G–SMEM–04/04
AT88SC1608
Ordering Code: 10PI-00
8-lead PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
–
MAX
0.210
0.195
0.022
0.070
0.045
0.014
0.400
–
NOM
–
NOTE
SYMBOL
D1
A2 A
A
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
–
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.100 BSC
0.300 BSC
0.130
0.325
0.280
b
E1
e
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
23
0971G–SMEM–04/04
Ordering Code: 10CI-00
8-lead LAP
Marked Pin1 Indentifier
E
A
D
A1
Top View
Side View
Pin1 Corner
L1
0.10 mm
TYP
8
7
1
e
COMMON DIMENSIONS
(Unit of Measure = mm)
2
3
MIN
0.94
0.30
0.36
7.90
4.90
MAX
1.14
0.38
0.46
8.10
5.10
NOM
1.04
NOTE
SYMBOL
A
6
5
A1
b
0.34
b
0.41
1
4
D
8.00
E
5.00
e1
L
e
1.27 BSC
0.60 REF
.0.67
e1
L
Bottom View
0.62
0.92
0.72
1.02
1
1
L1
0.97
Note: 1. Metal Pad Dimensions.
11/13/01
DRAWING NO.
REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
8CN1, 8-lead (8 x 5 x 1.04 mm Body), Lead Pitch 1.27 mm,
Leadless Array Package (LAP)
8CN1
A
R
24
AT88SC1608
0971G–SMEM–04/04
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
2325 Orchard Parkway
San Jose, CA 95131
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Regional Headquarters
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
Tel: 1(719) 576-3300
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
Tel: 1(719) 576-3300
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard
warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibiilty for any
errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and
does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are
granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use
as critical components in life support devices or systems.
© Atmel Corporation 2004. All rights reserved. Atmel® and combinations thereof are registered trademarks
of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others.
Printed on recycled paper.
0971G–SMEM–04/04
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明