AT89SC168 [ATMEL]
Microcontroller, 8-Bit, FLASH, 8MHz, CMOS, PDSO32, SOIC-32;
| 型号： | AT89SC168 |
| 厂家： | 
ATMEL |
| 描述： | Microcontroller, 8-Bit, FLASH, 8MHz, CMOS, PDSO32, SOIC-32 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 微控制器 光电二极管 外围集成电路 |
| 文件： | 总8页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Compatible with MCS-51™ products
• On-chip Flash Program Memory
– Endurance: 125,000 Write/Erase Cycles
• On-chip EEPROM Data Memory
– Endurance: 125,000 Write/Erase Cycles
• 512 x 8-bit RAM
• ISO 7816 I/O Port
• Random Word Generator
• Two 16-bit Timers
• Six Interrupt Sources, Two-level Interrupt Priority
• Security features
8-bit Flash
Secure
Microcontroller
– Power-down Protection
– Low-frequency Protection and High-frequency Filter
• Low-power Idle and Power-down Modes
• Bond Pads Locations Conform to ISO 7816-3
• Temperature Range: -20°C to +85°C
Description
AT89SCXXXXA
Summary
The AT89SC series is a low-power, high-performance 8-bit microcontroller family with
Flash programmable and erasable read only memory and EEPROM data memory.
The devices are manufactured using Atmel’s high-density CMOS technology and are
compatible with the industry standard 80C51 and 80C52 instruction set.
Complete datasheet
available under NDA
By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89SC
is a powerful microcontroller which provides a highly flexible and cost-effective solu-
tion to many data storage and/or data transfer applications which require a high level
of security.
The AT89SC family provides the following standard features: 16K to 24K bytes of sys-
tem programmable Flash, 8K to 16K bytes of EEPROM, 512 bytes of RAM, two 16-bit
timers, a six-vector, two-level interrupt and clock circuitry. For product references see
Table 2 on page 6.
Pin Configuration
SOIC Top View
NC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NC
NC
NC
NC
NC
NC
Ground
NC
NC
I/O
NC
NC
NC
NC
NC
NC
1
NC
2
NC
3
NC
4
NC
5
NC
6
Clock
Reset
NC
7
8
9
Vdd
NC
10
11
12
13
14
15
16
NC
NC
NC
NC
NC
NC: No connect
Rev. 1263AS–02/99
Block Diagram
Figure 1. AT89SC System Block Diagram
RAM ADDR.
REGISTER
EEPROM
VCC
RAM
FLASH
GND
PROGRAM
ADDRESS
REGISTER
B
STACK
POINTER
ACC
REGISTER
BUFFER
TMP2
TMP1
PC
INCRE-
MENTER
ALU
PROGRAM
COUNTER
PSW
RST
CLK
TIMING
AND
CONTROL
DPTR
POWER&
FREQUENCY
PROTECTION
RANDOM WORD
GENERATOR
ISO 7816
I/O PORT
INTERRUPT
TIMERS
INOUT
Overview
In addition, the devices are designed using static logic
which does not require continuous clocking. That is, the
clock frequency can be slowed or even stopped while wait-
ing for an internal event.
CPU
The CPU is compatible with the industry standard 80C51
and 80C52 instruction set.
Reduced Power Modes
Security Features
The AT89SC microcontroller provides the following security
features:
To exploit the power savings for secure systems available
in CMOS circuitry, Atmel’s microcontrollers have two soft-
ware-invoked reduced power modes.
• Power-down protection
IDLE MODE: The CPU is turned off while the RAM and
other on-chip peripherals continue operating. In this mode,
current draw is reduced to approximately 15 percent of the
current drawn when the device is fully active.
• Low-frequency protection against static analysis
• High-frequency filter against intrusion
• Shipping and initialization protected by Transport Code
• Unique serial number
POWER-DOWN MODE: All on-chip activities are sus-
pended while the on-chip RAM continues to hold its data.
• Hardware Protection: layout, bus scrambling, others
(undisclosed)
AT89SCXXXXA
2
AT89SCXXXXA
Memory Organization
The AT89SC microcontrollers have the following memory
organization, as shown in Figure 2.
Program Memory
The AT89SC Microcontroller has separate address spaces
for program memory and data memory. Each product con-
tains 16K or 24K bytes of Flash program memory. The
EEPROM can be optionally used as a program memory
extension if more space is needed.
• 16-bit addressable Flash programmable and erasable
read-only memory
• 16-bit addressable data/program memory (EEPROM)
• 16-bit addressable data memory (external on-chip RAM)
Data Memory
• 8-bit addressable data memory (internal RAM plus
SFRs)
The AT89SC can directly address up to 16K bytes of
EEPROM data memory. The MOVX instruction accesses
the EEPROM data memory. (Refer to the Instruction Set
section in this datasheet for a more detailed description of
instructions).
The logical separation of program and data memory allows
the data memory to be accessed by 8-bit addresses, which
can be more quickly stored and manipulated by an 8-bit
CPU. Nevertheless, 16-bit data memory can also be gener-
ated through the DPTR register.
The AT89SC family also features 256 bytes of internal
RAM including a number of Special Function Registers
(SFR). The lower 128 bytes of RAM can be accessed either
by direct addressing (MOV data addr) or by indirect
addressing (MOV @Ri). The upper 128 bytes of RAM can
only be accessed by indirect addressing. Figure 2 shows
the AT89SC data memory organization. In addition, 256
bytes of external on-chip RAM are accessible with the
MOVX @ DPTR instruction from address FF00H to
FFFFH.
Program memory is read-only in normal operational mode.
Both Flash memory and EEPROM memory program loca-
tions are directly addressable. The EEPROM memory pro-
gram locations follow the Flash memory space.
Figure 2. The AT89SC Memory(1)
Internal RAM (Data)
External
on-chip
RAM
FFH
FFFFH
FF00H
Figure 3. The Lower 128 Bytes of Internal RAM
Data
Upper
128
SFR
Space
80H
7FH
7FH
5FFFH**
4000H*
Data/
Program
EEPROM
Flash
Lower
128
Program
00H
2FH
BANK
BIT-ADDRESSABLE SPACE
(BIT ADDRESSES 0-7F)
SELECT
BITS IN
PSW
20H
1FH
11
Note:
1. These addresses apply to the AT89SC168A. The
addresses followed by * and ** should be scaled
according to the memory size of the device as
shown in the table below.
{
{
{
{
18H
10H
08H
0
17H
0FH
10
01
4 BANKS OF
8 REGISTERS
R0-R7
Device
*
**
RESET VALUE OF
STACK POINTER
07H
00
AT89SC168A
AT89SC1616A
AT89SC248A
4000H
4000H
6000H
5FFFH
7FFFH
7FFFH
3
The Instruction Set
Interrupt Structure
All members of the Atmel AT89SC 8-bit microcontroller
family execute the same instruction set. This instruction set
is optimized for 8-bit control applications and provides a
variety of fast addressing modes for accessing the RAM to
facilitate byte operations on small data structures. The
instruction set provides extensive support for 1-bit variables
as a separate data type, allowing direct bit manipulation in
control and logic systems that require Boolean processing.
The AT89SC core provides up to five interrupt sources: two
timer interrupts, a security interrupt, a memory interrupt,
and an external interrupt.
Each of the interrupt sources can be individually enabled or
disabled by setting or clearing the corresponding Interrupt
Enable (IE) bit in the SFR. This register also contains a glo-
bal disable bit, which can be cleared to disable all interrupts
at once, disregarding the state of each individual bit enable.
Addressing Modes
The AT89SC microcontroller instruction set includes the
following addressing modes:
Each interrupt source can also be individually programmed
to one of two priority levels by setting or clearing the corre-
sponding Interrupt Priority (IP) bit in the SFR.
• Direct Addressing: Operand is specified by an 8-bit
address field.
Random Word Generator
The random word generator provides a 32-bit random word
located in four SFRs: RDW0, RDW1, RDW2, RDW3.
These four registers operate as a 32-bit shift register with
feedback. The feedback loop gives the longest cycle (num-
ber of clock runs between two occurrences of the same
sequence) and the maximum spread between two consec-
utive generated numbers (two snapshots separated by one
clock pulse).
• Indirect Addressing: Operand is specified by an 8- or 16-
bit register.
• Register Instructions: Operand is a register (R0-R7) of
selected bank.
• Register-Specific Instructions: Instruction is specific to a
certain register and operand is implicit.
• Immediate Constants: Operand is specified by an 8- or
16-bit register field.
Reset
The active low RST pin is filtered to generate an active high
internal reset signal. Holding this RST pin low for at least
two machine cycles (12 MCLK periods) while the oscillator
is running accomplishes a CPU reset. If the clock fre-
quency reaches the maximum clock input frequency or if
the power supply is less than the minimum supply voltage,
the internal reset line is automatically driven high. It is
released once the power supply or the clock frequency has
returned to its normal operating value.
• Indexed Addressing: Access to program memory.
Instruction Type
• Data Transfers
- From/to internal RAM
- From/to external on-chip RAM (except AT89SC168)
- From/to EEPROM
- From Flash
• Arithmetic and logical Instructions
- Manipulations on bytes
Power-On Reset
• Boolean Instructions
The AT89SC microcontrollers have an internal Power-On
reset. When power is turned on, the circuit holds this signal
high for three machine cycles. The CPU reset is a logical
OR between power-on reset and the internal reset signal.
- Manipulations and test on bits
• Jump Instructions
- Unconditional jump
- Conditional jump
- Subroutine call and return
- Interrupt Return
Timers
The AT89SC features two 16-bit timer registers: Timer 0
and Timer 1. These registers are incremented every
machine cycle. Thus, the register counts machine cycles.
Since a machine cycle consists of 6 MCLK periods, the
count rate is 1/6 of the MCLK frequency.
Download Mode
The AT89SC microcontroller has a special functional mode
which allows the Flash to be written for new software down-
load. The new software is loaded through the ISO port and
written into the Flash memory. This download mode is soft-
ware controlled, so if the software in use does not contain
the download facility, no new program can be loaded.
In addition to the timer functions, Timer 0 and Timer 1 have
four operating modes: 13-bit timer, 16-bit timer, 8-bit auto-
reload, split timer.
I/O Port
Master Clock Generation
The I/O Port is supported by a single I/O port line. It is man-
aged by software which conforms to ISO 7816 standards.
An interrupt can be generated on each falling edge of the
I/O line.
The master clock of the CPU is generated from the external
ISO 7816 clock. In the rest of this document, all timing val-
ues will be given with reference to the master clock MCLK.
AT89SCXXXXA
4
AT89SCXXXXA
CPU Timing
The internal clock generator defines the sequence of states
that make up the microcontroller machine cycle.
program fetches are generated during each machine cycle,
even if the instruction being executed does not require it. If
the instruction being executed does not need more code
bytes, the CPU ignores the extra fetch, and the Program
Counter is not incremented.
Machine Cycles
A machine cycle consists of a sequence of 6 states, num-
bered S1 through S6. Each state time lasts 1 MCLK period.
Thus, a machine cycle lasts 6 MCLK periods or 1.68 µs if
the clock frequency is 3.57 MHz.
Execution of a one-cycle instruction (Figure 4, A and B)
begins during State 1 of the machine cycle, when the
opcode is latched into the Instruction register. A second
fetch occurs during S4 of the same machine cycle. Execu-
tion is complete at the end of State 6 of this machine cycle.
Each state is divided into a Phase 1 half and a Phase 2
half. Figure 4 shows the fetch/execute sequences in states
and phases for various kinds of instructions. Normally two
Figure 4. State Sequences
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
MCLK
ALE
(A) 1-byte, 1-cycle instruction, e.g., INC A
READ OPCODE
READ NEXT
OPCODE
READ NEXT OPCODE AGAIN
(DISCARD)
S1
S2
S3
S4
S5
S6
(B) 2-byte, 1-cycle instruction, e.g., ADD A, #data
READ OPCODE
READ 2ND BYTE
READ NEXT OPCODE
S1
S2
S3
S4
S4
S4
S5
S6
(C) 1-byte, 2-cycle instruction, e.g., INC DPTR
READ OPCODE
READ NEXT
OPCODE AGAIN
READ NEXT OPCODE (DISCARD)
S1
S2
S3
S5
S6
S1
S2
S3
S4
S5
S6
(D) MOVX (1-byte, 2-cycle)
NO
FETCH
READ
OPCODE
(MOVX)
READ NEXT
OPCODE
(DISCARD)
NO FETCH
READ NEXT
OPCODE
AGAIN
NO
ALE
S1
S2
S3
S5
S6
S1
S2
S3
S4
S5
S6
ADDR
DATA
Access External Memory
5
AT89SC AC/DC Characteristics
Table 1. AT89SC AC/DC Characteristics
Symbol
Parameter
Condition
Min
2.7
0.8
0.5
Typ
Max
5.5
8
Units
V
VCC
Supply voltage
VCC = 5.0V
MHz
MHz
MCLK
mA
mA
µA
FOSC
TCYC
Clock input frequency
CPU cycle time
VCC = 3.0V
4
6
6
Active mode, 5.0V/4 MHz
Active mode, 3.0V/4 MHz
2.5
100
60
40
20
Power-Down mode, 5.0V/4 MHz
Power-Down mode, 3.0V/4 MHz
Power-Down mode, 5.0V/no clock
Power-Down mode, 3.0V/no clock
ICC
Power Consumption
µA
µA
µA
Notes: 1. A 200KΩ pull-up resistor has been added to all the input ports.
2. A Schmitt trigger has been added to all the input ports to improve the noise immunity.
3. MCLK is the master clock period which is 1/Fosc for the AT89SCXXXXA products.
Table 2. The AT89SC Family
Device Name
AT89SC168(1)
AT89SC168A
AT89SC1616A
AT89SC248A
Flash
EEPROM
8K bytes
8K bytes
16K bytes
8K bytes
RAM
16K bytes
16K bytes
16K bytes
24K bytes
256 bytes
512 bytes
512 bytes
512 bytes
Notes: 1. The description of the AT89SC family of products found in this datasheet is not valid for the AT89SC168. For this particular
product, please refer to the first edition of AT89SC Microcontrollers for Smart Cards datasheet (literature number 0674A).
AT89SCXXXXA
6
AT89SCXXXXA
Package Outline
PIN 1
Table 3. Dimensions in mm
Table 4. Dimensions in Inches
Symbol
Min
Max
Symbol
Min
Max
0.12
A
2.29
3.048
0.279
A
A1
A2
B
0.090
0.004
A1
A2
B
0.102
0.011
0.356
0.10
0.508
0.318
0.014
0.004
0.435
0.020
0.0125
0.450
C
E
C
E
11.05
1.27 BSC
13.868
0.53
11.430
e
e
0.05 BSC
H
L
14.4
1.08
10°
H
L
0.546
0.021
0°
0.567
0.0425
10°
α
0°
α
D
20.14
20.75
D
0.793
0.817
7
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© Atmel Corporation 1999.
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Printed on recycled paper.
Rev. 1263AS–02/99/2.5M
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