AT90USB646_技术文档

Features

• High Performance, Low Power AVR^®8-Bit Microcontroller

• Advanced RISC Architecture

– 135 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-Chip 2-cycle Multiplier

• Non-volatile Program and Data Memories

8-bit

– 64/128K Bytes of In-System Self-Programmable Flash

• Endurance: 100,000 Write/Erase Cycles

Microcontroller

with

64/128K Bytes

of ISP Flash

and USB

– Optional Boot Code Section with Independent Lock Bits

• In-System Programming by On-chip Boot Program hardware activated after

reset

• True Read-While-Write Operation

– 2K/4K (64K/128K Flash version) Bytes EEPROM

• Endurance: 100,000 Write/Erase Cycles

– 4K/8K (64K/128K Flash version) Bytes Internal SRAM

– Up to 64K Bytes Optional External Memory Space

– Programming Lock for Software Security

Controller

• JTAG (IEEE std. 1149.1 compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• USB 2.0 Full-speed/Low-speed Device and On-The-Go Module

– Complies fully with:

AT90USB646

AT90USB647

AT90USB1286

AT90USB1287

– Universal Serial Bus Specification REV 2.0

– On-The-Go Supplement to the USB 2.0 Specification Rev 1.0

– Supports data transfer rates up to 12 Mbit/s and 1.5 Mbit/s

• USB Full-speed/Low Speed Device Module with Interrupt on Transfer Completion

– Endpoint 0 for Control Transfers : up to 64-bytes

– 6 Programmable Endpoints with IN or Out Directions and with Bulk, Interrupt or

Isochronous Transfers

Preliminary

– Configurable Endpoints size up to 256 bytes in double bank mode

– Fully independant 832 bytes USB DPRAM for endpoint memory allocation

– Suspend/Resume Interrupts

– Power-on Reset and USB Bus Reset

– 48 MHz PLL for Full-speed Bus Operation

– USB Bus Disconnection on Microcontroller Request

• USB OTG:

– Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)

for OTG dual-role devices

– Provide Status and control signals for software implementation of HNP and SRP

– Provides programmable times required for HNP and SRP

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

– Two16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode

– Real Time Counter with Separate Oscillator

– Two 8-bit PWM Channels

7593D–AVR–07/06

– Six PWM Channels with Programmable Resolution from 2 to 16 Bits

– Output Compare Modulator

– 8-channels, 10-bit ADC

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Byte Oriented 2-wire Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

– Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby

• I/O and Packages

– 48 Programmable I/O Lines

– 64-lead TQFP and 64-lead QFN

• Operating Voltages

– 2.7 - 5.5V

– 2.2 - 5.5V (Check availabilty)

• Operating temperature

– Industrial (-40°C to +85°C)

• Maximum Frequency

– 8 MHz at 2.7V - Industrial range

– 16 MHz at 4.5V - Industrial range

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AT90USB64/128

1. Pin Configurations

Figure 1-1. Pinout AT90USB64/128-TQFP

1

2

PA3 (AD3)

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

(INT.6/AIN.0) PE6

(INT.7/AIN.1/UVcon) PE7

UVcc

PA4 (AD4)

INDEX CORNER

3

PA5 (AD5)

4

D-

PA6 (AD6)

5

D+

PA7 (AD7)

6

UGnd

PE2 (ALE/HWB)

PC7 (A15/IC.3/CLK0)

PC6 (A14/OC.3A)

PC5 (A13/OC.3B)

PC4 (A12/OC.3C)

PC3 (A11/T.3)

PC2 (A10)

7

UCap

8

VBus

AVR USB

TQFP64

9

(IUID) PE3

10

11

12

13

14

15

16

(SS/PCINT0) PB0

(PCINT1/SCLK) PB1

(PDI/PCINT2/MOSI) PB2

(PDO/PCINT3/MISO) PB3

(PCINT4/OC.2A) PB4

(PCINT5/OC.1A) PB5

(PCINT6/OC.1B) PB6

PC1 (A9)

PC0 (A8)

PE1 (RD)

PE0 (WR)

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Figure 1-2. Pinout AT90USB64/128-QFN

(INT.6/AIN.0) PE6

(INT.7/AIN.1/UVcon) PE7

UVcc

PA3 (AD3)

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

PA4 (AD4)

3

PA5 (AD5)

INDEX CORNER

D-

4

PA6 (AD6)

D+

5

PA7 (AD7)

UGnd

6

PE2 (ALE/HWB)

PC7 (A15/IC.3/CLK0)

PC6 (A14/OC.3A)

PC5 (A13/OC.3B)

PC4 (A12/OC.3C)

PC3 (A11/T.3)

PC2 (A10)

UCap

7

VBus

8

AT90USB128

(64-lead QFN top view)

(IUID) PE3

9

(SS/PCINT0) PB0

(PCINT1/SCLK) PB1

(PDI/PCINT2/MOSI) PB2

(PDO/PCINT3/MISO) PB3

(PCINT4/OC.2A) PB4

(PCINT5/OC.1A) PB5

(PCINT6/OC.1B) PB6

10

11

12

13

14

15

16

PC1 (A9)

PC0 (A8)

PE1 (RD)

PE0 (WR)

Note:

The large center pad underneath the MLF packages is made of metal and internally connected to

GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center

pad is left unconnected, the package might loosen from the board.

1.1

Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of

other AVR microcontrollers manufactured on the same process technology. Min and Max values

will be available after the device is characterized.

2. Overview

The AT90USB64/128 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced

RISC architecture. By executing powerful instructions in a single clock cycle, the

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AT90USB64/128

AT90USB64/128 achieves throughputs approaching 1 MIPS per MHz allowing the system

designer to optimize power consumption versus processing speed.

2.1

Block Diagram

Figure 2-1. Block Diagram

PF7 - PF0

PA7 - PA0

PC7 - PC0

VCC

GND

PORTA DRIVERS

PORTF DRIVERS

PORTC DRIVERS

DATA REGISTER

PORTF

DATA DIR.

REG. PORTF

DATA REGISTER

PORTA

DATA DIR.

REG. PORTA

DATA REGISTER

PORTC

DATA DIR.

REG. PORTC

8-BIT DATA BUS

POR - BOD

RESET

INTERNAL

OSCILLATOR

AVCC

CALIB. OSC

ADC

AGND

AREF

OSCILLATOR

WATCHDOG

TIMER

PROGRAM

COUNTER

STACK

POINTER

JTAG TAP

TIMING AND

CONTROL

PROGRAM

FLASH

MCU CONTROL

REGISTER

SRAM

ON-CHIP DEBUG

BOUNDARY-

SCAN

INSTRUCTION

REGISTER

TIMER/

COUNTERS

GENERAL

PURPOSE

REGISTERS

X

Y

Z

PROGRAMMING

LOGIC

INSTRUCTION

DECODER

INTERRUPT

UNIT

CONTROL

LINES

ALU

EEPROM

PLL

STATUS

REGISTER

TWO-WIRE SERIAL

INTERFACE

USB

USART0

SPI

DATA REGISTER

PORTE

DATA DIR.

REG. PORTE

DATA REGISTER

PORTB

DATA DIR.

REG. PORTB

DATA REGISTER

PORTD

DATA DIR.

REG. PORTD

DATA REG. DATA DIR.

PORTG

REG. PORTG

PORTB DRIVERS

PORTD DRIVERS

PORTG DRIVERS

PORTE DRIVERS

PE7 - PE0

PB7 - PB0

PD7 - PD0

PG4 - PG0

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

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The AT90USB64/128 provides the following features: 64/128K bytes of In-System Programma-

ble Flash with Read-While-Write capabilities, 2K/4K bytes EEPROM, 4K/8K bytes SRAM, 48

general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), four

flexible Timer/Counters with compare modes and PWM, one USART, a byte oriented 2-wire

Serial Interface, a 8-channels, 10-bit ADC with optional differential input stage with programma-

ble gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std.

1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and

programming and six software selectable power saving modes. The Idle mode stops the CPU

while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue function-

ing. The Power-down mode saves the register contents but freezes the Oscillator, disabling all

other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asyn-

chronous timer continues to run, allowing the user to maintain a timer base while the rest of the

device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except

Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby

mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This

allows very fast start-up combined with low power consumption. In Extended Standby mode,

both the main Oscillator and the Asynchronous Timer continue to run.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-

chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial

interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program

running on the AVR core. The boot program can use any interface to download the application

program in the application Flash memory. Software in the Boot Flash section will continue to run

while the Application Flash section is updated, providing true Read-While-Write operation. By

combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,

the Atmel AT90USB64/128 is a powerful microcontroller that provides a highly flexible and cost

effective solution to many embedded control applications.

The AT90USB64/128 AVR is supported with a full suite of program and system development

tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emula-

tors, and evaluation kits.

2.2

Pin Descriptions

2.2.1

VCC

Digital supply voltage.

2.2.2

2.2.3

GND

Ground.

Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port A output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port A also serves the functions of various special features of the AT90USB64/128 as listed on

page 81.

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AT90USB64/128

2.2.4

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B has better driving capabilities than the other ports.

Port B also serves the functions of various special features of the AT90USB64/128 as listed on

page 82.

2.2.5

Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port C output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port C also serves the functions of special features of the AT90USB64/128 as listed on page 85.

2.2.6

Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port D also serves the functions of various special features of the AT90USB64/128 as listed on

page 86.

2.2.7

Port E (PE7..PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port E output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port E also serves the functions of various special features of the AT90USB64/128 as listed on

page 89.

2.2.8

Port F (PF7..PF0)

Port F serves as analog inputs to the A/D Converter.

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins

can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym-

metrical drive characteristics with both high sink and source capability. As inputs, Port F pins

that are externally pulled low will source current if the pull-up resistors are activated. The Port F

pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the

JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will

be activated even if a reset occurs.

Port F also serves the functions of the JTAG interface.

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2.2.9

D-

USB Full speed / Low Speed Negative Data Upstream Port. Should be connected to the USB D-

connector pin with a serial 22 Ohms resistor.

2.2.10

D+

USB Full speed / Low Speed Positive Data Upstream Port. Should be connected to the USB D+

connector pin with a serial 22 Ohms resistor.

2.2.11

2.2.12

2.2.13

UGND

UVCC

UCAP

USB Pads Ground.

USB Pads Internal Regulator Input supply voltage.

USB Pads Internal Regulator Output supply voltage. Should be connected to an external capac-

itor (1µF).

2.2.14

2.2.15

VBUS

USB VBUS monitor and OTG negociations.

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running. The minimum pulse length is given in Table 8-1 on page

60. Shorter pulses are not guaranteed to generate a reset.

2.2.16

2.2.17

2.2.18

XTAL1

XTAL2

AVCC

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting Oscillator amplifier.

AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con-

nected to V_CC, even if the ADC is not used. If the ADC is used, it should be connected to V_CC

through a low-pass filter.

2.2.19

AREF

This is the analog reference pin for the A/D Converter.

3. About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of

the device. Be aware that not all C compiler vendors include bit definitions in the header files

and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-

tation for more details.

These code examples assume that the part specific header file is included before compilation.

For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI"

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AT90USB64/128

instructions must be replaced with instructions that allow access to extended I/O. Typically

"LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".

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4. AVR CPU Core

4.1

Introduction

This section discusses the AVR core architecture in general. The main function of the CPU core

is to ensure correct program execution. The CPU must therefore be able to access memories,

perform calculations, control peripherals, and handle interrupts.

4.2

Architectural Overview

Figure 4-1. Block Diagram of the AVR Architecture

Data Bus 8-bit

Program

Counter

Status

and Control

Flash

Program

Memory

Interrupt

Unit

32 x 8

General

Purpose

Registrers

Instruction

Register

SPI

Unit

Instruction

Decoder

Watchdog

Timer

ALU

Analog

Comparator

Control Lines

I/O Module1

I/O Module 2

I/O Module n

Data

SRAM

EEPROM

I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with

separate memories and buses for program and data. Instructions in the program memory are

executed with a single level pipelining. While one instruction is being executed, the next instruc-

tion is pre-fetched from the program memory. This concept enables instructions to be executed

in every clock cycle. The program memory is In-System Reprogrammable Flash memory.

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AT90USB64/128

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single

clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-

ical ALU operation, two operands are output from the Register File, the operation is executed,

and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data

Space addressing – enabling efficient address calculations. One of the these address pointers

can also be used as an address pointer for look up tables in Flash program memory. These

added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and

a register. Single register operations can also be executed in the ALU. After an arithmetic opera-

tion, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to

directly address the whole address space. Most AVR instructions have a single 16-bit word for-

mat. Every program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and the

Application Program section. Both sections have dedicated Lock bits for write and read/write

protection. The SPM instruction that writes into the Application Flash memory section must

reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the

Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack

size is only limited by the total SRAM size and the usage of the SRAM. All user programs must

initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack

Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed

through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global

Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the

Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi-

tion. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-

ters, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data

Space locations following those of the Register File, 0x20 - 0x5F. In addition, the

AT90USB64/128 has Extended I/O space from 0x60 - 0x0FF in SRAM where only the

ST/STS/STD and LD/LDS/LDD instructions can be used.

4.3

ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose

working registers. Within a single clock cycle, arithmetic operations between general purpose

registers or between a register and an immediate are executed. The ALU operations are divided

into three main categories – arithmetic, logical, and bit-functions. Some implementations of the

architecture also provide a powerful multiplier supporting both signed/unsigned multiplication

and fractional format. See the “Instruction Set” section for a detailed description.

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4.4

Status Register

The Status Register contains information about the result of the most recently executed arith-

metic instruction. This information can be used for altering program flow in order to perform

conditional operations. Note that the Status Register is updated after all ALU operations, as

specified in the Instruction Set Reference. This will in many cases remove the need for using the

dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored

when returning from an interrupt. This must be handled by software.

The AVR Status Register – SREG – is defined as:

Bit

7

6

5

4

3

2

1

0

I

T

H

S

V

N

Z

C

SREG

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-

rupt enable control is then performed in separate control registers. If the Global Interrupt Enable

Register is cleared, none of the interrupts are enabled independent of the individual interrupt

enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by

the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by

the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-

nation for the operated bit. A bit from a register in the Register File can be copied into T by the

BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the

BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful

in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement

Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the

“Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the

“Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction

Set Description” for detailed information.

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AT90USB64/128

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set

Description” for detailed information.

4.5

General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve

the required performance and flexibility, the following input/output schemes are supported by the

Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 4-2. AVR CPU General Purpose Working Registers

7

0

Addr.

R0

0x00

0x01

0x02

R1

R2

…

R13

R14

R15

R16

R17

…

0x0D

0x0E

0x0F

0x10

0x11

General

Purpose

Working

Registers

R26

R27

R28

R29

R30

R31

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

X-register Low Byte

X-register High Byte

Y-register Low Byte

Y-register High Byte

Z-register Low Byte

Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and

most of them are single cycle instructions.

As shown in Figure 4-2, each register is also assigned a data memory address, mapping them

directly into the first 32 locations of the user Data Space. Although not being physically imple-

mented as SRAM locations, this memory organization provides great flexibility in access of the

registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

4.5.1

The X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These reg-

isters are 16-bit address pointers for indirect addressing of the data space. The three indirect

address registers X, Y, and Z are defined as described in Figure 4-3.

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Figure 4-3. The X-, Y-, and Z-registers

15

XH

XL

0

X-register

7

0

7

R27 (0x1B)

R26 (0x1A)

15

YH

YL

ZL

0

Y-register

Z-register

7

R29 (0x1D)

R28 (0x1C)

15

ZH

0

7

0

R31 (0x1F)

R30 (0x1E)

In the different addressing modes these address registers have functions as fixed displacement,

automatic increment, and automatic decrement (see the instruction set reference for details).

4.6

Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing

return addresses after interrupts and subroutine calls. The Stack Pointer Register always points

to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-

tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack

Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt

Stacks are located. This Stack space in the data SRAM must be defined by the program before

any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to

point above 0x0100. The initial value of the stack pointer is the last address of the internal

SRAM. The Stack Pointer is decremented by one when data is pushed onto the Stack with the

PUSH instruction, and it is decremented by three when the return address is pushed onto the

Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is

popped from the Stack with the POP instruction, and it is incremented by three when data is

popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of

bits actually used is implementation dependent. Note that the data space in some implementa-

tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register

will not be present.

Bit

15

14

13

12

11

10

9

8

SP15

SP7

7

SP14

SP6

6

SP13

SP5

5

SP12

SP4

4

SP11

SP3

3

SP10

SP2

2

SP9

SP1

1

SP8

SP0

0

SPH

SPL

Read/Write

Initial Value

R/W

0

R/W

0

R/W

1

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

1

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AT90USB64/128

4.6.1

Extended Z-pointer Register for ELPM/SPM - RAMPZ

Bit

7

6

5

4

3

2

1

0

RAMPZ

7

RAMPZ

6

RAMPZ

5

RAMPZ

4

RAMPZ

3

RAMPZ

2

RAMPZ1

RAMPZ0

RAMPZ

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown

in Figure 4-4. Note that LPM is not affected by the RAMPZ setting.

Figure 4-4. The Z-pointer used by ELPM and SPM

Bit (

Individually)

7

0

7

0

8

7

0

RAMPZ

ZH

ZL

Bit (Z-pointer)

23

16

15

7

The actual number of bits is implementation dependent. Unused bits in an implementation will

always read as zero. For compatibility with future devices, be sure to write these bits to zero.

4.7

Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR

CPU is driven by the CPU clock clk_CPU, directly generated from the selected clock source for the

chip. No internal clock division is used.

Figure 4-5 shows the parallel instruction fetches and instruction executions enabled by the Har-

vard architecture and the fast-access Register File concept. This is the basic pipelining concept

to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,

functions per clocks, and functions per power-unit.

Figure 4-5. The Parallel Instruction Fetches and Instruction Executions

T1

T2

T3

T4

clk_CPU

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 4-6 shows the internal timing concept for the Register File. In a single clock cycle an ALU

operation using two register operands is executed, and the result is stored back to the destina-

tion register.

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7593D–AVR–07/06

Figure 4-6. Single Cycle ALU Operation

T1

T2

T3

T4

clk_CPU

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

4.8

Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset

Vector each have a separate program vector in the program memory space. All interrupts are

assigned individual enable bits which must be written logic one together with the Global Interrupt

Enable bit in the Status Register in order to enable the interrupt. Depending on the Program

Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12

are programmed. This feature improves software security. See the section “Memory Program-

ming” on page 368 for details.

The lowest addresses in the program memory space are by default defined as the Reset and

Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 70. The list also

determines the priority levels of the different interrupts. The lower the address the higher is the

priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request

0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL

bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 70 for more information.

The Reset Vector can also be moved to the start of the Boot Flash section by programming the

BOOTRST Fuse, see “Memory Programming” on page 368.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-

abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled

interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a

Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the

Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec-

tor in order to execute the interrupt handling routine, and hardware clears the corresponding

Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)

to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is

cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is

cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt

Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the

Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These

interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the

interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one

more instruction before any pending interrupt is served.

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AT90USB64/128

Note that the Status Register is not automatically stored when entering an interrupt routine, nor

restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.

No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the

CLI instruction. The following example shows how this can be used to avoid interrupts during the

timed EEPROM write sequence..

Assembly Code Example

in r16, SREG

; store SREG value

cli ; disable interrupts during timed sequence

sbiEECR, EEMPE ; start EEPROM write

sbiEECR, EEPE

outSREG, r16

; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG;/* store SREG value */

/* disable interrupts during timed sequence */

__disable_interrupt();

EECR |= (1<<EEMPE); /* start EEPROM write */

EECR |= (1<<EEPE);

SREG = cSREG; /* restore SREG value (I-bit) */

When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-

cuted before any pending interrupts, as shown in this example.

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Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */

__sleep(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

4.8.1

Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is five clock cycles minimum.

After five clock cycles the program vector address for the actual interrupt handling routine is exe-

cuted. During these five clock cycle period, the Program Counter is pushed onto the Stack. The

vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an

interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before

the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt exe-

cution response time is increased by five clock cycles. This increase comes in addition to the

start-up time from the selected sleep mode.

A return from an interrupt handling routine takes five clock cycles. During these five clock cycles,

the Program Counter (three bytes) is popped back from the Stack, the Stack Pointer is incre-

mented by three, and the I-bit in SREG is set.

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AT90USB64/128

5. AVR AT90USB64/128 Memories

This section describes the different memories in the AT90USB64/128. The AVR architecture has

two main memory spaces, the Data Memory and the Program Memory space. In addition, the

AT90USB64/128 features an EEPROM Memory for data storage. All three memory spaces are

linear and regular.

Table 5-1.

Memory

Memory Mapping.

Mnemonic

AT90USB64

64 K bytes

0x00000

AT90USB128

Size

Flash size

-

128K bytes

Start Address

Flash

0x0FFFF⁽¹⁾

0x7FFF⁽²⁾

0x1FFFF⁽¹⁾

0xFFFF⁽²⁾

End Address

Flash end

Size

-

32 bytes

0x0000

32

Registers

Start Address

End Address

Size

-

0x001F

-

64 bytes

0x0020

I/O

Start Address

End Address

Size

-

Registers

-

0x005F

-

160 bytes

0x0060

Ext I/O

Start Address

End Address

Size

-

Registers

-

0x00FF

4 K bytes

0x0100

ISRAM size

ISRAM start

ISRAM end

XMem size

XMem start

XMem end

E2 size

-

8 K bytes

0x20FF

0x2100

Internal

SRAM

Start Address

End Address

Size

0x10FF

0-64 K bytes

0x1100

External

Memory

Start Address

End Address

Size

0xFFFF

2 K bytes

0x0000

4K bytes

0x0FFF

EEPROM

Start Address

End Address

E2 end

0x07FF

Notes: 1. Byte address.

2. Word (16-bit) address.

5.1

In-System Reprogrammable Flash Program Memory

The AT90USB64/128 contains 128K bytes On-chip In-System Reprogrammable Flash memory

for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as

64K x 16. For software security, the Flash Program memory space is divided into two sections,

Boot Program section and Application Program section.

The Flash memory has an endurance of at least 100,000 write/erase cycles. The

AT90USB64/128 Program Counter (PC) is 16 bits wide, thus addressing the 128K program

19

7593D–AVR–07/06

memory locations. The operation of Boot Program section and associated Boot Lock bits for

software protection are described in detail in “Memory Programming” on page 368. “Memory

Programming” on page 368 contains a detailed description on Flash data serial downloading

using the SPI pins or the JTAG interface.

Constant tables can be allocated within the entire program memory address space (see the LPM

– Load Program Memory instruction description and ELPM - Extended Load Program Memory

instruction description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-

ing” on page 15.

Figure 5-1. Program Memory Map

Program Memory

0x00000

Application Flash Section

Boot Flash Section

Flash End

5.2

SRAM Data Memory

Figure 5-2 shows how the AT90USB64/128 SRAM Memory is organized.

The AT90USB64/128 is a complex microcontroller with more peripheral units than can be sup-

ported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the

Extended I/O space from $060 - $1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instruc-

tions can be used.

The first 4,608/8,704 Data Memory locations address both the Register File, the I/O Memory,

Extended I/O Memory, and the internal data SRAM. The first 32 locations address the Register

file, the next 64 location the standard I/O Memory, then 416 locations of Extended I/O memory

and the next 8,192 locations address the internal data SRAM.

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AT90USB64/128

An optional external data SRAM can be used with the AT90USB64/128. This SRAM will occupy

an area in the remaining address locations in the 64K address space. This area starts at the

address following the internal SRAM. The Register file, I/O, Extended I/O and Internal SRAM

occupies the lowest 4,608/8,704 bytes, so when using 64KB (65,536 bytes) of External Memory,

60,478/56,832 Bytes of External Memory are available. See “External Memory Interface” on

page 30 for details on how to take advantage of the external memory map.

When the addresses accessing the SRAM memory space exceeds the internal data memory

locations, the external data SRAM is accessed using the same instructions as for the internal

data memory access. When the internal data memories are accessed, the read and write strobe

pins (PE0 and PE1) are inactive during the whole access cycle. External SRAM operation is

enabled by setting the SRE bit in the XMCRA Register.

Accessing external SRAM takes one additional clock cycle per byte compared to access of the

internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD, PUSH, and POP

take one additional clock cycle. If the Stack is placed in external SRAM, interrupts, subroutine

calls and returns take three clock cycles extra because the three-byte program counter is

pushed and popped, and external memory access does not take advantage of the internal pipe-

line memory access. When external SRAM interface is used with wait-state, one-byte external

access takes two, three, or four additional clock cycles for one, two, and three wait-states

respectively. Interrupts, subroutine calls and returns will need five, seven, or nine clock cycles

more than specified in the instruction set manual for one, two, and three wait-states.

The five different addressing modes for the data memory cover: Direct, Indirect with Displace-

ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register file,

registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given

by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-incre-

ment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O registers, and the 8,192 bytes of internal data

SRAM in the AT90USB64/128 are all accessible through all these addressing modes. The Reg-

ister File is described in “General Purpose Register File” on page 13.

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7593D–AVR–07/06

Figure 5-2. Data Memory Map

D

ata Memory

$0000

$0020

$0060

-

$001

$005

$00FF

F

32

64 I/O

160

R

eg

xt I/O

i

st

e

r

s

e

R

i

st

r

s

eg.

E

ISRAM start

I

n

(

t

e

r

na

l

8192

S

R

x 8)

A

M

ISRAM end

XMem start

E

xt

e

-

r

nal

64

S

K

R

x

AM

8)

(

0

$

FFFF

5.2.1

Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clk_CPUcycles as described in Figure 5-3.

22

AT90USB64/128

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AT90USB64/128

Figure 5-3. On-chip Data SRAM Access Cycles

T1

T2

T3

clk_CPU

Address valid

Compute Address

Address

Data

WR

Data

RD

Memory Access Instruction

Next Instruction

5.3

EEPROM Data Memory

The AT90USB64/128 contains 2K/4K bytes of data EEPROM memory. It is organized as a sep-

arate data space, in which single bytes can be read and written. The EEPROM has an

endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the

CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM

Data Register, and the EEPROM Control Register.

For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see

page 382, page 387, and page 371 respectively.

5.3.1

EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 5-3. A self-timing function, however,

lets the user software detect when the next byte can be written. If the user code contains instruc-

tions that write the EEPROM, some precautions must be taken. In heavily filtered power

supplies, V_CCis likely to rise or fall slowly on power-up/down. This causes the device for some

period of time to run at a voltage lower than specified as minimum for the clock frequency used.

See “Preventing EEPROM Corruption” on page 28. for details on how to avoid problems in these

situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed.

5.3.2

The EEPROM Address Register – EEARH and EEARL

Bit

15

14

13

12

11

10

9

8

–

EEAR11

EEAR3

EEAR10

EEAR2

EEAR9

EEAR1

EEAR8

EEAR0

EEARH

EEAR7

EEAR6

EEAR5

EEAR4

EEARL

23

7593D–AVR–07/06

7

6

5

4

3

2

1

0

Read/Write

Initial Value

R

R/W

X

R/W

X

R/W

X

R/W

X

R/W

0

R/W

0

R/W

0

R/W

0

X

• Bits 15..12 – Res: Reserved Bits

These bits are reserved bits in the AT90USB64/128 and will always read as zero.

• Bits 11..0 – EEAR8..0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 4K

bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096.

The initial value of EEAR is undefined. A proper value must be written before the EEPROM may

be accessed.

5.3.3

The EEPROM Data Register – EEDR

Bit

7

6

5

4

3

2

1

0

MSB

R/W

0

LSB

R/W

0

EEDR

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bits 7..0 – EEDR7.0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to the

EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the

EEDR contains the data read out from the EEPROM at the address given by EEAR.

5.3.4

The EEPROM Control Register – EECR

Bit

7

6

5

4

3

2

1

0

–

EEPM1

R/W

X

EEPM0

R/W

X

EERIE

R/W

0

EEMPE

R/W

0

EEPE

R/W

X

EERE

R/W

0

EECR

Read/Write

Initial Value

R

0

R

0

• Bits 7..6 – Res: Reserved Bits

These bits are reserved bits in the AT90USB64/128 and will always read as zero.

• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits

The EEPROM Programming mode bit setting defines which programming action that will be trig-

gered when writing EEPE. It is possible to program data in one atomic operation (erase the old

value and program the new value) or to split the Erase and Write operations in two different

operations. The Programming times for the different modes are shown in Table 5-2. While EEPE

is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00

unless the EEPROM is busy programming.

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AT90USB64/128

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AT90USB64/128

Table 5-2.

EEPROM Mode Bits

Programming

EEPM1 EEPM0

Time

3.4 ms

1.8 ms

–

Operation

0

1

0

1

0

1

Erase and Write in one operation (Atomic Operation)

Erase Only

Write Only

Reserved for future use

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing

EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-

rupt when EEPE is cleared.

• Bit 2 – EEMPE: EEPROM Master Programming Enable

The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written.

When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at the

selected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been

written to one by software, hardware clears the bit to zero after four clock cycles. See the

description of the EEPE bit for an EEPROM write procedure.

• Bit 1 – EEPE: EEPROM Programming Enable

The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address

and data are correctly set up, the EEPE bit must be written to one to write the value into the

EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, other-

wise no EEPROM write takes place. The following procedure should be followed when writing

the EEPROM (the order of steps 3 and 4 is not essential):

1. Wait until EEPE becomes zero.

2. Wait until SELFPRGEN in SPMCSR becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.

6. Within four clock cycles after setting EEMPE, write a logical one to EEPE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software

must check that the Flash programming is completed before initiating a new EEPROM write.

Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the

Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Memory Pro-

gramming” on page 368 for details about Boot programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the

EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is

interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the

interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared

during all the steps to avoid these problems.

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7593D–AVR–07/06

When the write access time has elapsed, the EEPE bit is cleared by hardware. The user soft-

ware can poll this bit and wait for a zero before writing the next byte. When EEPE has been set,

the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct

address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the

EEPROM read. The EEPROM read access takes one instruction, and the requested data is

available immediately. When the EEPROM is read, the CPU is halted for four cycles before the

next instruction is executed.

The user should poll the EEPE bit before starting the read operation. If a write operation is in

progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 5-3 lists the typical pro-

gramming time for EEPROM access from the CPU.

Table 5-3.

Symbol

EEPROM Programming Time

Number of Calibrated RC Oscillator Cycles

Typ Programming Time

EEPROM write

(from CPU)

26,368

3.3 ms

The following code examples show one assembly and one C function for writing to the

EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts glo-

bally) so that no interrupts will occur during execution of these functions. The examples also

assume that no Flash Boot Loader is present in the software. If such code is present, the

EEPROM write function must also wait for any ongoing SPM command to finish.

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AT90USB64/128

Assembly Code Example⁽¹⁾

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_write

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r16) to Data Register

out EEDR,r16

; Write logical one to EEMPE

sbi EECR,EEMPE

; Start eeprom write by setting EEPE

sbi EECR,EEPE

ret

C Code Example⁽¹⁾

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set up address and Data Registers */

EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMPE */

EECR |= (1<<EEMPE);

/* Start eeprom write by setting EEPE */

EECR |= (1<<EEPE);

}

Note:

1. See “About Code Examples” on page 8.

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7593D–AVR–07/06

The next code examples show assembly and C functions for reading the EEPROM. The exam-

ples assume that interrupts are controlled so that no interrupts will occur during execution of

these functions.

Assembly Code Example⁽¹⁾

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from Data Register

in r16,EEDR

ret

C Code Example⁽¹⁾

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set up address register */

EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from Data Register */

return EEDR;

}

Note:

1. See “About Code Examples” on page 8.

5.3.5

Preventing EEPROM Corruption

During periods of low V_CC,the EEPROM data can be corrupted because the supply voltage is

too low for the CPU and the EEPROM to operate properly. These issues are the same as for

board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First,

a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec-

ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can

be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal

BOD does not match the needed detection level, an external low V_CCreset Protection circuit can

be used. If a reset occurs while a write operation is in progress, the write operation will be com-

pleted provided that the power supply voltage is sufficient.

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AT90USB64/128

5.4

I/O Memory

The I/O space definition of the AT90USB64/128 is shown in “Register Summary” on page 414.

All AT90USB64/128 I/Os and peripherals are placed in the I/O space. All I/O locations may be

accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32

general purpose working registers and the I/O space. I/O Registers within the address range

0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the

value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the

instruction set section for more details. When using the I/O specific commands IN and OUT, the

I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using

LD and ST instructions, 0x20 must be added to these addresses. The AT90USB64/128 is a

complex microcontroller with more peripheral units than can be supported within the 64 location

reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 -

0x1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most

other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore

be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-

isters 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

5.4.1

General Purpose I/O Registers

The AT90USB64/128 contains three General Purpose I/O Registers. These registers can be

used for storing any information, and they are particularly useful for storing global variables and

Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly

bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

5.4.2

5.4.3

5.4.4

General Purpose I/O Register 2 – GPIOR2

Bit

7

6

5

4

3

2

1

0

MSB

R/W

0

LSB

R/W

0

GPIOR2

GPIOR1

GPIOR0

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

General Purpose I/O Register 1 – GPIOR1

Bit

7

6

5

4

3

2

1

0

MSB

R/W

0

LSB

R/W

0

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

General Purpose I/O Register 0 – GPIOR0

Bit

7

6

5

4

3

2

1

0

MSB

R/W

0

LSB

R/W

0

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

29

7593D–AVR–07/06

5.5

External Memory Interface

With all the features the External Memory Interface provides, it is well suited to operate as an

interface to memory devices such as External SRAM and Flash, and peripherals such as LCD-

display, A/D, and D/A. The main features are:

• Four different wait-state settings (including no wait-state).

• Independent wait-state setting for different external Memory sectors (configurable sector size).

• The number of bits dedicated to address high byte is selectable.

• Bus keepers on data lines to minimize current consumption (optional).

5.5.1

Overview

When the eXternal MEMory (XMEM) is enabled, address space outside the internal SRAM

becomes available using the dedicated External Memory pins (see Figure 2-1 on page 5, Table

10-3 on page 81, and Table 10-9 on page 85). The memory configuration is shown in Figure 5-4.

Figure 5-4. External Memory with Sector Select

M

e

m

or

y

C

onfigu

r

a

t

ion

A

0x0000

I

nternal memory

ISRAM end

XMem start

Lower sector

S

R

W

01

00

SRL[2..0]

E

xt

e

-

r

na

60

l

K

Memory

x 8)

U

ppe

r

s

e

cto

r

(

0

S

R

W

11

10

0xFFFF

5.5.2

Using the External Memory Interface

The interface consists of:

• AD7:0: Multiplexed low-order address bus and data bus.

• A15:8: High-order address bus (configurable number of bits).

• ALE: Address latch enable.

• RD: Read strobe.

• WR: Write strobe.

The control bits for the External Memory Interface are located in two registers, the External

Memory Control Register A – XMCRA, and the External Memory Control Register B – XMCRB.

30

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

When the XMEM interface is enabled, the XMEM interface will override the setting in the data

direction registers that corresponds to the ports dedicated to the XMEM interface. For details

about the port override, see the alternate functions in section “I/O-Ports” on page 74. The XMEM

interface will auto-detect whether an access is internal or external. If the access is external, the

XMEM interface will output address, data, and the control signals on the ports according to Fig-

ure 5-6 (this figure shows the wave forms without wait-states). When ALE goes from high-to-low,

there is a valid address on AD7:0. ALE is low during a data transfer. When the XMEM interface

is enabled, also an internal access will cause activity on address, data and ALE ports, but the

RD and WR strobes will not toggle during internal access. When the External Memory Interface

is disabled, the normal pin and data direction settings are used. Note that when the XMEM inter-

face is disabled, the address space above the internal SRAM boundary is not mapped into the

internal SRAM. Figure 5-5 illustrates how to connect an external SRAM to the AVR using an

octal latch (typically “74 x 573” or equivalent) which is transparent when G is high.

5.5.3

Address Latch Requirements

Due to the high-speed operation of the XRAM interface, the address latch must be selected with

care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V. When operating at condi-

tions above these frequencies, the typical old style 74HC series latch becomes inadequate. The

External Memory Interface is designed in compliance to the 74AHC series latch. However, most

latches can be used as long they comply with the main timing parameters. The main parameters

for the address latch are:

• D to Q propagation delay (t_PD).

• Data setup time before G low (t_SU).

• Data (address) hold time after G low (_TH).

The External Memory Interface is designed to guaranty minimum address hold time after G is

asserted low of t_h= 5 ns. Refer to t_{LAXX_LD}/t_{LLAXX_ST}in “External Data Memory Timing” Tables 30-

7 through Tables 30-13 on pages 408 - 411. The D-to-Q propagation delay (t_PD) must be taken

into consideration when calculating the access time requirement of the external component. The

data setup time before G low (t_SU) must not exceed address valid to ALE low (t_AVLLC) minus PCB

wiring delay (dependent on the capacitive load).

Figure 5-5. External SRAM Connected to the AVR

D[7:0]

AD7:0

ALE

D

G

Q

A[7:0]

SRAM

A[15:8]

AVR

A15:8

RD

WR

31

7593D–AVR–07/06

5.5.4

Pull-up and Bus-keeper

The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to

one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by

writing the Port register to zero before entering sleep.

The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper can be dis-

abled and enabled in software as described in “External Memory Control Register B – XMCRB”

on page 35. When enabled, the bus-keeper will keep the previous value on the AD7:0 bus while

these lines are tri-stated by the XMEM interface.

5.5.5

Timing

External Memory devices have different timing requirements. To meet these requirements, the

XMEM interface provides four different wait-states as shown in Table 5-5. It is important to con-

sider the timing specification of the External Memory device before selecting the wait-state. The

most important parameters are the access time for the external memory compared to the set-up

requirement. The access time for the External Memory is defined to be the time from receiving

the chip select/address until the data of this address actually is driven on the bus. The access

time cannot exceed the time from the ALE pulse must be asserted low until data is stable during

a read sequence (See t_LLRL+ t_RLRH- t_DVRHin Tables 30-6 through Tables 30-13 on pages 408 -

411). The different wait-states are set up in software. As an additional feature, it is possible to

divide the external memory space in two sectors with individual wait-state settings. This makes it

possible to connect two different memory devices with different timing requirements to the same

XMEM interface. For XMEM interface timing details, please refer to Tables 30-6 through Tables

30-13 and Figure 30-7 to Figure 30-10 in the “External Data Memory Timing” on page 408.

Note that the XMEM interface is asynchronous and that the waveforms in the following figures

are related to the internal system clock. The skew between the internal and external clock

(XTAL1) is not guarantied (varies between devices temperature, and supply voltage). Conse-

quently, the XMEM interface is not suited for synchronous operation.

Figure 5-6. External Data Memory Cycles without Wait-state (SRWn1=0 and SRWn0=0)

T1

T2

T3

T4

System Clock (CLK_CPU

)

ALE

A15:8 Prev. addr.

DA7:0 Prev. data

WR

Address

Data

Address

XX

DA7:0 (XMBK = 0) Prev. data

DA7:0 (XMBK = 1) Prev. data

RD

Data

Address

Note:

1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or

SRW00 (lower sector). The ALE pulse in period T4 is only present if the next instruction

accesses the RAM (internal or external).

32

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

Figure 5-7. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1⁽¹⁾

T1

T2

T3

T4

T5

System Clock (CLK_CPU

)

ALE

A15:8 Prev. addr.

DA7:0 Prev. data

WR

Address

Data

Address

XX

DA7:0 (XMBK = 0) Prev. data

DA7:0 (XMBK = 1) Prev. data

RD

Data

Address

Note:

1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or

SRW00 (lower sector).

The ALE pulse in period T5 is only present if the next instruction accesses the RAM (internal

or external).

Figure 5-8. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0⁽¹⁾

T1

T2

T3

T4

T5

System Clock (CLK_CPU

)

ALE

A15:8 Prev. addr.

DA7:0 Prev. data

WR

Address

Data

Address

XX

DA7:0 (XMBK = 0) Prev. data

DA7:0 (XMBK = 1) Prev. data

RD

Data

Address

Note:

1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or

SRW00 (lower sector).

The ALE pulse in period T6 is only present if the next instruction accesses the RAM (internal

or external).

33

7593D–AVR–07/06

Figure 5-9. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1⁽¹⁾

T1

T2

T3

T4

T5

T6

System Clock (CLK_CPU

)

ALE

A15:8 Prev. addr.

DA7:0 Prev. data

WR

Address

Data

Address

XX

DA7:0 (XMBK = 0) Prev. data

DA7:0 (XMBK = 1) Prev. data

RD

Data

Address

Note:

1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or

SRW00 (lower sector).

The ALE pulse in period T7 is only present if the next instruction accesses the RAM (internal

or external).

5.5.6

External Memory Control Register A – XMCRA

Bit

7

6

5

4

3

2

1

0

SRE

R/W

0

SRL2

R/W

0

SRL1

R/W

0

SRL0

R/W

0

SRW11

R/W

0

SRW10

R/W

0

SRW01

R/W

0

SRW00

R/W

0

XMCRA

Read/Write

Initial Value

• Bit 7 – SRE: External SRAM/XMEM Enable

Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8,

ALE, WR, and RD are activated as the alternate pin functions. The SRE bit overrides any pin

direction settings in the respective data direction registers. Writing SRE to zero, disables the

External Memory Interface and the normal pin and data direction settings are used.

• Bit 6..4 – SRL2:0: Wait-state Sector Limit

It is possible to configure different wait-states for different External Memory addresses. The

external memory address space can be divided in two sectors that have separate wait-state bits.

The SRL2, SRL1, and SRL0 bits select the split of the sectors, see Table 5-4 and Figure 5-4. By

default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external memory address

space is treated as one sector. When the entire SRAM address space is configured as one sec-

tor, the wait-states are configured by the SRW11 and SRW10 bits.

34

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

Table 5-4.

SRL2

Sector limits with different settings of SRL2..0

SRL1

SRL0

Sector Limits

Lower sector = N/A

Upper sector = 0x2100 - 0xFFFF

0

1

0

x

Lower sector = 0x2100 - 0x3FFF

Upper sector = 0x4000 - 0xFFFF

1

0

1

0

1

0

1

0

1

Lower sector = 0x2100 - 0x5FFF

Upper sector = 0x6000 - 0xFFFF

Lower sector = 0x2100 - 0x7FFF

Upper sector = 0x8000 - 0xFFFF

Lower sector = 0x2100 - 0x9FFF

Upper sector = 0xA000 - 0xFFFF

Lower sector = 0x2100 - 0xBFFF

Upper sector = 0xC000 - 0xFFFF

Lower sector = 0x2100 - 0xDFFF

Upper sector = 0xE000 - 0xFFFF

• Bit 3..2 – SRW11, SRW10: Wait-state Select Bits for Upper Sector

The SRW11 and SRW10 bits control the number of wait-states for the upper sector of the exter-

nal memory address space, see Table 5-5.

• Bit 1..0 – SRW01, SRW00: Wait-state Select Bits for Lower Sector

The SRW01 and SRW00 bits control the number of wait-states for the lower sector of the exter-

nal memory address space, see Table 5-5.

Table 5-5.

SRWn1 SRWn0 Wait States

Wait States⁽¹⁾

0

1

0

1

0

No wait-states

Wait one cycle during read/write strobe

Wait two cycles during read/write strobe

Wait two cycles during read/write and wait one cycle before driving out

new address

1

Note:

1. n = 0 or 1 (lower/upper sector).

For further details of the timing and wait-states of the External Memory Interface, see Figures

5-6 through Figures 5-9 for how the setting of the SRW bits affects the timing.

5.5.7

External Memory Control Register B – XMCRB

Bit

7

6

–

R

0

5

–

R

0

4

–

R

0

3

–

R

0

2

1

0

XMBK

R/W

0

XMM2

R/W

0

XMM1

R/W

0

XMM0

R/W

0

XMCRB

Read/Write

Initial Value

• Bit 7– XMBK: External Memory Bus-keeper Enable

Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper is

enabled, AD7:0 will keep the last driven value on the lines even if the XMEM interface has tri-

stated the lines. Writing XMBK to zero disables the bus keeper. XMBK is not qualified with SRE,

35

7593D–AVR–07/06

so even if the XMEM interface is disabled, the bus keepers are still activated as long as XMBK is

one.

• Bit 6..3 – Res: Reserved Bits

These bits are reserved and will always read as zero. When writing to this address location,

write these bits to zero for compatibility with future devices.

• Bit 2..0 – XMM2, XMM1, XMM0: External Memory High Mask

When the External Memory is enabled, all Port C pins are default used for the high address byte.

If the full 60KB address space is not required to access the External Memory, some, or all, Port

C pins can be released for normal Port Pin function as described in Table 5-6. As described in

“Using all 64KB Locations of External Memory” on page 37, it is possible to use the XMMn bits to

access all 64KB locations of the External Memory.

Table 5-6.

Port C Pins Released as Normal Port Pins when the External Memory is Enabled

XMM2 XMM1 XMM0 # Bits for External Memory Address

Released Port Pins

None

0

1

0

1

0

1

0

1

0

1

0

1

0

1

8 (Full 56KB space)

7

PC7

6

PC7 - PC6

PC7 - PC5

PC7 - PC4

PC7 - PC3

PC7 - PC2

Full Port C

5

4

3

2

No Address high bits

5.5.8

Using all Locations of External Memory Smaller than 64 KB

Since the external memory is mapped after the internal memory as shown in Figure 5-4, the

external memory is not addressed when addressing the first 8,448/4,352 bytes (128/64Kbytes

version) of data space. It may appear that the first 8,448/4,352 bytes of the external memory are

inaccessible (external memory addresses 0x0000 to 0x10FF or 0x0000 to 0x20FF). However,

when connecting an external memory smaller than 64 KB, for example 32 KB, these locations

are easily accessed simply by addressing from address 0x8000 to 0xA1FF. Since the External

Memory Address bit A15 is not connected to the external memory, addresses 0x8000 to 0xA1FF

will appear as addresses 0x0000 to 0x21FF for the external memory. Addressing above address

0xA1FF is not recommended, since this will address an external memory location that is already

accessed by another (lower) address. To the Application software, the external 32 KB memory

will appear as one linear 32 KB address space from 0x2200 to 0xA1FF. This is illustrated in Fig-

ure 5-10.

36

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

Figure 5-10. Address Map with 32 KB External Memory

M

e

m

o

r

y

C

on

f

i

gu

r

a

t

i

on

A

AV

R

M

e

mo

r

y

M

ap

External 32K S RAM

0

x0000

0x0000

I

n

t

e

rna

l

M

e

mo

ry

0

x

20FF

2100

ISRAM end

XMem start

x

E

xternal

0

x

7

FFF

0x7FFF

x8000

Memory

ISRAM end + 0x8000

XMem start + 0x8000

(Unused)

0xFFFF

5.5.9

Using all 64KB Locations of External Memory

Since the External Memory is mapped after the Internal Memory as shown in Figure 5-4, only

56KB of External Memory is available by default (address space 0x0000 to 0x20FF is reserved

for internal memory). However, it is possible to take advantage of the entire External Memory by

masking the higher address bits to zero. This can be done by using the XMMn bits and control

by software the most significant bits of the address. By setting Port C to output 0x00, and releas-

ing the most significant bits for normal Port Pin operation, the Memory Interface will address

0x0000 - 0x2FFF. See the following code examples.

Care must be exercised using this option as most of the memory is masked away.

37

7593D–AVR–07/06

Assembly Code Example⁽¹⁾

; OFFSET is defined to 0x4000 to ensure

; external memory access

; Configure Port C (address high byte) to

; output 0x00 when the pins are released

; for normal Port Pin operation

ldi r16, 0xFF

out DDRC, r16

ldi r16, 0x00

out PORTC, r16

; release PC7:6

ldi r16, (1<<XMM1)

sts XMCRB, r16

; write 0xAA to address 0x0001 of external

; memory

ldi r16, 0xaa

sts 0x0001+OFFSET, r16

; re-enable PC7:6 for external memory

ldi r16, (0<<XMM1)

sts XMCRB, r16

; store 0x55 to address (OFFSET + 1) of

; external memory

ldi r16, 0x55

sts 0x0001+OFFSET, r16

C Code Example⁽¹⁾

#define OFFSET 0x4000

void XRAM_example(void)

{

unsigned char *p = (unsigned char *) (OFFSET + 1);

DDRC = 0xFF;

PORTC = 0x00;

XMCRB = (1<<XMM1);

*p = 0xaa;

XMCRB = 0x00;

*p = 0x55;

}

Note:

1. See “About Code Examples” on page 8.

38

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

6. System Clock and Clock Options

6.1

Clock Systems and their Distribution

Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks

need not be active at a given time. In order to reduce power consumption, the clocks to modules

not being used can be halted by using different sleep modes, as described in “Power Manage-

ment and Sleep Modes” on page 53. The clock systems are detailed below.

Figure 6-1. Clock Distribution

Asynchronous

Timer/Counter

General I/O

Modules

Flash and

EEPROM

ADC

CPU Core

RAM

USB

clk_ADC

clk_I/O

clk_CPU

AVR Clock

Control Unit

clk_{USB (48MHz)}

clk_ASY

clk_FLASH

USB PLL

X24

Reset Logic

Watchdog Timer

clk_{Pllin (2MHz)}

Source clock

Watchdog clock

System Clock

Prescaler

PLL Clock

Prescaler

Clock

Multiplexer

clk_{XTAL (2-16 MHz)}

Timer/Counter

Oscillator

Calibrated RC

Oscillator

Watchdog

Oscillator

Crystal

Oscillator

External Clock

6.1.1

6.1.2

CPU Clock – clk_CPU

The CPU clock is routed to parts of the system concerned with operation of the AVR core.

Examples of such modules are the General Purpose Register File, the Status Register and the

data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing

general operations and calculations.

I/O Clock – clk_I/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.

The I/O clock is also used by the External Interrupt module, but note that some external inter-

rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O

clock is halted. Also note that start condition detection in the USI module is carried out asynchro-

nously when clk_I/Ois halted, TWI address recognition in all sleep modes.

6.1.3

Flash Clock – clk_FLASH

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-

taneously with the CPU clock.

39

7593D–AVR–07/06

6.1.4

6.1.5

6.1.6

Asynchronous Timer Clock – clk_ASY

The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly

from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows

using this Timer/Counter as a real-time counter even when the device is in sleep mode.

ADC Clock – clk_ADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks

in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion

results.

USB Clock – clk_USB

The USB is provided with a dedicated clock domain. This clock is generated with an on-chip PLL

running at 48MHz. The PLL always multiply its input frequency by 24. Thus the PLL clock regis-

ter should be programmed by software to generate a 2MHz clock on the PLL input.

6.2

Clock Sources

The device has the following clock source options, selectable by Flash Fuse bits as shown

below. The clock from the selected source is input to the AVR clock generator, and routed to the

appropriate modules.

Table 6-1.

Device Clocking Options Select⁽¹⁾

Device Clocking Option

Low Power Crystal Oscillator

Reserved

CKSEL3..0

1111 - 1000

0111 - 0110

0101 - 0100

0011

Low Frequency Crystal Oscillator

Internal 128 kHz RC Oscillator

Calibrated Internal RC Oscillator

External Clock

0010

0000

Reserved

0001

Note:

1. For all fuses “1” means unprogrammed while “0” means programmed.

6.2.1

6.2.2

Default Clock Source

The device is shipped with internal RC oscillator at 8.0MHz and with the fuse CKDIV8 pro-

grammed, resulting in 1.0MHz system clock. The startup time is set to maximum and time-out

period enabled. (CKSEL = "0010", SUT = "10", CKDIV8 = "0"). The default setting ensures that

all users can make their desired clock source setting using any available programming interface.

Clock Startup Sequence

Any clock source needs a sufficient V_CCto start oscillating and a minimum number of oscillating

cycles before it can be considered stable.

To ensure sufficient V_CC, the device issues an internal reset with a time-out delay (t_TOUT) after

the device reset is released by all other reset sources. “On-chip Debug System” on page 58

describes the start conditions for the internal reset. The delay (t_TOUT) is timed from the Watchdog

Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The

selectable delays are shown in Table 6-2. The frequency of the Watchdog Oscillator is voltage

40

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

dependent as shown in “AT90USB64/128 Typical Characteristics – Preliminary Data” on page

429.

Table 6-2.

Number of Watchdog Oscillator Cycles

Typ Time-out (V_CC= 5.0V)

Typ Time-out (V_CC= 3.0V)

Number of Cycles

0 ms

4.1 ms

65 ms

0 ms

4.3 ms

69 ms

0

512

8K (8,192)

Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum Vcc. The

delay will not monitor the actual voltage and it will be required to select a delay longer than the

Vcc rise time. If this is not possible, an internal or external Brown-Out Detection circuit should be

used. A BOD circuit will ensure sufficient Vcc before it releases the reset, and the time-out delay

can be disabled. Disabling the time-out delay without utilizing a Brown-Out Detection circuit is

not recommended.

The oscillator is required to oscillate for a minimum number of cycles before the clock is consid-

ered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal

reset active for a given number of clock cycles. The reset is then released and the device will

start to execute. The recommended oscillator start-up time is dependent on the clock type, and

varies from 6 cycles for an externally applied clock to 32K cycles for a low frequency crystal.

The start-up sequence for the clock includes both the time-out delay and the start-up time when

the device starts up from reset. When starting up from Power-save or Power-down mode, Vcc is

assumed to be at a sufficient level and only the start-up time is included.

6.3

Low Power Crystal Oscillator

Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be

configured for use as an On-chip Oscillator, as shown in Figure 6-2. Either a quartz crystal or a

ceramic resonator may be used.

This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 out-

put. It gives the lowest power consumption, but is not capable of driving other clock inputs, and

may be more susceptible to noise in noisy environments. In these cases, refer to the “These

options are intended for use with ceramic resonators and will ensure frequency stability at start-

up. They can also be used with crystals when not operating close to the maximum frequency of

the device, and if frequency stability at start-up is not important for the application.” on page 43.

C1 and C2 should always be equal for both crystals and resonators. The optimal value of the

capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the

electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for

use with crystals are given in Table 6-3. For ceramic resonators, the capacitor values given by

the manufacturer should be used.

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7593D–AVR–07/06

Figure 6-2. Crystal Oscillator Connections

C2

XTAL2

XTAL1

GND

C1

The Low Power Oscillator can operate in three different modes, each optimized for a specific fre-

quency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 6-3.

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Table 6-3.

Low Power Crystal Oscillator Operating Modes⁽³⁾

Recommended Range for Capacitors

Frequency Range⁽¹⁾(MHz)

CKSEL3..1

100⁽²⁾

101

C1 and C2 (pF)

0.4 - 0.9

0.9 - 3.0

3.0 - 8.0

8.0 - 16.0

–

12 - 22

110

111

Notes: 1. The frequency ranges are preliminary values. Actual values are TBD.

2. This option should not be used with crystals, only with ceramic resonators.

3. If 8 MHz frequency exceeds the specification of the device (depends on V_CC), the CKDIV8

Fuse can be programmed in order to divide the internal frequency by 8. It must be ensured

that the resulting divided clock meets the frequency specification of the device.

The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table

6-4.

Table 6-4.

Start-up Times for the Low Power Crystal Oscillator Clock Selection

Start-up Time from

Power-down and

Power-save

Additional Delay

from Reset

Oscillator Source /

Power Conditions

(V_CC= 5.0V)

CKSEL0 SUT1..0

Ceramic resonator, fast

rising power

258 CK

1K CK

14CK + 4.1 ms⁽¹⁾

14CK + 65 ms⁽¹⁾

14CK⁽²⁾

0

1

00

01

10

11

00

01

10

11

Ceramic resonator,

slowly rising power

Ceramic resonator,

BOD enabled

Ceramic resonator, fast

rising power

1K CK

14CK + 4.1 ms⁽²⁾

14CK + 65 ms⁽²⁾

14CK

Ceramic resonator,

slowly rising power

1K CK

Crystal Oscillator, BOD

enabled

16K CK

Crystal Oscillator, fast

rising power

14CK + 4.1 ms

14CK + 65 ms

Crystal Oscillator,

slowly rising power

Notes: 1. These options should only be used when not operating close to the maximum frequency of the

device, and only if frequency stability at start-up is not important for the application. These

options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure frequency stability

at start-up. They can also be used with crystals when not operating close to the maximum fre-

quency of the device, and if frequency stability at start-up is not important for the application.

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Table 6-5.

Start-up times for the internal calibrated RC Oscillator clock selection

Start-up Time from Power-

down and Power-save

Additional Delay from

Reset (V_CC= 5.0V)

Power Conditions

BOD enabled

SUT1..0

00

6 CK

14CK

Fast rising power

Slowly rising power

14CK + 4.1 ms

14CK + 65 ms⁽¹⁾

01

6 CK

10

Reserved

11

Note:

1. The device is shipped with this option selected.

6.4

Low Frequency Crystal Oscillator

The device can utilize a 32.768 kHz watch crystal as clock source by a dedicated Low Fre-

quency Crystal Oscillator. The crystal should be connected as shown in Figure 6-2. When this

Oscillator is selected, start-up times are determined by the SUT Fuses and CKSEL0 as shown in

Table 6-6.

Start-up Times for the Low Frequency Crystal Oscillator Clock Selection

Start-up Time from

Power-down and

Power-save

Additional Delay

from Reset

Power Conditions

BOD enabled

(V_CC= 5.0V)

CKSEL0 SUT1..0

1K CK

14CK⁽¹⁾

0

1

00

01

10

11

00

01

10

11

Fast rising power

Slowly rising power

14CK + 4.1 ms⁽¹⁾

14CK + 65 ms⁽¹⁾

1K CK

Reserved

32K CK

Reserved

BOD enabled

14CK

Fast rising power

Slowly rising power

14CK + 4.1 ms

14CK + 65 ms

Note:

1. These options should only be used if frequency stability at start-up is not important for the

application.

6.5

Calibrated Internal RC Oscillator

The calibrated internal RC Oscillator by default provides a 8.0 MHz clock. The frequency is nom-

inal value at 3V and 25°C. The device is shipped with the CKDIV8 Fuse programmed. See

“System Clock Prescaler” on page 48 for more details. This clock may be selected as the system

clock by programming the CKSEL Fuses as shown in Table 6-7. If selected, it will operate with

no external components. During reset, hardware loads the calibration byte into the OSCCAL

Register and thereby automatically calibrates the RC Oscillator. At 3V and 25°C, this calibration

gives a frequency of 8 MHz ± 1%. The oscillator can be calibrated to any frequency in the range

7.3 - 8.1 MHz within ±1% accuracy, by changing the OSCCAL register. When this Oscillator is

used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for

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the Reset Time-out. For more information on the pre-programmed calibration value, see the sec-

tion “Calibration Byte” on page 371

Table 6-7.

Internal Calibrated RC Oscillator Operating Modes⁽¹⁾⁽³⁾

Frequency Range⁽²⁾(MHz)

CKSEL3..0

0010

7.3 - 8.1

Notes: 1. The device is shipped with this option selected.

2. The frequency ranges are preliminary values. Actual values are TBD.

3. If 8 MHz frequency exceeds the specification of the device (depends on V_CC), the CKDIV8

Fuse can be programmed in order to divide the internal frequency by 8.

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in

Table 6-5 on page 44.

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Table 6-8.

Start-up times for the internal calibrated RC Oscillator clock selection

Start-up Time from Power-

down and Power-save

Additional Delay from

Reset (V_CC= 5.0V)

Power Conditions

BOD enabled

SUT1..0

00

6 CK

14CK

Fast rising power

Slowly rising power

14CK + 4.1 ms

14CK + 65 ms⁽¹⁾

01

6 CK

10

Reserved

11

Note:

1. The device is shipped with this option selected.

6.5.1

Oscillator Calibration Register – OSCCAL

Bit

7

6

5

4

3

2

1

0

CAL7

R/W

CAL6

R/W

CAL5

R/W

CAL4

R/W

CAL3

R/W

CAL2

R/W

CAL1

R/W

CAL0

R/W

OSCCAL

Read/Write

Initial Value

Device Specific Calibration Value

• Bits 7..0 – CAL7..0: Oscillator Calibration Value

The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to

remove process variations from the oscillator frequency. The factory-calibrated value is automat-

ically written to this register during chip reset, giving an oscillator frequency of 8.0 MHz at 25°C.

The application software can write this register to change the oscillator frequency. The oscillator

can be calibrated to any frequency in the range 7.3 - 8.1 MHz within ±1% accuracy. Calibration

outside that range is not guaranteed.

Note that this oscillator is used to time EEPROM and Flash write accesses, and these write

times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more

than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.

The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the

lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre-

quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher

frequency than OSCCAL = 0x80.

The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00

gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the

range. Incrementing CAL6..0 by 1 will give a frequency increment of less than 2% in the fre-

quency range 7.3 - 8.1 MHz.

6.6

128 kHz Internal Oscillator

The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre-

quency is nominal at 3V and 25°C. This clock may be select as the system clock by

programming the CKSEL Fuses to “11” as shown in Table 6-9.

Table 6-9.

128 kHz Internal Oscillator Operating Modes

Nominal Frequency

CKSEL3..0

128 kHz

0011

Note:

1. The frequency is preliminary value. Actual value is TBD.

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When this clock source is selected, start-up times are determined by the SUT Fuses as shown in

Table 6-10.

Table 6-10. Start-up Times for the 128 kHz Internal Oscillator

Start-up Time from Power-

down and Power-save

Additional Delay from

Reset

Power Conditions

BOD enabled

SUT1..0

00

6 CK

14CK

Fast rising power

Slowly rising power

14CK + 4 ms

14CK + 64 ms

01

6 CK

10

Reserved

11

6.7

External Clock

The device can utilize a external clock source as shown in Figure 6-3. To run the device on an

external clock, the CKSEL Fuses must be programmed as shown in Table 6-1.

Figure 6-3. External Clock Drive Configuration

NC

XTAL2

EXTERNAL

CLOCK

XTAL1

GND

SIGNAL

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in

Table 6-11.

Table 6-11. Start-up Times for the External Clock Selection

Start-up Time from Power-

down and Power-save

Additional Delay from

Reset (V_CC= 5.0V)

Power Conditions

BOD enabled

SUT1..0

00

6 CK

14CK

Fast rising power

Slowly rising power

14CK + 4.1 ms

14CK + 65 ms

01

6 CK

10

Reserved

11

When applying an external clock, it is required to avoid sudden changes in the applied clock fre-

quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from

one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is

required, ensure that the MCU is kept in Reset during the changes.

Note that the System Clock Prescaler can be used to implement run-time changes of the internal

clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page

48 for details.

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6.8

6.9

Clock Output Buffer

The device can output the system clock on the CLKO pin. To enable the output, the CKOUT

Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-

cuits on the system. The clock also will be output during reset, and the normal operation of I/O

pin will be overridden when the fuse is programmed. Any clock source, including the internal RC

Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is

used, it is the divided system clock that is output.

Timer/Counter Oscillator

The device can operate its Timer/Counter2 from an external 32.768 kHz watch crystal or a exter-

nal clock source. See Figure 6-2 on page 42 for crystal connection.

Applying an external clock source to TOSC1 requires EXCLK in the ASSR Register written to

logic one. See “Asynchronous operation of the Timer/Counter” on page 167 for further descrip-

tion on selecting external clock as input instead of a 32 kHz crystal.

6.10 System Clock Prescaler

The AVR USB has a system clock prescaler, and the system clock can be divided by setting the

“Clock Prescale Register – CLKPR” on page 48. This feature can be used to decrease the sys-

tem clock frequency and the power consumption when the requirement for processing power is

low. This can be used with all clock source options, and it will affect the clock frequency of the

CPU and all synchronous peripherals. clk_I/O, clk_ADC, clk_CPU, and clk_FLASHare divided by a factor

as shown in Table 6-12.

When switching between prescaler settings, the System Clock Prescaler ensures that no

glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than

neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-

sponding to the new setting.

The ripple counter that implements the prescaler runs at the frequency of the undivided clock,

which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the

state of the prescaler - even if it were readable, and the exact time it takes to switch from one

clock division to the other cannot be exactly predicted. From the time the CLKPS values are writ-

ten, it takes between T1 + T2 and T1 + 2 * T2 before the new clock frequency is active. In this

interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the

period corresponding to the new prescaler setting.

To avoid unintentional changes of clock frequency, a special write procedure must be followed

to change the CLKPS bits:

1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in

CLKPR to zero.

2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure the write procedure is

not interrupted.

6.10.1

Clock Prescale Register – CLKPR

Bit

7

6

5

4

3

2

1

0

CLK-

PCE

–

CLKPS

3

CLKPS

2

CLKPS

1

CLKPS

0

CLKPR

Read/Write

Initial Value

R/W

0

R

0

R

0

R

0

R/W

See Bit Description

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AT90USB64/128

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE

bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is

cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the

CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the

CLKPCE bit.

• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0

These bits define the division factor between the selected clock source and the internal system

clock. These bits can be written run-time to vary the clock frequency to suit the application

requirements. As the divider divides the master clock input to the MCU, the speed of all synchro-

nous peripherals is reduced when a division factor is used. The division factors are given in

Table 6-12.

The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed,

the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to

“0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock

source has a higher frequency than the maximum frequency of the device at the present operat-

ing conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8

Fuse setting. The Application software must ensure that a sufficient division factor is chosen if

the selected clock source has a higher frequency than the maximum frequency of the device at

the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.

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Table 6-12. Clock Prescaler Select

CLKPS3

CLKPS2

CLKPS1

CLKPS0

Clock Division Factor

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

16

32

64

128

256

Reserved

6.11 PLL

The PLL is used to generate internal high frequency (48 MHz) clock for USB interface, the PLL

input is generated from an external low-frequency (the crystal oscillator or external clock input

pin from XTAL1). The internal RC Oscillator can not be used for USB operations.

6.11.1

Internal PLL for USB interface

The internal PLL in AT90USB64/128 generates a clock frequency that is 24x multiplied from

nominally 2 MHz input. The source of the 2 MHz PLL input clock is the output of the internal PLL

clock prescaler that generates the 2 MHz (See Section 6.11.2 for PLL interface).

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AT90USB64/128

Figure 6-4. PLL Clocking System

PLLE

PLOCK

Lock

Detector

clk

2MHz

clk

USB (48MHz)

PLL clock

Prescaler

PLL

24x

XTAL1

OSCILLATORS

XTAL2

System Clock

RC OSCILLATOR

8 MHz

Watchdog

OSCILLATOR

6.11.2

PLL Control and Status Register – PLLCSR

Bit

7

6

5

4

3

2

1

0

$29 ($29)

Read/Write

Initial Value

PLLP2

PLLP1

PLLP0

PLLE

R/W

0/1

PLOCK

PLLCSR

R

0

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 7..5 – Res: Reserved Bits

These bits are reserved bits in the AT90USB64/128 and always read as zero.

• Bit 4..2 – PLLP2:0 PLL prescaler

These bits allow to configure the PLL input prescaler to generate the 2MHz input clock for the

PLL.

Table 6-13. PLL input prescaler configurations

Clock Division

Factor

External XTAL required for USB

operation (MHz)

PLLP2

PLLP1

PLLP0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved

4

-

8

-

Reserved

8

-

16

-

Reserved

• Bit 1 – PLLE: PLL Enable

When the PLLE is set, the PLL is started.

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• Bit 0 – PLOCK: PLL Lock Detector

When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable PCK

for Timer/Counter1. After the PLL is enabled, it takes about 100 ms for the PLL to lock.

To clear PLOCK, clear PLLE and PLLPx bits.

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7. Power Management and Sleep Modes

Sleep modes enable the application to shut down unused modules in the MCU, thereby saving

power. The AVR provides various sleep modes allowing the user to tailor the power consump-

tion to the application’s requirements.

To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a

SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select

which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, or Standby) will be

activated by the SLEEP instruction. See Table 7-1 for a summary. If an enabled interrupt occurs

while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in

addition to the start-up time, executes the interrupt routine, and resumes execution from the

instruction following SLEEP. The contents of the Register File and SRAM are unaltered when

the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and

executes from the Reset Vector.

Figure 6-1 on page 39 presents the different clock systems in the AT90USB64/128, and their

distribution. The figure is helpful in selecting an appropriate sleep mode.

7.0.1

Sleep Mode Control Register – SMCR

The Sleep Mode Control Register contains control bits for power management.

Bit

7

–

R

0

6

–

R

0

5

–

R

0

4

–

R

0

3

2

1

0

SM2

R/W

0

SM1

R/W

0

SM0

R/W

0

SE

R/W

0

SMCR

Read/Write

Initial Value

• Bits 3, 2, 1 – SM2..0: Sleep Mode Select Bits 2, 1, and 0

These bits select between the six available sleep modes as shown in Table 7-1.

Table 7-1.

Sleep Mode Select

SM2

SM1

SM0

Sleep Mode

Idle

0

1

0

1

0

1

0

1

0

1

0

1

0

1

ADC Noise Reduction

Power-down

Power-save

Reserved

Standby⁽¹⁾

Extended Standby⁽¹⁾

Note:

1. Standby modes are only recommended for use with external crystals or resonators.

• Bit 1 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP

instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s

purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of

the SLEEP instruction and to clear it immediately after waking up.

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7.1

Idle Mode

When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle

mode, stopping the CPU but allowing the USB, SPI, USART, Analog Comparator, ADC, 2-wire

Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This

sleep mode basically halts clk_CPUand clk_FLASH, while allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal

ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the

Analog Comparator interrupt is not required, the Analog Comparator can be powered down by

setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will

reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-

cally when this mode is entered.

7.2

ADC Noise Reduction Mode

When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC

Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, 2-wire

Serial Interface address match, Timer/Counter2 and the Watchdog to continue operating (if

enabled). This sleep mode basically halts clkI/O, clkCPU, and clkFLASH, while allowing the

other clocks to run (including clkUSB).

This improves the noise environment for the ADC, enabling higher resolution measurements. If

the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the

ADC Conversion Complete interrupt, only an External Reset, a Watchdog System Reset, a

Watchdog interrupt, a Brown-out Reset, a 2-wire serial interface interrupt, a Timer/Counter2

interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT7:4 or a pin

change interrupt can wakeup the MCU from ADC Noise Reduction mode.

7.3

Power-down Mode

When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-

down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the 2-

wire Serial Interface, and the Watchdog continue operating (if enabled). Only an External Reset,

a Watchdog Reset, a Brown-out Reset, 2-wire Serial Interface address match, an external level

interrupt on INT7:4, an external interrupt on INT3:0, a pin change interrupt or an asynchronous

USB interrupt sources (VBUSTI, WAKEUPI, IDTI and HWUPI), can wake up the MCU. This

sleep mode basically halts all generated clocks, allowing operation of asynchronous modules

only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed

level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 96

for details.

When waking up from Power-down mode, there is a delay from the wake-up condition occurs

until the wake-up becomes effective. This allows the clock to restart and become stable after

having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the

Reset Time-out period, as described in “Clock Sources” on page 40.

7.4

Power-save Mode

When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-

save mode. This mode is identical to Power-down, with one exception:

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If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up from

either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding

Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Global Interrupt Enable bit in

SREG is set.

If Timer/Counter2 is not running, Power-down mode is recommended instead of Power-save

mode.

The Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save

mode. If the Timer/Counter2 is not using the asynchronous clock, the Timer/Counter Oscillator is

stopped during sleep. If the Timer/Counter2 is not using the synchronous clock, the clock source

is stopped during sleep. Note that even if the synchronous clock is running in Power-save, this

clock is only available for the Timer/Counter2.

7.5

Standby Mode

When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the

SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down

with the exception that the Oscillator is kept running. From Standby mode, the device wakes up

in six clock cycles.

7.6

Extended Standby Mode

When the SM2..0 bits are 111 and an external crystal/resonator clock option is selected, the

SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to

Power-save mode with the exception that the Oscillator is kept running. From Extended Standby

mode, the device wakes up in six clock cycles.

Table 7-2.

Active Clock Domains and Wake-up Sources in the Different Sleep Modes.

Active Clock Domains

Oscillators

Wake-up Sources

Sleep Mode

Idle

X

X⁽²⁾

X

ADCNRM

Power-down

Power-save

Standby⁽¹⁾

X⁽³⁾

X⁽²⁾

X

X⁽²⁾

X

Extended

Standby

X⁽²⁾

X⁽³⁾

X

Notes: 1. Only recommended with external crystal or resonator selected as clock source.

2. If Timer/Counter2 is running in asynchronous mode.

3. For INT7:4, only level interrupt.

4. Asynchronous USB interrupts are VBUSTI, WAKEUPI, IDTI, WAKEUPI and HWUPI.

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7.7

Power Reduction Register

The Power Reduction Register, PRR, provides a method to stop the clock to individual peripher-

als to reduce power consumption. The current state of the peripheral is frozen and the I/O

registers can not be read or written. Resources used by the peripheral when stopping the clock

will remain occupied, hence the peripheral should in most cases be disabled before stopping the

clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the

same state as before shutdown.

Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall

power consumption. See “Supply Current of IO modules” on page 429 for examples. In all other

sleep modes, the clock is already stopped.

7.7.1

Power Reduction Register 0 - PRR0

Bit

7

6

5

4

–

R

0

3

2

1

-

0

PRTWI

R/W

0

PRTIM2

R/W

0

PRTIM0

R/W

0

PRTIM1

R/W

0

PRSPI

R/W

0

PRADC

R/W

0

PRR0

Read/Write

Initial Value

R

0

• Bit 7 - PRTWI: Power Reduction TWI

Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When

waking up the TWI again, the TWI should be re initialized to ensure proper operation.

• Bit 6 - PRTIM2: Power Reduction Timer/Counter2

Writing a logic one to this bit shuts down the Timer/Counter2 module in synchronous mode (AS2

is 0). When the Timer/Counter2 is enabled, operation will continue like before the shutdown.

• Bit 5 - PRTIM0: Power Reduction Timer/Counter0

Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0

is enabled, operation will continue like before the shutdown.

• Bit 4 - Res: Reserved bit

This bit is reserved and will always read as zero.

• Bit 3 - PRTIM1: Power Reduction Timer/Counter1

Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1

is enabled, operation will continue like before the shutdown.

• Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface

Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to

the module. When waking up the SPI again, the SPI should be re initialized to ensure proper

operation.

• Bit 1 - Res: Reserved bit

These bits are reserved and will always read as zero.

• Bit 0 - PRADC: Power Reduction ADC

Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down.

The analog comparator cannot use the ADC input MUX when the ADC is shut down.

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AT90USB64/128

7.7.2

Power Reduction Register 1 - PRR1

Bit

7

6

–

R

0

5

–

R

0

4

–

R

0

3

2

–

R

0

1

–

R

0

PRUSB

R/W

0

PRTIM3

R/W

0

PRUSART1

PRR1

Read/Write

Initial Value

R/W

0

• Bit 7 - PRUSB: Power Reduction USB

Writing a logic one to this bit shuts down the USB by stopping the clock to the module. When

waking up the USB again, the USB should be re initialized to ensure proper operation.

• Bit 6..4 - Res: Reserved bits

These bits are reserved and will always read as zero.

• Bit 3 - PRTIM3: Power Reduction Timer/Counter3

Writing a logic one to this bit shuts down the Timer/Counter3 module. When the Timer/Counter3

is enabled, operation will continue like before the shutdown.

• Bit 2..1 - Res: Reserved bits

These bits are reserved and will always read as zero.

• Bit 0 - PRUSART1: Power Reduction USART1

Writing a logic one to this bit shuts down the USART1 by stopping the clock to the module.

When waking up the USART1 again, the USART1 should be re initialized to ensure proper

operation.

7.8

Minimizing Power Consumption

There are several issues to consider when trying to minimize the power consumption in an AVR

controlled system. In general, sleep modes should be used as much as possible, and the sleep

mode should be selected so that as few as possible of the device’s functions are operating. All

functions not needed should be disabled. In particular, the following modules may need special

consideration when trying to achieve the lowest possible power consumption.

7.8.1

7.8.2

Analog to Digital Converter

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-

abled before entering any sleep mode. When the ADC is turned off and on again, the next

conversion will be an extended conversion. Refer to “Analog to Digital Converter - ADC” on page

316 for details on ADC operation.

Analog Comparator

When entering Idle mode, the Analog Comparator should be disabled if not used. When entering

ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes,

the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up

to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all

sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep

mode. Refer to “Analog Comparator” on page 313 for details on how to configure the Analog

Comparator.

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7.8.3

7.8.4

Brown-out Detector

If the Brown-out Detector is not needed by the application, this module should be turned off. If

the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep

modes, and hence, always consume power. In the deeper sleep modes, this will contribute sig-

nificantly to the total current consumption. Refer to “Brown-out Detection” on page 61 for details

on how to configure the Brown-out Detector.

Internal Voltage Reference

The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the

Analog Comparator or the ADC. If these modules are disabled as described in the sections

above, the internal voltage reference will be disabled and it will not be consuming power. When

turned on again, the user must allow the reference to start up before the output is used. If the

reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Volt-

age Reference” on page 64 for details on the start-up time.

7.8.5

7.8.6

Watchdog Timer

If the Watchdog Timer is not needed in the application, the module should be turned off. If the

Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume

power. In the deeper sleep modes, this will contribute significantly to the total current consump-

tion. Refer to “Interrupts” on page 70 for details on how to configure the Watchdog Timer.

Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. The

most important is then to ensure that no pins drive resistive loads. In sleep modes where both

the I/O clock (clk_I/O) and the ADC clock (clk_ADC) are stopped, the input buffers of the device will

be disabled. This ensures that no power is consumed by the input logic when not needed. In

some cases, the input logic is needed for detecting wake-up conditions, and it will then be

enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 78 for details on

which pins are enabled. If the input buffer is enabled and the input signal is left floating or have

an analog signal level close to V_CC/2, the input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal

level close to V_CC/2 on an input pin can cause significant current even in active mode. Digital

input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and

DIDR0). Refer to “Digital Input Disable Register 1 – DIDR1” on page 315 and “Digital Input Dis-

able Register 1 – DIDR1” on page 315 for details.

7.8.7

On-chip Debug System

If the On-chip debug system is enabled by the OCDEN Fuse and the chip enters sleep mode,

the main clock source is enabled, and hence, always consumes power. In the deeper sleep

modes, this will contribute significantly to the total current consumption.

There are three alternative ways to disable the OCD system:

• Disable the OCDEN Fuse.

• Disable the JTAGEN Fuse.

• Write one to the JTD bit in MCUCR.

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AT90USB64/128

8. System Control and Reset

8.0.1

Resetting the AVR

During reset, all I/O Registers are set to their initial values, and the program starts execution

from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute

Jump – instruction to the reset handling routine. If the program never enables an interrupt

source, the Interrupt Vectors are not used, and regular program code can be placed at these

locations. This is also the case if the Reset Vector is in the Application section while the Interrupt

Vectors are in the Boot section or vice versa. The circuit diagram in Figure 8-1 shows the reset

logic. Table 8-1 defines the electrical parameters of the reset circuitry.

The I/O ports of the AVR are immediately reset to their initial state when a reset source goes

active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the internal

reset. This allows the power to reach a stable level before normal operation starts. The time-out

period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-

ferent selections for the delay period are presented in “Clock Sources” on page 40.

8.0.2

Reset Sources

The AT90USB64/128 has five sources of reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset

threshold (V_POT).

• External Reset. The MCU is reset when a low level is present on the RESET pin for longer

than the minimum pulse length.

• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the

Watchdog is enabled.

• Brown-out Reset. The MCU is reset when the supply voltage V_CCis below the Brown-out

Reset threshold (V_BOT) and the Brown-out Detector is enabled.

• JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one

of the scan chains of the JTAG system. Refer to the section “IEEE 1149.1 (JTAG) Boundary-

scan” on page 341 for details.

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7593D–AVR–07/06

Figure 8-1. Reset Logic

DATA BUS

MCU Status

Register (MCUSR)

Power-on Reset

Circuit

Brown-out

Reset Circuit

BODLEVEL [2..0]

Pull-up Resistor

SPIKE

FILTER

JTAG Reset

Register

Watchdog

Oscillator

Delay Counters

Clock

CK

Generator

TIMEOUT

CKSEL[3:0]

SUT[1:0]

Table 8-1.

Symbol Parameter

Power-on Reset Threshold

Reset Characteristics⁽¹⁾

Condition

Min

Typ

Max Units

TBD TBD TBD

V

Voltage (rising)

V_POT

Power-on Reset Threshold

Voltage (falling)⁽²⁾

TBD TBD TBD

V

V_RST

t_RST

RESET Pin Threshold Voltage

Minimum pulse width on RESET

ns

Notes: 1. Values are guidelines only. Actual values are TBD.

2. The Power-on Reset will not work unless the supply voltage has been below V_POT(falling)

8.0.3

Power-on Reset

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level

is defined in Table 8-1. The POR is activated whenever V_CCis below the detection level. The

POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply

voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the

Power-on Reset threshold voltage invokes the delay counter, which determines how long the

device is kept in RESET after V_CCrise. The RESET signal is activated again, without any delay,

when V_CCdecreases below the detection level.

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AT90USB64/128

Figure 8-2. MCU Start-up, RESET Tied to V_CC

V_POT

V_CC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

Figure 8-3. MCU Start-up, RESET Extended Externally

V_POT

V_CC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

8.0.4

External Reset

An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the

minimum pulse width (see Table 8-1) will generate a reset, even if the clock is not running.

Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the

Reset Threshold Voltage – V_RST– on its positive edge, the delay counter starts the MCU after

the Time-out period – t_TOUT– has expired.

Figure 8-4. External Reset During Operation

CC

8.0.5

Brown-out Detection

AT90USB64/128 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V_CClevel

during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be

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7593D–AVR–07/06

selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free

Brown-out Detection. The hysteresis on the detection level should be interpreted as V_BOT+

_BOT+ V_HYST/2 and V_BOT-= V_BOT- V_HYST/2.

=

V

Table 8-2.

BODLEVEL Fuse Coding⁽¹⁾

BODLEVEL 2..0 Fuses Min V_BOT

Typ V_BOT

Max V_BOT

Units

111

110

101

100

011

010

001

000

BOD Disabled

2.0

2.2

2.4

2.6

3.4

3.5

4.3

V

Note:

1. V_BOTmay be below nominal minimum operating voltage for some devices. For devices where

this is the case, the device is tested down to V_CC= V_BOTduring the production test. This guar-

antees that a Brown-Out Reset will occur before V_CCdrops to a voltage where correct

operation of the microcontroller is no longer guaranteed. The test is performed using

BODLEVEL = 110 for AT90USB64/128 and BODLEVEL = 101 for AT90USB64/128L.

Table 8-3.

Symbol

V_HYST

Brown-out Characteristics

Parameter

Min

Typ

Max

Units

mV

Brown-out Detector Hysteresis

Min Pulse Width on Brown-out Reset

50

t_BOD

ns

When the BOD is enabled, and V_CCdecreases to a value below the trigger level (V_BOT-in Figure

8-5), the Brown-out Reset is immediately activated. When V_CCincreases above the trigger level

(V_BOT+in Figure 8-5), the delay counter starts the MCU after the Time-out period t_TOUThas

expired.

The BOD circuit will only detect a drop in V_CCif the voltage stays below the trigger level for

longer than t_BODgiven in Table 8-1.

Figure 8-5. Brown-out Reset During Operation

V_BOT+

V_CC

V_BOT-

RESET

t

TOUT

TIME-OUT

INTERNAL

RESET

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AT90USB64/128

8.0.6

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On

the falling edge of this pulse, the delay timer starts counting the Time-out period t_TOUT. Refer to

page 64 for details on operation of the Watchdog Timer.

Figure 8-6. Watchdog Reset During Operation

CC

CK

8.0.7

MCU Status Register – MCUSR

The MCU Status Register provides information on which reset source caused an MCU reset.

Bit

7

–

R

0

6

–

R

0

5

–

R

0

4

3

2

1

0

JTRF

R/W

WDRF

R/W

BORF

R/W

EXTRF

R/W

PORF

R/W

MCUSR

Read/Write

Initial Value

See Bit Description

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by

the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic

zero to the flag.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.

To make use of the Reset Flags to identify a reset condition, the user should read and then

Reset the MCUSR as early as possible in the program. If the register is cleared before another

reset occurs, the source of the reset can be found by examining the Reset Flags.

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8.1

Internal Voltage Reference

AT90USB64/128 features an internal bandgap reference. This reference is used for Brown-out

Detection, and it can be used as an input to the Analog Comparator or the ADC.

8.1.1

Voltage Reference Enable Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used. The

start-up time is given in Table 8-4. To save power, the reference is not always turned on. The

reference is on during the following situations:

1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse).

2. When the bandgap reference is connected to the Analog Comparator (by setting the

ACBG bit in ACSR).

3. When the ADC is enabled.

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user

must always allow the reference to start up before the output from the Analog Comparator or

ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three

conditions above to ensure that the reference is turned off before entering Power-down mode.

Table 8-4.

Symbol Parameter

V_BGBandgap reference voltage

t_BG

Internal Voltage Reference Characteristics⁽¹⁾

Condition Min

Typ

1.1

40

Max Units

TBD

70

V

Bandgap reference start-up time

µs

Bandgap reference current

consumption

I_BG

TBD

10

TBD

µA

Note:

1. Values are guidelines only. Actual values are TBD.

8.2

Watchdog Timer

AT90USB64/128 has an Enhanced Watchdog Timer (WDT). The main features are:

• Clocked from separate On-chip Oscillator

• 3 Operating modes

– Interrupt

– System Reset

– Interrupt and System Reset

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AT90USB64/128

• Selectable Time-out period from 16ms to 8s

• Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode

Figure 8-7. Watchdog Timer

128kHz

OSCILLATOR

WDP0

WDP1

WDP2

WDP3

WATCHDOG

RESET

WDE

WDIF

WDIE

MCU RESET

INTERRUPT

The Watchdog Timer (WDT) is a timer counting cycles of a separate on-chip 128 kHz oscillator.

The WDT gives an interrupt or a system reset when the counter reaches a given time-out value.

In normal operation mode, it is required that the system uses the WDR - Watchdog Timer Reset

- instruction to restart the counter before the time-out value is reached. If the system doesn't

restart the counter, an interrupt or system reset will be issued.

In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used

to wake the device from sleep-modes, and also as a general system timer. One example is to

limit the maximum time allowed for certain operations, giving an interrupt when the operation

has run longer than expected. In System Reset mode, the WDT gives a reset when the timer

expires. This is typically used to prevent system hang-up in case of runaway code. The third

mode, Interrupt and System Reset mode, combines the other two modes by first giving an inter-

rupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown

by saving critical parameters before a system reset.

The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to Sys-

tem Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt

mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, alter-

ations to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE

and changing time-out configuration is as follows:

1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE)

and WDE. A logic one must be written to WDE regardless of the previous value of the

WDE bit.

2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as

desired, but with the WDCE bit cleared. This must be done in one operation.

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7593D–AVR–07/06

The following code example shows one assembly and one C function for turning off the Watch-

dog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts

globally) so that no interrupts will occur during the execution of these functions.

Assembly Code Example⁽¹⁾

WDT_off:

; Turn off global interrupt

cli

; Reset Watchdog Timer

wdr

; Clear WDRF in MCUSR

in

andi r16, (0xff & (0<<WDRF))

out MCUSR, r16

r16, MCUSR

; Write logical one to WDCE and WDE

; Keep old prescaler setting to prevent unintentional time-out

in

r16, WDTCSR

ori

out

r16, (1<<WDCE) | (1<<WDE)

WDTCSR, r16

; Turn off WDT

ldi

out

r16, (0<<WDE)

WDTCSR, r16

; Turn on global interrupt

sei

ret

C Code Example⁽¹⁾

void WDT_off(void)

{

__disable_interrupt();

__watchdog_reset();

/* Clear WDRF in MCUSR */

MCUSR &= ~(1<<WDRF);

/* Write logical one to WDCE and WDE */

/* Keep old prescaler setting to prevent unintentional time-out

*/

WDTCSR |= (1<<WDCE) | (1<<WDE);

/* Turn off WDT */

WDTCSR = 0x00;

__enable_interrupt();

}

Note:

1. The example code assumes that the part specific header file is included.

Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out

condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not

set up to handle the Watchdog, this might lead to an eternal loop of time-out resets. To avoid this

situation, the application software should always clear the Watchdog System Reset Flag

(WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use.

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AT90USB64/128

The following code example shows one assembly and one C function for changing the time-out

value of the Watchdog Timer.

Assembly Code Example⁽¹⁾

WDT_Prescaler_Change:

; Turn off global interrupt

cli

; Reset Watchdog Timer

wdr

; Start timed sequence

in

r16, WDTCSR

ori

out

r16, (1<<WDCE) | (1<<WDE)

WDTCSR, r16

; -- Got four cycles to set the new values from here -

; Set new prescaler(time-out) value = 64K cycles (~0.5 s)

ldi

out

r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0)

WDTCSR, r16

; -- Finished setting new values, used 2 cycles -

; Turn on global interrupt

sei

ret

C Code Example⁽¹⁾

void WDT_Prescaler_Change(void)

{

__disable_interrupt();

__watchdog_reset();

/* Start timed equence */

WDTCSR |= (1<<WDCE) | (1<<WDE);

/* Set new prescaler(time-out) value = 64K cycles (~0.5 s) */

WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0);

__enable_interrupt();

}

Note:

1. The example code assumes that the part specific header file is included.

Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change

in the WDP bits can result in a time-out when switching to a shorter time-out period.

8.2.1

Watchdog Timer Control Register - WDTCSR

Bit

7

6

5

4

3

2

1

0

WDIF

WDIE

WDP3

R/W

0

WDCE

R/W

0

WDE

R/W

X

WDP2

R/W

0

WDP1

R/W

0

WDP0

R/W

0

WDTCSR

Read/Write

Initial Value

R/W

0

R/W

0

• Bit 7 - WDIF: Watchdog Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config-

ured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt

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handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in

SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.

• Bit 6 - WDIE: Watchdog Interrupt Enable

When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is

enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt

Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs.

If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in

the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE

and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is use-

ful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and

System Reset Mode, WDIE must be set after each interrupt. This should however not be done

within the interrupt service routine itself, as this might compromise the safety-function of the

Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a Sys-

tem Reset will be applied.

Table 8-5.

Watchdog Timer Configuration

WDTON

WDE

WDIE

Mode

Action on Time-out

None

0

1

0

1

0

Stopped

Interrupt Mode

System Reset Mode

Interrupt

Reset

Interrupt and System

Reset Mode

Interrupt, then go to

System Reset Mode

0

1

x

1

x

System Reset Mode

Reset

• Bit 4 - WDCE: Watchdog Change Enable

This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit,

and/or change the prescaler bits, WDCE must be set.

Once written to one, hardware will clear WDCE after four clock cycles.

• Bit 3 - WDE: Watchdog System Reset Enable

WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is

set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during con-

ditions causing failure, and a safe start-up after the failure.

• Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0

The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run-

ning. The different prescaling values and their corresponding time-out periods are shown in

Table 8-6 on page 69.

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AT90USB64/128

.

Table 8-6.

Watchdog Timer Prescale Select

Number of WDT Oscillator

Cycles

Typical Time-out at

V_CC= 5.0V

WDP3 WDP2 WDP1 WDP0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2K (2048) cycles

4K (4096) cycles

16 ms

32 ms

64 ms

0.125 s

0.25 s

0.5 s

8K (8192) cycles

16K (16384) cycles

32K (32768) cycles

64K (65536) cycles

128K (131072) cycles

256K (262144) cycles

512K (524288) cycles

1024K (1048576) cycles

1.0 s

2.0 s

4.0 s

8.0 s

Reserved

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9. Interrupts

This section describes the specifics of the interrupt handling as performed in AT90USB64/128.

For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling”

on page 16.

9.1

Interrupt Vectors in AT90USB64/128

Table 9-1.

Reset and Interrupt Vectors

Program

Vector

No.

Address⁽²⁾Source

Interrupt Definition

External Pin, Power-on Reset, Brown-out Reset,

Watchdog Reset, and JTAG AVR Reset

1

$0000⁽¹⁾

RESET

2

3

$0002

$0004

$0006

$0008

$000A

$000C

$000E

$0010

$0012

$0014

INT0

External Interrupt Request 0

External Interrupt Request 1

External Interrupt Request 2

External Interrupt Request 3

External Interrupt Request 4

External Interrupt Request 5

External Interrupt Request 6

External Interrupt Request 7

Pin Change Interrupt Request 0

USB General Interrupt request

INT1

4

INT2

5

INT3

6

INT4

7

INT5

8

INT6

9

INT7

10

11

PCINT0

USB General

USB

Endpoint/Pipe

12

$0016

USB ENdpoint/Pipe Interrupt request

Watchdog Time-out Interrupt

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

$0018

$001A

$001C

$001E

$0020

$0022

$0024

$0026

$0028

$002A

$002C

$002E

$0030

$0032

$0034

$0036

WDT

TIMER2 COMPA Timer/Counter2 Compare Match A

TIMER2 COMPB Timer/Counter2 Compare Match B

TIMER2 OVF

TIMER1 CAPT

Timer/Counter2 Overflow

Timer/Counter1 Capture Event

TIMER1 COMPA Timer/Counter1 Compare Match A

TIMER1 COMPB Timer/Counter1 Compare Match B

TIMER1 COMPC Timer/Counter1 Compare Match C

TIMER1 OVF

Timer/Counter1 Overflow

TIMER0 COMPA Timer/Counter0 Compare Match A

TIMER0 COMPB Timer/Counter0 Compare match B

TIMER0 OVF

SPI, STC

Timer/Counter0 Overflow

SPI Serial Transfer Complete

USART1 Rx Complete

USART1 RX

USART1 UDRE

USART1TX

USART1 Data Register Empty

USART1 Tx Complete

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Table 9-1.

Reset and Interrupt Vectors (Continued)

Program

Vector

No.

Address⁽²⁾Source

Interrupt Definition

Analog Comparator

ADC Conversion Complete

EEPROM Ready

29

30

31

32

33

34

35

36

37

38

$0038

$003A

$003C

$003E

$0040

$0042

$0044

$0046

$0048

$004A

ANALOG COMP

ADC

EE READY

TIMER3 CAPT

Timer/Counter3 Capture Event

TIMER3 COMPA Timer/Counter3 Compare Match A

TIMER3 COMPB Timer/Counter3 Compare Match B

TIMER3 COMPC Timer/Counter3 Compare Match C

TIMER3 OVF

TWI

Timer/Counter3 Overflow

2-wire Serial Interface

SPM READY

Store Program Memory Ready

Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at

reset, see “Memory Programming” on page 368.

2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot

Flash Section. The address of each Interrupt Vector will then be the address in this table

added to the start address of the Boot Flash Section.

Table 9-2 shows reset and Interrupt Vectors placement for the various combinations of

BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt

Vectors are not used, and regular program code can be placed at these locations. This is also

the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the

Boot section or vice versa.

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Table 9-2.

Reset and Interrupt Vectors Placement⁽¹⁾

BOOTRST

IVSEL

Reset Address

0x0000

Interrupt Vectors Start Address

0x0002

1

0

1

0

1

0x0000

Boot Reset Address + 0x0002

0x0002

Boot Reset Address

Boot Reset Address + 0x0002

Note:

1. The Boot Reset Address is shown in Table 28-8 on page 366. For the BOOTRST Fuse “1”

means unprogrammed while “0” means programmed.

9.1.1

9.1.2

Moving Interrupts Between Application and Boot Space

The General Interrupt Control Register controls the placement of the Interrupt Vector table.

MCU Control Register – MCUCR

Bit

7

6

–

R

0

5

–

R

0

4

3

–

R

0

2

–

R

0

1

0

JTD

R/W

0

PUD

R/W

0

IVSEL

R/W

0

IVCE

R/W

0

MCUCR

Read/Write

Initial Value

• Bit 1 – IVSEL: Interrupt Vector Select

When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash

memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot

Loader section of the Flash. The actual address of the start of the Boot Flash Section is deter-

mined by the BOOTSZ Fuses. Refer to the section “Memory Programming” on page 368 for

details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must

be followed to change the IVSEL bit:

a. Write the Interrupt Vector Change Enable (IVCE) bit to one.

b. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.

Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled

in the cycle IVCE is set, and they remain disabled until after the instruction following the write to

IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status

Register is unaffected by the automatic disabling.

Note:

If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is pro-

grammed, interrupts are disabled while executing from the Application section. If Interrupt Vectors

are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are dis-

abled while executing from the Boot Loader section. Refer to the section “Memory Programming”

on page 368 for details on Boot Lock bits.

• Bit 0 – IVCE: Interrupt Vector Change Enable

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The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by

hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable

interrupts, as explained in the IVSEL description above. See Code Example below.

Assembly Code Example

Move_interrupts:

; Enable change of Interrupt Vectors

ldi r16, (1<<IVCE)

out MCUCR, r16

; Move interrupts to Boot Flash section

ldi r16, (1<<IVSEL)

out MCUCR, r16

ret

C Code Example

void Move_interrupts(void)

{

/* Enable change of Interrupt Vectors */

MCUCR = (1<<IVCE);

/* Move interrupts to Boot Flash section */

MCUCR = (1<<IVSEL);

}

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10. I/O-Ports

10.1 Introduction

All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.

This means that the direction of one port pin can be changed without unintentionally changing

the direction of any other pin with the SBI and CBI instructions. The same applies when chang-

ing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as

input). Each output buffer has symmetrical drive characteristics with both high sink and source

capability. The pin driver is strong enough to drive LED displays directly. All port pins have indi-

vidually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have

protection diodes to both V_CCand Ground as indicated in Figure 10-1. Refer to “Electrical Char-

acteristics” on page 400 for a complete list of parameters.

Figure 10-1. I/O Pin Equivalent Schematic

All registers and bit references in this section are written in general form. A lower case “x” repre-

sents the numbering letter for the port, and a lower case “n” represents the bit number. However,

when using the register or bit defines in a program, the precise form must be used. For example,

PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Regis-

ters and bit locations are listed in “Register Description for I/O-Ports” on page 92.

Three I/O memory address locations are allocated for each port, one each for the Data Register

– PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins

I/O location is read only, while the Data Register and the Data Direction Register are read/write.

However, writing a logic one to a bit in the PINx Register, will result in a toggle in the correspond-

ing bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the

pull-up function for all pins in all ports when set.

Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page

75. Most port pins are multiplexed with alternate functions for the peripheral features on the

device. How each alternate function interferes with the port pin is described in “Alternate Port

Functions” on page 79. Refer to the individual module sections for a full description of the alter-

nate functions.

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Note that enabling the alternate function of some of the port pins does not affect the use of the

other pins in the port as general digital I/O.

10.2 Ports as General Digital I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a func-

tional description of one I/O-port pin, here generically called Pxn.

Figure 10-2. General Digital I/O⁽¹⁾

PUD

Q

D

DDxn

Q _CLR

WDx

RDx

RESET

1

0

Q

D

Pxn

PORTxn

Q _CLR

RESET

WPx

WRx

SLEEP

RRx

SYNCHRONIZER

RPx

D

Q

D

L

Q

PINxn

Q

clk _I/O

WDx:

RDx:

WRx:

RRx:

RPx:

WPx:

WRITE DDRx

READ DDRx

WRITE PORTx

PUD:

SLEEP:

clk_I/O

PULLUP DISABLE

SLEEP CONTROL

I/O CLOCK

:

READ PORTx REGISTER

READ PORTx PIN

WRITE PINx REGISTER

Note:

1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk_I/O

,

SLEEP, and PUD are common to all ports.

10.2.1

Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register

Description for I/O-Ports” on page 92, the DDxn bits are accessed at the DDRx I/O address, the

PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,

Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input

pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is

activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to

be configured as an output pin. The port pins are tri-stated when reset condition becomes active,

even if no clocks are running.

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7593D–AVR–07/06

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven

high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port

pin is driven low (zero).

10.2.2

10.2.3

Toggling the Pin

Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.

Note that the SBI instruction can be used to toggle one single bit in a port.

Switching Between Input and Output

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}

= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output

low ({DDxn, PORTxn} = 0b10) occurs. Normally, the pull-up enabled state is fully acceptable, as

a high-impedant environment will not notice the difference between a strong high driver and a

pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-

ups in all ports.

Switching between input with pull-up and output low generates the same problem. The user

must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}

= 0b11) as an intermediate step.

Table 10-1 summarizes the control signals for the pin value.

Table 10-1. Port Pin Configurations

PUD

DDxn PORTxn (in MCUCR)

I/O

Pull-up Comment

0

1

X

0

Input

No

Tri-state (Hi-Z)

Pxn will source current if ext. pulled

low.

Input

Yes

0

1

0

1

X

Input

Output

No

Tri-state (Hi-Z)

Output Low (Sink)

Output High (Source)

10.2.4

Reading the Pin Value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through the

PINxn Register bit. As shown in Figure 10-2, the PINxn Register bit and the preceding latch con-

stitute a synchronizer. This is needed to avoid metastability if the physical pin changes value

near the edge of the internal clock, but it also introduces a delay. Figure 10-3 shows a timing dia-

gram of the synchronization when reading an externally applied pin value. The maximum and

minimum propagation delays are denoted t_pd,maxand t_pd,minrespectively.

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AT90USB64/128

Figure 10-3. Synchronization when Reading an Externally Applied Pin value

SYSTEM CLK

INSTRUCTIONS

SYNC LATCH

PINxn

XXX

in r17, PINx

0x00

t_{pd, max}

0xFF

r17

t_{pd, min}

Consider the clock period starting shortly after the first falling edge of the system clock. The latch

is closed when the clock is low, and goes transparent when the clock is high, as indicated by the

shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock

goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-

cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed

between ½ and 1½ system clock period depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted as indi-

cated in Figure 10-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of

the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.

Figure 10-4. Synchronization when Reading a Software Assigned Pin Value

SYSTEM CLK

0xFF

r16

out PORTx, r16

nop

in r17, PINx

INSTRUCTIONS

SYNC LATCH

PINxn

0x00

t_pd

0xFF

r17

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define

the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin

values are read back again, but as previously discussed, a nop instruction is included to be able

to read back the value recently assigned to some of the pins.

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Assembly Code Example⁽¹⁾

...

; Define pull-ups and set outputs high

; Define directions for port pins

ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)

ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)

out PORTB,r16

out DDRB,r17

; Insert nop for synchronization

nop

; Read port pins

in

r16,PINB

...

C Code Example

unsigned char i;

...

/* Define pull-ups and set outputs high */

/* Define directions for port pins */

PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);

DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);

/* Insert nop for synchronization*/

__no_operation();

/* Read port pins */

i = PINB;

...

Note:

1. For the assembly program, two temporary registers are used to minimize the time from pull-

ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3

as low and redefining bits 0 and 1 as strong high drivers.

10.2.5

Digital Input Enable and Sleep Modes

As shown in Figure 10-2, the digital input signal can be clamped to ground at the input of the

schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in

Power-down mode, Power-save mode, and Standby mode to avoid high power consumption if

some input signals are left floating, or have an analog signal level close to V_CC/2.

SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt

request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various

other alternate functions as described in “Alternate Port Functions” on page 79.

If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as

“Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt

is not enabled, the corresponding External Interrupt Flag will be set when resuming from the

above mentioned Sleep mode, as the clamping in these sleep mode produces the requested

logic change.

10.2.6

78

Unconnected Pins

If some pins are unused, it is recommended to ensure that these pins have a defined level. Even

though most of the digital inputs are disabled in the deep sleep modes as described above, float-

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AT90USB64/128

ing inputs should be avoided to reduce current consumption in all other modes where the digital

inputs are enabled (Reset, Active mode and Idle mode).

The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.

In this case, the pull-up will be disabled during reset. If low power consumption during reset is

important, it is recommended to use an external pull-up or pull-down. Connecting unused pins

directly to V_CCor GND is not recommended, since this may cause excessive currents if the pin is

accidentally configured as an output.

10.3 Alternate Port Functions

Most port pins have alternate functions in addition to being general digital I/Os. Figure 10-5

shows how the port pin control signals from the simplified Figure 10-2 can be overridden by

alternate functions. The overriding signals may not be present in all port pins, but the figure

serves as a generic description applicable to all port pins in the AVR microcontroller family.

Figure 10-5. Alternate Port Functions⁽¹⁾

PUOExn

PUOVxn

1

PUD

0

DDOExn

DDOVxn

1

Q

D

0

DDxn

Q _CLR

WDx

RDx

PVOExn

PVOVxn

RESET

1

0

1

0

Pxn

Q

D

PORTxn

PTOExn

Q _CLR

DIEOExn

DIEOVxn

SLEEP

WPx

RESET

WRx

1

0

RRx

SYNCHRONIZER

RPx

SET

D

Q

D

L

Q

PINxn

_CLRQ

CLR

clk _I/O

DIxn

AIOxn

PUOExn: Pxn PULL-UP OVERRIDE ENABLE

PUOVxn: Pxn PULL-UP OVERRIDE VALUE

DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE

DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE

PVOExn: Pxn PORT VALUE OVERRIDE ENABLE

PVOVxn: Pxn PORT VALUE OVERRIDE VALUE

PUD:

WDx:

RDx:

RRx:

WRx:

RPx:

WPx:

PULLUP DISABLE

WRITE DDRx

READ DDRx

READ PORTx REGISTER

WRITE PORTx

READ PORTx PIN

WRITE PINx

DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE

DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE

clk_I/O

:

I/O CLOCK

SLEEP:

SLEEP CONTROL

DIxn:

DIGITAL INPUT PIN n ON PORTx

AIOxn:

ANALOG INPUT/OUTPUT PIN n ON PORTx

PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE

Note:

1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk_I/O

,

SLEEP, and PUD are common to all ports. All other signals are unique for each pin.

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Table 10-2 summarizes the function of the overriding signals. The pin and port indexes from Fig-

ure 10-5 are not shown in the succeeding tables. The overriding signals are generated internally

in the modules having the alternate function.

Table 10-2. Generic Description of Overriding Signals for Alternate Functions

Signal Name Full Name

Description

If this signal is set, the pull-up enable is controlled by the

PUOV signal. If this signal is cleared, the pull-up is

enabled when {DDxn, PORTxn, PUD} = 0b010.

Pull-up Override

Enable

PUOE

PUOV

DDOE

DDOV

If PUOE is set, the pull-up is enabled/disabled when

PUOV is set/cleared, regardless of the setting of the

DDxn, PORTxn, and PUD Register bits.

Pull-up Override

Value

If this signal is set, the Output Driver Enable is controlled

by the DDOV signal. If this signal is cleared, the Output

driver is enabled by the DDxn Register bit.

Data Direction

Override Enable

If DDOE is set, the Output Driver is enabled/disabled

when DDOV is set/cleared, regardless of the setting of

the DDxn Register bit.

Data Direction

Override Value

If this signal is set and the Output Driver is enabled, the

port value is controlled by the PVOV signal. If PVOE is

cleared, and the Output Driver is enabled, the port Value

is controlled by the PORTxn Register bit.

Port Value

Override Enable

PVOE

Port Value

Override Value

If PVOE is set, the port value is set to PVOV, regardless

of the setting of the PORTxn Register bit.

PVOV

PTOE

Port Toggle

Override Enable

If PTOE is set, the PORTxn Register bit is inverted.

If this bit is set, the Digital Input Enable is controlled by

the DIEOV signal. If this signal is cleared, the Digital Input

Enable is determined by MCU state (Normal mode, sleep

mode).

Digital Input

Enable Override

Enable

DIEOE

DIEOV

Digital Input

Enable Override

Value

If DIEOE is set, the Digital Input is enabled/disabled when

DIEOV is set/cleared, regardless of the MCU state

(Normal mode, sleep mode).

This is the Digital Input to alternate functions. In the

figure, the signal is connected to the output of the schmitt

trigger but before the synchronizer. Unless the Digital

Input is used as a clock source, the module with the

alternate function will use its own synchronizer.

DI

Digital Input

This is the Analog Input/output to/from alternate

functions. The signal is connected directly to the pad, and

can be used bi-directionally.

Analog

Input/Output

AIO

The following subsections shortly describe the alternate functions for each port, and relate the

overriding signals to the alternate function. Refer to the alternate function description for further

details.

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10.3.1

MCU Control Register – MCUCR

Bit

7

6

–

R

0

5

–

R

0

4

3

–

R

0

2

–

R

0

1

0

JTD

R/W

0

PUD

R/W

0

IVSEL

R/W

0

IVCE

R/W

0

MCUCR

Read/Write

Initial Value

• Bit 4 – PUD: Pull-up Disable

When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and

PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Con-

figuring the Pin” on page 75 for more details about this feature.

10.3.2

Alternate Functions of Port A

The Port A has an alternate function as the address low byte and data lines for the External

Memory Interface.

Table 10-3. Port A Pins Alternate Functions

Port Pin

PA7

Alternate Function

AD7 (External memory interface address and data bit 7)

AD6 (External memory interface address and data bit 6)

AD5 (External memory interface address and data bit 5)

AD4 (External memory interface address and data bit 4)

AD3 (External memory interface address and data bit 3)

AD2 (External memory interface address and data bit 2)

AD1 (External memory interface address and data bit 1)

AD0 (External memory interface address and data bit 0)

PA6

PA5

PA4

PA3

PA2

PA1

PA0

Table 10-4 and Table 10-5 relates the alternate functions of Port A to the overriding signals

shown in Figure 10-5 on page 79.

Table 10-4. Overriding Signals for Alternate Functions in PA7..PA4

Signal

Name

PA7/AD7

PA6/AD6

PA5/AD5

PA4/AD4

PUOE

SRE

~(WR | ADA⁽¹⁾) •

PORTA7 • PUD

~(WR | ADA) •

PORTA6 • PUD

~(WR | ADA) •

PORTA5 • PUD

~(WR | ADA) •

PORTA4 • PUD

PUOV

DDOE

DDOV

PVOE

SRE

WR | ADA

SRE

WR | ADA

SRE

WR | ADA

SRE

WR | ADA

SRE

A7 • ADA | D7

OUTPUT • WR

A6 • ADA | D6

OUTPUT • WR

A5 • ADA | D5

OUTPUT • WR

A4 • ADA | D4

OUTPUT • WR

PVOV

DIEOE

DIEOV

DI

0

D7 INPUT

–

D6 INPUT

–

D5 INPUT

–

D4 INPUT

–

AIO

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Note:

1. ADA is short for ADdress Active and represents the time when address is output. See “Exter-

nal Memory Interface” on page 30 for details.

Table 10-5. Overriding Signals for Alternate Functions in PA3..PA0

Signal

Name

PA3/AD3

PA2/AD2

PA1/AD1

PA0/AD0

PUOE

SRE

~(WR | ADA) •

PORTA3 • PUD

~(WR | ADA) •

PORTA2 • PUD

~(WR | ADA) •

PORTA1 • PUD

~(WR | ADA) •

PORTA0 • PUD

PUOV

DDOE

DDOV

PVOE

SRE

WR | ADA

SRE

WR | ADA

SRE

WR | ADA

SRE

WR | ADA

SRE

A3 • ADA | D3

OUTPUT • WR

A2• ADA | D2

OUTPUT • WR

A1 • ADA | D1

OUTPUT • WR

A0 • ADA | D0

OUTPUT • WR

PVOV

DIEOE

DIEOV

DI

0

D3 INPUT

–

D2 INPUT

–

D1 INPUT

–

D0 INPUT

–

AIO

10.3.3

Alternate Functions of Port B

The Port B pins with alternate functions are shown in Table 10-6.

Table 10-6. Port B Pins Alternate Functions

Port Pin Alternate Functions

OC0A/OC1C/PCINT7 (Output Compare and PWM Output A for Timer/Counter0,

Output Compare and PWM Output C for Timer/Counter1 or Pin Change Interrupt 7)

PB7

PB6

PB5

PB4

PB3

PB2

OC1B/PCINT6 (Output Compare and PWM Output B for Timer/Counter1 or Pin

Change Interrupt 6)

OC1A/PCINT5 (Output Compare and PWM Output A for Timer/Counter1 or Pin

Change Interrupt 5)

OC2A/PCINT4 (Output Compare and PWM Output A for Timer/Counter2 or Pin

Change Interrupt 4)

PDO/MISO/PCINT3 (Programming Data Output or SPI Bus Master Input/Slave

Output or Pin Change Interrupt 3)

PDI/MOSI/PCINT2 (Programming Data Input orSPI Bus Master Output/Slave Input

or Pin Change Interrupt 2)

PB1

PB0

SCK/PCINT1 (SPI Bus Serial Clock or Pin Change Interrupt 1)

SS/PCINT0 (SPI Slave Select input or Pin Change Interrupt 0)

The alternate pin configuration is as follows:

• OC0A/OC1C/PCINT7, Bit 7

OC0A, Output Compare Match A output: The PB7 pin can serve as an external output for the

Timer/Counter0 Output Compare. The pin has to be configured as an output (DDB7 set “one”) to

serve this function. The OC0A pin is also the output pin for the PWM mode timer function.

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OC1C, Output Compare Match C output: The PB7 pin can serve as an external output for the

Timer/Counter1 Output Compare C. The pin has to be configured as an output (DDB7 set (one))

to serve this function. The OC1C pin is also the output pin for the PWM mode timer function.

PCINT7, Pin Change Interrupt source 7: The PB7 pin can serve as an external interrupt source.

• OC1B/PCINT6, Bit 6

OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the

Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one))

to serve this function. The OC1B pin is also the output pin for the PWM mode timer function.

PCINT6, Pin Change Interrupt source 6: The PB7 pin can serve as an external interrupt source.

• OC1A/PCINT5, Bit 5

OC1A, Output Compare Match A output: The PB5 pin can serve as an external output for the

Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDB5 set (one))

to serve this function. The OC1A pin is also the output pin for the PWM mode timer function.

PCINT5, Pin Change Interrupt source 5: The PB7 pin can serve as an external interrupt source.

• OC2A/PCINT4, Bit 4

OC2A, Output Compare Match output: The PB4 pin can serve as an external output for the

Timer/Counter2 Output Compare. The pin has to be configured as an output (DDB4 set (one)) to

serve this function. The OC2A pin is also the output pin for the PWM mode timer function.

PCINT4, Pin Change Interrupt source 4: The PB7 pin can serve as an external interrupt source.

• PDO/MISO/PCINT3 – Port B, Bit 3

PDO, SPI Serial Programming Data Output. During Serial Program Downloading, this pin is

used as data output line for the AT90USB64/128.

MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a

master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is

enabled as a slave, the data direction of this pin is controlled by DDB3. When the pin is forced to

be an input, the pull-up can still be controlled by the PORTB3 bit.

PCINT3, Pin Change Interrupt source 3: The PB7 pin can serve as an external interrupt source.

• PDI/MOSI/PCINT2 – Port B, Bit 2

PDI, SPI Serial Programming Data Input. During Serial Program Downloading, this pin is used

as data input line for the AT90USB64/128.

MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a

slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is

enabled as a master, the data direction of this pin is controlled by DDB2. When the pin is forced

to be an input, the pull-up can still be controlled by the PORTB2 bit.

PCINT2, Pin Change Interrupt source 2: The PB7 pin can serve as an external interrupt source.

• SCK/PCINT1 – Port B, Bit 1

SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a

slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI0 is

enabled as a master, the data direction of this pin is controlled by DDB1. When the pin is forced

to be an input, the pull-up can still be controlled by the PORTB1 bit.

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PCINT1, Pin Change Interrupt source 1: The PB7 pin can serve as an external interrupt source.

• SS/PCINT0 – Port B, Bit 0

SS: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an

input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin is driven

low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB0.

When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit.

Table 10-7 and Table 10-8 relate the alternate functions of Port B to the overriding signals

shown in Figure 10-5 on page 79. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the

MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.

PCINT0, Pin Change Interrupt source 0: The PB7 pin can serve as an external interrupt source..

Table 10-7. Overriding Signals for Alternate Functions in PB7..PB4

Signal

Name

PB7/PCINT7/OC0A/

OC1C

PB6/PCINT6/OC

1B

PB5/PCINT5/OC PB4/PCINT4/OC

1A

2A

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

DIEOE

DIEOV

DI

0

OC0/OC1C ENABLE

OC1B ENABLE

OC1A ENABLE

OC2A ENABLE

OC0/OC1C

OC1B

OC1A

OC2A

PCINT7 • PCIE0

PCINT6 • PCIE0

PCINT5 • PCIE0

PCINT4 • PCIE0

1

PCINT7 INPUT

–

PCINT6 INPUT

–

PCINT5 INPUT

–

PCINT4 INPUT

–

AIO

Table 10-8. Overriding Signals for Alternate Functions in PB3..PB0

PB3/PD0/PCINT3/

MISO

PB2/PDI/PCINT2/

MOSI

PB1/PCINT1/

SCK

PB0/PCINT0/

SS

Signal

Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

SPE • MSTR

PORTB3 • PUD

SPE • MSTR

0

SPE • MSTR

PORTB2 • PUD

SPE • MSTR

0

SPE • MSTR

PORTB1 • PUD PORTB0 • PUD

SPE • MSTR

0

SPE • MSTR

0

SPE • MSTR

SPI SLAVE OUTPUT SPI MSTR OUTPUT SCK OUTPUT

PCINT1 •

PCINT0 •

PCIE0

DIEOE

DIEOV

DI

PCINT3 • PCIE0

1

PCINT2 • PCIE0

1

PCIE0

1

SPI MSTR INPUT

PCINT3 INPUT

SPI SLAVE INPUT

PCINT2 INPUT

SCK INPUT

SPI SS

PCINT1 INPUT

PCINT0 INPUT

AIO

–

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10.3.4

Alternate Functions of Port C

The Port C alternate function is as follows:

Table 10-9. Port C Pins Alternate Functions

Port Pin

Alternate Function

A15/IC.3/CLKO(External Memory interface address bit 15 or

Input Capture Timer 3 or CLK0 (Divided System Clock)

PC7

A14/OC.3A(External Memory interface address bit 14 or

Output Compare and PWM output A for Timer/Counter3)

PC6

PC5

PC4

PC3

A13/OC.3B(External Memory interface address bit 13 or

Output Compare and PWM output B for Timer/Counter3)

A12/OC.3C(External Memory interface address bit 12 or

Output Compare and PWM output C for Timer/Counter3)

A11/T.3(External Memory interface address bit 11or

Timer/Counter3 Clok Input)

PC2

PC1

PC0

A10(External Memory interface address bit 10)

A9(External Memory interface address bit 9)

A8(External Memory interface address bit 8)

Table 10-10 and Table 10-11 relate the alternate functions of Port C to the overriding signals

shown in Figure 10-5 on page 79.

Table 10-10. Overriding Signals for Alternate Functions in PC7..PC4

Signal

Name

PC7/A15/IC.3/CLK

O

PC6/A14/OC.3A

PC5/A13/OC.3B

PC4/A12/OC.3C

SRE •

PUOE

SRE • (XMM<1)

(XMM<2)|OC3A

enable

(XMM<3)|OC3B

enable

(XMM<4)|OC3C

enable

PUOV

DDOE

DDOV

PVOE

0

SRE • (XMM<1)

1

SRE • (XMM<2)

1

SRE • (XMM<3)

1

SRE • (XMM<4)

1

SRE • (XMM<1)

SRE • (XMM<2)

SRE • (XMM<3)

SRE • (XMM<4)

if (SRE.XMM<2)

then A14

if (SRE.XMM<2)

then A13

if (SRE.XMM<2)

then A12

PVOV

A15

else OC3A

else OC3B

else OC3C

DIEOE

DIEOV

DI

0

–

0

–

0

–

0

ICP3 input

–

AIO

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Table 10-11. Overriding Signals for Alternate Functions in PC3..PC0

Signal

Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

DIEOE

DIEOV

DI

PC3/A11/T.3

PC2/A10

PC1/A9

PC0/A8

SRE • (XMM<5)

SRE • (XMM<6)

SRE • (XMM<7)

0

SRE • (XMM<5)

SRE • (XMM<6)

SRE • (XMM<7)

1

SRE • (XMM<5)

SRE • (XMM<6)

SRE • (XMM<7)

A11

A10

0

A9

0

A8

0

T3 input

–

AIO

–

10.3.5

Alternate Functions of Port D

The Port D pins with alternate functions are shown in Table 10-12.

Table 10-12. Port D Pins Alternate Functions

Port Pin

PD7

Alternate Function

T0 (Timer/Counter0 Clock Input)

T1 (Timer/Counter1 Clock Input)

XCK1 (USART1 External Clock Input/Output)

ICP1 (Timer/Counter1 Input Capture Trigger)

PD6

PD5

PD4

PD3

INT3/TXD1 (External Interrupt3 Input or USART1 Transmit Pin)

INT2/RXD1 (External Interrupt2 Input or USART1 Receive Pin)

PD2

INT1/SDA/OC2B (External Interrupt1 Input or TWI Serial DAta or Output

Compare for Timer/Counter2)

PD1

PD0

INT0/SCL/OC0B (External Interrupt0 Input or TWI Serial CLock or Output

Compare for Timer/Counter0)

The alternate pin configuration is as follows:

• T0 – Port D, Bit 7

T0, Timer/Counter0 counter source.

• T1 – Port D, Bit 6

T1, Timer/Counter1 counter source.

• XCK1 – Port D, Bit 5

XCK1, USART1 External clock. The Data Direction Register (DDD5) controls whether the clock

is output (DDD5 set) or input (DDD5 cleared). The XCK1 pin is active only when the USART1

operates in Synchronous mode.

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• ICP1 – Port D, Bit 4

ICP1 – Input Capture Pin 1: The PD4 pin can act as an input capture pin for Timer/Counter1.

• INT3/TXD1 – Port D, Bit 3

INT3, External Interrupt source 3: The PD3 pin can serve as an external interrupt source to the

MCU.

TXD1, Transmit Data (Data output pin for the USART1). When the USART1 Transmitter is

enabled, this pin is configured as an output regardless of the value of DDD3.

• INT2/RXD1 – Port D, Bit 2

INT2, External Interrupt source 2. The PD2 pin can serve as an External Interrupt source to the

MCU.

RXD1, Receive Data (Data input pin for the USART1). When the USART1 receiver is enabled

this pin is configured as an input regardless of the value of DDD2. When the USART forces this

pin to be an input, the pull-up can still be controlled by the PORTD2 bit.

• INT1/SDA/OC2B – Port D, Bit 1

INT1, External Interrupt source 1. The PD1 pin can serve as an external interrupt source to the

MCU.

SDA, 2-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the 2-wire

Serial Interface, pin PD1 is disconnected from the port and becomes the Serial Data I/O pin for

the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes

shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-

rate limitation.

• INT0/SCL/OC0B – Port D, Bit 0

INT0, External Interrupt source 0. The PD0 pin can serve as an external interrupt source to the

MCU.

SCL, 2-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the 2-

wire Serial Interface, pin PD0 is disconnected from the port and becomes the Serial Clock I/O

pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress

spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with

slew-rate limitation.

Table 10-13 and Table 10-14 relates the alternate functions of Port D to the overriding signals

shown in Figure 10-5 on page 79.

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Table 10-13. Overriding Signals for Alternate Functions PD7..PD4

Signal Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

DIEOE

DIEOV

DI

PD7/T0

PD6/T1

PD5/XCK1

PD4/ICP1

0

XCK1 OUTPUT ENABLE

0

1

0

XCK1 OUTPUT ENABLE

0

XCK1 OUTPUT

0

T0 INPUT

–

T1 INPUT

–

XCK1 INPUT

–

ICP1 INPUT

–

AIO

Table 10-14. Overriding Signals for Alternate Functions in PD3..PD0⁽¹⁾

PD1/INT1/SDA/ PD0/INT0/SCL/

Signal Name PD3/INT3/TXD1 PD2/INT2/RXD1

OC2B

OC0B

PUOE

PUOV

DDOE

DDOV

TXEN1

RXEN1

PORTD2 • PUD

RXEN1

0

TWEN

0

PORTD1 • PUD PORTD0 • PUD

TXEN1

1

TWEN

SDA_OUT

SCL_OUT

TWEN | OC2B

ENABLE

TWEN | OC0B

ENABLE

PVOE

TXEN1

0

PVOV

DIEOE

DIEOV

DI

TXD1

0

OC2B

OC0B

INT3 ENABLE

INT2 ENABLE

1

INT1 ENABLE

1

INT0 ENABLE

1

INT3 INPUT

–

INT2 INPUT/RXD1 INT1 INPUT

– SDA INPUT

INT0 INPUT

SCL INPUT

AIO

Note:

1. When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0

and PD1. This is not shown in this table. In addition, spike filters are connected between the

AIO outputs shown in the port figure and the digital logic of the TWI module.

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10.3.6

Alternate Functions of Port E

The Port E pins with alternate functions are shown in Table 10-15.

Table 10-15. Port E Pins Alternate Functions

Port Pin Alternate Function

INT7/AIN.1/UVCON (External Interrupt 7 Input, Analog Comparator Positive Input

or VBUS Control)

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

INT6/AIN.0 (External Interrupt 6 Input or Analog Comparator Positive Input)

INT5/TOSC2 (External Interrupt 5 Input or RTC Oscillator Timer/Counter2))

INT4/TOSC2 (External Interrupt4 Input or RTC Oscillator Timer/Counter2)

UID

ALE/HWB (Address latch to extenal memory or Hardware bootloader activation)

RD (Read strobe to external memory)

WR (Write strobe to external memory)

• INT7/AIN.1/UVCON – Port E, Bit 7

INT7, External Interrupt source 7: The PE7 pin can serve as an external interrupt source.

AIN1 – Analog Comparator Negative input. This pin is directly connected to the negative input of

the Analog Comparator.

UVCON - When using USB host mode, this pin allows to control an external VBUS generator

(active high).

• INT6/AIN.0 – Port E, Bit 6

INT6, External Interrupt source 6: The PE6 pin can serve as an external interrupt source.

AIN0 – Analog Comparator Negative input. This pin is directly connected to the negative input of

the Analog Comparator.

• INT5/TOSC2 – Port E, Bit 5

INT5, External Interrupt source 5: The PE5 pin can serve as an External Interrupt source.

TOSC2, Timer/Counter2 Oscillator pin1. When the AS2 bit in ASSR is set to enable asynchro-

nous clocking of Timer/Counter2, pin PE5 is disconnected from the port, and becomes the ouput

of the inverting Oscillator amplifier. In this mode, a crystal is connected to this pin, and the pin

can not be used as an I/O pin.

• INT4/TOSC1 – Port E, Bit 4

INT4, External Interrupt source 4: The PE4 pin can serve as an External Interrupt source.

TOSC1, Timer/Counter2 Oscillator pin2. When the AS2 bit in ASSR is set to enable asynchro-

nous clocking of Timer/Counter2, pin PE4 is disconnected from the port, and becomes the input

of the inverting Oscillator amplifier. In this mode, a crystal is connected to this pin, and the pin

can not be used as an I/O pin.

• UID – Port E, Bit 3

ID pin of the USB bus.

• ALE/HWB – Port E, Bit 2

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ALE is the external data memory Address latch enable.

HWB allows to execute the bootloader section after reset when tied to ground during external

reset pulse. The HWB mode of this pin is active only when the HWBE fuse is enable.

• RD – Port E, Bit 1

RD is the external data memory read control enable.

• WR – Port E, Bit 0

WR is the external data memory write control enable.

Table 10-16. Overriding Signals for Alternate Functions PE7..PE4

PE7/INT7/AIN.1/

UVCON

PE5/INT5/

TOSC1

PE4/INT4/

TOSC2

Signal

Name

PE6/INT6/AIN.0

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

DIEOE

DIEOV

DI

0

UVCONE

UVCON

INT7 ENABLE

1

0

INT6 ENABLE

1

INT5 ENABLE

INT4 ENABLE

1

INT7 INPUT

AIN1 INPUT

INT6 INPUT

AIN0 INPUT

INT5 INPUT

–

INT4 INPUT

–

AIO

Table 10-17. Overriding Signals for Alternate Functions in PE3..PE0

Signal

Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

DIEOE

DIEOV

DI

PE3/UID

PE2/ALE/HWB

PE1/RD

PE0/WR

UIDE

0

SRE

0

SRE

0

1

0

UIDE

SRE

1

SRE

1

SRE

0

SRE

ALE

0

SRE

RD

0

SRE

WR

0

UIDE

1

0

1

UID

0

HWB

0

–

PE0

0

AIO

–

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10.3.7

Alternate Functions of Port F

The Port F has an alternate function as analog input for the ADC as shown in Table 10-18. If

some Port F pins are configured as outputs, it is essential that these do not switch when a con-

version is in progress. This might corrupt the result of the conversion. If the JTAG interface is

enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even

if a Reset occurs.

Table 10-18. Port F Pins Alternate Functions

Port Pin

PF7

Alternate Function

ADC7/TDI (ADC input channel 7 or JTAG Test Data Input)

ADC6/TDO (ADC input channel 6 or JTAG Test Data Output)

ADC5/TMS (ADC input channel 5 or JTAG Test Mode Select)

ADC4/TCK (ADC input channel 4 or JTAG Test ClocK)

ADC3 (ADC input channel 3)

PF6

PF5

PF4

PF3

PF2

ADC2 (ADC input channel 2)

PF1

ADC1 (ADC input channel 1)

PF0

ADC0 (ADC input channel 0)

• TDI, ADC7 – Port F, Bit 7

ADC7, Analog to Digital Converter, Channel 7.

TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or Data Reg-

ister (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin.

• TDO, ADC6 – Port F, Bit 6

ADC6, Analog to Digital Converter, Channel 6.

TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When

the JTAG interface is enabled, this pin can not be used as an I/O pin.

The TDO pin is tri-stated unless TAP states that shift out data are entered.

• TMS, ADC5 – Port F, Bit 5

ADC5, Analog to Digital Converter, Channel 5.

TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state

machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin.

• TCK, ADC4 – Port F, Bit 4

ADC4, Analog to Digital Converter, Channel 4.

TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is

enabled, this pin can not be used as an I/O pin.

• ADC3 – ADC0 – Port F, Bit 3..0

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Analog to Digital Converter, Channel 3..0.

Table 10-19. Overriding Signals for Alternate Functions in PF7..PF4

Signal

Name

PUOE

PUOV

DDOE

PF7/ADC7/TDI

JTAGEN

1

PF6/ADC6/TDO

JTAGEN

0

PF5/ADC5/TMS

JTAGEN

1

PF4/ADC4/TCK

JTAGEN

1

JTAGEN

SHIFT_IR +

SHIFT_DR

DDOV

0

PVOE

PVOV

DIEOE

DIEOV

DI

0

JTAGEN

0

TDO

0

JTAGEN

0

–

0

–

0

–

0

–

TMS/ADC5

INPUT

TCK/ADC4

INPUT

AIO

TDI/ADC7 INPUT ADC6 INPUT

Table 10-20. Overriding Signals for Alternate Functions in PF3..PF0

Signal Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

DIEOE

DIEOV

DI

PF3/ADC3

PF2/ADC2

PF1/ADC1

PF0/ADC0

0

–

AIO

ADC3 INPUT

ADC2 INPUT

ADC1 INPUT

ADC0 INPUT

10.4 Register Description for I/O-Ports

10.4.1

Port A Data Register – PORTA

Bit

7

6

5

4

3

2

1

0

PORTA

7

PORTA

6

PORTA

5

PORTA

4

PORTA

3

PORTA

2

PORTA

1

PORTA

0

PORTA

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

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10.4.2

10.4.3

10.4.4

Port A Data Direction Register – DDRA

Bit

7

6

5

4

3

2

1

0

DDA7

R/W

0

DDA6

R/W

0

DDA5

R/W

0

DDA4

R/W

0

DDA3

R/W

0

DDA2

R/W

0

DDA1

R/W

0

DDA0

R/W

0

DDRA

Read/Write

Initial Value

Port A Input Pins Address – PINA

Bit

7

6

5

4

3

2

1

0

PINA7

R/W

N/A

PINA6

R/W

N/A

PINA5

R/W

N/A

PINA4

R/W

N/A

PINA3

R/W

N/A

PINA2

R/W

N/A

PINA1

R/W

N/A

PINA0

R/W

N/A

PINA

Read/Write

Initial Value

Port B Data Register – PORTB

Bit

7

6

5

4

3

2

1

0

PORTB

7

PORTB

6

PORTB

5

PORTB

4

PORTB

3

PORTB

2

PORTB

1

PORTB

0

PORTB

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

10.4.5

10.4.6

10.4.7

Port B Data Direction Register – DDRB

Bit

7

6

5

4

3

2

1

0

DDB7

R/W

0

DDB6

R/W

0

DDB5

R/W

0

DDB4

R/W

0

DDB3

R/W

0

DDB2

R/W

0

DDB1

R/W

0

DDB0

R/W

0

DDRB

Read/Write

Initial Value

Port B Input Pins Address – PINB

Bit

7

6

5

4

3

2

1

0

PINB7

R/W

N/A

PINB6

R/W

N/A

PINB5

R/W

N/A

PINB4

R/W

N/A

PINB3

R/W

N/A

PINB2

R/W

N/A

PINB1

R/W

N/A

PINB0

R/W

N/A

PINB

Read/Write

Initial Value

Port C Data Register – PORTC

Bit

7

6

5

4

3

2

1

0

PORTC

7

PORTC

6

PORTC

5

PORTC

4

PORTC

3

PORTC

2

PORTC

1

PORTC

0

PORTC

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

10.4.8

10.4.9

Port C Data Direction Register – DDRC

Bit

7

6

5

4

3

2

1

0

DDC7

R/W

0

DDC6

R/W

0

DDC5

R/W

0

DDC4

R/W

0

DDC3

R/W

0

DDC2

R/W

0

DDC1

R/W

0

DDC0

R/W

0

DDRC

Read/Write

Initial Value

Port C Input Pins Address – PINC

Bit

7

6

5

4

3

2

1

0

PINC7

R/W

N/A

PINC6

R/W

N/A

PINC5

R/W

N/A

PINC4

R/W

N/A

PINC3

R/W

N/A

PINC2

R/W

N/A

PINC1

R/W

N/A

PINC0

R/W

N/A

PINC

Read/Write

Initial Value

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10.4.10 Port D Data Register – PORTD

Bit

7

6

5

4

3

2

1

0

PORTD

7

PORTD

6

PORTD

5

PORTD

4

PORTD

3

PORTD

2

PORTD

1

PORTD

0

PORTD

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

10.4.11 Port D Data Direction Register – DDRD

Bit

7

6

5

4

3

2

1

0

DDD7

R/W

0

DDD6

R/W

0

DDD5

R/W

0

DDD4

R/W

0

DDD3

R/W

0

DDD2

R/W

0

DDD1

R/W

0

DDD0

R/W

0

DDRD

Read/Write

Initial Value

10.4.12 Port D Input Pins Address – PIND

Bit

7

6

5

4

3

2

1

0

PIND7

R/W

N/A

PIND6

R/W

N/A

PIND5

R/W

N/A

PIND4

R/W

N/A

PIND3

R/W

N/A

PIND2

R/W

N/A

PIND1

R/W

N/A

PIND0

R/W

N/A

PIND

Read/Write

Initial Value

10.4.13 Port E Data Register – PORTE

Bit

7

6

5

4

3

2

1

0

PORTE

7

PORTE

6

PORTE

5

PORTE

4

PORTE

3

PORTE

2

PORTE

1

PORTE

0

PORTE

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

10.4.14 Port E Data Direction Register – DDRE

Bit

7

6

5

4

3

2

1

0

DDE7

R/W

0

DDE6

R/W

0

DDE5

R/W

0

DDE4

R/W

0

DDE3

R/W

0

DDE2

R/W

0

DDE1

R/W

0

DDE0

R/W

0

DDRE

Read/Write

Initial Value

10.4.15 Port E Input Pins Address – PINE

Bit

7

6

5

4

3

2

1

0

PINE7

R/W

N/A

PINE6

R/W

N/A

PINE5

R/W

N/A

PINE4

R/W

N/A

PINE3

R/W

N/A

PINE2

R/W

N/A

PINE1

R/W

N/A

PINE0

R/W

N/A

PINE

Read/Write

Initial Value

10.4.16 Port F Data Register – PORTF

Bit

7

6

5

4

3

2

1

0

PORTF

7

PORTF

6

PORTF

5

PORTF

4

PORTF

3

PORTF

2

PORTF

1

PORTF

0

PORTF

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

10.4.17 Port F Data Direction Register – DDRF

Bit

7

6

5

4

3

2

1

0

DDF7

R/W

0

DDF6

R/W

0

DDF5

R/W

0

DDF4

R/W

0

DDF3

R/W

0

DDF2

R/W

0

DDF1

R/W

0

DDF0

R/W

0

DDRF

Read/Write

Initial Value

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10.4.18 Port F Input Pins Address – PINF

Bit

7

6

5

4

3

2

1

0

PINF7

R/W

N/A

PINF6

R/W

N/A

PINF5

R/W

N/A

PINF4

R/W

N/A

PINF3

R/W

N/A

PINF2

R/W

N/A

PINF1

R/W

PINF0

R/W

PINF

Read/Write

Initial Value

N/A

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11. External Interrupts

The External Interrupts are triggered by the INT7:0 pin or any of the PCINT23..0 pins. Observe

that, if enabled, the interrupts will trigger even if the INT7:0 or PCINT23..0 pins are configured as

outputs. This feature provides a way of generating a software interrupt.

The Pin change interrupt PCI0 will trigger if any enabled PCINT7:0 pin toggles. PCMSK0 Regis-

ter control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT7

..0 are detected asynchronously. This implies that these interrupts can be used for waking the

part also from sleep modes other than Idle mode.

The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up

as indicated in the specification for the External Interrupt Control Registers – EICRA (INT3:0)

and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered,

the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising

edge interrupts on INT7:4 requires the presence of an I/O clock, described in “System Clock and

Clock Options” on page 39. Low level interrupts and the edge interrupt on INT3:0 are detected

asynchronously. This implies that these interrupts can be used for waking the part also from

sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode.

Note that if a level triggered interrupt is used for wake-up from Power-down, the required level

must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If

the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-

rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described

in “System Clock and Clock Options” on page 39.

11.0.1

External Interrupt Control Register A – EICRA

The External Interrupt Control Register A contains control bits for interrupt sense control.

Bit

7

6

5

4

3

2

1

0

ISC31

R/W

0

ISC30

R/W

0

ISC21

R/W

0

ISC20

R/W

0

ISC11

R/W

0

ISC10

R/W

0

ISC01

R/W

0

ISC00

R/W

0

EICRA

Read/Write

Initial Value

• Bits 7..0 – ISC31, ISC30 – ISC00, ISC00: External Interrupt 3 - 0 Sense Control Bits

The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the

corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that

activate the interrupts are defined in Table 11-1. Edges on INT3..INT0 are registered asynchro-

nously. Pulses on INT3:0 pins wider than the minimum pulse width given in Table 11-2 will

generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level

interrupt is selected, the low level must be held until the completion of the currently executing

instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an inter-

rupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur.

Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the

EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be

cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the

interrupt is re-enabled.

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Table 11-1.

Interrupt Sense Control⁽¹⁾

ISCn0 Description

ISCn1

0

1

0

1

0

1

The low level of INTn generates an interrupt request.

Any edge of INTn generates asynchronously an interrupt request.

The falling edge of INTn generates asynchronously an interrupt request.

The rising edge of INTn generates asynchronously an interrupt request.

Note:

1. n = 3, 2, 1or 0.

When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt

Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.

Table 11-2. Asynchronous External Interrupt Characteristics

Symbol Parameter Condition Min

Minimum pulse width for

Typ

Max

Units

t_INT

50

ns

asynchronous external interrupt

11.0.2

External Interrupt Control Register B – EICRB

Bit

7

6

5

4

3

2

1

0

ISC71

R/W

0

ISC70

R/W

0

ISC61

R/W

0

ISC60

R/W

0

ISC51

R/W

0

ISC50

R/W

0

ISC41

R/W

0

ISC40

R/W

0

EICRB

Read/Write

Initial Value

• Bits 7..0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt 7 - 4 Sense Control Bits

The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the

corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that

activate the interrupts are defined in Table 11-3. The value on the INT7:4 pins are sampled

before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one

clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an inter-

rupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL

divider is enabled. If low level interrupt is selected, the low level must be held until the comple-

tion of the currently executing instruction to generate an interrupt. If enabled, a level triggered

interrupt will generate an interrupt request as long as the pin is held low.

Table 11-3.

ISCn1 ISCn0 Description

Interrupt Sense Control⁽¹⁾

0

1

The low level of INTn generates an interrupt request.

Any logical change on INTn generates an interrupt request

The falling edge between two samples of INTn generates an interrupt

request.

1

0

1

The rising edge between two samples of INTn generates an interrupt

request.

1

Note:

1. n = 7, 6, 5 or 4.

When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt

Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.

11.0.3

External Interrupt Mask Register – EIMSK

Bit

7

6

5

4

3

2

1

0

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INT7

R/W

0

INT6

R/W

0

INT5

R/W

0

INT4

R/W

0

INT3

R/W

0

INT2

R/W

0

INT1

R/W

0

IINT0

R/W

0

EIMSK

Read/Write

Initial Value

• Bits 7..0 – INT7 – INT0: External Interrupt Request 7 - 0 Enable

When an INT7 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set

(one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the

External Interrupt Control Registers – EICRA and EICRB – defines whether the external inter-

rupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger

an interrupt request even if the pin is enabled as an output. This provides a way of generating a

software interrupt.

11.0.4

External Interrupt Flag Register – EIFR

Bit

7

6

5

4

3

2

1

0

INTF7

INTF6

INTF5

R/W

0

INTF4

R/W

0

INTF3

R/W

0

INTF2

R/W

0

INTF1

R/W

0

IINTF0

R/W

0

EIFR

Read/Write

Initial Value

R/W

0

R/W

0

• Bits 7..0 – INTF7 - INTF0: External Interrupt Flags 7 - 0

When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0 becomes

set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT7:0 in EIMSK, are

set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine

is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are

always cleared when INT7:0 are configured as level interrupt. Note that when entering sleep

mode with the INT3:0 interrupts disabled, the input buffers on these pins will be disabled. This

may cause a logic change in internal signals which will set the INTF3:0 flags. See “Digital Input

Enable and Sleep Modes” on page 78 for more information.

11.0.5

Pin Change Interrupt Control Register - PCICR

Bit

7

6

5

4

–

R

0

3

–

R

0

2

–

R

0

1

–

R

0

–

R

0

PCIE0

R/W

0

PCICR

Read/Write

Initial Value

R

0

R

0

• Bit 0 – PCIE0: Pin Change Interrupt Enable 0

When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an

interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from

the PCI0 Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.

11.0.6

Pin Change Interrupt Flag Register – PCIFR

Bit

7

6

5

4

–

R

0

3

–

R

0

2

–

R

0

1

–

R

0

–

R

0

PCIF0

R/W

0

PCIFR

Read/Write

Initial Value

R

0

R

0

• Bit 0 – PCIF0: Pin Change Interrupt Flag 0

When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set

(one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the MCU will jump to the

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corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

11.0.7

Pin Change Mask Register 0 – PCMSK0

Bit

7

6

5

4

3

2

1

0

PCINT7

PCINT6

PCINT5

R/W

0

PCINT4

R/W

0

PCINT3

R/W

0

PCINT2

R/W

0

PCINT1

R/W

0

PCINT0

R/W

0

PCMSK0

Read/Write

Initial Value

R/W

0

R/W

0

• Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0

Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O

pin. If PCINT7..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the

corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin

is disabled.

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12. Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers

Timer/Counter0, 1, and 3 share the same prescaler module, but the Timer/Counters can have

different prescaler settings. The description below applies to all Timer/Counters. Tn is used as a

general name, n = 0, 1 or 3.

12.1 Internal Clock Source

The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This

provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system

clock frequency (f_{CLK_I/O}). Alternatively, one of four taps from the prescaler can be used as a

clock source. The prescaled clock has a frequency of either f_{CLK_I/O}/8, f_{CLK_I/O}/64, f_{CLK_I/O}/256, or

f_{CLK_I/O}/1024.

12.2 Prescaler Reset

The prescaler is free running, i.e., operates independently of the Clock Select logic of the

Timer/Counter, and it is shared by the Timer/Counter Tn. Since the prescaler is not affected by

the Timer/Counter’s clock select, the state of the prescaler will have implications for situations

where a prescaled clock is used. One example of prescaling artifacts occurs when the timer is

enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock cycles from

when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles,

where N equals the prescaler divisor (8, 64, 256, or 1024).

It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-

tion. However, care must be taken if the other Timer/Counter that shares the same prescaler

also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is

connected to.

12.3 External Clock Source

An external clock source applied to the Tn pin can be used as Timer/Counter clock (clk_Tn). The

Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-

nized (sampled) signal is then passed through the edge detector. Figure 1 shows a functional

equivalent block diagram of the Tn synchronization and edge detector logic. The registers are

clocked at the positive edge of the internal system clock (clk_I/O). The latch is transparent in the

high period of the internal system clock.

The edge detector generates one clk_Tnpulse for each positive (CSn2:0 = 7) or negative (CSn2:0

= 6) edge it detects.

Figure 1. Tn/T0 Pin Sampling

Tn_sync

(To Clock

Tn

D

Q

D

Q

D

Q

Select Logic)

LE

clk_I/O

Synchronization

Edge Detector

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles

from an edge has been applied to the Tn pin to the counter is updated.

Enabling and disabling of the clock input must be done when Tn has been stable for at least one

system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

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Each half period of the external clock applied must be longer than one system clock cycle to

ensure correct sampling. The external clock must be guaranteed to have less than half the sys-

tem clock frequency (f_ExtClk< f_{clk_I/O}/2) given a 50/50% duty cycle. Since the edge detector uses

sampling, the maximum frequency of an external clock it can detect is half the sampling fre-

quency (Nyquist sampling theorem). However, due to variation of the system clock frequency

and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is

recommended that maximum frequency of an external clock source is less than f_{clk_I/O}/2.5.

An external clock source can not be prescaled.

Figure 2. Prescaler for synchronous Timer/Counters

clk_I/O

Clear

PSR10

Tn

Synchronization

Tn

Synchronization

CSn0

CSn1

CSn2

CSn0

CSn1

CSn2

TIMER/COUNTERn CLOCK SOURCE

clk_Tn

TIMER/COUNTERn CLOCK SOURCE

clk_Tn

12.4 General Timer/Counter Control Register – GTCCR

Bit

7

6

5

4

3

–

2

–

1

0

TSM

–

PSRA-

SY

PSRSY

NC

GTCCR

Read/Write

Initial Value

R/W

0

R

0

R

0

R

0

R

0

R

0

R/W

0

R/W

0

• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the

value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the correspond-

ing prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are

halted and can be configured to the same value without the risk of one of them advancing during

configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared

by hardware, and the Timer/Counters start counting simultaneously.

• Bit 0 – PSRSYNC: Prescaler Reset for Synchronous Timer/Counters

When this bit is one, Timer/Counter0 and Timer/Counter1 and Timer/Counter3 prescaler will be

Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note

that Timer/Counter0, Timer/Counter1 and Timer/Counter3 share the same prescaler and a reset

of this prescaler will affect all timers.

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13. 8-bit Timer/Counter0 with PWM

Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output

Compare Units, and with PWM support. It allows accurate program execution timing (event man-

agement) and wave generation. The main features are:

• Two Independent Output Compare Units

• Double Buffered Output Compare Registers

• Clear Timer on Compare Match (Auto Reload)

• Glitch Free, Phase Correct Pulse Width Modulator (PWM)

• Variable PWM Period

• Frequency Generator

• Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)

13.1 Overview

A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 13-1. For the actual

placement of I/O pins, refer to “Pinout AT90USB64/128-TQFP” on page 3. CPU accessible I/O

Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register

and bit locations are listed in the “8-bit Timer/Counter Register Description” on page 112.

Figure 13-1. 8-bit Timer/Counter Block Diagram

Count

TOVn

(Int.Req.)

Clear

Control Logic

Clock Select

Direction

clk_Tn

Edge

Detector

Tn

TOP

BOTTOM

( From Prescaler )

Timer/Counter

TCNTn

=

0

OCnA

(Int.Req.)

Waveform

Generation

OCnA

OCnB

=

OCRnA

Fixed

TOP

Value

OCnB

(Int.Req.)

Waveform

Generation

=

OCRnB

TCCRnA

TCCRnB

13.1.1

Registers

The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit

registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the

Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Inter-

rupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on

the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter

uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source

is selected. The output from the Clock Select logic is referred to as the timer clock (clk_T0).

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The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the

Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-

erator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and

OC0B). See “Output Compare Unit” on page 104. for details. The Compare Match event will also

set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare

interrupt request.

13.1.2

Definitions

Many register and bit references in this section are written in general form. A lower case “n”

replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com-

pare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or

bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing

Timer/Counter0 counter value and so on.

The definitions in the table below are also used extensively throughout the document.

BOTTOM The counter reaches the BOTTOM when it becomes 0x00.

MAX

TOP

The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

The counter reaches the TOP when it becomes equal to the highest

value in the count sequence. The TOP value can be assigned to be the

fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The

assignment is dependent on the mode of operation.

13.2 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source

is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits

located in the Timer/Counter Control Register (TCCR0B). For details on clock sources and pres-

caler, see “Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers” on page 100.

13.3 Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

13-2 shows a block diagram of the counter and its surroundings.

Figure 13-2. Counter Unit Block Diagram

TOVn

(Int.Req.)

DATA BUS

Clock Select

count

clear

Edge

Detector

Tn

clk_Tn

TCNTn

Control Logic

direction

( From Prescaler )

bottom

top

Signal description (internal signals):

count

Increment or decrement TCNT0 by 1.

Select between increment and decrement.

Clear TCNT0 (set all bits to zero).

direction

clear

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clk_Tn

top

Timer/Counter clock, referred to as clk_T0in the following.

Signalize that TCNT0 has reached maximum value.

Signalize that TCNT0 has reached minimum value (zero).

bottom

Depending of the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clk_T0). clk_T0can be generated from an external or internal clock source,

selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the

timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of

whether clk_T0is present or not. A CPU write overrides (has priority over) all counter clear or

count operations.

The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in

the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter

Control Register B (TCCR0B). There are close connections between how the counter behaves

(counts) and how waveforms are generated on the Output Compare outputs OC0A and OC0B.

For more details about advanced counting sequences and waveform generation, see “Modes of

Operation” on page 107.

The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by

the WGM02:0 bits. TOV0 can be used for generating a CPU interrupt.

13.4 Output Compare Unit

The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers

(OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a

match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock

cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output

Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is exe-

cuted. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit

location. The Waveform Generator uses the match signal to generate an output according to

operating mode set by the WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The max

and bottom signals are used by the Waveform Generator for handling the special cases of the

extreme values in some modes of operation (“Modes of Operation” on page 107).

Figure 13-3 shows a block diagram of the Output Compare unit.

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Figure 13-3. Output Compare Unit, Block Diagram

DATA BUS

OCRnx

TCNTn

= (8-bit Comparator )

OCFnx (Int.Req.)

top

bottom

Waveform Generator

OCnx

FOCn

WGMn1:0

COMnX1:0

The OCR0x Registers are double buffered when using any of the Pulse Width Modulation

(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou-

ble buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare

Registers to either top or bottom of the counting sequence. The synchronization prevents the

occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR0x Register access may seem complex, but this is not case. When the double buffering

is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is dis-

abled the CPU will access the OCR0x directly.

13.4.1

Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOC0x) bit. Forcing Compare Match will not set the

OCF0x Flag or reload/clear the timer, but the OC0x pin will be updated as if a real Compare

Match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set, cleared or

toggled).

13.4.2

13.4.3

Compare Match Blocking by TCNT0 Write

All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the

next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initial-

ized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is

enabled.

Using the Output Compare Unit

Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer

clock cycle, there are risks involved when changing TCNT0 when using the Output Compare

Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0

equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform

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generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is

down-counting.

The setup of the OC0x should be performed before setting the Data Direction Register for the

port pin to output. The easiest way of setting the OC0x value is to use the Force Output Com-

pare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when

changing between Waveform Generation modes.

Be aware that the COM0x1:0 bits are not double buffered together with the compare value.

Changing the COM0x1:0 bits will take effect immediately.

13.5 Compare Match Output Unit

The Compare Output mode (COM0x1:0) bits have two functions. The Waveform Generator uses

the COM0x1:0 bits for defining the Output Compare (OC0x) state at the next Compare Match.

Also, the COM0x1:0 bits control the OC0x pin output source. Figure 13-4 shows a simplified

schematic of the logic affected by the COM0x1:0 bit setting. The I/O Registers, I/O bits, and I/O

pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers

(DDR and PORT) that are affected by the COM0x1:0 bits are shown. When referring to the

OC0x state, the reference is for the internal OC0x Register, not the OC0x pin. If a system reset

occur, the OC0x Register is reset to “0”.

Figure 13-4. Compare Match Output Unit, Schematic

COMnx1

Waveform

Generator

COMnx0

FOCn

D

Q

1

0

OCnx

D

Q

PORT

D

Q

DDR

clk_I/O

The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform

Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or out-

put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction

Register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visi-

ble on the pin. The port override function is independent of the Waveform Generation mode.

The design of the Output Compare pin logic allows initialization of the OC0x state before the out-

put is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of

operation. See “8-bit Timer/Counter Register Description” on page 112.

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13.5.1

Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes.

For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the

OC0x Register is to be performed on the next Compare Match. For compare output actions in

the non-PWM modes refer to Table 13-1 on page 113. For fast PWM mode, refer to Table 13-2

on page 113, and for phase correct PWM refer to Table 13-3 on page 113.

A change of the COM0x1:0 bits state will have effect at the first Compare Match after the bits are

written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOC0x strobe bits.

13.6 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is

defined by the combination of the Waveform Generation mode (WGM02:0) and Compare Output

mode (COM0x1:0) bits. The Compare Output mode bits do not affect the counting sequence,

while the Waveform Generation mode bits do. The COM0x1:0 bits control whether the PWM out-

put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes

the COM0x1:0 bits control whether the output should be set, cleared, or toggled at a Compare

Match (See “Compare Match Output Unit” on page 106.).

For detailed timing information see “Timer/Counter Timing Diagrams” on page 111.

13.6.1

Normal Mode

The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting

direction is always up (incrementing), and no counter clear is performed. The counter simply

overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-

tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same

timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth

bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt

that automatically clears the TOV0 Flag, the timer resolution can be increased by software.

There are no special cases to consider in the Normal mode, a new counter value can be written

anytime.

The Output Compare Unit can be used to generate interrupts at some given time. Using the Out-

put Compare to generate waveforms in Normal mode is not recommended, since this will

occupy too much of the CPU time.

13.6.2

Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used to

manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter

value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence

also its resolution. This mode allows greater control of the Compare Match output frequency. It

also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 13-5. The counter value (TCNT0)

increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter

(TCNT0) is cleared.

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Figure 13-5. CTC Mode, Timing Diagram

OCnx Interrupt Flag Set

TCNTn

OCn

(Toggle)

(COMnx1:0 = 1)

1

2

3

4

Period

An interrupt can be generated each time the counter value reaches the TOP value by using the

OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating

the TOP value. However, changing TOP to a value close to BOTTOM when the counter is run-

ning with none or a low prescaler value must be done with care since the CTC mode does not

have the double buffering feature. If the new value written to OCR0A is lower than the current

value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to

its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can

occur.

For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical

level on each Compare Match by setting the Compare Output mode bits to toggle mode

(COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for

the pin is set to output. The waveform generated will have a maximum frequency of f_OC0

_{clk_I/O}/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following

equation:

=

f

clk_I/O

f

= -------------------------------------------------

OCnx

2 ⋅ N ⋅ (1 + OCRnx)

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the

counter counts from MAX to 0x00.

13.6.3

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high fre-

quency PWM waveform generation option. The fast PWM differs from the other PWM option by

its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOT-

TOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when WGM2:0 = 7. In non-

inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match

between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the out-

put is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the

operating frequency of the fast PWM mode can be twice as high as the phase correct PWM

mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited

for power regulation, rectification, and DAC applications. High frequency allows physically small

sized external components (coils, capacitors), and therefore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the TOP value.

The counter is then cleared at the following timer clock cycle. The timing diagram for the fast

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PWM mode is shown in Figure 13-6. The TCNT0 value is in the timing diagram shown as a his-

togram for illustrating the single-slope operation. The diagram includes non-inverted and

inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Com-

pare Matches between OCR0x and TCNT0.

Figure 13-6. Fast PWM Mode, Timing Diagram

OCRnx Interrupt Flag Set

OCRnx Update and

TOVn Interrupt Flag Set

TCNTn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCnx

1

2

3

4

5

6

7

Period

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.

Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output

can be generated by setting the COM0x1:0 to three: Setting the COM0A1:0 bits to one allows

the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available

for the OC0B pin (See Table 13-2 on page 113). The actual OC0x value will only be visible on

the port pin if the data direction for the port pin is set as output. The PWM waveform is gener-

ated by setting (or clearing) the OC0x Register at the Compare Match between OCR0x and

TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the counter is

cleared (changes from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

f

clk_I/O

f

= -----------------

OCnxPWM

N ⋅ 256

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0A Register represents special cases when generating a PWM

waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will

be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result

in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0

bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-

ting OC0x to toggle its logical level on each Compare Match (COM0x1:0 = 1). The waveform

generated will have a maximum frequency of f_OC0= f_{clk_I/O}/2 when OCR0A is set to zero. This

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feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Out-

put Compare unit is enabled in the fast PWM mode.

13.6.4

Phase Correct PWM Mode

The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct

PWM waveform generation option. The phase correct PWM mode is based on a dual-slope

operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOT-

TOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5. In non-

inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match

between TCNT0 and OCR0x while upcounting, and set on the Compare Match while down-

counting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation

has lower maximum operation frequency than single slope operation. However, due to the sym-

metric feature of the dual-slope PWM modes, these modes are preferred for motor control

applications.

In phase correct PWM mode the counter is incremented until the counter value matches TOP.

When the counter reaches TOP, it changes the count direction. The TCNT0 value will be equal

to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown

on Figure 13-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating

the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The

small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x

and TCNT0.

Figure 13-7. Phase Correct PWM Mode, Timing Diagram

OCnx Interrupt Flag Set

OCRnx Update

TOVn Interrupt Flag Set

TCNTn

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

OCnx

1

2

3

Period

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The

Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM

value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the

OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted

PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to

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one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is

not available for the OC0B pin (See Table 13-3 on page 113). The actual OC0x value will only

be visible on the port pin if the data direction for the port pin is set as output. The PWM wave-

form is generated by clearing (or setting) the OC0x Register at the Compare Match between

OCR0x and TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at

Compare Match between OCR0x and TCNT0 when the counter decrements. The PWM fre-

quency for the output when using phase correct PWM can be calculated by the following

equation:

f

clk_I/O

f

= -----------------

OCnxPCPWM

N ⋅ 510

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0A Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the

output will be continuously low and if set equal to MAX the output will be continuously high for

non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.

At the very start of period 2 in Figure 13-7 OCnx has a transition from high to low even though

there is no Compare Match. The point of this transition is to guarantee symmetry around BOT-

TOM. There are two cases that give a transition without Compare Match.

• OCR0A changes its value from MAX, like in Figure 13-7. When the OCR0A value is MAX the

OCn pin value is the same as the result of a down-counting Compare Match. To ensure

symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-

counting Compare Match.

• The timer starts counting from a value higher than the one in OCR0A, and for that reason

misses the Compare Match and hence the OCn change that would have happened on the

way up.

13.7 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk_T0) is therefore shown as a

clock enable signal in the following figures. The figures include information on when Interrupt

Flags are set. Figure 13-8 contains timing data for basic Timer/Counter operation. The figure

shows the count sequence close to the MAX value in all modes other than phase correct PWM

mode.

Figure 13-8. Timer/Counter Timing Diagram, no Prescaling

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

Figure 13-9 shows the same timing data, but with the prescaler enabled.

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Figure 13-9. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

Figure 13-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC

mode and PWM mode, where OCR0A is TOP.

Figure 13-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

OCRnx

OCFnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

Figure 13-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast

PWM mode where OCR0A is TOP.

Figure 13-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-

caler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

(CTC)

TOP - 1

TOP

BOTTOM

BOTTOM + 1

OCRnx

TOP

OCFnx

13.8 8-bit Timer/Counter Register Description

13.8.1

Timer/Counter Control Register A – TCCR0A

Bit

7

6

5

4

3

–

2

–

1

0

COM0A

1

COM0A

0

COM0B

1

COM0B

0

WGM0

1

WGM0

0

TCCR0A

Read/Write

R/W

R

R/W

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Initial Value

0

• Bits 7:6 – COM01A:0: Compare Match Output A Mode

These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0

bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin

must be set in order to enable the output driver.

When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the

WGM02:0 bit setting. Table 13-1 shows the COM0A1:0 bit functionality when the WGM02:0 bits

are set to a normal or CTC mode (non-PWM).

Table 13-1. Compare Output Mode, non-PWM Mode

COM0A1

COM0A0

Description

0

1

0

1

0

1

Normal port operation, OC0A disconnected.

Toggle OC0A on Compare Match

Clear OC0A on Compare Match

Set OC0A on Compare Match

Table 13-2 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM

mode.

Table 13-2. Compare Output Mode, Fast PWM Mode⁽¹⁾

COM0A1

COM0A0

Description

0

Normal port operation, OC0A disconnected.

WGM02 = 0: Normal Port Operation, OC0A Disconnected.

WGM02 = 1: Toggle OC0A on Compare Match.

0

1

0

1

Clear OC0A on Compare Match, set OC0A at TOP

Set OC0A on Compare Match, clear OC0A at TOP

Note:

1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 108

for more details.

Table 13-3 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase cor-

rect PWM mode.

Table 13-3. Compare Output Mode, Phase Correct PWM Mode⁽¹⁾

COM0A1

COM0A0

Description

0

Normal port operation, OC0A disconnected.

WGM02 = 0: Normal Port Operation, OC0A Disconnected.

WGM02 = 1: Toggle OC0A on Compare Match.

0

1

0

1

Clear OC0A on Compare Match when up-counting. Set OC0A on

Compare Match when down-counting.

Set OC0A on Compare Match when up-counting. Clear OC0A on

Compare Match when down-counting.

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Note:

1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on

page 110 for more details.

• Bits 5:4 – COM0B1:0: Compare Match Output B Mode

These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0

bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin

must be set in order to enable the output driver.

When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the

WGM02:0 bit setting. Table 13-1 shows the COM0A1:0 bit functionality when the WGM02:0 bits

are set to a normal or CTC mode (non-PWM).

Table 13-4. Compare Output Mode, non-PWM Mode

COM01

COM00

Description

0

1

0

1

0

1

Normal port operation, OC0B disconnected.

Toggle OC0B on Compare Match

Clear OC0B on Compare Match

Set OC0B on Compare Match

Table 13-2 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM

mode.

Table 13-5. Compare Output Mode, Fast PWM Mode⁽¹⁾

COM01

COM00

Description

0

1

0

1

0

1

Normal port operation, OC0B disconnected.

Reserved

Clear OC0B on Compare Match, set OC0B at TOP

Set OC0B on Compare Match, clear OC0B at TOP

Note:

1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 108

for more details.

Table 13-3 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase cor-

rect PWM mode.

Table 13-6. Compare Output Mode, Phase Correct PWM Mode⁽¹⁾

COM0A1

COM0A0

Description

0

1

Normal port operation, OC0B disconnected.

Reserved

Clear OC0B on Compare Match when up-counting. Set OC0B on

Compare Match when down-counting.

1

0

1

Set OC0B on Compare Match when up-counting. Clear OC0B on

Compare Match when down-counting.

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Note:

1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on

page 110 for more details.

• Bits 3, 2 – Res: Reserved Bits

These bits are reserved bits in the AT90USB64/128 and will always read as zero.

• Bits 1:0 – WGM01:0: Waveform Generation Mode

Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting

sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-

form generation to be used, see Table 13-7. Modes of operation supported by the Timer/Counter

unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of

Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 107).

Table 13-7. Waveform Generation Mode Bit Description

Timer/Counter

Mode of

Update of

OCRx at

TOV Flag

Mode WGM2 WGM1 WGM0 Operation

TOP

Set on⁽¹⁾⁽²⁾

0

1

0

1

Normal

0xFF

Immediate

TOP

MAX

PWM, Phase

Correct

0xFF

BOTTOM

2

3

4

0

1

0

1

0

CTC

OCRA Immediate

MAX

–

Fast PWM

Reserved

0xFF

–

TOP

–

PWM, Phase

Correct

5

1

0

1

OCRA

TOP

BOTTOM

6

7

1

0

1

Reserved

Fast PWM

–

OCRA

TOP

Notes: 1. MAX

= 0xFF

2. BOTTOM = 0x00

13.8.2

Timer/Counter Control Register B – TCCR0B

Bit

7

6

5

–

R

0

4

–

R

0

3

2

1

0

FOC0A

FOC0B

WGM02

R/W

0

CS02

R/W

0

CS01

R/W

0

CS00

R/W

0

TCCR0B

Read/Write

Initial Value

W

0

W

0

• Bit 7 – FOC0A: Force Output Compare A

The FOC0A bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero when

TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit,

an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is

changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a

strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the

forced compare.

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A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using

OCR0A as TOP.

The FOC0A bit is always read as zero.

• Bit 6 – FOC0B: Force Output Compare B

The FOC0B bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero when

TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit,

an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is

changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is implemented as a

strobe. Therefore it is the value present in the COM0B1:0 bits that determines the effect of the

forced compare.

A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using

OCR0B as TOP.

The FOC0B bit is always read as zero.

• Bits 5:4 – Res: Reserved Bits

These bits are reserved bits and will always read as zero.

• Bit 3 – WGM02: Waveform Generation Mode

See the description in the “Timer/Counter Control Register A – TCCR0A” on page 112.

• Bits 2:0 – CS02:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter.

Table 13-8. Clock Select Bit Description

CS02

CS01

CS00 Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No clock source (Timer/Counter stopped)

clk_I/O/(No prescaling)

clk_I/O/8 (From prescaler)

clk_I/O/64 (From prescaler)

clk_I/O/256 (From prescaler)

clk_I/O/1024 (From prescaler)

External clock source on T0 pin. Clock on falling edge.

External clock source on T0 pin. Clock on rising edge.

If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the

counter even if the pin is configured as an output. This feature allows software control of the

counting.

13.8.3

Timer/Counter Register – TCNT0

Bit

7

6

5

4

3

2

1

0

TCNT0[7:0]

TCNT0

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

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The Timer/Counter Register gives direct access, both for read and write operations, to the

Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare

Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,

introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers.

13.8.4

13.8.5

13.8.6

Output Compare Register A – OCR0A

Bit

7

6

5

4

3

2

1

0

OCR0A[7:0]

OCR0A

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Register A contains an 8-bit value that is continuously compared with the

counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to

generate a waveform output on the OC0A pin.

Output Compare Register B – OCR0B

Bit

7

6

5

4

3

2

1

0

OCR0B[7:0]

OCR0B

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Register B contains an 8-bit value that is continuously compared with the

counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to

generate a waveform output on the OC0B pin.

Timer/Counter Interrupt Mask Register – TIMSK0

Bit

7

6

5

4

–

R

0

3

–

R

0

2

1

0

–

OCIE0B

R/W

0

OCIE0A

R/W

0

TOIE0

R/W

0

TIMSK0

Read/Write

Initial Value

R

0

R

0

R

0

• Bits 7..3, 0 – Res: Reserved Bits

These bits are reserved bits and will always read as zero.

• Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable

When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if

a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter

Interrupt Flag Register – TIFR0.

• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable

When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed

if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the

Timer/Counter 0 Interrupt Flag Register – TIFR0.

• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an

overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Inter-

rupt Flag Register – TIFR0.

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13.8.7

Timer/Counter 0 Interrupt Flag Register – TIFR0

Bit

7

–

R

0

6

–

R

0

5

–

R

0

4

–

R

0

3

–

R

0

2

1

0

OCF0B

R/W

0

OCF0A

R/W

0

TOV0

R/W

0

TIFR0

Read/Write

Initial Value

• Bits 7..3, 0 – Res: Reserved Bits

These bits are reserved bits in the AT90USB64/128 and will always read as zero.

• Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag

The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in

OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the cor-

responding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to

the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable),

and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.

• Bit 1 – OCF0A: Timer/Counter 0 Output Compare A Match Flag

The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data

in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the cor-

responding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to

the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable),

and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.

• Bit 0 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware

when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by

writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt

Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.

The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 13-7, “Waveform

Generation Mode Bit Description” on page 115.

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14. 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)

The 16-bit Timer/Counter unit allows accurate program execution timing (event management),

wave generation, and signal timing measurement. The main features are:

• True 16-bit Design (i.e., Allows 16-bit PWM)

• Three independent Output Compare Units

• Double Buffered Output Compare Registers

• One Input Capture Unit

• Input Capture Noise Canceler

• Clear Timer on Compare Match (Auto Reload)

• Glitch-free, Phase Correct Pulse Width Modulator (PWM)

• Variable PWM Period

• Frequency Generator

• External Event Counter

• Twenty independent interrupt sources (TOV1, OCF1A, OCF1B, OCF1C, ICF1, TOV3, OCF3A,

OCF3B, OCF3C, ICF3, TOV4, OCF4A, OCF4B, OCF4C, ICF4, TOV5, OCF5A, OCF5B, OCF5C and

ICF5)

14.1 Overview

Most register and bit references in this section are written in general form. A lower case “n”

replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit

channel. However, when using the register or bit defines in a program, the precise form must be

used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on.

A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 14-1. For the actual

placement of I/O pins, see “Pinout AT90USB64/128-TQFP” on page 3. CPU accessible I/O Reg-

isters, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit

locations are listed in the “16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)” on page

119.

The Power Reduction Timer/Counter1 bit, PRTIM1, in “Power Reduction Register 0 - PRR0” on

page 56 must be written to zero to enable Timer/Counter1 module.

The Power Reduction Timer/Counter3 bit, PRTIM3, in “Power Reduction Register 1 - PRR1” on

page 57 must be written to zero to enable Timer/Counter3 module.

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Figure 14-1. 16-bit Timer/Counter Block Diagram⁽¹⁾

Count

TOVn

(Int.Req.)

Clear

Control Logic

Direction

Clock Select

TCLK

Edge

Detector

Tn

TOP BOTTOM

( From Prescaler )

Timer/Counter

TCNTn

=

= 0

OCFnA

(Int.Req.)

Waveform

Generation

OCnA

OCnB

OCnC

=

OCRnA

OCFnB

(Int.Req.)

Fixed

TOP

Values

Waveform

Generation

=

OCRnB

OCFnC

(Int.Req.)

Waveform

Generation

=

OCRnC

( From Analog

Comparator Ouput )

ICFn (Int.Req.)

Edge

Detector

Noise

Canceler

ICRn

ICPn

TCCRnA

TCCRnB

TCCRnC

Note:

1. Refer to Figure 1-1 on page 3, Table 10-6 on page 82, and Table 10-9 on page 85 for

Timer/Counter1 and 3 and 3 pin placement and description.

14.1.1

Registers

The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Reg-

ister (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16-

bit registers. These procedures are described in the section “Accessing 16-bit Registers” on

page 121. The Timer/Counter Control Registers (TCCRnA/B/C) are 8-bit registers and have no

CPU access restrictions. Interrupt requests (shorten as Int.Req.) signals are all visible in the

Timer Interrupt Flag Register (TIFRn). All interrupts are individually masked with the Timer Inter-

rupt Mask Register (TIMSKn). TIFRn and TIMSKn are not shown in the figure since these

registers are shared by other timer units.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on

the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter

uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source

is selected. The output from the clock select logic is referred to as the timer clock (clk ).

n

T

The double buffered Output Compare Registers (OCRnA/B/C) are compared with the

Timer/Counter value at all time. The result of the compare can be used by the Waveform Gener-

ator to generate a PWM or variable frequency output on the Output Compare pin (OCnA/B/C).

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See “Output Compare Units” on page 128.. The compare match event will also set the Compare

Match Flag (OCFnA/B/C) which can be used to generate an Output Compare interrupt request.

The Input Capture Register can capture the Timer/Counter value at a given external (edge trig-

gered) event on either the Input Capture pin (ICPn) or on the Analog Comparator pins (See

“Analog Comparator” on page 313.) The Input Capture unit includes a digital filtering unit (Noise

Canceler) for reducing the chance of capturing noise spikes.

The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined

by either the OCRnA Register, the ICRn Register, or by a set of fixed values. When using

OCRnA as TOP value in a PWM mode, the OCRnA Register can not be used for generating a

PWM output. However, the TOP value will in this case be double buffered allowing the TOP

value to be changed in run time. If a fixed TOP value is required, the ICRn Register can be used

as an alternative, freeing the OCRnA to be used as PWM output.

14.1.2

Definitions

The following definitions are used extensively throughout the document:

BOTTOM

MAX

The counter reaches the BOTTOM when it becomes 0x0000.

The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).

The counter reaches the TOP when it becomes equal to the highest value in the

count sequence. The TOP value can be assigned to be one of the fixed values:

0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCRnA or ICRn

Register. The assignment is dependent of the mode of operation.

TOP

14.2 Accessing 16-bit Registers

The TCNTn, OCRnA/B/C, and ICRn are 16-bit registers that can be accessed by the AVR CPU

via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write opera-

tions. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-

bit access. The same Temporary Register is shared between all 16-bit registers within each 16-

bit timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of

a 16-bit register is written by the CPU, the high byte stored in the Temporary Register, and the

low byte written are both copied into the 16-bit register in the same clock cycle. When the low

byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the

Temporary Register in the same clock cycle as the low byte is read.

Not all 16-bit accesses uses the Temporary Register for the high byte. Reading the OCRnA/B/C

16-bit registers does not involve using the Temporary Register.

To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low

byte must be read before the high byte.

The following code examples show how to access the 16-bit timer registers assuming that no

interrupts updates the temporary register. The same principle can be used directly for accessing

the OCRnA/B/C and ICRn Registers. Note that when using “C”, the compiler handles the 16-bit

access.

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Assembly Code Examples⁽¹⁾

...

; Set TCNTn to 0x01FF

ldir17,0x01

ldir16,0xFF

outTCNTnH,r17

outTCNTnL,r16

; Read TCNTn into r17:r16

in r16,TCNTnL

in r17,TCNTnH

...

C Code Examples⁽¹⁾

unsigned int i;

...

/* Set TCNTn to 0x01FF */

TCNTn = 0x1FF;

/* Read TCNTn into i */

i = TCNTn;

...

Note:

1. See “About Code Examples” on page 8.

The assembly code example returns the TCNTn value in the r17:r16 register pair.

It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt

occurs between the two instructions accessing the 16-bit register, and the interrupt code

updates the temporary register by accessing the same or any other of the 16-bit Timer Regis-

ters, then the result of the access outside the interrupt will be corrupted. Therefore, when both

the main code and the interrupt code update the temporary register, the main code must disable

the interrupts during the 16-bit access.

The following code examples show how to do an atomic read of the TCNTn Register contents.

Reading any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.

Assembly Code Example⁽¹⁾

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TIM16_ReadTCNTn:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Read TCNTn into r17:r16

in r16,TCNTnL

in r17,TCNTnH

; Restore global interrupt flag

outSREG,r18

ret

C Code Example⁽¹⁾

unsigned int TIM16_ReadTCNTn( void )

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

__disable_interrupt();

/* Read TCNTn into i */

i = TCNTn;

/* Restore global interrupt flag */

SREG = sreg;

return i;

}

Note:

1. See “About Code Examples” on page 8.

The assembly code example returns the TCNTn value in the r17:r16 register pair.

The following code examples show how to do an atomic write of the TCNTn Register contents.

Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.

Assembly Code Example⁽¹⁾

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TIM16_WriteTCNTn:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Set TCNTn to r17:r16

outTCNTnH,r17

outTCNTnL,r16

; Restore global interrupt flag

outSREG,r18

ret

C Code Example⁽¹⁾

void TIM16_WriteTCNTn( unsigned int i )

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

__disable_interrupt();

/* Set TCNTn to i */

TCNTn = i;

/* Restore global interrupt flag */

SREG = sreg;

}

Note:

1. See “About Code Examples” on page 8.

The assembly code example requires that the r17:r16 register pair contains the value to be writ-

ten to TCNTn.

14.2.1

Reusing the Temporary High Byte Register

If writing to more than one 16-bit register where the high byte is the same for all registers written,

then the high byte only needs to be written once. However, note that the same rule of atomic

operation described previously also applies in this case.

14.3 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source

is selected by the Clock Select logic which is controlled by the Clock Select (CSn2:0) bits

located in the Timer/Counter control Register B (TCCRnB). For details on clock sources and

prescaler, see “Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers” on page 100.

14.4 Counter Unit

The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.

Figure 14-2 shows a block diagram of the counter and its surroundings.

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Figure 14-2. Counter Unit Block Diagram

DATA BUS (8-bit)

TOVn

(Int.Req.)

TEMP (8-bit)

Clock Select

Count

Edge

Detector

Tn

TCNTnH (8-bit)

TCNTnL (8-bit)

Clear

clk_Tn

Control Logic

Direction

TCNTn (16-bit Counter)

( From Prescaler )

TOP

BOTTOM

Signal description (internal signals):

Count

Increment or decrement TCNTn by 1.

Select between increment and decrement.

Clear TCNTn (set all bits to zero).

Direction

Clear

clk_T

Timer/Counter clock.

n

TOP

Signalize that TCNTn has reached maximum value.

Signalize that TCNTn has reached minimum value (zero).

BOTTOM

The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) con-

taining the upper eight bits of the counter, and Counter Low (TCNTnL) containing the lower eight

bits. The TCNTnH Register can only be indirectly accessed by the CPU. When the CPU does an

access to the TCNTnH I/O location, the CPU accesses the high byte temporary register (TEMP).

The temporary register is updated with the TCNTnH value when the TCNTnL is read, and

TCNTnH is updated with the temporary register value when TCNTnL is written. This allows the

CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.

It is important to notice that there are special cases of writing to the TCNTn Register when the

counter is counting that will give unpredictable results. The special cases are described in the

sections where they are of importance.

Depending on the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clk ). The clk _ncan be generated from an external or internal clock source,

n

T

selected by the Clock Select bits (CSn2:0). When no clock source is selected (CSn2:0 = 0) the

timer is stopped. However, the TCNTn value can be accessed by the CPU, independent of

whether clk_Tis present or not. A CPU write overrides (has priority over) all counter clear or

n

count operations.

The counting sequence is determined by the setting of the Waveform Generation mode bits

(WGMn3:0) located in the Timer/Counter Control Registers A and B (TCCRnA and TCCRnB).

There are close connections between how the counter behaves (counts) and how waveforms

are generated on the Output Compare outputs OCnx. For more details about advanced counting

sequences and waveform generation, see “Modes of Operation” on page 131.

The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by

the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt.

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14.5 Input Capture Unit

The Timer/Counter incorporates an input capture unit that can capture external events and give

them a time-stamp indicating time of occurrence. The external signal indicating an event, or mul-

tiple events, can be applied via the ICPn pin or alternatively, for the Timer/Counter1 only, via the

Analog Comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle,

and other features of the signal applied. Alternatively the time-stamps can be used for creating a

log of the events.

The Input Capture unit is illustrated by the block diagram shown in Figure 14-3. The elements of

the block diagram that are not directly a part of the input capture unit are gray shaded. The small

“n” in register and bit names indicates the Timer/Counter number.

Figure 14-3. Input Capture Unit Block Diagram

DATA BUS (8-bit)

TEMP (8-bit)

ICRnH (8-bit)

ICRnL (8-bit)

TCNTnH (8-bit)

TCNTnL (8-bit)

ICRn (16-bit Register)

TCNTn (16-bit Counter)

WRITE

ACO*

ACIC*

ICNC

ICES

Analog

Comparator

Noise

Canceler

Edge

Detector

ICFn (Int.Req.)

ICPn

Note:

The Analog Comparator Output (ACO) can only trigger the Timer/Counter1 ICP – not

Timer/Counter3, 4 or 5.

When a change of the logic level (an event) occurs on the Input Capture Pin (ICPn), alternatively

on the analog Comparator output (ACO), and this change confirms to the setting of the edge

detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter

(TCNTn) is written to the Input Capture Register (ICRn). The Input Capture Flag (ICFn) is set at

the same system clock as the TCNTn value is copied into ICRn Register. If enabled (TICIEn =

1), the input capture flag generates an input capture interrupt. The ICFn flag is automatically

cleared when the interrupt is executed. Alternatively the ICFn flag can be cleared by software by

writing a logical one to its I/O bit location.

Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low

byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high byte is copied

into the high byte Temporary Register (TEMP). When the CPU reads the ICRnH I/O location it

will access the TEMP Register.

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The ICRn Register can only be written when using a Waveform Generation mode that utilizes

the ICRn Register for defining the counter’s TOP value. In these cases the Waveform Genera-

tion mode (WGMn3:0) bits must be set before the TOP value can be written to the ICRn

Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location

before the low byte is written to ICRnL.

For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers”

on page 121.

14.5.1

Input Capture Trigger Source

The main trigger source for the input capture unit is the Input Capture Pin (ICPn).

Timer/Counter1 can alternatively use the analog comparator output as trigger source for the

input capture unit. The Analog Comparator is selected as trigger source by setting the analog

Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register

(ACSR). Be aware that changing trigger source can trigger a capture. The input capture flag

must therefore be cleared after the change.

Both the Input Capture Pin (ICPn) and the Analog Comparator output (ACO) inputs are sampled

using the same technique as for the Tn pin (Figure 1 on page 100). The edge detector is also

identical. However, when the noise canceler is enabled, additional logic is inserted before the

edge detector, which increases the delay by four system clock cycles. Note that the input of the

noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Wave-

form Generation mode that uses ICRn to define TOP.

An input capture can be triggered by software by controlling the port of the ICPn pin.

14.5.2

Noise Canceler

The noise canceler improves noise immunity by using a simple digital filtering scheme. The

noise canceler input is monitored over four samples, and all four must be equal for changing the

output that in turn is used by the edge detector.

The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNCn) bit in

Timer/Counter Control Register B (TCCRnB). When enabled the noise canceler introduces addi-

tional four system clock cycles of delay from a change applied to the input, to the update of the

ICRn Register. The noise canceler uses the system clock and is therefore not affected by the

prescaler.

14.5.3

Using the Input Capture Unit

The main challenge when using the Input Capture unit is to assign enough processor capacity

for handling the incoming events. The time between two events is critical. If the processor has

not read the captured value in the ICRn Register before the next event occurs, the ICRn will be

overwritten with a new value. In this case the result of the capture will be incorrect.

When using the Input Capture interrupt, the ICRn Register should be read as early in the inter-

rupt handler routine as possible. Even though the Input Capture interrupt has relatively high

priority, the maximum interrupt response time is dependent on the maximum number of clock

cycles it takes to handle any of the other interrupt requests.

Using the Input Capture unit in any mode of operation when the TOP value (resolution) is

actively changed during operation, is not recommended.

Measurement of an external signal’s duty cycle requires that the trigger edge is changed after

each capture. Changing the edge sensing must be done as early as possible after the ICRn

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Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be

cleared by software (writing a logical one to the I/O bit location). For measuring frequency only,

the clearing of the ICFn Flag is not required (if an interrupt handler is used).

14.6 Output Compare Units

The 16-bit comparator continuously compares TCNTn with the Output Compare Register

(OCRnx). If TCNT equals OCRnx the comparator signals a match. A match will set the Output

Compare Flag (OCFnx) at the next timer clock cycle. If enabled (OCIEnx = 1), the Output Com-

pare Flag generates an Output Compare interrupt. The OCFnx Flag is automatically cleared

when the interrupt is executed. Alternatively the OCFnx Flag can be cleared by software by writ-

ing a logical one to its I/O bit location. The Waveform Generator uses the match signal to

generate an output according to operating mode set by the Waveform Generation mode

(WGMn3:0) bits and Compare Output mode (COMnx1:0) bits. The TOP and BOTTOM signals

are used by the Waveform Generator for handling the special cases of the extreme values in

some modes of operation (See “Modes of Operation” on page 131.)

A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e.,

counter resolution). In addition to the counter resolution, the TOP value defines the period time

for waveforms generated by the Waveform Generator.

Figure 14-4 shows a block diagram of the Output Compare unit. The small “n” in the register and

bit names indicates the device number (n = n for Timer/Counter n), and the “x” indicates Output

Compare unit (A/B/C). The elements of the block diagram that are not directly a part of the Out-

put Compare unit are gray shaded.

Figure 14-4. Output Compare Unit, Block Diagram

DATA BUS (8-bit)

TEMP (8-bit)

OCRnxH Buf. (8-bit)

OCRnxL Buf. (8-bit)

TCNTnH (8-bit)

TCNTnL (8-bit)

OCRnx Buffer (16-bit Register)

TCNTn (16-bit Counter)

OCRnxH (8-bit)

OCRnxL (8-bit)

OCRnx (16-bit Register)

=

(16-bit Comparator )

OCFnx (Int.Req.)

TOP

OCnx

Waveform Generator

BOTTOM

WGMn3:0

COMnx1:0

The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation

(PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the

double buffering is disabled. The double buffering synchronizes the update of the OCRnx Com-

pare Register to either TOP or BOTTOM of the counting sequence. The synchronization

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prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the out-

put glitch-free.

The OCRnx Register access may seem complex, but this is not case. When the double buffering

is enabled, the CPU has access to the OCRnx Buffer Register, and if double buffering is dis-

abled the CPU will access the OCRnx directly. The content of the OCR1x (Buffer or Compare)

Register is only changed by a write operation (the Timer/Counter does not update this register

automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the high byte

temporary register (TEMP). However, it is a good practice to read the low byte first as when

accessing other 16-bit registers. Writing the OCRnx Registers must be done via the TEMP Reg-

ister since the compare of all 16 bits is done continuously. The high byte (OCRnxH) has to be

written first. When the high byte I/O location is written by the CPU, the TEMP Register will be

updated by the value written. Then when the low byte (OCRnxL) is written to the lower eight bits,

the high byte will be copied into the upper 8-bits of either the OCRnx buffer or OCRnx Compare

Register in the same system clock cycle.

For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers”

on page 121.

14.6.1

Force Output Compare

In non-PWM Waveform Generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOCnx) bit. Forcing compare match will not set the

OCFnx Flag or reload/clear the timer, but the OCnx pin will be updated as if a real compare

match had occurred (the COMn1:0 bits settings define whether the OCnx pin is set, cleared or

toggled).

14.6.2

14.6.3

Compare Match Blocking by TCNTn Write

All CPU writes to the TCNTn Register will block any compare match that occurs in the next timer

clock cycle, even when the timer is stopped. This feature allows OCRnx to be initialized to the

same value as TCNTn without triggering an interrupt when the Timer/Counter clock is enabled.

Using the Output Compare Unit

Since writing TCNTn in any mode of operation will block all compare matches for one timer clock

cycle, there are risks involved when changing TCNTn when using any of the Output Compare

channels, independent of whether the Timer/Counter is running or not. If the value written to

TCNTn equals the OCRnx value, the compare match will be missed, resulting in incorrect wave-

form generation. Do not write the TCNTn equal to TOP in PWM modes with variable TOP

values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF.

Similarly, do not write the TCNTn value equal to BOTTOM when the counter is downcounting.

The setup of the OCnx should be performed before setting the Data Direction Register for the

port pin to output. The easiest way of setting the OCnx value is to use the Force Output Com-

pare (FOCnx) strobe bits in Normal mode. The OCnx Register keeps its value even when

changing between Waveform Generation modes.

Be aware that the COMnx1:0 bits are not double buffered together with the compare value.

Changing the COMnx1:0 bits will take effect immediately.

14.7 Compare Match Output Unit

The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses

the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match.

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Secondly the COMnx1:0 bits control the OCnx pin output source. Figure 14-5 shows a simplified

schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O

pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers

(DDR and PORT) that are affected by the COMnx1:0 bits are shown. When referring to the

OCnx state, the reference is for the internal OCnx Register, not the OCnx pin. If a system reset

occur, the OCnx Register is reset to “0”.

Figure 14-5. Compare Match Output Unit, Schematic

COMnx1

Waveform

Generator

COMnx0

FOCnx

D

Q

1

0

OCnx

D

Q

PORT

D

Q

DDR

clk_I/O

The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform

Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or out-

put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction

Register bit for the OCnx pin (DDR_OCnx) must be set as output before the OCnx value is visi-

ble on the pin. The port override function is generally independent of the Waveform Generation

mode, but there are some exceptions. Refer to Table 14-1, Table 14-2 and Table 14-3 for

details.

The design of the Output Compare pin logic allows initialization of the OCnx state before the out-

put is enabled. Note that some COMnx1:0 bit settings are reserved for certain modes of

operation. See “16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)” on page 119.

The COMnx1:0 bits have no effect on the Input Capture unit.

14.7.1

Compare Output Mode and Waveform Generation

The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes.

For all modes, setting the COMnx1:0 = 0 tells the Waveform Generator that no action on the

OCnx Register is to be performed on the next compare match. For compare output actions in the

non-PWM modes refer to Table 14-1 on page 142. For fast PWM mode refer to Table 14-2 on

page 142, and for phase correct and phase and frequency correct PWM refer to Table 14-3 on

page 143.

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A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are

written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOCnx strobe bits.

14.8 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is

defined by the combination of the Waveform Generation mode (WGMn3:0) and Compare Output

mode (COMnx1:0) bits. The Compare Output mode bits do not affect the counting sequence,

while the Waveform Generation mode bits do. The COMnx1:0 bits control whether the PWM out-

put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes

the COMnx1:0 bits control whether the output should be set, cleared or toggle at a compare

match (See “Compare Match Output Unit” on page 129.)

For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 138.

14.8.1

Normal Mode

The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode the counting

direction is always up (incrementing), and no counter clear is performed. The counter simply

overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the

BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOVn) will be set in

the same timer clock cycle as the TCNTn becomes zero. The TOVn Flag in this case behaves

like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow

interrupt that automatically clears the TOVn Flag, the timer resolution can be increased by soft-

ware. There are no special cases to consider in the Normal mode, a new counter value can be

written anytime.

The Input Capture unit is easy to use in Normal mode. However, observe that the maximum

interval between the external events must not exceed the resolution of the counter. If the interval

between events are too long, the timer overflow interrupt or the prescaler must be used to

extend the resolution for the capture unit.

The Output Compare units can be used to generate interrupts at some given time. Using the

Output Compare to generate waveforms in Normal mode is not recommended, since this will

occupy too much of the CPU time.

14.8.2

Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGMn3:0 = 4 or 12), the OCRnA or ICRn Register

are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when

the counter value (TCNTn) matches either the OCRnA (WGMn3:0 = 4) or the ICRn (WGMn3:0 =

12). The OCRnA or ICRn define the top value for the counter, hence also its resolution. This

mode allows greater control of the compare match output frequency. It also simplifies the opera-

tion of counting external events.

The timing diagram for the CTC mode is shown in Figure 14-6. The counter value (TCNTn)

increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn)

is cleared.

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Figure 14-6. CTC Mode, Timing Diagram

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

TCNTn

OCnA

(Toggle)

(COMnA1:0 = 1)

1

2

3

4

Period

An interrupt can be generated at each time the counter value reaches the TOP value by either

using the OCFnA or ICFn Flag according to the register used to define the TOP value. If the

interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. How-

ever, changing the TOP to a value close to BOTTOM when the counter is running with none or a

low prescaler value must be done with care since the CTC mode does not have the double buff-

ering feature. If the new value written to OCRnA or ICRn is lower than the current value of

TCNTn, the counter will miss the compare match. The counter will then have to count to its max-

imum value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur.

In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode

using OCRnA for defining TOP (WGMn3:0 = 15) since the OCRnA then will be double buffered.

For generating a waveform output in CTC mode, the OCnA output can be set to toggle its logical

level on each compare match by setting the Compare Output mode bits to toggle mode

(COMnA1:0 = 1). The OCnA value will not be visible on the port pin unless the data direction for

the pin is set to output (DDR_OCnA = 1). The waveform generated will have a maximum fre-

quency of f_{OC A}= f_{clk_I/O}/2 when OCRnA is set to zero (0x0000). The waveform frequency is

n

defined by the following equation:

f

clk_I/O

f

= --------------------------------------------------

OCnA

2 ⋅ N ⋅ (1 + OCRnA)

The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).

As for the Normal mode of operation, the TOVn Flag is set in the same timer clock cycle that the

counter counts from MAX to 0x0000.

14.8.3

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGMn3:0 = 5, 6, 7, 14, or 15) provides a

high frequency PWM waveform generation option. The fast PWM differs from the other PWM

options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts

from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is set on

the compare match between TCNTn and OCRnx, and cleared at TOP. In inverting Compare

Output mode output is cleared on compare match and set at TOP. Due to the single-slope oper-

ation, the operating frequency of the fast PWM mode can be twice as high as the phase correct

and phase and frequency correct PWM modes that use dual-slope operation. This high fre-

quency makes the fast PWM mode well suited for power regulation, rectification, and DAC

applications. High frequency allows physically small sized external components (coils, capaci-

tors), hence reduces total system cost.

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The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or

OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the max-

imum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be

calculated by using the following equation:

log(TOP + 1)

R

= ----------------------------------

FPWM

log(2)

In fast PWM mode the counter is incremented until the counter value matches either one of the

fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 5, 6, or 7), the value in ICRn (WGMn3:0 =

14), or the value in OCRnA (WGMn3:0 = 15). The counter is then cleared at the following timer

clock cycle. The timing diagram for the fast PWM mode is shown in Figure 14-7. The figure

shows fast PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the

timing diagram shown as a histogram for illustrating the single-slope operation. The diagram

includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn

slopes represent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will

be set when a compare match occurs.

Figure 14-7. Fast PWM Mode, Timing Diagram

OCRnx / TOP Update

and TOVn Interrupt Flag

Set and OCnA Interrupt

Flag Set or ICFn

Interrupt Flag Set

(Interrupt on TOP)

TCNTn

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

OCnx

1

2

3

4

5

6

7

8

Period

The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addition

the OCnA or ICFn Flag is set at the same timer clock cycle as TOVn is set when either OCRnA

or ICRn is used for defining the TOP value. If one of the interrupts are enabled, the interrupt han-

dler routine can be used for updating the TOP and compare values.

When changing the TOP value the program must ensure that the new TOP value is higher or

equal to the value of all of the Compare Registers. If the TOP value is lower than any of the

Compare Registers, a compare match will never occur between the TCNTn and the OCRnx.

Note that when using fixed TOP values the unused bits are masked to zero when any of the

OCRnx Registers are written.

The procedure for updating ICRn differs from updating OCRnA when used for defining the TOP

value. The ICRn Register is not double buffered. This means that if ICRn is changed to a low

value when the counter is running with none or a low prescaler value, there is a risk that the new

ICRn value written is lower than the current value of TCNTn. The result will then be that the

counter will miss the compare match at the TOP value. The counter will then have to count to the

MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur.

The OCRnA Register however, is double buffered. This feature allows the OCRnA I/O location

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to be written anytime. When the OCRnA I/O location is written the value written will be put into

the OCRnA Buffer Register. The OCRnA Compare Register will then be updated with the value

in the Buffer Register at the next timer clock cycle the TCNTn matches TOP. The update is done

at the same timer clock cycle as the TCNTn is cleared and the TOVn Flag is set.

Using the ICRn Register for defining TOP works well when using fixed TOP values. By using

ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However,

if the base PWM frequency is actively changed (by changing the TOP value), using the OCRnA

as TOP is clearly a better choice due to its double buffer feature.

In fast PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins.

Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output

can be generated by setting the COMnx1:0 to three (see Table on page 142). The actual OCnx

value will only be visible on the port pin if the data direction for the port pin is set as output

(DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at

the compare match between OCRnx and TCNTn, and clearing (or setting) the OCnx Register at

the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

f

clk_I/O

f

= ----------------------------------

OCnxPWM

N ⋅ (1 + TOP)

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCRnx Register represents special cases when generating a PWM

waveform output in the fast PWM mode. If the OCRnx is set equal to BOTTOM (0x0000) the out-

put will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCRnx equal to TOP

will result in a constant high or low output (depending on the polarity of the output set by the

COMnx1:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-

ting OCnA to toggle its logical level on each compare match (COMnA1:0 = 1). This applies only

if OCR1A is used to define the TOP value (WGM13:0 = 15). The waveform generated will have

a maximum frequency of f_{OC A}= f_{clk_I/O}/2 when OCRnA is set to zero (0x0000). This feature is

n

similar to the OCnA toggle in CTC mode, except the double buffer feature of the Output Com-

pare unit is enabled in the fast PWM mode.

14.8.4

Phase Correct PWM Mode

The phase correct Pulse Width Modulation or phase correct PWM mode (WGMn3:0 = 1, 2, 3,

10, or 11) provides a high resolution phase correct PWM waveform generation option. The

phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-

slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from

TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is

cleared on the compare match between TCNTn and OCRnx while upcounting, and set on the

compare match while downcounting. In inverting Output Compare mode, the operation is

inverted. The dual-slope operation has lower maximum operation frequency than single slope

operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes

are preferred for motor control applications.

The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined

by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to

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0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolu-

tion in bits can be calculated by using the following equation:

log(TOP + 1)

R

= ----------------------------------

PCPWM

log(2)

In phase correct PWM mode the counter is incremented until the counter value matches either

one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 1, 2, or 3), the value in ICRn

(WGMn3:0 = 10), or the value in OCRnA (WGMn3:0 = 11). The counter has then reached the

TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clock

cycle. The timing diagram for the phase correct PWM mode is shown on Figure 14-8. The figure

shows phase correct PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn

value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The

diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on

the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx Inter-

rupt Flag will be set when a compare match occurs.

Figure 14-8. Phase Correct PWM Mode, Timing Diagram

OCRnx/TOP Update and

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

TOVn Interrupt Flag Set

(Interrupt on Bottom)

TCNTn

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

OCnx

1

2

3

4

Period

The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. When

either OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn Flag is set accord-

ingly at the same timer clock cycle as the OCRnx Registers are updated with the double buffer

value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter

reaches the TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is higher or

equal to the value of all of the Compare Registers. If the TOP value is lower than any of the

Compare Registers, a compare match will never occur between the TCNTn and the OCRnx.

Note that when using fixed TOP values, the unused bits are masked to zero when any of the

OCRnx Registers are written. As the third period shown in Figure 14-8 illustrates, changing the

TOP actively while the Timer/Counter is running in the phase correct mode can result in an

unsymmetrical output. The reason for this can be found in the time of update of the OCRnx Reg-

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ister. Since the OCRnx update occurs at TOP, the PWM period starts and ends at TOP. This

implies that the length of the falling slope is determined by the previous TOP value, while the

length of the rising slope is determined by the new TOP value. When these two values differ the

two slopes of the period will differ in length. The difference in length gives the unsymmetrical

result on the output.

It is recommended to use the phase and frequency correct mode instead of the phase correct

mode when changing the TOP value while the Timer/Counter is running. When using a static

TOP value there are practically no differences between the two modes of operation.

In phase correct PWM mode, the compare units allow generation of PWM waveforms on the

OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted

PWM output can be generated by setting the COMnx1:0 to three (See Table 14-3 on page 143).

The actual OCnx value will only be visible on the port pin if the data direction for the port pin is

set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx

Register at the compare match between OCRnx and TCNTn when the counter increments, and

clearing (or setting) the OCnx Register at compare match between OCRnx and TCNTn when

the counter decrements. The PWM frequency for the output when using phase correct PWM can

be calculated by the following equation:

f

clk_I/O

f

= ---------------------------

OCnxPCPWM

2 ⋅ N ⋅ TOP

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCRnx Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the

output will be continuously low and if set equal to TOP the output will be continuously high for

non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If

OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1:0 = 1, the OC1A output

will toggle with a 50% duty cycle.

14.8.5

Phase and Frequency Correct PWM Mode

The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM

mode (WGMn3:0 = 8 or 9) provides a high resolution phase and frequency correct PWM wave-

form generation option. The phase and frequency correct PWM mode is, like the phase correct

PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM

(0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the

Output Compare (OCnx) is cleared on the compare match between TCNTn and OCRnx while

upcounting, and set on the compare match while downcounting. In inverting Compare Output

mode, the operation is inverted. The dual-slope operation gives a lower maximum operation fre-

quency compared to the single-slope operation. However, due to the symmetric feature of the

dual-slope PWM modes, these modes are preferred for motor control applications.

The main difference between the phase correct, and the phase and frequency correct PWM

mode is the time the OCRnx Register is updated by the OCRnx Buffer Register, (see Figure 14-

8 and Figure 14-9).

The PWM resolution for the phase and frequency correct PWM mode can be defined by either

ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and

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the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can

be calculated using the following equation:

log(TOP + 1)

R

= ----------------------------------

PFCPWM

log(2)

In phase and frequency correct PWM mode the counter is incremented until the counter value

matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA (WGMn3:0 = 9). The

counter has then reached the TOP and changes the count direction. The TCNTn value will be

equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency

correct PWM mode is shown on Figure 14-9. The figure shows phase and frequency correct

PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing dia-

gram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-

inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes repre-

sent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a

compare match occurs.

Figure 14-9. Phase and Frequency Correct PWM Mode, Timing Diagram

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

OCRnx/TOP Updateand

TOVn Interrupt Flag Set

(Interrupt on Bottom)

TCNTn

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

OCnx

1

2

3

4

Period

The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx

Registers are updated with the double buffer value (at BOTTOM). When either OCRnA or ICRn

is used for defining the TOP value, the OCnA or ICFn Flag set when TCNTn has reached TOP.

The Interrupt Flags can then be used to generate an interrupt each time the counter reaches the

TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is higher or

equal to the value of all of the Compare Registers. If the TOP value is lower than any of the

Compare Registers, a compare match will never occur between the TCNTn and the OCRnx.

As Figure 14-9 shows the output generated is, in contrast to the phase correct mode, symmetri-

cal in all periods. Since the OCRnx Registers are updated at BOTTOM, the length of the rising

and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore

frequency correct.

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Using the ICRn Register for defining TOP works well when using fixed TOP values. By using

ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However,

if the base PWM frequency is actively changed by changing the TOP value, using the OCRnA as

TOP is clearly a better choice due to its double buffer feature.

In phase and frequency correct PWM mode, the compare units allow generation of PWM wave-

forms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and

an inverted PWM output can be generated by setting the COMnx1:0 to three (See Table 14-3 on

page 143). The actual OCnx value will only be visible on the port pin if the data direction for the

port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing)

the OCnx Register at the compare match between OCRnx and TCNTn when the counter incre-

ments, and clearing (or setting) the OCnx Register at compare match between OCRnx and

TCNTn when the counter decrements. The PWM frequency for the output when using phase

and frequency correct PWM can be calculated by the following equation:

f

clk_I/O

f

= ---------------------------

OCnxPFCPWM

2 ⋅ N ⋅ TOP

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCRnx Register represents special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the

output will be continuously low and if set equal to TOP the output will be set to high for non-

inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A

is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle

with a 50% duty cycle.

14.9 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk_Tn) is therefore shown as a

clock enable signal in the following figures. The figures include information on when Interrupt

Flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for

modes utilizing double buffering). Figure 14-10 shows a timing diagram for the setting of OCFnx.

Figure 14-10. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

OCRnx

OCFnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

Figure 14-11 shows the same timing data, but with the prescaler enabled.

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Figure 14-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

OCRnx

OCFnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

Figure 14-12 shows the count sequence close to TOP in various modes. When using phase and

frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams

will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.

The same renaming applies for modes that set the TOVn Flag at BOTTOM.

Figure 14-12. Timer/Counter Timing Diagram, no Prescaling

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

TOP - 1

TOP

BOTTOM

TOP - 1

BOTTOM + 1

TOP - 2

(CTC and FPWM)

TCNTn

(PC and PFC PWM)

TOVn (FPWM)

and ICFn (if used

as TOP)

OCRnx

(Update at TOP)

New OCRnx Value

Old OCRnx Value

Figure 14-13 shows the same timing data, but with the prescaler enabled.

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Figure 14-13. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)

clk

I/O

clk

(clk^T/ⁿ8)

I/O

TCNTn

TOP - 1

TOP

BOTTOM

TOP - 1

BOTTOM + 1

TOP - 2

(CTC and FPWM)

TCNTn

(PC and PFC PWM)

TOVn(FPWM)

and ICFn(if used

as TOP)

OCRnx

(Update at TOP)

Old OCRnx Value

New OCRnx Value

14.10 16-bit Timer/Counter Register Description

14.10.1 Timer/Counter1 Control Register A – TCCR1A

Bit

7

6

5

4

3

2

1

0

COM1A

1

COM1A

0

COM1B

1

COM1B

0

COM1C

1

COM1C

0

WGM11

WGM1

0

TCCR1

A

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

14.10.2 Timer/Counter3 Control Register A – TCCR3A

Bit

7

6

5

4

3

2

1

0

COM3A

1

COM3A

0

COM3B

1

COM3B

0

COM3C

1

COM3C

0

WGM3

1

WGM3

0

TCCR3

A

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A

• Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B

• Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C

The COMnA1:0, COMnB1:0, and COMnC1:0 control the output compare pins (OCnA, OCnB,

and OCnC respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the

OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or

both of the COMnB1:0 bits are written to one, the OCnB output overrides the normal port func-

tionality of the I/O pin it is connected to. If one or both of the COMnC1:0 bits are written to one,

the OCnC output overrides the normal port functionality of the I/O pin it is connected to. How-

ever, note that the Data Direction Register (DDR) bit corresponding to the OCnA, OCnB or

OCnC pin must be set in order to enable the output driver.

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When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is

dependent of the WGMn3:0 bits setting. Table 14-1 shows the COMnx1:0 bit functionality when

the WGMn3:0 bits are set to a normal or a CTC mode (non-PWM).

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.

Table 14-1. Compare Output Mode, non-PWM

COMnA1/COMnB1/

COMnC1

COMnA0/COMnB0/

COMnC0

Description

Normal port operation, OCnA/OCnB/OCnC

disconnected.

0

1

0

1

0

1

Toggle OCnA/OCnB/OCnC on compare

match.

Clear OCnA/OCnB/OCnC on compare

match (set output to low level).

Set OCnA/OCnB/OCnC on compare match

(set output to high level).

Table 14-2 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast

PWM mode.

Table 14-2. Compare Output Mode, Fast PWM

COMnA1/COMnB1/

COMnC0

COMnA0/COMnB0/

COMnC0

Description

Normal port operation, OCnA/OCnB/OCnC

disconnected.

0

WGM13:0 = 14 or 15: Toggle OC1A on

Compare Match, OC1B and OC1C

0

1

disconnected (normal port operation). For all

other WGM1 settings, normal port operation,

OC1A/OC1B/OC1C disconnected.

Clear OCnA/OCnB/OCnC on compare

match, set OCnA/OCnB/OCnC at TOP

1

0

1

Set OCnA/OCnB/OCnC on compare match,

clear OCnA/OCnB/OCnC at TOP

Note:

A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and

COMnA1/COMnB1/COMnC1 is set. In this case the compare match is ignored, but the set or clear

is done at TOP. See “Fast PWM Mode” on page 108. for more details.

Table 14-3 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase

correct and frequency correct PWM mode.

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Table 14-3. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM

COMnA1/COMnB/

COMnC1

COMnA0/COMnB0/

COMnC0

Description

Normal port operation, OCnA/OCnB/OCnC

disconnected.

0

WGM13:0 = 8, 9 10 or 11: Toggle OC1A on

Compare Match, OC1B and OC1C

0

1

disconnected (normal port operation). For all

other WGM1 settings, normal port operation,

OC1A/OC1B/OC1C disconnected.

Clear OCnA/OCnB/OCnC on compare

match when up-counting. Set

OCnA/OCnB/OCnC on compare match

when downcounting.

1

0

1

Set OCnA/OCnB/OCnC on compare match

when up-counting. Clear

OCnA/OCnB/OCnC on compare match

when downcounting.

Note:

A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and

COMnA1/COMnB1//COMnC1 is set. See “Phase Correct PWM Mode” on page 110. for more

details.

• Bit 1:0 – WGMn1:0: Waveform Generation Mode

Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting

sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-

form generation to be used, see Table 14-4. Modes of operation supported by the Timer/Counter

unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types

of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 107.).

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Table 14-4. Waveform Generation Mode Bit Description⁽¹⁾

WGMn2

(CTCn)

WGMn1

WGMn0

Timer/Counter Mode of

Update of

OCRnx at

TOVn Flag

Set on

Mode

WGMn3

(PWMn1) (PWMn0) Operation

TOP

0

1

2

3

4

5

6

7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Normal

0xFFFF

0x00FF

0x01FF

0x03FF

OCRnA

0x00FF

0x01FF

0x03FF

Immediate

TOP

MAX

PWM, Phase Correct, 8-bit

PWM, Phase Correct, 9-bit

PWM, Phase Correct, 10-bit

CTC

BOTTOM

MAX

TOP

Immediate

TOP

Fast PWM, 8-bit

TOP

Fast PWM, 9-bit

TOP

Fast PWM, 10-bit

TOP

PWM, Phase and Frequency

Correct

8

9

1

0

1

ICRn

BOTTOM

PWM, Phase and Frequency

Correct

OCRnA

10

11

12

13

14

15

1

0

1

0

1

0

1

0

1

0

1

PWM, Phase Correct

CTC

ICRn

OCRnA

ICRn

–

TOP

Immediate

–

BOTTOM

MAX

(Reserved)

–

Fast PWM

ICRn

OCRnA

TOP

Fast PWM

TOP

Note:

1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and

location of these bits are compatible with previous versions of the timer.

14.10.3 Timer/Counter1 Control Register B – TCCR1B

Bit

7

6

5

–

R

0

4

3

2

1

0

ICNC1

R/W

0

ICES1

R/W

0

WGM13

R/W

0

WGM12

R/W

0

CS12

R/W

0

CS11

R/W

0

CS10

R/W

0

TCCR1B

Read/Write

Initial Value

14.10.4 Timer/Counter3 Control Register B – TCCR3B

Bit

7

6

5

–

R

0

4

3

2

1

0

ICNC3

R/W

0

ICES3

R/W

0

WGM33

R/W

0

WGM32

R/W

0

CS32

R/W

0

CS31

R/W

0

CS30

R/W

0

TCCR3B

Read/Write

Initial Value

• Bit 7 – ICNCn: Input Capture Noise Canceler

Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is

activated, the input from the Input Capture Pin (ICPn) is filtered. The filter function requires four

successive equal valued samples of the ICPn pin for changing its output. The input capture is

therefore delayed by four Oscillator cycles when the noise canceler is enabled.

• Bit 6 – ICESn: Input Capture Edge Select

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This bit selects which edge on the Input Capture Pin (ICPn) that is used to trigger a capture

event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and

when the ICESn bit is written to one, a rising (positive) edge will trigger the capture.

When a capture is triggered according to the ICESn setting, the counter value is copied into the

Input Capture Register (ICRn). The event will also set the Input Capture Flag (ICFn), and this

can be used to cause an Input Capture Interrupt, if this interrupt is enabled.

When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the

TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the input cap-

ture function is disabled.

• Bit 5 – Reserved Bit

This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be

written to zero when TCCRnB is written.

• Bit 4:3 – WGMn3:2: Waveform Generation Mode

See TCCRnA Register description.

• Bit 2:0 – CSn2:0: Clock Select

The three clock select bits select the clock source to be used by the Timer/Counter, see Figure

13-8 and Figure 13-9.

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Table 14-5. Clock Select Bit Description

CSn2

CSn1

CSn0

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No clock source. (Timer/Counter stopped)

clk_I/O/1 (No prescaling

clk_I/O/8 (From prescaler)

clk_I/O/64 (From prescaler)

clk_I/O/256 (From prescaler)

clk_I/O/1024 (From prescaler)

External clock source on Tn pin. Clock on falling edge

External clock source on Tn pin. Clock on rising edge

If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the

counter even if the pin is configured as an output. This feature allows software control of the

counting.

14.10.5 Timer/Counter1 Control Register C – TCCR1C

Bit

7

6

5

4

–

R

0

3

–

R

0

2

–

R

0

1

–

R

0

–

R

0

FOC1A

FOC1B

FOC1C

TCCR1C

Read/Write

Initial Value

W

0

W

0

W

0

14.10.6 Timer/Counter3 Control Register C – TCCR3C

Bit

7

6

5

4

–

R

0

3

–

R

0

2

–

R

0

1

–

R

0

–

R

0

FOC3A

FOC3B

FOC3C

TCCR3C

Read/Write

Initial Value

W

0

W

0

W

0

• Bit 7 – FOCnA: Force Output Compare for Channel A

• Bit 6 – FOCnB: Force Output Compare for Channel B

• Bit 5 – FOCnC: Force Output Compare for Channel C

The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM

mode. When writing a logical one to the FOCnA/FOCnB/FOCnC bit, an immediate compare

match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed

according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are imple-

mented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the

effect of the forced compare.

A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in Clear

Timer on Compare Match (CTC) mode using OCRnA as TOP.

The FOCnA/FOCnB/FOCnB bits are always read as zero.

• Bit 4:0 – Reserved Bits

These bits are reserved for future use. For ensuring compatibility with future devices, these bits

must be written to zero when TCCRnC is written.

14.10.7 Timer/Counter1 – TCNT1H and TCNT1L

Bit

7

6

5

4

3

2

1

0

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TCNT1[15:8]

TCNT1[7:0]

TCNT1H

TCNT1L

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

14.10.8 Timer/Counter3 – TCNT3H and TCNT3L

Bit

7

6

5

4

3

2

1

0

TCNT3[15:8]

TCNT3[7:0]

TCNT3H

TCNT3L

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct

access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To

ensure that both the high and low bytes are read and written simultaneously when the CPU

accesses these registers, the access is performed using an 8-bit temporary High Byte Register

(TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit

Registers” on page 121.

Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a com-

pare match between TCNTn and one of the OCRnx Registers.

Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock

for all compare units.

14.10.9 Output Compare Register 1 A – OCR1AH and OCR1AL

Bit

7

6

5

4

3

2

1

0

OCR1A[15:8]

OCR1A[7:0]

OCR1AH

OCR1AL

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

14.10.10 Output Compare Register 1 B – OCR1BH and OCR1BL

Bit

7

6

5

4

3

2

1

0

OCR1B[15:8]

OCR1B[7:0]

OCR1BH

OCR1BL

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

14.10.11 Output Compare Register 1 C – OCR1CH and OCR1CL

Bit

7

6

5

4

3

2

1

0

OCR1C[15:8]

OCR1C[7:0]

OCR1CH

OCR1CL

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

14.10.12 Output Compare Register 3 A – OCR3AH and OCR3AL

Bit

7

6

5

4

3

2

1

0

OCR3A[15:8]

OCR3A[7:0]

OCR3AH

OCR3AL

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

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14.10.13 Output Compare Register 3 B – OCR3BH and OCR3BL

Bit

7

6

5

4

3

2

1

0

OCR3B[15:8]

OCR3B[7:0]

OCR3BH

OCR3BL

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

14.10.14 Output Compare Register 3 C – OCR3CH and OCR3CL

Bit

7

6

5

4

3

2

1

0

OCR3C[15:8]

OCR3C[7:0]

OCR3CH

OCR3CL

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Registers contain a 16-bit value that is continuously compared with the

counter value (TCNTn). A match can be used to generate an Output Compare interrupt, or to

generate a waveform output on the OCnx pin.

The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are

written simultaneously when the CPU writes to these registers, the access is performed using an

8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other

16-bit registers. See “Accessing 16-bit Registers” on page 121.

14.10.15 Input Capture Register 1 – ICR1H and ICR1L

Bit

7

6

5

4

3

2

1

0

ICR1[15:8]

ICR1[7:0]

R/W

ICR1H

ICR1L

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

14.10.16 Input Capture Register 3 – ICR3H and ICR3L

Bit

7

6

5

4

3

2

1

0

ICR3[15:8]

ICR3[7:0]

R/W

ICR3H

ICR3L

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the

ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture

can be used for defining the counter TOP value.

The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read

simultaneously when the CPU accesses these registers, the access is performed using an 8-bit

temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit

registers. See “Accessing 16-bit Registers” on page 121.

14.10.17 Timer/Counter1 Interrupt Mask Register – TIMSK1

Bit

7

6

5

4

3

2

1

0

–

ICIE1

–

OCIE1

C

OCIE1B

OCIE1A

TOIE1

TIMSK1

Read/Write

Initial Value

R

0

R

0

R/W

0

R

0

R/W

0

R/W

0

R/W

0

R/W

0

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14.10.18 Timer/Counter3 Interrupt Mask Register – TIMSK3

Bit

7

6

5

4

3

2

1

0

–

ICIE3

–

OCIE3

C

OCIE3B

OCIE3A

TOIE3

TIMSK3

Read/Write

Initial Value

R

0

R

0

R/W

0

R

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt

Vector (See “Interrupts” on page 70.) is executed when the ICFn Flag, located in TIFRn, is set.

• Bit 3 – OCIEnC: Timer/Countern, Output Compare C Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The corresponding

Interrupt Vector (See “Interrupts” on page 70.) is executed when the OCFnC Flag, located in

TIFRn, is set.

• Bit 2 – OCIEnB: Timer/Countern, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The corresponding

Interrupt Vector (See “Interrupts” on page 70.) is executed when the OCFnB Flag, located in

TIFRn, is set.

• Bit 1 – OCIEnA: Timer/Countern, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Countern Output Compare A Match interrupt is enabled. The corresponding

Interrupt Vector (See “Interrupts” on page 70.) is executed when the OCFnA Flag, located in

TIFRn, is set.

• Bit 0 – TOIEn: Timer/Countern, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Countern Overflow interrupt is enabled. The corresponding Interrupt Vector

(See “Interrupts” on page 70.) is executed when the TOVn Flag, located in TIFRn, is set.

14.10.19 Timer/Counter1 Interrupt Flag Register – TIFR1

Bit

7

6

5

4

–

R

0

3

2

1

0

–

ICF1

OCF1C

R/W

0

OCF1B

R/W

0

OCF1A

R/W

0

TOV1

R/W

0

TIFR1

Read/Write

Initial Value

R

0

R

0

R/W

0

14.10.20 Timer/Counter3 Interrupt Flag Register – TIFR3

Bit

7

–

R

0

6

–

R

0

5

4

–

R

0

3

2

1

0

ICF3

R/W

0

OCF3C

R/W

0

OCF3B

R/W

0

OCF3A

R/W

0

TOV3

R/W

0

TIFR3

Read/Write

Initial Value

• Bit 5 – ICFn: Timer/Countern, Input Capture Flag

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This flag is set when a capture event occurs on the ICPn pin. When the Input Capture Register

(ICRn) is set by the WGMn3:0 to be used as the TOP value, the ICFn Flag is set when the

counter reaches the TOP value.

ICFn is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,

ICFn can be cleared by writing a logic one to its bit location.

• Bit 3– OCFnC: Timer/Countern, Output Compare C Match Flag

This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output

Compare Register C (OCRnC).

Note that a Forced Output Compare (FOCnC) strobe will not set the OCFnC Flag.

OCFnC is automatically cleared when the Output Compare Match C Interrupt Vector is exe-

cuted. Alternatively, OCFnC can be cleared by writing a logic one to its bit location.

• Bit 2 – OCFnB: Timer/Counter1, Output Compare B Match Flag

This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output

Compare Register B (OCRnB).

Note that a Forced Output Compare (FOCnB) strobe will not set the OCFnB Flag.

OCFnB is automatically cleared when the Output Compare Match B Interrupt Vector is exe-

cuted. Alternatively, OCFnB can be cleared by writing a logic one to its bit location.

• Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag

This flag is set in the timer clock cycle after the counter (TCNTn value matches the Output Com-

pare Register A (OCRnA).

Note that a Forced Output Compare (FOCnA) strobe will not set the OCFnA Flag.

OCFnA is automatically cleared when the Output Compare Match A Interrupt Vector is exe-

cuted. Alternatively, OCFnA can be cleared by writing a logic one to its bit location.

• Bit 0 – TOVn: Timer/Countern, Overflow Flag

The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes,

the TOVn Flag is set when the timer overflows. Refer to Table 14-4 on page 144 for the TOVn

Flag behavior when using another WGMn3:0 bit setting.

TOVn is automatically cleared when the Timer/Countern Overflow Interrupt Vector is executed.

Alternatively, TOVn can be cleared by writing a logic one to its bit location.

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15. 8-bit Timer/Counter2 with PWM and Asynchronous Operation

Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main

features are:

• Single Channel Counter

• Clear Timer on Compare Match (Auto Reload)

• Glitch-free, Phase Correct Pulse Width Modulator (PWM)

• Frequency Generator

• 10-bit Clock Prescaler

• Overflow and Compare Match Interrupt Sources (TOV2, OCF2A and OCF2B)

• Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock

15.1 Overview

A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 15-1.. For the actual

placement of I/O pins, see “Pin Configurations” on page 3. CPU accessible I/O Registers, includ-

ing I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations

are listed in the “8-bit Timer/Counter Register Description” on page 162.

The Power Reduction Timer/Counter2 bit, PRTIM2, in “Power Reduction Register 0 - PRR0” on

page 56 must be written to zero to enable Timer/Counter2 module.

Figure 15-1. 8-bit Timer/Counter Block Diagram

Count

TOVn

(Int.Req.)

Clear

Control Logic

Direction

clk_Tn

TOSC1

TOSC2

T/C

Oscillator

Prescaler

TOP

BOTTOM

clk_I/O

Timer/Counter

TCNTn

=

0

OCnA

(Int.Req.)

Waveform

Generation

OCnA

OCnB

=

OCRnA

Fixed

TOP

Value

OCnB

(Int.Req.)

Waveform

Generation

=

OCRnB

clk_I/O

Synchronized Status flags

Synchronization Unit

clk_ASY

asynchronous mode

select (ASn)

Status flags

ASSRn

TCCRnA

TCCRnB

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15.1.1

Registers

The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit reg-

isters. Interrupt request (abbreviated to Int.Req.) signals are all visible in the Timer Interrupt Flag

Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register

(TIMSK2). TIFR2 and TIMSK2 are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from

the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by

the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock

source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inac-

tive when no clock source is selected. The output from the Clock Select logic is referred to as the

timer clock (clk_T2).

The double buffered Output Compare Register (OCR2A and OCR2B) are compared with the

Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-

erator to generate a PWM or variable frequency output on the Output Compare pins (OC2A and

OC2B). See “Output Compare Unit” on page 153. for details. The compare match event will also

set the Compare Flag (OCF2A or OCF2B) which can be used to generate an Output Compare

interrupt request.

15.1.2

Definitions

Many register and bit references in this document are written in general form. A lower case “n”

replaces the Timer/Counter number, in this case 2. However, when using the register or bit

defines in a program, the precise form must be used, i.e., TCNT2 for accessing Timer/Counter2

counter value and so on.

The definitions in the table below are also used extensively throughout the section.

BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00).

MAX

TOP

The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

The counter reaches the TOP when it becomes equal to the highest

value in the count sequence. The TOP value can be assigned to be the

fixed value 0xFF (MAX) or the value stored in the OCR2A Register. The

assignment is dependent on the mode of operation.

15.2 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal synchronous or an external asynchronous

clock source. The clock source clk_T2is by default equal to the MCU clock, clk_I/O. When the AS2

bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter

Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see “Asyn-

chronous Status Register – ASSR” on page 167. For details on clock sources and prescaler, see

“Timer/Counter Prescaler” on page 171.

15.3 Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

15-2 shows a block diagram of the counter and its surrounding environment.

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Figure 15-2. Counter Unit Block Diagram

TOVn

(Int.Req.)

DATA BUS

TOSC1

count

clear

T/C

Oscillator

clk _Tn

TCNTn

Control Logic

Prescaler

direction

TOSC2

clk

bottom

top

I/O

Signal description (internal signals):

count

direction

clear

Increment or decrement TCNT2 by 1.

Selects between increment and decrement.

Clear TCNT2 (set all bits to zero).

clk_Tn

Timer/Counter clock, referred to as clk_T2in the following.

Signalizes that TCNT2 has reached maximum value.

Signalizes that TCNT2 has reached minimum value (zero).

top

bottom

Depending on the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clk_T2). clk_T2can be generated from an external or internal clock source,

selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the

timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of

whether clk_T2is present or not. A CPU write overrides (has priority over) all counter clear or

count operations.

The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in

the Timer/Counter Control Register (TCCR2A) and the WGM22 located in the Timer/Counter

Control Register B (TCCR2B). There are close connections between how the counter behaves

(counts) and how waveforms are generated on the Output Compare outputs OC2A and OC2B.

For more details about advanced counting sequences and waveform generation, see “Modes of

Operation” on page 156.

The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by

the WGM22:0 bits. TOV2 can be used for generating a CPU interrupt.

15.4 Output Compare Unit

The 8-bit comparator continuously compares TCNT2 with the Output Compare Register

(OCR2A and OCR2B). Whenever TCNT2 equals OCR2A or OCR2B, the comparator signals a

match. A match will set the Output Compare Flag (OCF2A or OCF2B) at the next timer clock

cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output

Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is exe-

cuted. Alternatively, the Output Compare Flag can be cleared by software by writing a logical

one to its I/O bit location. The Waveform Generator uses the match signal to generate an output

according to operating mode set by the WGM22:0 bits and Compare Output mode (COM2x1:0)

bits. The max and bottom signals are used by the Waveform Generator for handling the special

cases of the extreme values in some modes of operation (“Modes of Operation” on page 156).

Figure 14-10 on page 138 shows a block diagram of the Output Compare unit.

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Figure 15-3. Output Compare Unit, Block Diagram

DATA BUS

OCRnx

TCNTn

=

(8-bit Comparator )

OCFnx (Int.Req.)

top

bottom

FOCn

Waveform Generator

OCnx

WGMn1:0

COMnX1:0

The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM)

modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double

buffering is disabled. The double buffering synchronizes the update of the OCR2x Compare

Register to either top or bottom of the counting sequence. The synchronization prevents the

occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR2x Register access may seem complex, but this is not case. When the double buffering

is enabled, the CPU has access to the OCR2x Buffer Register, and if double buffering is dis-

abled the CPU will access the OCR2x directly.

15.4.1

Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOC2x) bit. Forcing compare match will not set the

OCF2x Flag or reload/clear the timer, but the OC2x pin will be updated as if a real compare

match had occurred (the COM2x1:0 bits settings define whether the OC2x pin is set, cleared or

toggled).

15.4.2

15.4.3

Compare Match Blocking by TCNT2 Write

All CPU write operations to the TCNT2 Register will block any compare match that occurs in the

next timer clock cycle, even when the timer is stopped. This feature allows OCR2x to be initial-

ized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is

enabled.

Using the Output Compare Unit

Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock

cycle, there are risks involved when changing TCNT2 when using the Output Compare channel,

independently of whether the Timer/Counter is running or not. If the value written to TCNT2

equals the OCR2x value, the compare match will be missed, resulting in incorrect waveform

generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is

downcounting.

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The setup of the OC2x should be performed before setting the Data Direction Register for the

port pin to output. The easiest way of setting the OC2x value is to use the Force Output Com-

pare (FOC2x) strobe bit in Normal mode. The OC2x Register keeps its value even when

changing between Waveform Generation modes.

Be aware that the COM2x1:0 bits are not double buffered together with the compare value.

Changing the COM2x1:0 bits will take effect immediately.

15.5 Compare Match Output Unit

The Compare Output mode (COM2x1:0) bits have two functions. The Waveform Generator uses

the COM2x1:0 bits for defining the Output Compare (OC2x) state at the next compare match.

Also, the COM2x1:0 bits control the OC2x pin output source. Figure 15-4 shows a simplified

schematic of the logic affected by the COM2x1:0 bit setting. The I/O Registers, I/O bits, and I/O

pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers

(DDR and PORT) that are affected by the COM2x1:0 bits are shown. When referring to the

OC2x state, the reference is for the internal OC2x Register, not the OC2x pin.

Figure 15-4. Compare Match Output Unit, Schematic

COMnx1

Waveform

Generator

COMnx0

FOCnx

D

Q

1

0

OCnx

D

Q

PORT

D

Q

DDR

clk_I/O

The general I/O port function is overridden by the Output Compare (OC2x) from the Waveform

Generator if either of the COM2x1:0 bits are set. However, the OC2x pin direction (input or out-

put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction

Register bit for the OC2x pin (DDR_OC2x) must be set as output before the OC2x value is visi-

ble on the pin. The port override function is independent of the Waveform Generation mode.

The design of the Output Compare pin logic allows initialization of the OC2x state before the out-

put is enabled. Note that some COM2x1:0 bit settings are reserved for certain modes of

operation. See “8-bit Timer/Counter Register Description” on page 162.

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15.5.1

Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes.

For all modes, setting the COM2x1:0 = 0 tells the Waveform Generator that no action on the

OC2x Register is to be performed on the next compare match. For compare output actions in the

non-PWM modes refer to Table 15-4 on page 163. For fast PWM mode, refer to Table 15-5 on

page 164, and for phase correct PWM refer to Table 15-6 on page 164.

A change of the COM2x1:0 bits state will have effect at the first compare match after the bits are

written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOC2x strobe bits.

15.6 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is

defined by the combination of the Waveform Generation mode (WGM22:0) and Compare Output

mode (COM2x1:0) bits. The Compare Output mode bits do not affect the counting sequence,

while the Waveform Generation mode bits do. The COM2x1:0 bits control whether the PWM out-

put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes

the COM2x1:0 bits control whether the output should be set, cleared, or toggled at a compare

match (See “Compare Match Output Unit” on page 155.).

For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 160.

15.6.1

Normal Mode

The simplest mode of operation is the Normal mode (WGM22:0 = 0). In this mode the counting

direction is always up (incrementing), and no counter clear is performed. The counter simply

overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-

tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same

timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case behaves like a ninth

bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt

that automatically clears the TOV2 Flag, the timer resolution can be increased by software.

There are no special cases to consider in the Normal mode, a new counter value can be written

anytime.

The Output Compare unit can be used to generate interrupts at some given time. Using the Out-

put Compare to generate waveforms in Normal mode is not recommended, since this will

occupy too much of the CPU time.

15.6.2

Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM22:0 = 2), the OCR2A Register is used to

manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter

value (TCNT2) matches the OCR2A. The OCR2A defines the top value for the counter, hence

also its resolution. This mode allows greater control of the compare match output frequency. It

also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Table 15-5. The counter value (TCNT2)

increases until a compare match occurs between TCNT2 and OCR2A, and then counter

(TCNT2) is cleared.

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Figure 15-5. CTC Mode, Timing Diagram

OCnx Interrupt Flag Set

TCNTn

OCnx

(Toggle)

(COMnx1:0 = 1)

1

2

3

4

Period

An interrupt can be generated each time the counter value reaches the TOP value by using the

OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating

the TOP value. However, changing TOP to a value close to BOTTOM when the counter is run-

ning with none or a low prescaler value must be done with care since the CTC mode does not

have the double buffering feature. If the new value written to OCR2A is lower than the current

value of TCNT2, the counter will miss the compare match. The counter will then have to count to

its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can

occur.

For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical

level on each compare match by setting the Compare Output mode bits to toggle mode

(COM2A1:0 = 1). The OC2A value will not be visible on the port pin unless the data direction for

the pin is set to output. The waveform generated will have a maximum frequency of f_OC2A

_{clk_I/O}/2 when OCR2A is set to zero (0x00). The waveform frequency is defined by the following

equation:

=

f

clk_I/O

f

= -------------------------------------------------

OCnx

2 ⋅ N ⋅ (1 + OCRnx)

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the

counter counts from MAX to 0x00.

15.6.3

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM22:0 = 3 or 7) provides a high fre-

quency PWM waveform generation option. The fast PWM differs from the other PWM option by

its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOT-

TOM. TOP is defined as 0xFF when WGM22:0 = 3, and OCR2A when MGM22:0 = 7. In non-

inverting Compare Output mode, the Output Compare (OC2x) is cleared on the compare match

between TCNT2 and OCR2x, and set at BOTTOM. In inverting Compare Output mode, the out-

put is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the

operating frequency of the fast PWM mode can be twice as high as the phase correct PWM

mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited

for power regulation, rectification, and DAC applications. High frequency allows physically small

sized external components (coils, capacitors), and therefore reduces total system cost.

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In fast PWM mode, the counter is incremented until the counter value matches the TOP value.

The counter is then cleared at the following timer clock cycle. The timing diagram for the fast

PWM mode is shown in Figure 15-6. The TCNT2 value is in the timing diagram shown as a his-

togram for illustrating the single-slope operation. The diagram includes non-inverted and

inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare

matches between OCR2x and TCNT2.

Figure 15-6. Fast PWM Mode, Timing Diagram

OCRnx Interrupt Flag Set

OCRnx Update and

TOVn Interrupt Flag Set

TCNTn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCnx

1

2

3

4

5

6

7

Period

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches TOP. If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin.

Setting the COM2x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output

can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3,

and OCR2A when WGM2:0 = 7 (See Table 15-2 on page 163). The actual OC2x value will only

be visible on the port pin if the data direction for the port pin is set as output. The PWM wave-

form is generated by setting (or clearing) the OC2x Register at the compare match between

OCR2x and TCNT2, and clearing (or setting) the OC2x Register at the timer clock cycle the

counter is cleared (changes from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

f

clk_I/O

f

= -----------------

OCnxPWM

N ⋅ 256

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

The extreme values for the OCR2A Register represent special cases when generating a PWM

waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will

be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result

in a constantly high or low output (depending on the polarity of the output set by the COM2A1:0

bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-

ting OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The waveform

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generated will have a maximum frequency of f_oc2= f_{clk_I/O}/2 when OCR2A is set to zero. This fea-

ture is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output

Compare unit is enabled in the fast PWM mode.

15.6.4

Phase Correct PWM Mode

The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phase correct

PWM waveform generation option. The phase correct PWM mode is based on a dual-slope

operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOT-

TOM. TOP is defined as 0xFF when WGM22:0 = 1, and OCR2A when MGM22:0 = 5. In non-

inverting Compare Output mode, the Output Compare (OC2x) is cleared on the compare match

between TCNT2 and OCR2x while upcounting, and set on the compare match while downcount-

ing. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has

lower maximum operation frequency than single slope operation. However, due to the symmet-

ric feature of the dual-slope PWM modes, these modes are preferred for motor control

applications.

In phase correct PWM mode the counter is incremented until the counter value matches TOP.

When the counter reaches TOP, it changes the count direction. The TCNT2 value will be equal

to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown

on Figure 15-7. The TCNT2 value is in the timing diagram shown as a histogram for illustrating

the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The

small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x

and TCNT2.

Figure 15-7. Phase Correct PWM Mode, Timing Diagram

OCnx Interrupt Flag Set

OCRnx Update

TOVn Interrupt Flag Set

TCNTn

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

OCnx

1

2

3

Period

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The

Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM

value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the

OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM

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output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when

WGM2:0 = 3, and OCR2A when MGM2:0 = 7 (See Table 15-3 on page 163). The actual OC2x

value will only be visible on the port pin if the data direction for the port pin is set as output. The

PWM waveform is generated by clearing (or setting) the OC2x Register at the compare match

between OCR2x and TCNT2 when the counter increments, and setting (or clearing) the OC2x

Register at compare match between OCR2x and TCNT2 when the counter decrements. The

PWM frequency for the output when using phase correct PWM can be calculated by the follow-

ing equation:

f

clk_I/O

f

= -----------------

OCnxPCPWM

N ⋅ 510

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

The extreme values for the OCR2A Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the

output will be continuously low and if set equal to MAX the output will be continuously high for

non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.

At the very start of period 2 in Figure 15-7 OCnx has a transition from high to low even though

there is no Compare Match. The point of this transition is to guarantee symmetry around BOT-

TOM. There are two cases that give a transition without Compare Match.

• OCR2A changes its value from MAX, like in Figure 15-7. When the OCR2A value is MAX the

OCn pin value is the same as the result of a down-counting compare match. To ensure

symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-

counting Compare Match.

• The timer starts counting from a value higher than the one in OCR2A, and for that reason

misses the Compare Match and hence the OCn change that would have happened on the

way up.

15.7 Timer/Counter Timing Diagrams

The following figures show the Timer/Counter in synchronous mode, and the timer clock (clk_T2)

is therefore shown as a clock enable signal. In asynchronous mode, clk_I/Oshould be replaced by

the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are

set. Figure 15-8 contains timing data for basic Timer/Counter operation. The figure shows the

count sequence close to the MAX value in all modes other than phase correct PWM mode.

Figure 15-8. Timer/Counter Timing Diagram, no Prescaling

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

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Figure 15-9 shows the same timing data, but with the prescaler enabled.

Figure 15-9. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

Figure 15-10 shows the setting of OCF2A in all modes except CTC mode.

Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

OCRnx

OCFnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

Figure 15-11 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode.

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Figure 15-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-

caler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

(CTC)

TOP - 1

TOP

BOTTOM

BOTTOM + 1

OCRnx

TOP

OCFnx

15.8 8-bit Timer/Counter Register Description

15.8.1

Timer/Counter Control Register A – TCCR2A

Bit

7

6

5

4

3

2

–

1

0

COM2A

1

COM2A

0

COM2B

1

COM2B

0

–

WGM2

1

WGM2

0

TCCR2A

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R

0

R

0

R/W

0

R/W

0

• Bits 7:6 – COM2A1:0: Compare Match Output A Mode

These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0

bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2A pin

must be set in order to enable the output driver.

When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the

WGM22:0 bit setting. Table 15-1 shows the COM2A1:0 bit functionality when the WGM22:0 bits

are set to a normal or CTC mode (non-PWM).

Table 15-1. Compare Output Mode, non-PWM Mode

COM2A1

COM2A0

Description

0

1

0

1

0

1

Normal port operation, OC0A disconnected.

Toggle OC2A on Compare Match

Clear OC2A on Compare Match

Set OC2A on Compare Match

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Table 15-2 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM

mode.

Table 15-2. Compare Output Mode, Fast PWM Mode⁽¹⁾

COM2A1

COM2A0

Description

0

Normal port operation, OC2A disconnected.

WGM22 = 0: Normal Port Operation, OC0A Disconnected.

WGM22 = 1: Toggle OC2A on Compare Match.

0

1

0

1

Clear OC2A on Compare Match, set OC2A at TOP

Set OC2A on Compare Match, clear OC2A at TOP

Note:

1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 157

for more details.

Table 15-3 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase cor-

rect PWM mode.

Table 15-3. Compare Output Mode, Phase Correct PWM Mode⁽¹⁾

COM2A1

COM2A0

Description

0

Normal port operation, OC2A disconnected.

WGM22 = 0: Normal Port Operation, OC2A Disconnected.

WGM22 = 1: Toggle OC2A on Compare Match.

0

1

0

1

Clear OC2A on Compare Match when up-counting. Set OC2A on

Compare Match when down-counting.

Set OC2A on Compare Match when up-counting. Clear OC2A on

Compare Match when down-counting.

Note:

1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on

page 159 for more details.

• Bits 5:4 – COM2B1:0: Compare Match Output B Mode

These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0

bits are set, the OC2B output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2B pin

must be set in order to enable the output driver.

When OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the

WGM22:0 bit setting. Table 15-4 shows the COM2B1:0 bit functionality when the WGM22:0 bits

are set to a normal or CTC mode (non-PWM).

Table 15-4. Compare Output Mode, non-PWM Mode

COM2B1

COM2B0

Description

0

1

0

1

0

1

Normal port operation, OC2B disconnected.

Toggle OC2B on Compare Match

Clear OC2B on Compare Match

Set OC2B on Compare Match

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Table 15-5 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to fast PWM

mode.

Table 15-5. Compare Output Mode, Fast PWM Mode⁽¹⁾

COM2B1

COM2B0

Description

0

1

0

1

0

1

Normal port operation, OC2B disconnected.

Reserved

Clear OC2B on Compare Match, set OC2B at TOP

Set OC2B on Compare Match, clear OC2B at TOP

Note:

1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 157

for more details.

Table 15-6 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase cor-

rect PWM mode.

Table 15-6. Compare Output Mode, Phase Correct PWM Mode⁽¹⁾

COM2B1

COM2B0

Description

0

1

Normal port operation, OC2B disconnected.

Reserved

Clear OC2B on Compare Match when up-counting. Set OC2B on

Compare Match when down-counting.

1

0

1

Set OC2B on Compare Match when up-counting. Clear OC2B on

Compare Match when down-counting.

Note:

1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on

page 159 for more details.

• Bits 3, 2 – Res: Reserved Bits

These bits are reserved bits in the AT90USB64/128 and will always read as zero.

• Bits 1:0 – WGM21:0: Waveform Generation Mode

Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting

sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-

form generation to be used, see Table 15-7. Modes of operation supported by the Timer/Counter

unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of

Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 156).

Table 15-7. Waveform Generation Mode Bit Description

Timer/Counter

Mode of

Update of

OCRx at

TOV Flag

Mode WGM2 WGM1 WGM0 Operation

TOP

Set on⁽¹⁾⁽²⁾

0

1

2

0

1

0

1

0

Normal

0xFF

Immediate

TOP

MAX

BOTTOM

MAX

PWM, Phase

Correct

0xFF

CTC

OCRA Immediate

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Table 15-7. Waveform Generation Mode Bit Description

Timer/Counter

Mode of

Mode WGM2 WGM1 WGM0 Operation

Update of

OCRx at

TOV Flag

TOP

Set on⁽¹⁾⁽²⁾

3

4

0

1

0

1

0

Fast PWM

Reserved

0xFF

–

TOP

–

MAX

–

PWM, Phase

Correct

5

1

0

1

OCRA

TOP

BOTTOM

6

7

1

0

1

Reserved

Fast PWM

–

OCRA

TOP

Notes: 1. MAX= 0xFF

2. BOTTOM= 0x00

15.8.2

Timer/Counter Control Register B – TCCR2B

Bit

7

6

5

–

R

0

4

–

R

0

3

2

1

0

FOC2A

FOC2B

WGM22

R/W

0

CS22

R/W

0

CS21

R/W

0

CS20

TCCR2B

Read/Write

Initial Value

W

0

W

0

R/W

0

• Bit 7 – FOC2A: Force Output Compare A

The FOC2A bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero when

TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2A bit,

an immediate Compare Match is forced on the Waveform Generation unit. The OC2A output is

changed according to its COM2A1:0 bits setting. Note that the FOC2A bit is implemented as a

strobe. Therefore it is the value present in the COM2A1:0 bits that determines the effect of the

forced compare.

A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using

OCR2A as TOP.

The FOC2A bit is always read as zero.

• Bit 6 – FOC2B: Force Output Compare B

The FOC2B bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero when

TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2B bit,

an immediate Compare Match is forced on the Waveform Generation unit. The OC2B output is

changed according to its COM2B1:0 bits setting. Note that the FOC2B bit is implemented as a

strobe. Therefore it is the value present in the COM2B1:0 bits that determines the effect of the

forced compare.

A FOC2B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using

OCR2B as TOP.

The FOC2B bit is always read as zero.

• Bits 5:4 – Res: Reserved Bits

These bits are reserved bits in the AT90USB64/128 and will always read as zero.

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• Bit 3 – WGM22: Waveform Generation Mode

See the description in the “Timer/Counter Control Register A – TCCR2A” on page 162.

• Bit 2:0 – CS22:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table

15-8.

Table 15-8. Clock Select Bit Description

CS22

CS21

CS20

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No clock source (Timer/Counter stopped).

clk_T2S/(No prescaling)

clk_T2S/8 (From prescaler)

clk_T2S/32 (From prescaler)

clk_T2S/64 (From prescaler)

clk_T2S/128 (From prescaler)

clk_{T S}/256 (From prescaler)

2

clk_{T S}/1024 (From prescaler)

2

If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the

counter even if the pin is configured as an output. This feature allows software control of the

counting.

15.8.3

Timer/Counter Register – TCNT2

Bit

7

6

5

4

3

2

1

0

TCNT2[7:0]

TCNT2

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Timer/Counter Register gives direct access, both for read and write operations, to the

Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare

Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running,

introduces a risk of missing a Compare Match between TCNT2 and the OCR2x Registers.

15.8.4

Output Compare Register A – OCR2A

Bit

7

6

5

4

3

2

1

0

OCR2A[7:0]

OCR2A

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Register A contains an 8-bit value that is continuously compared with the

counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to

generate a waveform output on the OC2A pin.

15.8.5

Output Compare Register B – OCR2B

Bit

7

6

5

4

3

2

1

0

OCR2B[7:0]

OCR2B

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

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The Output Compare Register B contains an 8-bit value that is continuously compared with the

counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to

generate a waveform output on the OC2B pin.

15.9 Asynchronous operation of the Timer/Counter

15.9.1

Asynchronous Status Register – ASSR

Bit

7

6

5

4

3

2

1

0

–

EXCLK

AS2

R/W

0

TCN2UB

OCR2AUB

OCR2BUB

TCR2AUB

TCR2BUB

ASSR

Read/Write

Initial Value

R

0

R/W

0

R

0

R

0

R

0

R

0

R

0

• Bit 6 – EXCLK: Enable External Clock Input

When EXCLK is written to one, and asynchronous clock is selected, the external clock input

buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead

of a 32 kHz crystal. Writing to EXCLK should be done before asynchronous operation is

selected. Note that the crystal Oscillator will only run when this bit is zero.

• Bit 5 – AS2: Asynchronous Timer/Counter2

When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clk_I/O. When AS2 is

written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscil-

lator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A,

OCR2B, TCCR2A and TCCR2B might be corrupted.

• Bit 4 – TCN2UB: Timer/Counter2 Update Busy

When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set.

When TCNT2 has been updated from the temporary storage register, this bit is cleared by hard-

ware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value.

• Bit 3 – OCR2AUB: Output Compare Register2 Update Busy

When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set.

When OCR2A has been updated from the temporary storage register, this bit is cleared by hard-

ware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new value.

• Bit 2 – OCR2BUB: Output Compare Register2 Update Busy

When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set.

When OCR2B has been updated from the temporary storage register, this bit is cleared by hard-

ware. A logical zero in this bit indicates that OCR2B is ready to be updated with a new value.

• Bit 1 – TCR2AUB: Timer/Counter Control Register2 Update Busy

When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set.

When TCCR2A has been updated from the temporary storage register, this bit is cleared by

hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new

value.

• Bit 0 – TCR2BUB: Timer/Counter Control Register2 Update Busy

When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes set.

When TCCR2B has been updated from the temporary storage register, this bit is cleared by

hardware. A logical zero in this bit indicates that TCCR2B is ready to be updated with a new

value.

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If a write is performed to any of the five Timer/Counter2 Registers while its update busy flag is

set, the updated value might get corrupted and cause an unintentional interrupt to occur.

The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different.

When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A

and TCCR2B the value in the temporary storage register is read.

15.9.2

Asynchronous Operation of Timer/Counter2

When Timer/Counter2 operates asynchronously, some considerations must be taken.

• Warning: When switching between asynchronous and synchronous clocking of

Timer/Counter2, the Timer Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A

safe procedure for switching clock source is:

a. Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2.

b. Select clock source by setting AS2 as appropriate.

c. Write new values to TCNT2, OCR2x, and TCCR2x.

d. To switch to asynchronous operation: Wait for TCN2UB, OCR2xUB, and

TCR2xUB.

e. Clear the Timer/Counter2 Interrupt Flags.

f. Enable interrupts, if needed.

• The CPU main clock frequency must be more than four times the Oscillator frequency.

• When writing to one of the registers TCNT2, OCR2x, or TCCR2x, the value is transferred to a

temporary register, and latched after two positive edges on TOSC1. The user should not

write a new value before the contents of the temporary register have been transferred to its

destination. Each of the five mentioned registers have their individual temporary register,

which means that e.g. writing to TCNT2 does not disturb an OCR2x write in progress. To

detect that a transfer to the destination register has taken place, the Asynchronous Status

Register – ASSR has been implemented.

• When entering Power-save or ADC Noise Reduction mode after having written to TCNT2,

OCR2x, or TCCR2x, the user must wait until the written register has been updated if

Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode

before the changes are effective. This is particularly important if any of the Output Compare2

interrupt is used to wake up the device, since the Output Compare function is disabled during

writing to OCR2x or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode

before the corresponding OCR2xUB bit returns to zero, the device will never receive a

compare match interrupt, and the MCU will not wake up.

• If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise Reduction

mode, precautions must be taken if the user wants to re-enter one of these modes: The

interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and re-

entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the

device will fail to wake up. If the user is in doubt whether the time before re-entering Power-

save or ADC Noise Reduction mode is sufficient, the following algorithm can be used to

ensure that one TOSC1 cycle has elapsed:

a. Write a value to TCCR2x, TCNT2, or OCR2x.

b. Wait until the corresponding Update Busy Flag in ASSR returns to zero.

c. Enter Power-save or ADC Noise Reduction mode.

• When the asynchronous operation is selected, the 32.768 kHz Oscillator for Timer/Counter2

is always running, except in Power-down and Standby modes. After a Power-up Reset or

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wake-up from Power-down or Standby mode, the user should be aware of the fact that this

Oscillator might take as long as one second to stabilize. The user is advised to wait for at

least one second before using Timer/Counter2 after power-up or wake-up from Power-down

or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after

a wake-up from Power-down or Standby mode due to unstable clock signal upon start-up, no

matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin.

• Description of wake up from Power-save or ADC Noise Reduction mode when the timer is

clocked asynchronously: When the interrupt condition is met, the wake up process is started

on the following cycle of the timer clock, that is, the timer is always advanced by at least one

before the processor can read the counter value. After wake-up, the MCU is halted for four

cycles, it executes the interrupt routine, and resumes execution from the instruction following

SLEEP.

• Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect

result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be

done through a register synchronized to the internal I/O clock domain. Synchronization takes

place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O

clock (clk_I/O) again becomes active, TCNT2 will read as the previous value (before entering

sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from

Power-save mode is essentially unpredictable, as it depends on the wake-up time. The

recommended procedure for reading TCNT2 is thus as follows:

a. Write any value to either of the registers OCR2x or TCCR2x.

b. Wait for the corresponding Update Busy Flag to be cleared.

c. Read TCNT2.

• During asynchronous operation, the synchronization of the Interrupt Flags for the

asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is therefore

advanced by at least one before the processor can read the timer value causing the setting of

the Interrupt Flag. The Output Compare pin is changed on the timer clock and is not

synchronized to the processor clock.

15.9.3

Timer/Counter2 Interrupt Mask Register – TIMSK2

Bit

7

6

5

4

3

–

R

0

2

1

0

–

OCIE2B

R/W

0

OCIE2A

R/W

0

TOIE2

R/W

0

TIMSK2

Read/Write

Initial Value

R

0

R

0

R

0

R

0

• Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable

When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the

Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt is executed

if a compare match in Timer/Counter2 occurs, i.e., when the OCF2B bit is set in the

Timer/Counter 2 Interrupt Flag Register – TIFR2.

• Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable

When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the

Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed

if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is set in the

Timer/Counter 2 Interrupt Flag Register – TIFR2.

• Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable

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When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the

Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an

overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2 Interrupt

Flag Register – TIFR2.

15.9.4

Timer/Counter2 Interrupt Flag Register – TIFR2

Bit

7

6

5

4

–

R

0

3

–

R

0

2

1

0

–

OCF2B

R/W

0

OCF2A

R/W

0

TOV2

R/W

0

TIFR2

Read/Write

Initial Value

R

0

R

0

R

0

• Bit 2 – OCF2B: Output Compare Flag 2 B

The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the

data in OCR2B – Output Compare Register2. OCF2B is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF2B is cleared by writing a logic

one to the flag. When the I-bit in SREG, OCIE2B (Timer/Counter2 Compare match Interrupt

Enable), and OCF2B are set (one), the Timer/Counter2 Compare match Interrupt is executed.

• Bit 1 – OCF2A: Output Compare Flag 2 A

The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the

data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic

one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 Compare match Interrupt

Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed.

• Bit 0 – TOV2: Timer/Counter2 Overflow Flag

The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hard-

ware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared

by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Inter-

rupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In

PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00.

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15.10 Timer/Counter Prescaler

Figure 15-12. Prescaler for Timer/Counter2

clk_I/O

clk_T2S

10-BIT T/C PRESCALER

Clear

TOSC1

AS2

PSRASY

0

CS20

CS21

CS22

TIMER/COUNTER2 CLOCK SOURCE

clk_T2

The clock source for Timer/Counter2 is named clk_T2S. clk_T2Sis by default connected to the main

system I/O clock clk_IO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously

clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter

(RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can

then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock

source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz crystal. Apply-

ing an external clock source to TOSC1 is not recommended.

For Timer/Counter2, the possible prescaled selections are: clk_T2S/8, clk_T2S/32, clk_T2S/64,

clk_T2S/128, clk_T2S/256, and clk_T2S/1024. Additionally, clk_T2Sas well as 0 (stop) may be selected.

Setting the PSRASY bit in GTCCR resets the prescaler. This allows the user to operate with a

predictable prescaler.

15.10.1 General Timer/Counter Control Register – GTCCR

Bit

7

6

5

4

–

3

–

2

–

1

0

TSM

–

PSRA-

SY

PSRSY

NC

GTCCR

Read/Write

Initial Value

R/W

0

R

0

R

0

R

0

R

0

R

0

R/W

0

R/W

0

• Bit 1 – PSRASY: Prescaler Reset Timer/Counter2

When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared

immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous

mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by

hardware if the TSM bit is set. Refer to the description of the “General Timer/Counter Control

Register – GTCCR” on page 101 for a description of the Timer/Counter Synchronization mode.

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16. Output Compare Modulator (OCM1C0A)

16.1 Overview

The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier

frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit

Timer/Counter1 and the Output Compare Unit of the 8-bit Timer/Counter0. For more details

about these Timer/Counters see “Timer/Counter0, Timer/Counter1, and Timer/Counter3 Pres-

calers” on page 100 and “8-bit Timer/Counter2 with PWM and Asynchronous Operation” on

page 151.

Figure 16-1. Output Compare Modulator, Block Diagram

OC1C

Timer/Counter 1

OC1C /

OC0A / PB7

OC0A

Timer/Counter 0

When the modulator is enabled, the two output compare channels are modulated together as

shown in the block diagram (Figure 16-1).

16.2 Description

The Output Compare unit 1C and Output Compare unit 2 shares the PB7 port pin for output. The

outputs of the Output Compare units (OC1C and OC0A) overrides the normal PORTB7 Register

when one of them is enabled (i.e., when COMnx1:0 is not equal to zero). When both OC1C and

OC0A are enabled at the same time, the modulator is automatically enabled.

The functional equivalent schematic of the modulator is shown on Figure 16-2. The schematic

includes part of the Timer/Counter units and the port B pin 7 output driver circuit.

Figure 16-2. Output Compare Modulator, Schematic

COMA01

COMA00

Vcc

COM1C1

COM1C0

Modulator

0

1

( From Waveform Generator )

D

Q

1

0

OC1C

OC1C /

OC0A/ PB7

( From Waveform Generator )

D

Q

OC0A

D

Q

D

Q

PORTB7

DDRB7

DATABUS

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When the modulator is enabled the type of modulation (logical AND or OR) can be selected by

the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the

COMnx1:0 bit setting.

16.2.1

Timing Example

Figure 16-3 illustrates the modulator in action. In this example the Timer/Counter1 is set to oper-

ate in fast PWM mode (non-inverted) and Timer/Counter0 uses CTC waveform mode with toggle

Compare Output mode (COMnx1:0 = 1).

Figure 16-3. Output Compare Modulator, Timing Diagram

clk_I/O

OC1C

(FPWM Mode)

OC0A

(CTC Mode)

PB7

(PORTB7 = 0)

PB7

(PORTB7 = 1)

1

2

3

(Period)

In this example, Timer/Counter2 provides the carrier, while the modulating signal is generated

by the Output Compare unit C of the Timer/Counter1.

The resolution of the PWM signal (OC1C) is reduced by the modulation. The reduction factor is

equal to the number of system clock cycles of one period of the carrier (OC0A). In this example

the resolution is reduced by a factor of two. The reason for the reduction is illustrated in Figure

16-3 at the second and third period of the PB7 output when PORTB7 equals zero. The period 2

high time is one cycle longer than the period 3 high time, but the result on the PB7 output is

equal in both periods.

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17. Serial Peripheral Interface – SPI

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the

AT90USB64/128 and peripheral devices or between several AVR devices. The

AT90USB64/128 SPI includes the following features:

• Full-duplex, Three-wire Synchronous Data Transfer

• Master or Slave Operation

• LSB First or MSB First Data Transfer

• Seven Programmable Bit Rates

• End of Transmission Interrupt Flag

• Write Collision Flag Protection

• Wake-up from Idle Mode

• Double Speed (CK/2) Master SPI Mode

USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 208.

The Power Reduction SPI bit, PRSPI, in “Power Reduction Register 0 - PRR0” on page 56 on

page 50 must be written to zero to enable SPI module.

Figure 17-1. SPI Block Diagram⁽¹⁾

DIVIDER

/2/4/8/16/32/64/128

Note:

1. Refer to Figure 1-1 on page 3, and Table 10-6 on page 82 for SPI pin placement.

The interconnection between Master and Slave CPUs with SPI is shown in Figure 17-2. The sys-

tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the

communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and

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Slave prepare the data to be sent in their respective shift Registers, and the Master generates

the required clock pulses on the SCK line to interchange data. Data is always shifted from Mas-

ter to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In

– Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling

high the Slave Select, SS, line.

When configured as a Master, the SPI interface has no automatic control of the SS line. This

must be handled by user software before communication can start. When this is done, writing a

byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight

bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of

Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an

interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or

signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be

kept in the Buffer Register for later use.

When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long

as the SS pin is driven high. In this state, software may update the contents of the SPI Data

Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin

until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission

Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt

is requested. The Slave may continue to place new data to be sent into SPDR before reading

the incoming data. The last incoming byte will be kept in the Buffer Register for later use.

Figure 17-2. SPI Master-slave Interconnection

SHIFT

ENABLE

The system is single buffered in the transmit direction and double buffered in the receive direc-

tion. This means that bytes to be transmitted cannot be written to the SPI Data Register before

the entire shift cycle is completed. When receiving data, however, a received character must be

read from the SPI Data Register before the next character has been completely shifted in. Oth-

erwise, the first byte is lost.

In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure

correct sampling of the clock signal, the frequency of the SPI clock should never exceed f_osc/4.

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When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden

according to Table 17-1. For more details on automatic port overrides, refer to “Alternate Port

Functions” on page 79.

Table 17-1. SPI Pin Overrides⁽¹⁾

MOSI

MISO

SCK

SS

Direction, Master SPI

User Defined

Input

Direction, Slave SPI

Input

User Defined

Input

User Defined

Input

Note:

1. See “Alternate Functions of Port B” on page 82 for a detailed description of how to define the

direction of the user defined SPI pins.

The following code examples show how to initialize the SPI as a Master and how to perform a

simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction

Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the

actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI

with DDB5 and DDR_SPI with DDRB.

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Assembly Code Example⁽¹⁾

SPI_MasterInit:

; Set MOSI and SCK output, all others input

ldi r17,(1<<DD_MOSI)|(1<<DD_SCK)

out DDR_SPI,r17

; Enable SPI, Master, set clock rate fck/16

ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)

out SPCR,r17

ret

SPI_MasterTransmit:

; Start transmission of data (r16)

out SPDR,r16

Wait_Transmit:

; Wait for transmission complete

sbis SPSR,SPIF

rjmp Wait_Transmit

ret

C Code Example⁽¹⁾

void SPI_MasterInit(void)

{

/* Set MOSI and SCK output, all others input */

DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);

/* Enable SPI, Master, set clock rate fck/16 */

SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);

}

void SPI_MasterTransmit(char cData)

{

/* Start transmission */

SPDR = cData;

/* Wait for transmission complete */

while(!(SPSR & (1<<SPIF)))

;

}

Note:

1. See “About Code Examples” on page 8.

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The following code examples show how to initialize the SPI as a Slave and how to perform a

simple reception.

Assembly Code Example⁽¹⁾

SPI_SlaveInit:

; Set MISO output, all others input

ldi r17,(1<<DD_MISO)

out DDR_SPI,r17

; Enable SPI

ldi r17,(1<<SPE)

out SPCR,r17

ret

SPI_SlaveReceive:

; Wait for reception complete

sbis SPSR,SPIF

rjmp SPI_SlaveReceive

; Read received data and return

in

r16,SPDR

ret

C Code Example⁽¹⁾

void SPI_SlaveInit(void)

{

/* Set MISO output, all others input */

DDR_SPI = (1<<DD_MISO);

/* Enable SPI */

SPCR = (1<<SPE);

}

char SPI_SlaveReceive(void)

{

/* Wait for reception complete */

while(!(SPSR & (1<<SPIF)))

;

/* Return Data Register */

return SPDR;

}

Note:

1. See “About Code Examples” on page 8.

17.1 SS Pin Functionality

17.1.1

Slave Mode

When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is

held low, the SPI is activated, and MISO becomes an output if configured so by the user. All

other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which

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means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin

is driven high.

The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous

with the master clock generator. When the SS pin is driven high, the SPI slave will immediately

reset the send and receive logic, and drop any partially received data in the Shift Register.

17.1.2

Master Mode

When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the

direction of the SS pin.

If SS is configured as an output, the pin is a general output pin which does not affect the SPI

system. Typically, the pin will be driving the SS pin of the SPI Slave.

If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin

is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin

defined as an input, the SPI system interprets this as another master selecting the SPI as a

slave and starting to send data to it. To avoid bus contention, the SPI system takes the following

actions:

1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of

the SPI becoming a Slave, the MOSI and SCK pins become inputs.

2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG

is set, the interrupt routine will be executed.

Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possi-

bility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the

MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master

mode.

17.1.3

SPI Control Register – SPCR

Bit

7

6

5

4

3

2

1

0

SPIE

R/W

0

SPE

R/W

0

DORD

R/W

0

MSTR

R/W

0

CPOL

R/W

0

CPHA

R/W

0

SPR1

R/W

0

SPR0

R/W

0

SPCR

Read/Write

Initial Value

• Bit 7 – SPIE: SPI Interrupt Enable

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if

the Global Interrupt Enable bit in SREG is set.

• Bit 6 – SPE: SPI Enable

When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI

operations.

• Bit 5 – DORD: Data Order

When the DORD bit is written to one, the LSB of the data word is transmitted first.

When the DORD bit is written to zero, the MSB of the data word is transmitted first.

• Bit 4 – MSTR: Master/Slave Select

This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic

zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,

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and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-

ter mode.

• Bit 3 – CPOL: Clock Polarity

When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low

when idle. Refer to Figure 17-3 and Figure 17-4 for an example. The CPOL functionality is sum-

marized below:

Table 17-2. CPOL Functionality

CPOL

Leading Edge

Rising

Trailing Edge

Falling

0

1

Falling

Rising

• Bit 2 – CPHA: Clock Phase

The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or

trailing (last) edge of SCK. Refer to Figure 17-3 and Figure 17-4 for an example. The CPOL

functionality is summarized below:

Table 17-3. CPHA Functionality

CPHA

Leading Edge

Sample

Trailing Edge

Setup

0

1

Setup

Sample

• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0

These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have

no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f_oscis

shown in the following table:

Table 17-4. Relationship Between SCK and the Oscillator Frequency

SPI2X

SPR1

SPR0

SCK Frequency

f_osc/4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

f_osc/16

f_osc/64

f_osc/128

f_osc/2

f_osc/8

f_osc/32

f_osc/64

17.1.4

SPI Status Register – SPSR

Bit

7

6

5

–

R

0

4

–

R

0

3

–

R

0

2

–

R

0

1

–

R

0

SPIF

R

WCOL

SPI2X

R/W

0

SPSR

Read/Write

Initial Value

R

0

• Bit 7 – SPIF: SPI Interrupt Flag

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When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in

SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is

in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the

corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the

SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).

• Bit 6 – WCOL: Write COLlision Flag

The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The

WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set,

and then accessing the SPI Data Register.

• Bit 5..1 – Res: Reserved Bits

These bits are reserved bits in the AT90USB64/128 and will always read as zero.

• Bit 0 – SPI2X: Double SPI Speed Bit

When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI

is in Master mode (see Table 17-4). This means that the minimum SCK period will be two CPU

clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f_osc/4

or lower.

The SPI interface on the AT90USB64/128 is also used for program memory and EEPROM

downloading or uploading. See page 382 for serial programming and verification.

17.1.5

SPI Data Register – SPDR

Bit

7

6

5

4

3

2

1

0

MSB

R/W

X

LSB

R/W

X

SPDR

Read/Write

Initial Value

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

Undefined

The SPI Data Register is a read/write register used for data transfer between the Register File

and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis-

ter causes the Shift Register Receive buffer to be read.

17.2 Data Modes

There are four combinations of SCK phase and polarity with respect to serial data, which are

determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure

17-3 and Figure 17-4. Data bits are shifted out and latched in on opposite edges of the SCK sig-

nal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing

Table 17-2 and Table 17-3, as done below:

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Table 17-5. CPOL Functionality

Leading Edge

Trailing eDge

Setup (Falling)

Sample (Falling)

Setup (Rising)

Sample (Rising)

SPI Mode

CPOL=0, CPHA=0

CPOL=0, CPHA=1

CPOL=1, CPHA=0

CPOL=1, CPHA=1

Sample (Rising)

Setup (Rising)

Sample (Falling)

Setup (Falling)

0

1

2

3

Figure 17-3. SPI Transfer Format with CPHA = 0

SCK (CPOL = 0)

mode 0

SCK (CPOL = 1)

mode 2

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SS

MSB first (DORD = 0) MSB

LSB first (DORD = 1) LSB

Bit 6

Bit 1

Bit 5

Bit 2

Bit 4

Bit 3

Bit 4

Bit 2

Bit 5

Bit 1

Bit 6

LSB

MSB

Figure 17-4. SPI Transfer Format with CPHA = 1

SCK (CPOL = 0)

mode 1

SCK (CPOL = 1)

mode 3

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SS

MSB first (DORD = 0)

LSB first (DORD = 1)

MSB

LSB

Bit 6

Bit 1

Bit 5

Bit 2

Bit 4

Bit 3

Bit 4

Bit 2

Bit 5

Bit 1

Bit 6

LSB

MSB

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18. USART

The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a

highly flexible serial communication device. The main features are:

• Full Duplex Operation (Independent Serial Receive and Transmit Registers)

• Asynchronous or Synchronous Operation

• Master or Slave Clocked Synchronous Operation

• High Resolution Baud Rate Generator

• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits

• Odd or Even Parity Generation and Parity Check Supported by Hardware

• Data OverRun Detection

• Framing Error Detection

• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter

• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete

• Multi-processor Communication Mode

• Double Speed Asynchronous Communication Mode

.

18.1 Overview

A simplified block diagram of the USART Transmitter is shown in Figure 18-1 on page 184. CPU

accessible I/O Registers and I/O pins are shown in bold.

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Figure 18-1. USART Block Diagram⁽¹⁾

Clock Generator

UBRR[H:L]

OSC

BAUD RATE GENERATOR

SYNC LOGIC

CONTROL

XCK

TxD

RxD

Transmitter

TX

CONTROL

UDR (Transmit)

PARITY

GENERATOR

CONTROL

TRANSMIT SHIFT REGISTER

Receiver

CLOCK

RECOVERY

RX

CONTROL

DATA

RECOVERY

CONTROL

RECEIVE SHIFT REGISTER

PARITY

CHECKER

UDR (Receive)

UCSRA

UCSRB

UCSRC

Note:

1. See Figure 1-1 on page 3, Table 10-12 on page 86 and for USART pin placement.

The dashed boxes in the block diagram separate the three main parts of the USART (listed from

the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units.

The Clock Generation logic consists of synchronization logic for external clock input used by

synchronous slave operation, and the baud rate generator. The XCKn (Transfer Clock) pin is

only used by synchronous transfer mode. The Transmitter consists of a single write buffer, a

serial Shift Register, Parity Generator and Control logic for handling different serial frame for-

mats. The write buffer allows a continuous transfer of data without any delay between frames.

The Receiver is the most complex part of the USART module due to its clock and data recovery

units. The recovery units are used for asynchronous data reception. In addition to the recovery

units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level

receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and

can detect Frame Error, Data OverRun and Parity Errors.

18.2 Clock Generation

The Clock Generation logic generates the base clock for the Transmitter and Receiver. The

USARTn supports four modes of clock operation: Normal asynchronous, Double Speed asyn-

chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART

Control and Status Register C (UCSRnC) selects between asynchronous and synchronous

operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the

UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register

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for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or

external (Slave mode). The XCKn pin is only active when using synchronous mode.

Figure 18-2 shows a block diagram of the clock generation logic.

Figure 18-2. Clock Generation Logic, Block Diagram

UBRR

U2X

fosc

UBRR+1

Prescaling

Down-Counter

/2

/4

/2

0

1

0

1

OSC

txclk

UMSEL

rxclk

DDR_XCK

Sync

Register

Edge

Detector

xcki

0

1

XCK

xcko

DDR_XCK

UCPOL

1

0

Signal description:

txclk

Transmitter clock (Internal Signal).

Receiver base clock (Internal Signal).

rxclk

xcki

Input from XCK pin (internal Signal). Used for synchronous slave

operation.

xcko

Clock output to XCK pin (Internal Signal). Used for synchronous master

operation.

f_OSC

XTAL pin frequency (System Clock).

18.2.1

Internal Clock Generation – The Baud Rate Generator

Internal clock generation is used for the asynchronous and the synchronous master modes of

operation. The description in this section refers to Figure 18-2.

The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a

programmable prescaler or baud rate generator. The down-counter, running at system clock

(f_osc), is loaded with the UBRRn value each time the counter has counted down to zero or when

the UBRRLn Register is written. A clock is generated each time the counter reaches zero. This

clock is the baud rate generator clock output (= f_osc/(UBRRn+1)). The Transmitter divides the

baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator out-

put is used directly by the Receiver’s clock and data recovery units. However, the recovery units

use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the

UMSELn, U2Xn and DDR_XCKn bits.

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Table 18-1 contains equations for calculating the baud rate (in bits per second) and for calculat-

ing the UBRRn value for each mode of operation using an internally generated clock source.

Table 18-1. Equations for Calculating Baud Rate Register Setting

Equation for Calculating

Baud Rate⁽¹⁾

Equation for Calculating

UBRR Value

Operating Mode

f

OSC

UBRRn = ----------------------- – 1

16BAUD

f

Asynchronous Normal

mode (U2Xn = 0)

OSC

BAUD = -----------------------------------------

16(UBRRn + 1)

f

OSC

UBRRn = -------------------- – 1

8BAUD

f

Asynchronous Double

Speed mode (U2Xn = 1)

OSC

BAUD = --------------------------------------

8(UBRRn + 1)

f

OSC

UBRRn = -------------------- – 1

2BAUD

f

Synchronous Master

mode

OSC

BAUD = --------------------------------------

2(UBRRn + 1)

Note:

1. The baud rate is defined to be the transfer rate in bit per second (bps)

BAUD

Baud rate (in bits per second, bps)

f_OSC

System Oscillator clock frequency

UBRRn

Contents of the UBRRHn and UBRRLn Registers, (0-4095)

Some examples of UBRRn values for some system clock frequencies are found in Table 18-9 on

page 205.

18.2.2

Double Speed Operation (U2Xn)

The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has

effect for the asynchronous operation. Set this bit to zero when using synchronous operation.

Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling

the transfer rate for asynchronous communication. Note however that the Receiver will in this

case only use half the number of samples (reduced from 16 to 8) for data sampling and clock

recovery, and therefore a more accurate baud rate setting and system clock are required when

this mode is used. For the Transmitter, there are no downsides.

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18.2.3

External Clock

External clocking is used by the synchronous slave modes of operation. The description in this

section refers to Figure 18-2 for details.

External clock input from the XCKn pin is sampled by a synchronization register to minimize the

chance of meta-stability. The output from the synchronization register must then pass through

an edge detector before it can be used by the Transmitter and Receiver. This process intro-

duces a two CPU clock period delay and therefore the maximum external XCKn clock frequency

is limited by the following equation:

f

OSC

f

< -----------

XCK

4

Note that f_oscdepends on the stability of the system clock source. It is therefore recommended to

add some margin to avoid possible loss of data due to frequency variations.

18.2.4

Synchronous Clock Operation

When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input

(Slave) or clock output (Master). The dependency between the clock edges and data sampling

or data change is the same. The basic principle is that data input (on RxDn) is sampled at the

opposite XCKn clock edge of the edge the data output (TxDn) is changed.

Figure 18-3. Synchronous Mode XCKn Timing.

UCPOL = 1

XCK

RxD / TxD

Sample

UCPOL = 0

XCK

RxD / TxD

The UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling and which is

used for data change. As Figure 18-3 shows, when UCPOLn is zero the data will be changed at

rising XCKn edge and sampled at falling XCKn edge. If UCPOLn is set, the data will be changed

at falling XCKn edge and sampled at rising XCKn edge.

18.3 Frame Formats

A serial frame is defined to be one character of data bits with synchronization bits (start and stop

bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of

the following as valid frame formats:

• 1 start bit

• 5, 6, 7, 8, or 9 data bits

• no, even or odd parity bit

• 1 or 2 stop bits

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A frame starts with the start bit followed by the least significant data bit. Then the next data bits,

up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit

is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can

be directly followed by a new frame, or the communication line can be set to an idle (high) state.

Figure 18-4 illustrates the possible combinations of the frame formats. Bits inside brackets are

optional.

Figure 18-4. Frame Formats

FRAME

(IDLE)

St

0

1

2

3

4

[5]

[6]

[7]

[8]

[P] Sp1 [Sp2] (St / IDLE)

St

Start bit, always low.

Data bits (0 to 8).

(n)

P

Parity bit. Can be odd or even.

Stop bit, always high.

Sp

IDLE

must be

No transfers on the communication line (RxDn or TxDn). An IDLE line

high.

The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in

UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing

the setting of any of these bits will corrupt all ongoing communication for both the Receiver and

Transmitter.

The USART Character SiZe (UCSZn2:0) bits select the number of data bits in the frame. The

USART Parity mode (UPMn1:0) bits enable and set the type of parity bit. The selection between

one or two stop bits is done by the USART Stop Bit Select (USBSn) bit. The Receiver ignores

the second stop bit. An FE (Frame Error) will therefore only be detected in the cases where the

first stop bit is zero.

18.3.1

Parity Bit Calculation

The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the

result of the exclusive or is inverted. The relation between the parity bit and data bits is as

follows::

P

= d

⊕ … ⊕ d ⊕ d ⊕ d ⊕ d ⊕ 0

3 2 1 0

even

n – 1

⊕ … ⊕ d ⊕ d ⊕ d ⊕ d ⊕ 1

odd

3 2 1 0

P_even

P^odd

d_n

Parity bit using even parity

Parity bit using odd parity

Data bit n of the character

If used, the parity bit is located between the last data bit and first stop bit of a serial frame.

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18.4 USART Initialization

The USART has to be initialized before any communication can take place. The initialization pro-

cess normally consists of setting the baud rate, setting frame format and enabling the

Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the

Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the

initialization.

Before doing a re-initialization with changed baud rate or frame format, be sure that there are no

ongoing transmissions during the period the registers are changed. The TXCn Flag can be used

to check that the Transmitter has completed all transfers, and the RXC Flag can be used to

check that there are no unread data in the receive buffer. Note that the TXCn Flag must be

cleared before each transmission (before UDRn is written) if it is used for this purpose.

The following simple USART initialization code examples show one assembly and one C func-

tion that are equal in functionality. The examples assume asynchronous operation using polling

(no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter.

For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16

Registers.

Assembly Code Example⁽¹⁾

USART_Init:

; Set baud rate

out UBRRHn, r17

out UBRRLn, r16

; Enable receiver and transmitter

ldi r16, (1<<RXENn)|(1<<TXENn)

out UCSRnB,r16

; Set frame format: 8data, 2stop bit

ldi r16, (1<<USBSn)|(3<<UCSZn0)

out UCSRnC,r16

ret

C Code Example⁽¹⁾

void USART_Init( unsigned int baud )

{

/* Set baud rate */

UBRRHn = (unsigned char)(baud>>8);

UBRRLn = (unsigned char)baud;

/* Enable receiver and transmitter */

UCSRnB = (1<<RXENn)|(1<<TXENn);

/* Set frame format: 8data, 2stop bit */

UCSRnC = (1<<USBSn)|(3<<UCSZn0);

}

Note:

1. See “About Code Examples” on page 8.

More advanced initialization routines can be made that include frame format as parameters, dis-

able interrupts and so on. However, many applications use a fixed setting of the baud and

control registers, and for these types of applications the initialization code can be placed directly

in the main routine, or be combined with initialization code for other I/O modules.

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18.5 Data Transmission – The USART Transmitter

The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRnB

Register. When the Transmitter is enabled, the normal port operation of the TxDn pin is overrid-

den by the USART and given the function as the Transmitter’s serial output. The baud rate,

mode of operation and frame format must be set up once before doing any transmissions. If syn-

chronous operation is used, the clock on the XCKn pin will be overridden and used as

transmission clock.

18.5.1

Sending Frames with 5 to 8 Data Bit

A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The

CPU can load the transmit buffer by writing to the UDRn I/O location. The buffered data in the

transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new

frame. The Shift Register is loaded with new data if it is in idle state (no ongoing transmission) or

immediately after the last stop bit of the previous frame is transmitted. When the Shift Register is

loaded with new data, it will transfer one complete frame at the rate given by the Baud Register,

U2Xn bit or by XCKn depending on mode of operation.

The following code examples show a simple USART transmit function based on polling of the

Data Register Empty (UDREn) Flag. When using frames with less than eight bits, the most sig-

nificant bits written to the UDRn are ignored. The USART has to be initialized before the function

can be used. For the assembly code, the data to be sent is assumed to be stored in Register

R16

Assembly Code Example⁽¹⁾

USART_Transmit:

; Wait for empty transmit buffer

sbis UCSRnA,UDREn

rjmp USART_Transmit

; Put data (r16) into buffer, sends the data

out UDRn,r16

ret

C Code Example⁽¹⁾

void USART_Transmit( unsigned char data )

{

/* Wait for empty transmit buffer */

while ( !( UCSRnA & (1<<UDREn)) )

;

/* Put data into buffer, sends the data */

UDRn = data;

}

Note:

1. See “About Code Examples” on page 8.

The function simply waits for the transmit buffer to be empty by checking the UDREn Flag,

before loading it with new data to be transmitted. If the Data Register Empty interrupt is utilized,

the interrupt routine writes the data into the buffer.

18.5.2

190

Sending Frames with 9 Data Bit

If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8 bit in UCS-

RnB before the low byte of the character is written to UDRn. The following code examples show

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a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is

assumed to be stored in registers R17:R16.

Assembly Code Example⁽¹⁾⁽²⁾

USART_Transmit:

; Wait for empty transmit buffer

sbis UCSRnA,UDREn

rjmp USART_Transmit

; Copy 9th bit from r17 to TXB8

cbi UCSRnB,TXB8

sbrc r17,0

sbi UCSRnB,TXB8

; Put LSB data (r16) into buffer, sends the data

out UDRn,r16

ret

C Code Example⁽¹⁾⁽²⁾

void USART_Transmit( unsigned int data )

{

/* Wait for empty transmit buffer */

while ( !( UCSRnA & (1<<UDREn))) )

;

/* Copy 9th bit to TXB8 */

UCSRnB &= ~(1<<TXB8);

if ( data & 0x0100 )

UCSRnB |= (1<<TXB8);

/* Put data into buffer, sends the data */

UDRn = data;

}

Notes: 1. These transmit functions are written to be general functions. They can be optimized if the con-

tents of the UCSRnB is static. For example, only the TXB8 bit of the UCSRnB Register is used

after initialization.

2. See “About Code Examples” on page 8.

The ninth bit can be used for indicating an address frame when using multi processor communi-

cation mode or for other protocol handling as for example synchronization.

18.5.3

Transmitter Flags and Interrupts

The USART Transmitter has two flags that indicate its state: USART Data Register Empty

(UDREn) and Transmit Complete (TXCn). Both flags can be used for generating interrupts.

The Data Register Empty (UDREn) Flag indicates whether the transmit buffer is ready to receive

new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer

contains data to be transmitted that has not yet been moved into the Shift Register. For compat-

ibility with future devices, always write this bit to zero when writing the UCSRnA Register.

When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRnB is written to one, the

USART Data Register Empty Interrupt will be executed as long as UDREn is set (provided that

global interrupts are enabled). UDREn is cleared by writing UDRn. When interrupt-driven data

transmission is used, the Data Register Empty interrupt routine must either write new data to

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UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new

interrupt will occur once the interrupt routine terminates.

The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit Shift

Register has been shifted out and there are no new data currently present in the transmit buffer.

The TXCn Flag bit is automatically cleared when a transmit complete interrupt is executed, or it

can be cleared by writing a one to its bit location. The TXCn Flag is useful in half-duplex commu-

nication interfaces (like the RS-485 standard), where a transmitting application must enter

receive mode and free the communication bus immediately after completing the transmission.

When the Transmit Compete Interrupt Enable (TXCIEn) bit in UCSRnB is set, the USART

Transmit Complete Interrupt will be executed when the TXCn Flag becomes set (provided that

global interrupts are enabled). When the transmit complete interrupt is used, the interrupt han-

dling routine does not have to clear the TXCn Flag, this is done automatically when the interrupt

is executed.

18.5.4

18.5.5

Parity Generator

The Parity Generator calculates the parity bit for the serial frame data. When parity bit is enabled

(UPMn1 = 1), the transmitter control logic inserts the parity bit between the last data bit and the

first stop bit of the frame that is sent.

Disabling the Transmitter

The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongo-

ing and pending transmissions are completed, i.e., when the Transmit Shift Register and

Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter

will no longer override the TxDn pin.

18.6 Data Reception – The USART Receiver

The USART Receiver is enabled by writing the Receive Enable (RXENn) bit in the

UCSRnB Register to one. When the Receiver is enabled, the normal pin operation of the RxDn

pin is overridden by the USART and given the function as the Receiver’s serial input. The baud

rate, mode of operation and frame format must be set up once before any serial reception can

be done. If synchronous operation is used, the clock on the XCKn pin will be used as transfer

clock.

18.6.1

Receiving Frames with 5 to 8 Data Bits

The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start

bit will be sampled at the baud rate or XCKn clock, and shifted into the Receive Shift Register

until the first stop bit of a frame is received. A second stop bit will be ignored by the Receiver.

When the first stop bit is received, i.e., a complete serial frame is present in the Receive Shift

Register, the contents of the Shift Register will be moved into the receive buffer. The receive

buffer can then be read by reading the UDRn I/O location.

The following code example shows a simple USART receive function based on polling of the

Receive Complete (RXCn) Flag. When using frames with less than eight bits the most significant

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bits of the data read from the UDRn will be masked to zero. The USART has to be initialized

before the function can be used.

Assembly Code Example⁽¹⁾

USART_Receive:

; Wait for data to be received

sbis UCSRnA, RXCn

rjmp USART_Receive

; Get and return received data from buffer

in

r16, UDRn

ret

C Code Example⁽¹⁾

unsigned char USART_Receive( void )

{

/* Wait for data to be received */

while ( !(UCSRnA & (1<<RXCn)) )

;

/* Get and return received data from buffer */

return UDRn;

}

Note:

1. See “About Code Examples” on page 8.

The function simply waits for data to be present in the receive buffer by checking the RXCn Flag,

before reading the buffer and returning the value.

18.6.2

Receiving Frames with 9 Data Bits

If 9-bit characters are used (UCSZn=7) the ninth bit must be read from the RXB8n bit in UCS-

RnB before reading the low bits from the UDRn. This rule applies to the FEn, DORn and UPEn

Status Flags as well. Read status from UCSRnA, then data from UDRn. Reading the UDRn I/O

location will change the state of the receive buffer FIFO and consequently the TXB8n, FEn,

DORn and UPEn bits, which all are stored in the FIFO, will change.

The following code example shows a simple USART receive function that handles both nine bit

characters and the status bits.

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Assembly Code Example⁽¹⁾

USART_Receive:

; Wait for data to be received

sbis UCSRnA, RXCn

rjmp USART_Receive

; Get status and 9th bit, then data from buffer

in

r18, UCSRnA

r17, UCSRnB

r16, UDRn

; If error, return -1

andi r18,(1<<FEn)|(1<<DORn)|(1<<UPEn)

breq USART_ReceiveNoError

ldi r17, HIGH(-1)

ldi r16, LOW(-1)

USART_ReceiveNoError:

; Filter the 9th bit, then return

lsr r17

andi r17, 0x01

ret

C Code Example⁽¹⁾

unsigned int USART_Receive( void )

{

unsigned char status, resh, resl;

/* Wait for data to be received */

while ( !(UCSRnA & (1<<RXCn)) )

;

/* Get status and 9th bit, then data */

/* from buffer */

status = UCSRnA;

resh = UCSRnB;

resl = UDRn;

/* If error, return -1 */

if ( status & (1<<FEn)|(1<<DORn)|(1<<UPEn) )

return -1;

/* Filter the 9th bit, then return */

resh = (resh >> 1) & 0x01;

return ((resh << 8) | resl);

}

Note:

1. See “About Code Examples” on page 8.

The receive function example reads all the I/O Registers into the Register File before any com-

putation is done. This gives an optimal receive buffer utilization since the buffer location read will

be free to accept new data as early as possible.

18.6.3

194

Receive Compete Flag and Interrupt

The USART Receiver has one flag that indicates the Receiver state.

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The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive

buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive

buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXENn = 0),

the receive buffer will be flushed and consequently the RXCn bit will become zero.

When the Receive Complete Interrupt Enable (RXCIEn) in UCSRnB is set, the USART Receive

Complete interrupt will be executed as long as the RXCn Flag is set (provided that global inter-

rupts are enabled). When interrupt-driven data reception is used, the receive complete routine

must read the received data from UDRn in order to clear the RXCn Flag, otherwise a new inter-

rupt will occur once the interrupt routine terminates.

18.6.4

Receiver Error Flags

The USART Receiver has three Error Flags: Frame Error (FEn), Data OverRun (DORn) and

Parity Error (UPEn). All can be accessed by reading UCSRnA. Common for the Error Flags is

that they are located in the receive buffer together with the frame for which they indicate the

error status. Due to the buffering of the Error Flags, the UCSRnA must be read before the

receive buffer (UDRn), since reading the UDRn I/O location changes the buffer read location.

Another equality for the Error Flags is that they can not be altered by software doing a write to

the flag location. However, all flags must be set to zero when the UCSRnA is written for upward

compatibility of future USART implementations. None of the Error Flags can generate interrupts.

The Frame Error (FEn) Flag indicates the state of the first stop bit of the next readable frame

stored in the receive buffer. The FEn Flag is zero when the stop bit was correctly read (as one),

and the FEn Flag will be one when the stop bit was incorrect (zero). This flag can be used for

detecting out-of-sync conditions, detecting break conditions and protocol handling. The FEn

Flag is not affected by the setting of the USBSn bit in UCSRnC since the Receiver ignores all,

except for the first, stop bits. For compatibility with future devices, always set this bit to zero

when writing to UCSRnA.

The Data OverRun (DORn) Flag indicates data loss due to a receiver buffer full condition. A

Data OverRun occurs when the receive buffer is full (two characters), it is a new character wait-

ing in the Receive Shift Register, and a new start bit is detected. If the DORn Flag is set there

was one or more serial frame lost between the frame last read from UDRn, and the next frame

read from UDRn. For compatibility with future devices, always write this bit to zero when writing

to UCSRnA. The DORn Flag is cleared when the frame received was successfully moved from

the Shift Register to the receive buffer.

The Parity Error (UPEn) Flag indicates that the next frame in the receive buffer had a Parity

Error when received. If Parity Check is not enabled the UPEn bit will always be read zero. For

compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more

details see “Parity Bit Calculation” on page 188 and “Parity Checker” on page 195.

18.6.5

Parity Checker

The Parity Checker is active when the high USART Parity mode (UPMn1) bit is set. Type of Par-

ity Check to be performed (odd or even) is selected by the UPMn0 bit. When enabled, the Parity

Checker calculates the parity of the data bits in incoming frames and compares the result with

the parity bit from the serial frame. The result of the check is stored in the receive buffer together

with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software

to check if the frame had a Parity Error.

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The UPEn bit is set if the next character that can be read from the receive buffer had a Parity

Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is

valid until the receive buffer (UDRn) is read.

18.6.6

18.6.7

Disabling the Receiver

In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing

receptions will therefore be lost. When disabled (i.e., the RXENn is set to zero) the Receiver will

no longer override the normal function of the RxDn port pin. The Receiver buffer FIFO will be

flushed when the Receiver is disabled. Remaining data in the buffer will be lost

Flushing the Receive Buffer

The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be

emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal

operation, due to for instance an error condition, read the UDRn I/O location until the RXCn Flag

is cleared. The following code example shows how to flush the receive buffer.

Assembly Code Example⁽¹⁾

USART_Flush:

sbis UCSRnA, RXCn

ret

in

rjmp USART_Flush

C Code Example⁽¹⁾

r16, UDRn

void USART_Flush( void )

{

unsigned char dummy;

while ( UCSRnA & (1<<RXCn) ) dummy = UDRn;

}

Note:

1. See “About Code Examples” on page 8.

18.7 Asynchronous Data Reception

The USART includes a clock recovery and a data recovery unit for handling asynchronous data

reception. The clock recovery logic is used for synchronizing the internally generated baud rate

clock to the incoming asynchronous serial frames at the RxDn pin. The data recovery logic sam-

ples and low pass filters each incoming bit, thereby improving the noise immunity of the

Receiver. The asynchronous reception operational range depends on the accuracy of the inter-

nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.

18.7.1

Asynchronous Clock Recovery

The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 18-5

illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times

the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The hor-

izontal arrows illustrate the synchronization variation due to the sampling process. Note the

larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples

denoted zero are samples done when the RxDn line is idle (i.e., no communication activity).

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Figure 18-5. Start Bit Sampling

RxD

IDLE

START

BIT 0

Sample

(U2X = 0)

0

1

2

3

2

4

5

3

6

7

4

8

9

5

10

11

6

12

13

7

14

15

8

16

1

2

3

2

Sample

(U2X = 1)

0

When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the

start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in

the figure. The clock recovery logic then uses samples 8, 9, and 10 for Normal mode, and sam-

ples 4, 5, and 6 for Double Speed mode (indicated with sample numbers inside boxes on the

figure), to decide if a valid start bit is received. If two or more of these three samples have logical

high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver starts

looking for the next high to low-transition. If however, a valid start bit is detected, the clock recov-

ery logic is synchronized and the data recovery can begin. The synchronization process is

repeated for each start bit.

18.7.2

Asynchronous Data Recovery

When the receiver clock is synchronized to the start bit, the data recovery can begin. The data

recovery unit uses a state machine that has 16 states for each bit in Normal mode and eight

states for each bit in Double Speed mode. Figure 18-6 shows the sampling of the data bits and

the parity bit. Each of the samples is given a number that is equal to the state of the recovery

unit.

Figure 18-6. Sampling of Data and Parity Bit

RxD

BIT n

Sample

(U2X = 0)

1

2

3

2

4

5

3

6

7

4

8

9

5

10

11

6

12

13

7

14

15

8

16

1

Sample

(U2X = 1)

The decision of the logic level of the received bit is taken by doing a majority voting of the logic

value to the three samples in the center of the received bit. The center samples are emphasized

on the figure by having the sample number inside boxes. The majority voting process is done as

follows: If two or all three samples have high levels, the received bit is registered to be a logic 1.

If two or all three samples have low levels, the received bit is registered to be a logic 0. This

majority voting process acts as a low pass filter for the incoming signal on the RxDn pin. The

recovery process is then repeated until a complete frame is received. Including the first stop bit.

Note that the Receiver only uses the first stop bit of a frame.

Figure 18-7 shows the sampling of the stop bit and the earliest possible beginning of the start bit

of the next frame.

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Figure 18-7. Stop Bit Sampling and Next Start Bit Sampling

(A)

(B)

(C)

RxD

STOP 1

Sample

(U2X = 0)

1

2

3

2

4

5

3

6

7

4

8

9

5

10

0/1 0/1 0/1

Sample

(U2X = 1)

6

0/1

The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop

bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.

A new high to low transition indicating the start bit of a new frame can come right after the last of

the bits used for majority voting. For Normal Speed mode, the first low level sample can be at

point marked (A) in Figure 18-7. For Double Speed mode the first low level must be delayed to

(B). (C) marks a stop bit of full length. The early start bit detection influences the operational

range of the Receiver.

18.7.3

Asynchronous Operational Range

The operational range of the Receiver is dependent on the mismatch between the received bit

rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too

slow bit rates, or the internally generated baud rate of the Receiver does not have a similar (see

Table 18-2) base frequency, the Receiver will not be able to synchronize the frames to the start

bit.

The following equations can be used to calculate the ratio of the incoming data rate and internal

receiver baud rate.

Table 1.

(D + 1)S

S – 1 + D ⋅ S + S

(D + 2)S

(D + 1)S + S

R

= ------------------------------------------

R

= -----------------------------------

slow

fast

F

M

D

S

Sum of character size and parity size (D = 5 to 10 bit)

Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed

mode.

S_F

First sample number used for majority voting. S_F= 8 for normal speed and S_F= 4

for Double Speed mode.

S_M

Middle sample number used for majority voting. S_M= 9 for normal speed and

S_M= 5 for Double Speed mode.

R_slow

is the ratio of the slowest incoming data rate that can be accepted in relation to the

receiver baud rate. R_fastis the ratio of the fastest incoming data rate that can be

accepted in relation to the receiver baud rate.

Table 18-2 and Table 18-3 list the maximum receiver baud rate error that can be tolerated. Note

that Normal Speed mode has higher toleration of baud rate variations.

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Table 18-2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode

(U2Xn = 0)

D

Recommended Max

Receiver Error (%)

# (Data+Parity Bit)

R

_slow(%)

93.20

94.12

94.81

95.36

95.81

96.17

R_fast(%)

106.67

105.79

105.11

104.58

104.14

103.78

Max Total Error (%)

+6.67/-6.8

5

6

± 3.0

± 2.5

± 2.0

± 1.5

+5.79/-5.88

+5.11/-5.19

7

8

+4.58/-4.54

+4.14/-4.19

+3.78/-3.83

9

10

Table 18-3. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode

(U2Xn = 1)

D

Recommended Max

Receiver Error (%)

# (Data+Parity Bit) R_slow(%) R_fast(%) Max Total Error (%)

5

6

94.12

94.92

95.52

96.00

96.39

96.70

105.66

104.92

104,35

103.90

103.53

103.23

+5.66/-5.88

+4.92/-5.08

+4.35/-4.48

+3.90/-4.00

+3.53/-3.61

+3.23/-3.30

± 2.5

± 2.0

± 1.5

± 1.0

7

8

9

10

The recommendations of the maximum receiver baud rate error was made under the assump-

tion that the Receiver and Transmitter equally divides the maximum total error.

There are two possible sources for the receivers baud rate error. The Receiver’s system clock

(XTAL) will always have some minor instability over the supply voltage range and the tempera-

ture range. When using a crystal to generate the system clock, this is rarely a problem, but for a

resonator the system clock may differ more than 2% depending of the resonators tolerance. The

second source for the error is more controllable. The baud rate generator can not always do an

exact division of the system frequency to get the baud rate wanted. In this case an UBRR value

that gives an acceptable low error can be used if possible.

18.8 Multi-processor Communication Mode

Setting the Multi-processor Communication mode (MPCMn) bit in UCSRnA enables a filtering

function of incoming frames received by the USART Receiver. Frames that do not contain

address information will be ignored and not put into the receive buffer. This effectively reduces

the number of incoming frames that has to be handled by the CPU, in a system with multiple

MCUs that communicate via the same serial bus. The Transmitter is unaffected by the MPCMn

setting, but has to be used differently when it is a part of a system utilizing the Multi-processor

Communication mode.

If the Receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indi-

cates if the frame contains data or address information. If the Receiver is set up for frames with

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nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When

the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the

frame type bit is zero the frame is a data frame.

The Multi-processor Communication mode enables several slave MCUs to receive data from a

master MCU. This is done by first decoding an address frame to find out which MCU has been

addressed. If a particular slave MCU has been addressed, it will receive the following data

frames as normal, while the other slave MCUs will ignore the received frames until another

address frame is received.

18.8.1

Using MPCMn

For an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZn = 7). The

ninth bit (TXB8n) must be set when an address frame (TXB8n = 1) or cleared when a data frame

(TXB = 0) is being transmitted. The slave MCUs must in this case be set to use a 9-bit character

frame format.

The following procedure should be used to exchange data in Multi-processor Communication

mode:

1. All Slave MCUs are in Multi-processor Communication mode (MPCMn in UCSRnA is

set).

2. The Master MCU sends an address frame, and all slaves receive and read this frame.

In the Slave MCUs, the RXCn Flag in UCSRnA will be set as normal.

3. Each Slave MCU reads the UDRn Register and determines if it has been selected. If

so, it clears the MPCMn bit in UCSRnA, otherwise it waits for the next address byte and

keeps the MPCMn setting.

4. The addressed MCU will receive all data frames until a new address frame is received.

The other Slave MCUs, which still have the MPCMn bit set, will ignore the data frames.

5. When the last data frame is received by the addressed MCU, the addressed MCU sets

the MPCMn bit and waits for a new address frame from master. The process then

repeats from 2.

Using any of the 5- to 8-bit character frame formats is possible, but impractical since the

Receiver must change between using n and n+1 character frame formats. This makes full-

duplex operation difficult since the Transmitter and Receiver uses the same character size set-

ting. If 5- to 8-bit character frames are used, the Transmitter must be set to use two stop bit

(USBSn = 1) since the first stop bit is used for indicating the frame type.

Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The

MPCMn bit shares the same I/O location as the TXCn Flag and this might accidentally be

cleared when using SBI or CBI instructions.

18.9 USART Register Description

18.9.1

USART I/O Data Register n– UDRn

Bit

7

6

5

4

3

2

1

0

RXB[7:0]

TXB[7:0]

R/W

UDRn (Read)

UDRn (Write)

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the

same I/O address referred to as USART Data Register or UDRn. The Transmit Data Buffer Reg-

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AT90USB64/128

ister (TXB) will be the destination for data written to the UDRn Register location. Reading the

UDRn Register location will return the contents of the Receive Data Buffer Register (RXB).

For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to

zero by the Receiver.

The transmit buffer can only be written when the UDREn Flag in the UCSRnA Register is set.

Data written to UDRn when the UDREn Flag is not set, will be ignored by the USART Transmit-

ter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter

will load the data into the Transmit Shift Register when the Shift Register is empty. Then the

data will be serially transmitted on the TxDn pin.

The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the

receive buffer is accessed. Due to this behavior of the receive buffer, do not use Read-Modify-

Write instructions (SBI and CBI) on this location. Be careful when using bit test instructions

(SBIC and SBIS), since these also will change the state of the FIFO.

18.9.2

USART Control and Status Register A – UCSRnA

Bit

7

6

5

4

3

2

1

0

RXCn

TXCn

UDREn

FEn

R

DORn

UPEn

U2Xn

R/W

0

MPCMn

R/W

0

UCSRnA

Read/Write

Initial Value

R

0

R/W

0

R

1

R

0

R

0

• Bit 7 – RXCn: USART Receive Complete

This flag bit is set when there are unread data in the receive buffer and cleared when the receive

buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive

buffer will be flushed and consequently the RXCn bit will become zero. The RXCn Flag can be

used to generate a Receive Complete interrupt (see description of the RXCIEn bit).

• Bit 6 – TXCn: USART Transmit Complete

This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and

there are no new data currently present in the transmit buffer (UDRn). The TXCn Flag bit is auto-

matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing

a one to its bit location. The TXCn Flag can generate a Transmit Complete interrupt (see

description of the TXCIEn bit).

• Bit 5 – UDREn: USART Data Register Empty

The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn

is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a

Data Register Empty interrupt (see description of the UDRIEn bit).

UDREn is set after a reset to indicate that the Transmitter is ready.

• Bit 4 – FEn: Frame Error

This bit is set if the next character in the receive buffer had a Frame Error when received. I.e.,

when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the

receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one.

Always set this bit to zero when writing to UCSRnA.

• Bit 3 – DORn: Data OverRun

This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive

buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a

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new start bit is detected. This bit is valid until the receive buffer (UDRn) is read. Always set this

bit to zero when writing to UCSRnA.

• Bit 2 – UPEn: USART Parity Error

This bit is set if the next character in the receive buffer had a Parity Error when received and the

Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer

(UDRn) is read. Always set this bit to zero when writing to UCSRnA.

• Bit 1 – U2Xn: Double the USART Transmission Speed

This bit only has effect for the asynchronous operation. Write this bit to zero when using syn-

chronous operation.

Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively dou-

bling the transfer rate for asynchronous communication.

• Bit 0 – MPCMn: Multi-processor Communication Mode

This bit enables the Multi-processor Communication mode. When the MPCMn bit is written to

one, all the incoming frames received by the USART Receiver that do not contain address infor-

mation will be ignored. The Transmitter is unaffected by the MPCMn setting. For more detailed

information see “Multi-processor Communication Mode” on page 199.

18.9.3

USART Control and Status Register n B – UCSRnB

Bit

7

6

5

4

3

2

1

0

RXCIEn

TXCIEn

UDRIEn

RXENn

R/W

0

TXENn

R/W

0

UCSZn2

R/W

0

RXB8n

TXB8n

R/W

0

UCSRnB

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R

0

• Bit 7 – RXCIEn: RX Complete Interrupt Enable n

Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete interrupt

will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is

written to one and the RXCn bit in UCSRnA is set.

• Bit 6 – TXCIEn: TX Complete Interrupt Enable n

Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt

will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is

written to one and the TXCn bit in UCSRnA is set.

• Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable n

Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will

be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written

to one and the UDREn bit in UCSRnA is set.

• Bit 4 – RXENn: Receiver Enable n

Writing this bit to one enables the USART Receiver. The Receiver will override normal port oper-

ation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer

invalidating the FEn, DORn, and UPEn Flags.

• Bit 3 – TXENn: Transmitter Enable n

Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port

operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to

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zero) will not become effective until ongoing and pending transmissions are completed, i.e.,

when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-

mitted. When disabled, the Transmitter will no longer override the TxDn port.

• Bit 2 – UCSZn2: Character Size n

The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits

(Character SiZe) in a frame the Receiver and Transmitter use.

• Bit 1 – RXB8n: Receive Data Bit 8 n

RXB8n is the ninth data bit of the received character when operating with serial frames with nine

data bits. Must be read before reading the low bits from UDRn.

• Bit 0 – TXB8n: Transmit Data Bit 8 n

TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames

with nine data bits. Must be written before writing the low bits to UDRn.

18.9.4

USART Control and Status Register n C – UCSRnC

Bit

7

6

5

4

3

2

1

0

UMSELn1

UMSELn0

UPMn1

UPMn0

R/W

0

USBSn

R/W

0

UCSZn1

R/W

1

UCSZn0

R/W

1

UCPOLn

UCSRnC

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

• Bits 7:6 – UMSELn1:0 USART Mode Select

These bits select the mode of operation of the USARTn as shown in Table 18-4..

Table 18-4. UMSELn Bits Settings

UMSELn1

UMSELn0

Mode

0

1

0

1

0

1

Asynchronous USART

Synchronous USART

(Reserved)

Master SPI (MSPIM)⁽¹⁾

Note:

1. See “USART in SPI Mode” on page 208 for full description of the Master SPI Mode (MSPIM)

operation

• Bits 5:4 – UPMn1:0: Parity Mode

These bits enable and set type of parity generation and check. If enabled, the Transmitter will

automatically generate and send the parity of the transmitted data bits within each frame. The

Receiver will generate a parity value for the incoming data and compare it to the UPMn setting.

If a mismatch is detected, the UPEn Flag in UCSRnA will be set.

Table 18-5. UPMn Bits Settings

UPMn1

UPMn0

Parity Mode

0

1

0

1

0

1

Disabled

Reserved

Enabled, Even Parity

Enabled, Odd Parity

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• Bit 3 – USBSn: Stop Bit Select

This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores

this setting.

Table 18-6. USBS Bit Settings

USBSn

Stop Bit(s)

1-bit

0

1

2-bit

• Bit 2:1 – UCSZn1:0: Character Size

The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits

(Character SiZe) in a frame the Receiver and Transmitter use.

Table 18-7. UCSZn Bits Settings

UCSZn2

UCSZn1

UCSZn0

Character Size

5-bit

0

1

0

1

0

1

0

1

0

1

0

1

0

1

6-bit

7-bit

8-bit

Reserved

9-bit

• Bit 0 – UCPOLn: Clock Polarity

This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is

used. The UCPOLn bit sets the relationship between data output change and data input sample,

and the synchronous clock (XCKn).

Table 18-8. UCPOLn Bit Settings

Transmitted Data Changed (Output

of TxDn Pin)

Received Data Sampled (Input on

RxDn Pin)

UCPOLn

0

1

Rising XCKn Edge

Falling XCKn Edge

Rising XCKn Edge

18.9.5

USART Baud Rate Registers – UBRRLn and UBRRHn

Bit

15

14

13

12

11

10

9

8

–

UBRR[11:8]

UBRRHn

UBRRLn

UBRR[7:0]

7

6

5

4

3

2

1

0

Read/Write

Initial Value

R

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 15:12 – Reserved Bits

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AT90USB64/128

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AT90USB64/128

These bits are reserved for future use. For compatibility with future devices, these bit must be

written to zero when UBRRH is written.

• Bit 11:0 – UBRR11:0: USART Baud Rate Register

This is a 12-bit register which contains the USART baud rate. The UBRRH contains the four

most significant bits, and the UBRRL contains the eight least significant bits of the USART baud

rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is

changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler.

18.10 Examples of Baud Rate Setting

For standard crystal and resonator frequencies, the most commonly used baud rates for asyn-

chronous operation can be generated by using the UBRR settings in Table 18-9 to Table 18-12.

UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate,

are bold in the table. Higher error ratings are acceptable, but the Receiver will have less noise

resistance when the error ratings are high, especially for large serial frames (see “Asynchronous

Operational Range” on page 198). The error values are calculated using the following equation:

BaudRate_{Closest Match}

⎛

⎞

Error[%] = ------------------------------------------------------- – 1 • 100%

⎝

⎠

BaudRate

Table 18-9. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies

f_osc= 1.0000 MHz f_osc= 1.8432 MHz

U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1

UBRR UBRR UBRR UBRR

f_osc= 2.0000 MHz

U2Xn = 0 U2Xn = 1

UBRR UBRR

Baud

Rate

(bps)

Error

0.2%

-7.0%

8.5%

-18.6%

8.5%

–

Error

0.2%

-3.5%

-7.0%

8.5%

-18.6%

8.5%

–

Error

0.0%

-25.0%

0.0%

–

Error

0.0%

–

Error

0.2%

-3.5%

-7.0%

8.5%

-18.6%

8.5%

–

Error

0.2%

2.1%

0.2%

-3.5%

-7.0%

8.5%

–

2400

25

12

6

51

25

12

8

47

23

11

7

95

47

23

15

11

7

51

25

12

8

103

51

25

16

12

8

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

3

2

6

5

6

1

3

1

2

5

2

6

0

1

3

1

3

–

1

2

1

2

–

0

1

0

1

–

0

–

0

0.0%

Max. ⁽¹⁾

62.5 kbps

UBRR = 0, Error = 0.0%

125 kbps

115.2 kbps

230.4 kbps

125 kbps

250 kbps

1.

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Table 18-10. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)

f_osc= 3.6864 MHz

U2Xn = 0

f_osc= 4.0000 MHz

U2Xn = 0

f_osc= 7.3728 MHz

U2Xn = 0

Baud

Rate

(bps)

U2Xn = 1

UBRR

Error

0.0%

-7.8%

–

UBRR

191

95

47

31

23

15

11

7

Error

0.0%

-7.8%

–

UBRR

Error

0.2%

2.1%

0.2%

-3.5%

-7.0%

8.5%

0.0%

–

UBRR

207

103

51

34

25

16

12

8

Error

0.2%

-0.8%

0.2%

2.1%

0.2%

-3.5%

-7.0%

8.5%

0.0%

–

UBRR

191

95

47

31

23

15

11

7

Error

0.0%

-7.8%

–

UBRR

383

191

95

63

47

31

23

15

11

7

Error

0.0%

-7.8%

2400

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

95

47

23

15

11

7

103

51

25

16

12

8

5

6

3

2

5

2

6

5

1

3

1

3

0

1

0

1

3

0

1

0

1

3

0.5M

–

0

–

0

1

1M

–

0

Max. ⁽¹⁾

230.4 kbps

UBRR = 0, Error = 0.0%

460.8 kbps

250 kbps

0.5 Mbps

460.8 kbps

921.6 kbps

1.

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AT90USB64/128

Table 18-11. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)

f_osc= 8.0000 MHz f_osc= 11.0592 MHz f_osc= 14.7456 MHz

U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1

UBRR UBRR UBRR UBRR UBRR UBRR

Baud

Rate

(bps)

Error

0.2%

-0.8%

0.2%

2.1%

0.2%

-3.5%

-7.0%

8.5%

0.0%

–

Error

-0.1%

0.2%

0.6%

0.2%

-0.8%

0.2%

2.1%

0.2%

-3.5%

8.5%

0.0%

Error

0.0%

-7.8%

–

Error

0.0%

-7.8%

–

Error

0.0%

-7.8%

Error

0.0%

5.3%

-7.8%

2400

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

207

103

51

34

25

16

12

8

416

207

103

68

51

34

25

16

12

8

287

143

71

47

35

23

17

11

8

575

287

143

95

71

47

35

23

17

11

5

383

191

95

63

47

31

23

15

11

7

767

383

191

127

95

63

47

31

23

15

7

6

3

5

1

3

2

3

1

3

2

5

3

6

0.5M

0

1

–

2

1

3

1M

–

0

–

0

1

Max. ⁽¹⁾

0.5 Mbps

UBRR = 0, Error = 0.0%

1 Mbps

691.2 kbps

1.3824 Mbps

921.6 kbps

1.8432 Mbps

1.

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Table 18-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)

f_osc= 16.0000 MHz f_osc= 18.4320 MHz f_osc= 20.0000 MHz

U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1

UBRR UBRR UBRR UBRR UBRR UBRR

Baud

Rate

(bps)

Error

-0.1%

0.2%

0.6%

0.2%

-0.8%

0.2%

2.1%

0.2%

-3.5%

8.5%

0.0%

Error

0.0%

-0.1%

0.2%

-0.1%

0.2%

0.6%

0.2%

-0.8%

0.2%

2.1%

-3.5%

0.0%

Error

0.0%

-7.8%

–

Error

0.0%

2.4%

-7.8%

–

Error

0.0%

0.2%

-0.2%

0.2%

0.9%

-1.4%

1.7%

-1.4%

8.5%

0.0%

–

Error

0.0%

0.2%

-0.2%

0.2%

-0.2%

0.2%

0.9%

-1.4%

0.0%

–

2400

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

416

207

103

68

51

34

25

16

12

8

832

416

207

138

103

68

51

34

25

16

8

479

239

119

79

59

39

29

19

14

9

959

479

239

159

119

79

59

39

29

19

9

520

259

129

86

64

42

32

21

15

10

4

1041

520

259

173

129

86

64

42

32

21

3

4

10

3

7

4

8

4

9

0.5M

1

3

–

4

–

4

1M

0

1

–

Max. ⁽¹⁾

1 Mbps

UBRR = 0, Error = 0.0%

2 Mbps

1.152 Mbps

2.304 Mbps

1.25 Mbps

2.5 Mbps

1.

19. USART in SPI Mode

The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can be

set to a master SPI compliant mode of operation. The Master SPI Mode (MSPIM) has the follow-

ing features:

• Full Duplex, Three-wire Synchronous Data Transfer

• Master Operation

• Supports all four SPI Modes of Operation (Mode 0, 1, 2, and 3)

• LSB First or MSB First Data Transfer (Configurable Data Order)

• Queued Operation (Double Buffered)

• High Resolution Baud Rate Generator

• High Speed Operation (fXCKmax = fCK/2)

• Flexible Interrupt Generation

19.1 Overview

Setting both UMSELn1:0 bits to one enables the USART in MSPIM logic. In this mode of opera-

tion the SPI master control logic takes direct control over the USART resources. These

resources include the transmitter and receiver shift register and buffers, and the baud rate gen-

erator. The parity generator and checker, the data and clock recovery logic, and the RX and TX

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control logic is disabled. The USART RX and TX control logic is replaced by a common SPI

transfer control logic. However, the pin control logic and interrupt generation logic is identical in

both modes of operation.

The I/O register locations are the same in both modes. However, some of the functionality of the

control registers changes when using MSPIM.

19.2 Clock Generation

The Clock Generation logic generates the base clock for the Transmitter and Receiver. For

USART MSPIM mode of operation only internal clock generation (i.e. master operation) is sup-

ported. The Data Direction Register for the XCKn pin (DDR_XCKn) must therefore be set to one

(i.e. as output) for the USART in MSPIM to operate correctly. Preferably the DDR_XCKn should

be set up before the USART in MSPIM is enabled (i.e. TXENn and RXENn bit set to one).

The internal clock generation used in MSPIM mode is identical to the USART synchronous mas-

ter mode. The baud rate or UBRRn setting can therefore be calculated using the same

equations, see Table 19-1:

Table 19-1. Equations for Calculating Baud Rate Register Setting

Equation for Calculating Baud

Rate⁽¹⁾

Equation for Calculating

UBRRn Value

Operating Mode

f

Synchronous Master

mode

OSC

BAUD = --------------------------------------

2(UBRRn + 1)

UBRRn = -------------------- – 1

2BAUD

Note:

1. The baud rate is defined to be the transfer rate in bit per second (bps)

BAUD

Baud rate (in bits per second, bps)

f_OSC

System Oscillator clock frequency

UBRRn

Contents of the UBRRnH and UBRRnL Registers, (0-4095)

19.3 SPI Data Modes and Timing

There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which

are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are

shown in Figure 19-1. Data bits are shifted out and latched in on opposite edges of the XCKn

signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and UCPHAn function-

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ality is summarized in Table 19-2. Note that changing the setting of any of these bits will corrupt

all ongoing communication for both the Receiver and Transmitter.

Table 19-2. UCPOLn and UCPHAn Functionality-

UCPOLn

UCPHAn

SPI Mode

Leading Edge

Sample (Rising)

Setup (Rising)

Sample (Falling)

Setup (Falling)

Trailing Edge

Setup (Falling)

Sample (Falling)

Setup (Rising)

Sample (Rising)

0

1

0

1

0

1

0

1

2

3

Figure 19-1. UCPHAn and UCPOLn data transfer timing diagrams.

UCPOL=0

UCPOL=1

XCK

Data setup (TXD)

Data sample (RXD)

Data setup (TXD)

Data sample (RXD)

XCK

Data setup (TXD)

Data sample (RXD)

Data setup (TXD)

Data sample (RXD)

19.4 Frame Formats

A serial frame for the MSPIM is defined to be one character of 8 data bits. The USART in MSPIM

mode has two valid frame formats:

• 8-bit data with MSB first

• 8-bit data with LSB first

A frame starts with the least or most significant data bit. Then the next data bits, up to a total of

eight, are succeeding, ending with the most or least significant bit accordingly. When a complete

frame is transmitted, a new frame can directly follow it, or the communication line can be set to

an idle (high) state.

The UDORDn bit in UCSRnC sets the frame format used by the USART in MSPIM mode. The

Receiver and Transmitter use the same setting. Note that changing the setting of any of these

bits will corrupt all ongoing communication for both the Receiver and Transmitter.

16-bit data transfer can be achieved by writing two data bytes to UDRn. A UART transmit com-

plete interrupt will then signal that the 16-bit value has been shifted out.

19.4.1

USART MSPIM Initialization

The USART in MSPIM mode has to be initialized before any communication can take place. The

initialization process normally consists of setting the baud rate, setting master mode of operation

(by setting DDR_XCKn to one), setting frame format and enabling the Transmitter and the

Receiver. Only the transmitter can operate independently. For interrupt driven USART opera-

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tion, the Global Interrupt Flag should be cleared (and thus interrupts globally disabled) when

doing the initialization.

Note:

To ensure immediate initialization of the XCKn output the baud-rate register (UBRRn) must be

zero at the time the transmitter is enabled. Contrary to the normal mode USART operation the

UBRRn must then be written to the desired value after the transmitter is enabled, but before the

first transmission is started. Setting UBRRn to zero before enabling the transmitter is not neces-

sary if the initialization is done immediately after a reset since UBRRn is reset to zero.

Before doing a re-initialization with changed baud rate, data mode, or frame format, be sure that

there is no ongoing transmissions during the period the registers are changed. The TXCn Flag

can be used to check that the Transmitter has completed all transfers, and the RXCn Flag can

be used to check that there are no unread data in the receive buffer. Note that the TXCn Flag

must be cleared before each transmission (before UDRn is written) if it is used for this purpose.

The following simple USART initialization code examples show one assembly and one C func-

tion that are equal in functionality. The examples assume polling (no interrupts enabled). The

baud rate is given as a function parameter. For the assembly code, the baud rate parameter is

assumed to be stored in the r17:r16 registers.

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Assembly Code Example⁽¹⁾

USART_Init:

clr r18

out UBRRnH,r18

out UBRRnL,r18

; Setting the XCKn port pin as output, enables master mode.

sbi XCKn_DDR, XCKn

; Set MSPI mode of operation and SPI data mode 0.

ldi r18, (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn)

out UCSRnC,r18

; Enable receiver and transmitter.

ldi r18, (1<<RXENn)|(1<<TXENn)

out UCSRnB,r18

; Set baud rate.

; IMPORTANT: The Baud Rate must be set after the transmitter is

enabled!

out UBRRnH, r17

out UBRRnL, r18

ret

C Code Example⁽¹⁾

void USART_Init( unsigned int baud )

{

UBRRn = 0;

/* Setting the XCKn port pin as output, enables master mode. */

XCKn_DDR |= (1<<XCKn);

/* Set MSPI mode of operation and SPI data mode 0. */

UCSRnC = (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn);

/* Enable receiver and transmitter. */

UCSRnB = (1<<RXENn)|(1<<TXENn);

/* Set baud rate. */

/* IMPORTANT: The Baud Rate must be set after the transmitter is

enabled */

UBRRn = baud;

}

Note:

1. See “About Code Examples” on page 8.

19.5 Data Transfer

Using the USART in MSPI mode requires the Transmitter to be enabled, i.e. the TXENn bit in

the UCSRnB register is set to one. When the Transmitter is enabled, the normal port operation

of the TxDn pin is overridden and given the function as the Transmitter's serial output. Enabling

the receiver is optional and is done by setting the RXENn bit in the UCSRnB register to one.

When the receiver is enabled, the normal pin operation of the RxDn pin is overridden and given

the function as the Receiver's serial input. The XCKn will in both cases be used as the transfer

clock.

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After initialization the USART is ready for doing data transfers. A data transfer is initiated by writ-

ing to the UDRn I/O location. This is the case for both sending and receiving data since the

transmitter controls the transfer clock. The data written to UDRn is moved from the transmit

buffer to the shift register when the shift register is ready to send a new frame.

Note:

To keep the input buffer in sync with the number of data bytes transmitted, the UDRn register must

be read once for each byte transmitted. The input buffer operation is identical to normal USART

mode, i.e. if an overflow occurs the character last received will be lost, not the first data in the

buffer. This means that if four bytes are transferred, byte 1 first, then byte 2, 3, and 4, and the

UDRn is not read before all transfers are completed, then byte 3 to be received will be lost, and

not byte 1.

The following code examples show a simple USART in MSPIM mode transfer function based on

polling of the Data Register Empty (UDREn) Flag and the Receive Complete (RXCn) Flag. The

USART has to be initialized before the function can be used. For the assembly code, the data to

be sent is assumed to be stored in Register R16 and the data received will be available in the

same register (R16) after the function returns.

The function simply waits for the transmit buffer to be empty by checking the UDREn Flag,

before loading it with new data to be transmitted. The function then waits for data to be present

in the receive buffer by checking the RXCn Flag, before reading the buffer and returning the

value..

Assembly Code Example⁽¹⁾

USART_MSPIM_Transfer:

; Wait for empty transmit buffer

sbis UCSRnA, UDREn

rjmp USART_MSPIM_Transfer

; Put data (r16) into buffer, sends the data

out UDRn,r16

; Wait for data to be received

USART_MSPIM_Wait_RXCn:

sbis UCSRnA, RXCn

rjmp USART_MSPIM_Wait_RXCn

; Get and return received data from buffer

in r16, UDRn

ret

C Code Example⁽¹⁾

unsigned char USART_Receive( void )

{

/* Wait for empty transmit buffer */

while ( !( UCSRnA & (1<<UDREn)) );

/* Put data into buffer, sends the data */

UDRn = data;

/* Wait for data to be received */

while ( !(UCSRnA & (1<<RXCn)) );

/* Get and return received data from buffer */

return UDRn;

}

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Note:

1. See “About Code Examples” on page 8.

19.5.1

19.5.2

Transmitter and Receiver Flags and Interrupts

The RXCn, TXCn, and UDREn flags and corresponding interrupts in USART in MSPIM mode

are identical in function to the normal USART operation. However, the receiver error status flags

(FE, DOR, and PE) are not in use and is always read as zero.

Disabling the Transmitter or Receiver

The disabling of the transmitter or receiver in USART in MSPIM mode is identical in function to

the normal USART operation.

19.6 USART MSPIM Register Description

The following section describes the registers used for SPI operation using the USART.

19.6.1

19.6.2

USART MSPIM I/O Data Register - UDRn

The function and bit description of the USART data register (UDRn) in MSPI mode is identical to

normal USART operation. See “USART I/O Data Register n– UDRn” on page 200.

USART MSPIM Control and Status Register n A - UCSRnA

Bit

7

6

5

4

3

2

-

1

-

0

-

RXCn

TXCn

UDREn

-

UCSRnA

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R

0

R

0

R

1

R

1

R

0

• Bit 7 - RXCn: USART Receive Complete

This flag bit is set when there are unread data in the receive buffer and cleared when the receive

buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive

buffer will be flushed and consequently the RXCn bit will become zero. The RXCn Flag can be

used to generate a Receive Complete interrupt (see description of the RXCIEn bit).

• Bit 6 - TXCn: USART Transmit Complete

This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and

there are no new data currently present in the transmit buffer (UDRn). The TXCn Flag bit is auto-

matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing

a one to its bit location. The TXCn Flag can generate a Transmit Complete interrupt (see

description of the TXCIEn bit).

• Bit 5 - UDREn: USART Data Register Empty

The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn

is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a

Data Register Empty interrupt (see description of the UDRIE bit). UDREn is set after a reset to

indicate that the Transmitter is ready.

• Bit 4:0 - Reserved Bits in MSPI mode

When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,

these bits must be written to zero when UCSRnA is written.

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19.6.3

USART MSPIM Control and Status Register n B - UCSRnB

Bit

7

6

5

4

3

2

-

1

0

-

RXCIEn

R/W

0

TXCIEn

R/W

0

UDRIE

R/W

0

RXENn

R/W

0

TXENn

R/W

0

-

UCSRnB

Read/Write

Initial Value

R

1

R

1

R

0

• Bit 7 - RXCIEn: RX Complete Interrupt Enable

Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete interrupt

will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is

written to one and the RXCn bit in UCSRnA is set.

• Bit 6 - TXCIEn: TX Complete Interrupt Enable

Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt

will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is

written to one and the TXCn bit in UCSRnA is set.

• Bit 5 - UDRIE: USART Data Register Empty Interrupt Enable

Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will

be generated only if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is written

to one and the UDREn bit in UCSRnA is set.

• Bit 4 - RXENn: Receiver Enable

Writing this bit to one enables the USART Receiver in MSPIM mode. The Receiver will override

normal port operation for the RxDn pin when enabled. Disabling the Receiver will flush the

receive buffer. Only enabling the receiver in MSPI mode (i.e. setting RXENn=1 and TXENn=0)

has no meaning since it is the transmitter that controls the transfer clock and since only master

mode is supported.

• Bit 3 - TXENn: Transmitter Enable

Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port

operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to

zero) will not become effective until ongoing and pending transmissions are completed, i.e.,

when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-

mitted. When disabled, the Transmitter will no longer override the TxDn port.

• Bit 2:0 - Reserved Bits in MSPI mode

When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,

these bits must be written to zero when UCSRnB is written.

19.6.4

USART MSPIM Control and Status Register n C - UCSRnC

Bit

7

6

5

4

3

2

1

0

UMSELn1

UMSELn0

-

UDORDn

UCPHAn

UCPOLn

UCSRnC

Read/Write

Initial Value

R/W

0

R/W

0

R

0

R

0

R

0

R/W

1

R/W

1

R/W

0

• Bit 7:6 - UMSELn1:0: USART Mode Select

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These bits select the mode of operation of the USART as shown in Table 19-3. See “USART

Control and Status Register n C – UCSRnC” on page 203 for full description of the normal

USART operation. The MSPIM is enabled when both UMSELn bits are set to one. The

UDORDn, UCPHAn, and UCPOLn can be set in the same write operation where the MSPIM is

enabled.

Table 19-3. UMSELn Bits Settings

UMSELn1

UMSELn0

Mode

0

1

0

Asynchronous USART

Synchronous USART

(Reserved)

1

0

1

Master SPI (MSPIM)

• Bit 5:3 - Reserved Bits in MSPI mode

When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,

these bits must be written to zero when UCSRnC is written.

• Bit 2 - UDORDn: Data Order

When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the

data word is transmitted first. Refer to the Frame Formats section page 4 for details.

• Bit 1 - UCPHAn: Clock Phase

The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing (last)

edge of XCKn. Refer to the SPI Data Modes and Timing section page 4 for details.

• Bit 0 - UCPOLn: Clock Polarity

The UCPOLn bit sets the polarity of the XCKn clock. The combination of the UCPOLn and

UCPHAn bit settings determine the timing of the data transfer. Refer to the SPI Data Modes and

Timing section page 4 for details.

19.6.5

USART MSPIM Baud Rate Registers - UBRRnL and UBRRnH

The function and bit description of the baud rate registers in MSPI mode is identical to normal

USART operation. See “USART Baud Rate Registers – UBRRLn and UBRRHn” on page 204.

19.7 AVR USART MSPIM vs. AVR SPI

The USART in MSPIM mode is fully compatible with the AVR SPI regarding:

• Master mode timing diagram.

• The UCPOLn bit functionality is identical to the SPI CPOL bit.

• The UCPHAn bit functionality is identical to the SPI CPHA bit.

• The UDORDn bit functionality is identical to the SPI DORD bit.

However, since the USART in MSPIM mode reuses the USART resources, the use of the

USART in MSPIM mode is somewhat different compared to the SPI. In addition to differences of

the control register bits, and that only master operation is supported by the USART in MSPIM

mode, the following features differ between the two modules:

• The USART in MSPIM mode includes (double) buffering of the transmitter. The SPI has no

buffer.

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• The USART in MSPIM mode receiver includes an additional buffer level.

• The SPI WCOL (Write Collision) bit is not included in USART in MSPIM mode.

• The SPI double speed mode (SPI2X) bit is not included. However, the same effect is

achieved by setting UBRRn accordingly.

• Interrupt timing is not compatible.

• Pin control differs due to the master only operation of the USART in MSPIM mode.

A comparison of the USART in MSPIM mode and the SPI pins is shown in Table 19-4 on page

217.

Table 19-4. Comparison of USART in MSPIM mode and SPI pins.

USART_MSPIM

TxDn

SPI

MOSI

MISO

SCK

SS

Comment

Master Out only

RxDn

Master In only

XCKn

(Functionally identical)

Not supported by USART in MSPIM

(N/A)

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20. 2-wire Serial Interface

20.1 Features

• Simple Yet Powerful and Flexible Communication Interface, only two Bus Lines Needed

• Both Master and Slave Operation Supported

• Device can Operate as Transmitter or Receiver

• 7-bit Address Space Allows up to 128 Different Slave Addresses

• Multi-master Arbitration Support

• Up to 400 kHz Data Transfer Speed

• Slew-rate Limited Output Drivers

• Noise Suppression Circuitry Rejects Spikes on Bus Lines

• Fully Programmable Slave Address with General Call Support

• Address Recognition Causes Wake-up When AVR is in Sleep Mode

20.2 2-wire Serial Interface Bus Definition

The 2-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The

TWI protocol allows the systems designer to interconnect up to 128 different devices using only

two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hard-

ware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All

devices connected to the bus have individual addresses, and mechanisms for resolving bus

contention are inherent in the TWI protocol.

Figure 20-1. TWI Bus Interconnection

V_CC

Device 1

Device 3

R1

R2

Device 2

Device n

........

SDA

SCL

20.2.1

TWI Terminology

The following definitions are frequently encountered in this section.

Table 20-1. TWI Terminology

Term

Description

The device that initiates and terminates a transmission. The Master also

generates the SCL clock.

Master

Slave

The device addressed by a Master.

Transmitter The device placing data on the bus.

Receiver

The device reading data from the bus.

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The Power Reduction TWI bit, PRTWI bit in “Power Reduction Register 0 - PRR0” on page 56

must be written to zero to enable the 2-wire Serial Interface.

20.2.2

Electrical Interconnection

As depicted in Figure 20-1, both bus lines are connected to the positive supply voltage through

pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector.

This implements a wired-AND function which is essential to the operation of the interface. A low

level on a TWI bus line is generated when one or more TWI devices output a zero. A high level

is output when all TWI devices trim-state their outputs, allowing the pull-up resistors to pull the

line high. Note that all AVR devices connected to the TWI bus must be powered in order to allow

any bus operation.

The number of devices that can be connected to the bus is only limited by the bus capacitance

limit of 400 pF and the 7-bit slave address space. A detailed specification of the electrical char-

acteristics of the TWI is given in “SPI Timing Characteristics” on page 405. Two different sets of

specifications are presented there, one relevant for bus speeds below 100 kHz, and one valid for

bus speeds up to 400 kHz.

20.3 Data Transfer and Frame Format

20.3.1

Transferring Bits

Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level

of the data line must be stable when the clock line is high. The only exception to this rule is for

generating start and stop conditions.

Figure 20-2. Data Validity

SDA

SCL

Data Stable

Data Change

20.3.2

START and STOP Conditions

The Master initiates and terminates a data transmission. The transmission is initiated when the

Master issues a START condition on the bus, and it is terminated when the Master issues a

STOP condition. Between a START and a STOP condition, the bus is considered busy, and no

other master should try to seize control of the bus. A special case occurs when a new START

condition is issued between a START and STOP condition. This is referred to as a REPEATED

START condition, and is used when the Master wishes to initiate a new transfer without relin-

quishing control of the bus. After a REPEATED START, the bus is considered busy until the next

STOP. This is identical to the START behavior, and therefore START is used to describe both

START and REPEATED START for the remainder of this datasheet, unless otherwise noted. As

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depicted below, START and STOP conditions are signalled by changing the level of the SDA

line when the SCL line is high.

Figure 20-3. START, REPEATED START and STOP conditions

SDA

SCL

START

STOP START

REPEATED START

STOP

20.3.3

Address Packet Format

All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one

READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read opera-

tion is to be performed, otherwise a write operation should be performed. When a Slave

recognizes that it is being addressed, it should acknowledge by pulling SDA low in the ninth SCL

(ACK) cycle. If the addressed Slave is busy, or for some other reason can not service the Mas-

ter’s request, the SDA line should be left high in the ACK clock cycle. The Master can then

transmit a STOP condition, or a REPEATED START condition to initiate a new transmission. An

address packet consisting of a slave address and a READ or a WRITE bit is called SLA+R or

SLA+W, respectively.

The MSB of the address byte is transmitted first. Slave addresses can freely be allocated by the

designer, but the address 0000 000 is reserved for a general call.

When a general call is issued, all slaves should respond by pulling the SDA line low in the ACK

cycle. A general call is used when a Master wishes to transmit the same message to several

slaves in the system. When the general call address followed by a Write bit is transmitted on the

bus, all slaves set up to acknowledge the general call will pull the SDA line low in the ack cycle.

The following data packets will then be received by all the slaves that acknowledged the general

call. Note that transmitting the general call address followed by a Read bit is meaningless, as

this would cause contention if several slaves started transmitting different data.

All addresses of the format 1111 xxx should be reserved for future purposes.

Figure 20-4. Address Packet Format

Addr MSB

Addr LSB

R/W

ACK

SDA

SCL

1

2

7

8

9

START

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20.3.4

Data Packet Format

All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and

an acknowledge bit. During a data transfer, the Master generates the clock and the START and

STOP conditions, while the Receiver is responsible for acknowledging the reception. An

Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL

cycle. If the Receiver leaves the SDA line high, a NACK is signalled. When the Receiver has

received the last byte, or for some reason cannot receive any more bytes, it should inform the

Transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first.

Figure 20-5. Data Packet Format

Data MSB

Data LSB

ACK

Aggregate

SDA

SDA from

Transmitter

SDA from

Receiver

SCL from

Master

1

2

7

8

9

STOP, REPEATED

START or Next

Data Byte

SLA+R/W

Data Byte

20.3.5

Combining Address and Data Packets into a Transmission

A transmission basically consists of a START condition, a SLA+R/W, one or more data packets

and a STOP condition. An empty message, consisting of a START followed by a STOP condi-

tion, is illegal. Note that the Wired-ANDing of the SCL line can be used to implement

handshaking between the Master and the Slave. The Slave can extend the SCL low period by

pulling the SCL line low. This is useful if the clock speed set up by the Master is too fast for the

Slave, or the Slave needs extra time for processing between the data transmissions. The Slave

extending the SCL low period will not affect the SCL high period, which is determined by the

Master. As a consequence, the Slave can reduce the TWI data transfer speed by prolonging the

SCL duty cycle.

Figure 20-6 shows a typical data transmission. Note that several data bytes can be transmitted

between the SLA+R/W and the STOP condition, depending on the software protocol imple-

mented by the application software.

Figure 20-6. Typical Data Transmission

Addr MSB

Addr LSB R/W

ACK

Data MSB

Data LSB ACK

SDA

SCL

1

2

7

8

9

1

2

7

8

9

START

SLA+R/W

Data Byte

STOP

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20.4 Multi-master Bus Systems, Arbitration and Synchronization

The TWI protocol allows bus systems with several masters. Special concerns have been taken

in order to ensure that transmissions will proceed as normal, even if two or more masters initiate

a transmission at the same time. Two problems arise in multi-master systems:

• An algorithm must be implemented allowing only one of the masters to complete the

transmission. All other masters should cease transmission when they discover that they have

lost the selection process. This selection process is called arbitration. When a contending

master discovers that it has lost the arbitration process, it should immediately switch to Slave

mode to check whether it is being addressed by the winning master. The fact that multiple

masters have started transmission at the same time should not be detectable to the slaves,

i.e. the data being transferred on the bus must not be corrupted.

• Different masters may use different SCL frequencies. A scheme must be devised to

synchronize the serial clocks from all masters, in order to let the transmission proceed in a

lockstep fashion. This will facilitate the arbitration process.

The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from

all masters will be wired-ANDed, yielding a combined clock with a high period equal to the one

from the Master with the shortest high period. The low period of the combined clock is equal to

the low period of the Master with the longest low period. Note that all masters listen to the SCL

line, effectively starting to count their SCL high and low time-out periods when the combined

SCL line goes high or low, respectively.

Figure 20-7. SCL Synchronization Between Multiple Masters

TA _low

TA _high

SCL from

Master A

SCL from

Master B

SCL Bus

Line

TB_low

TB_high

Masters Start

Counting Low Period

Counting High Period

Arbitration is carried out by all masters continuously monitoring the SDA line after outputting

data. If the value read from the SDA line does not match the value the Master had output, it has

lost the arbitration. Note that a Master can only lose arbitration when it outputs a high SDA value

while another Master outputs a low value. The losing Master should immediately go to Slave

mode, checking if it is being addressed by the winning Master. The SDA line should be left high,

but losing masters are allowed to generate a clock signal until the end of the current data or

address packet. Arbitration will continue until only one Master remains, and this may take many

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bits. If several masters are trying to address the same Slave, arbitration will continue into the

data packet.

Figure 20-8. Arbitration Between Two Masters

START

Master A Loses

Arbitration, SDA_ASDA

SDA from

Master A

SDA from

Master B

SDA Line

Synchronized

SCL Line

Note that arbitration is not allowed between:

• A REPEATED START condition and a data bit.

• A STOP condition and a data bit.

• A REPEATED START and a STOP condition.

It is the user software’s responsibility to ensure that these illegal arbitration conditions never

occur. This implies that in multi-master systems, all data transfers must use the same composi-

tion of SLA+R/W and data packets. In other words: All transmissions must contain the same

number of data packets, otherwise the result of the arbitration is undefined.

20.5 Overview of the TWI Module

The TWI module is comprised of several submodules, as shown in Figure 20-9. All registers

drawn in a thick line are accessible through the AVR data bus.

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Figure 20-9. Overview of the TWI Module

SCL

SDA

Spike

Filter

Spike

Filter

Slew-rate

Control

Slew-rate

Control

Bus Interface Unit

Bit Rate Generator

START / STOP

Spike Suppression

Prescaler

Control

Address/Data Shift

Register (TWDR)

Bit Rate Register

(TWBR)

Arbitration detection

Ack

Address Match Unit

Control Unit

Address Register

(TWAR)

Status Register

(TWSR)

Control Register

(TWCR)

State Machine and

Status control

Address Comparator

20.5.1

SCL and SDA Pins

These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a

slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike

suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR

pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as

explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need

for external ones.

20.5.2

Bit Rate Generator Unit

This unit controls the period of SCL when operating in a Master mode. The SCL period is con-

trolled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status

Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the

CPU clock frequency in the Slave must be at least 16 times higher than the SCL frequency. Note

that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock

period. The SCL frequency is generated according to the following equation:

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CPU Clock frequency

SCL frequency = -----------------------------------------------------------

TWPS

16 + 2(TWBR) ⋅ 4

• TWBR = Value of the TWI Bit Rate Register.

• TWPS = Value of the prescaler bits in the TWI Status Register.

Note:

TWBR should be 10 or higher if the TWI operates in Master mode. If TWBR is lower than 10, the

Master may produce an incorrect output on SDA and SCL for the reminder of the byte. The prob-

lem occurs when operating the TWI in Master mode, sending Start + SLA + R/W to a Slave (a

Slave does not need to be connected to the bus for the condition to happen).

20.5.3

Bus Interface Unit

This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and

Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted,

or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface Unit also

contains a register containing the (N)ACK bit to be transmitted or received. This (N)ACK Regis-

ter is not directly accessible by the application software. However, when receiving, it can be set

or cleared by manipulating the TWI Control Register (TWCR). When in Transmitter mode, the

value of the received (N)ACK bit can be determined by the value in the TWSR.

The START/STOP Controller is responsible for generation and detection of START, REPEATED

START, and STOP conditions. The START/STOP controller is able to detect START and STOP

conditions even when the AVR MCU is in one of the sleep modes, enabling the MCU to wake up

if addressed by a Master.

If the TWI has initiated a transmission as Master, the Arbitration Detection hardware continu-

ously monitors the transmission trying to determine if arbitration is in process. If the TWI has lost

an arbitration, the Control Unit is informed. Correct action can then be taken and appropriate

status codes generated.

20.5.4

Address Match Unit

The Address Match unit checks if received address bytes match the seven-bit address in the

TWI Address Register (TWAR). If the TWI General Call Recognition Enable (TWGCE) bit in the

TWAR is written to one, all incoming address bits will also be compared against the General Call

address. Upon an address match, the Control Unit is informed, allowing correct action to be

taken. The TWI may or may not acknowledge its address, depending on settings in the TWCR.

The Address Match unit is able to compare addresses even when the AVR MCU is in sleep

mode, enabling the MCU to wake up if addressed by a Master. If another interrupt (e.g., INT0)

occurs during TWI Power-down address match and wakes up the CPU, the TWI aborts opera-

tion and return to it’s idle state. If this cause any problems, ensure that TWI Address Match is the

only enabled interrupt when entering Power-down.

20.5.5

Control Unit

The Control unit monitors the TWI bus and generates responses corresponding to settings in the

TWI Control Register (TWCR). When an event requiring the attention of the application occurs

on the TWI bus, the TWI Interrupt Flag (TWINT) is asserted. In the next clock cycle, the TWI Sta-

tus Register (TWSR) is updated with a status code identifying the event. The TWSR only

contains relevant status information when the TWI Interrupt Flag is asserted. At all other times,

the TWSR contains a special status code indicating that no relevant status information is avail-

able. As long as the TWINT Flag is set, the SCL line is held low. This allows the application

software to complete its tasks before allowing the TWI transmission to continue.

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The TWINT Flag is set in the following situations:

• After the TWI has transmitted a START/REPEATED START condition.

• After the TWI has transmitted SLA+R/W.

• After the TWI has transmitted an address byte.

• After the TWI has lost arbitration.

• After the TWI has been addressed by own slave address or general call.

• After the TWI has received a data byte.

• After a STOP or REPEATED START has been received while still addressed as a Slave.

• When a bus error has occurred due to an illegal START or STOP condition.

20.6 TWI Register Description

20.6.1

TWI Bit Rate Register – TWBR

Bit

7

6

TWBR6

R/W

0

5

TWBR5

R/W

0

4

TWBR4

R/W

0

3

TWBR3

R/W

0

2

TWBR2

R/W

0

1

TWBR1

R/W

0

TWBR0

R/W

0

TWBR7

R/W

0

TWBR

Read/Write

Initial Value

• Bits 7..0 – TWI Bit Rate Register

TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency

divider which generates the SCL clock frequency in the Master modes. See “Bit Rate Generator

Unit” on page 224 for calculating bit rates.

20.6.2

TWI Control Register – TWCR

Bit

7

6

TWEA

R/W

0

5

TWSTA

R/W

0

4

TWSTO

R/W

0

3

2

TWEN

R/W

0

1

–

0

TWIE

R/W

0

TWINT

R/W

0

TWWC

TWCR

Read/Write

Initial Value

R

0

R

0

The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a

Master access by applying a START condition to the bus, to generate a Receiver acknowledge,

to generate a stop condition, and to control halting of the bus while the data to be written to the

bus are written to the TWDR. It also indicates a write collision if data is attempted written to

TWDR while the register is inaccessible.

• Bit 7 – TWINT: TWI Interrupt Flag

This bit is set by hardware when the TWI has finished its current job and expects application

software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the

TWI Interrupt Vector. While the TWINT Flag is set, the SCL low period is stretched. The TWINT

Flag must be cleared by software by writing a logic one to it. Note that this flag is not automati-

cally cleared by hardware when executing the interrupt routine. Also note that clearing this flag

starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Sta-

tus Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this

flag.

• Bit 6 – TWEA: TWI Enable Acknowledge Bit

The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to

one, the ACK pulse is generated on the TWI bus if the following conditions are met:

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1. The device’s own slave address has been received.

2. A general call has been received, while the TWGCE bit in the TWAR is set.

3. A data byte has been received in Master Receiver or Slave Receiver mode.

By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial

Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one

again.

• Bit 5 – TWSTA: TWI START Condition Bit

The application writes the TWSTA bit to one when it desires to become a Master on the 2-wire

Serial Bus. The TWI hardware checks if the bus is available, and generates a START condition

on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is

detected, and then generates a new START condition to claim the bus Master status. TWSTA

must be cleared by software when the START condition has been transmitted.

• Bit 4 – TWSTO: TWI STOP Condition Bit

Writing the TWSTO bit to one in Master mode will generate a STOP condition on the 2-wire

Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared auto-

matically. In Slave mode, setting the TWSTO bit can be used to recover from an error condition.

This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed

Slave mode and releases the SCL and SDA lines to a high impedance state.

• Bit 3 – TWWC: TWI Write Collision Flag

The TWWC bit is set when attempting to write to the TWI Data Register – TWDR when TWINT is

low. This flag is cleared by writing the TWDR Register when TWINT is high.

• Bit 2 – TWEN: TWI Enable Bit

The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to

one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the

slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI

transmissions are terminated, regardless of any ongoing operation.

• Bit 1 – Res: Reserved Bit

This bit is a reserved bit and will always read as zero.

• Bit 0 – TWIE: TWI Interrupt Enable

When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be acti-

vated for as long as the TWINT Flag is high.

20.6.3

TWI Status Register – TWSR

Bit

7

6

TWS6

R

5

TWS5

R

4

TWS4

R

3

TWS3

R

2

–

1

TWPS1

R/W

0

TWPS0

R/W

0

TWS7

TWSR

Read/Write

Initial Value

R

1

R

0

1

• Bits 7..3 – TWS: TWI Status

These 5 bits reflect the status of the TWI logic and the 2-wire Serial Bus. The different status

codes are described later in this section. Note that the value read from TWSR contains both the

5-bit status value and the 2-bit prescaler value. The application designer should mask the pres-

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caler bits to zero when checking the Status bits. This makes status checking independent of

prescaler setting. This approach is used in this datasheet, unless otherwise noted.

• Bit 2 – Res: Reserved Bit

This bit is reserved and will always read as zero.

• Bits 1..0 – TWPS: TWI Prescaler Bits

These bits can be read and written, and control the bit rate prescaler.

Table 20-2. TWI Bit Rate Prescaler

TWPS1

TWPS0

Prescaler Value

0

1

0

1

0

1

4

16

64

To calculate bit rates, see “Bit Rate Generator Unit” on page 224. The value of TWPS1..0 is

used in the equation.

20.6.4

TWI Data Register – TWDR

Bit

7

TWD7

R/W

1

6

TWD6

R/W

1

5

TWD5

R/W

1

4

TWD4

R/W

1

3

TWD3

R/W

1

2

TWD2

R/W

1

TWD1

R/W

1

0

TWD0

R/W

1

TWDR

Read/Write

Initial Value

In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR

contains the last byte received. It is writable while the TWI is not in the process of shifting a byte.

This occurs when the TWI Interrupt Flag (TWINT) is set by hardware. Note that the Data Regis-

ter cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains

stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously

shifted in. TWDR always contains the last byte present on the bus, except after a wake up from

a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case

of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the

ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.

• Bits 7..0 – TWD: TWI Data Register

These eight bits constitute the next data byte to be transmitted, or the latest data byte received

on the 2-wire Serial Bus.

20.6.5

TWI (Slave) Address Register – TWAR

Bit

7

6

5

TWA4

R/W

1

4

TWA3

R/W

1

3

TWA2

R/W

1

2

TWA1

R/W

1

TWA0

R/W

1

0

TWGCE

R/W

0

TWA6

R/W

1

TWA5

R/W

1

TWAR

Read/Write

Initial Value

The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of

TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver,

and not needed in the Master modes. In multimaster systems, TWAR must be set in masters

which can be addressed as Slaves by other Masters.

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The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an

associated address comparator that looks for the slave address (or general call address if

enabled) in the received serial address. If a match is found, an interrupt request is generated.

• Bits 7..1 – TWA: TWI (Slave) Address Register

These seven bits constitute the slave address of the TWI unit.

• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit

If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.

20.6.6

TWI (Slave) Address Mask Register – TWAMR

Bit

7

6

5

4

TWAM[6:0]

R/W

3

2

1

0

–

TWAMR

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R

0

• Bits 7..1 – TWAM: TWI Address Mask

The TWAMR can be loaded with a 7-bit Slave Address mask. Each of the bits in TWAMR can

mask (disable) the corresponding address bit in the TWI Address Register (TWAR). If the mask

bit is set to one then the address match logic ignores the compare between the incoming

address bit and the corresponding bit in TWAR. Figure 20-10 shows the address match logic in

detail.

Figure 20-10. TWI Address Match Logic, Block Diagram

TWAR0

Address

Match

Address

Bit 0

TWAMR0

Address Bit Comparator 0

Address Bit Comparator 6..1

• Bit 0 – Res: Reserved Bit

This bit is reserved and will always read as zero.

20.7 Using the TWI

The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like

reception of a byte or transmission of a START condition. Because the TWI is interrupt-based,

the application software is free to carry on other operations during a TWI byte transfer. Note that

the TWI Interrupt Enable (TWIE) bit in TWCR together with the Global Interrupt Enable bit in

SREG allow the application to decide whether or not assertion of the TWINT Flag should gener-

ate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT Flag in

order to detect actions on the TWI bus.

When the TWINT Flag is asserted, the TWI has finished an operation and awaits application

response. In this case, the TWI Status Register (TWSR) contains a value indicating the current

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state of the TWI bus. The application software can then decide how the TWI should behave in

the next TWI bus cycle by manipulating the TWCR and TWDR Registers.

Figure 20-11 is a simple example of how the application can interface to the TWI hardware. In

this example, a Master wishes to transmit a single data byte to a Slave. This description is quite

abstract, a more detailed explanation follows later in this section. A simple code example imple-

menting the desired behavior is also presented.

Figure 20-11. Interfacing the Application to the TWI in a Typical Transmission

3. Check TWSR to see if START was

sent. Application loads SLA+W into

TWDR, and loads appropriate control

signals into TWCR, makin sure that

TWINT is written to one,

5. Check TWSR to see if SLA+W was

sent and ACK received.

Application loads data into TWDR, and

loads appropriate control signals into

TWCR, making sure that TWINT is

written to one

1. Application

writes to TWCR to

initiate

transmission of

START

7. Check TWSR to see if data was sent

and ACK received.

Application loads appropriate control

signals to send STOP into TWCR,

making sure that TWINT is written to one

and TWSTA is written to zero.

TWI bus START

SLA+W

A

Data

A

STOP

Indicates

TWINT set

4. TWINT set.

Status code indicates

SLA+W sent, ACK

received

2. TWINT set.

Status code indicates

START condition sent

6. TWINT set.

Status code indicates

data sent, ACK received

1. The first step in a TWI transmission is to transmit a START condition. This is done by

writing a specific value into TWCR, instructing the TWI hardware to transmit a START

condition. Which value to write is described later on. However, it is important that the

TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI

will not start any operation as long as the TWINT bit in TWCR is set. Immediately after

the application has cleared TWINT, the TWI will initiate transmission of the START

condition.

2. When the START condition has been transmitted, the TWINT Flag in TWCR is set, and

TWSR is updated with a status code indicating that the START condition has success-

fully been sent.

3. The application software should now examine the value of TWSR, to make sure that

the START condition was successfully transmitted. If TWSR indicates otherwise, the

application software might take some special action, like calling an error routine.

Assuming that the status code is as expected, the application must load SLA+W into

TWDR. Remember that TWDR is used both for address and data. After TWDR has

been loaded with the desired SLA+W, a specific value must be written to TWCR,

instructing the TWI hardware to transmit the SLA+W present in TWDR. Which value to

write is described later on. However, it is important that the TWINT bit is set in the value

written. Writing a one to TWINT clears the flag. The TWI will not start any operation as

long as the TWINT bit in TWCR is set. Immediately after the application has cleared

TWINT, the TWI will initiate transmission of the address packet.

4. When the address packet has been transmitted, the TWINT Flag in TWCR is set, and

TWSR is updated with a status code indicating that the address packet has success-

fully been sent. The status code will also reflect whether a Slave acknowledged the

packet or not.

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5. The application software should now examine the value of TWSR, to make sure that

the address packet was successfully transmitted, and that the value of the ACK bit was

as expected. If TWSR indicates otherwise, the application software might take some

special action, like calling an error routine. Assuming that the status code is as

expected, the application must load a data packet into TWDR. Subsequently, a specific

value must be written to TWCR, instructing the TWI hardware to transmit the data

packet present in TWDR. Which value to write is described later on. However, it is

important that the TWINT bit is set in the value written. Writing a one to TWINT clears

the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set.

Immediately after the application has cleared TWINT, the TWI will initiate transmission

of the data packet.

6. When the data packet has been transmitted, the TWINT Flag in TWCR is set, and

TWSR is updated with a status code indicating that the data packet has successfully

been sent. The status code will also reflect whether a Slave acknowledged the packet

or not.

7. The application software should now examine the value of TWSR, to make sure that

the data packet was successfully transmitted, and that the value of the ACK bit was as

expected. If TWSR indicates otherwise, the application software might take some spe-

cial action, like calling an error routine. Assuming that the status code is as expected,

the application must write a specific value to TWCR, instructing the TWI hardware to

transmit a STOP condition. Which value to write is described later on. However, it is

important that the TWINT bit is set in the value written. Writing a one to TWINT clears

the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set.

Immediately after the application has cleared TWINT, the TWI will initiate transmission

of the STOP condition. Note that TWINT is NOT set after a STOP condition has been

sent.

Even though this example is simple, it shows the principles involved in all TWI transmissions.

These can be summarized as follows:

• When the TWI has finished an operation and expects application response, the TWINT Flag

is set. The SCL line is pulled low until TWINT is cleared.

• When the TWINT Flag is set, the user must update all TWI Registers with the value relevant

for the next TWI bus cycle. As an example, TWDR must be loaded with the value to be

transmitted in the next bus cycle.

• After all TWI Register updates and other pending application software tasks have been

completed, TWCR is written. When writing TWCR, the TWINT bit should be set. Writing a

one to TWINT clears the flag. The TWI will then commence executing whatever operation

was specified by the TWCR setting.

In the following an assembly and C implementation of the example is given. Note that the code

below assumes that several definitions have been made, for example by using include-files.

231

7593D–AVR–07/06

Table 2.

Assembly Code Example

C Example

TWCR = (1<<TWINT)|(1<<TWSTA)|

Comments

ldi r16,

(1<<TWINT)|(1<<TWSTA)|

(1<<TWEN)

1

2

Send START condition

(1<<TWEN)

out TWCR, r16

wait1:

while (!(TWCR & (1<<TWINT)))

Wait for TWINT Flag set. This

indicates that the START

condition has been transmitted

in

r16,TWCR

;

sbrs r16,TWINT

rjmp wait1

in

r16,TWSR

if ((TWSR & 0xF8) != START)

Check value of TWI Status

Register. Mask prescaler bits. If

status different from START go to

ERROR

andi r16, 0xF8

cpi r16, START

brne ERROR

ERROR();

3

4

5

ldi r16, SLA_W

out TWDR, r16

TWDR = SLA_W;

Load SLA_W into TWDR

Register. Clear TWINT bit in

TWCR to start transmission of

address

TWCR = (1<<TWINT) |

(1<<TWEN);

ldi r16, (1<<TWINT) |

(1<<TWEN)

out TWCR, r16

wait2:

while (!(TWCR & (1<<TWINT)))

Wait for TWINT Flag set. This

indicates that the SLA+W has

been transmitted, and

in

r16,TWCR

;

sbrs r16,TWINT

rjmp wait2

ACK/NACK has been received.

in

r16,TWSR

if ((TWSR & 0xF8) !=

MT_SLA_ACK)

Check value of TWI Status

Register. Mask prescaler bits. If

status different from

andi r16, 0xF8

cpi r16, MT_SLA_ACK

brne ERROR

ERROR();

MT_SLA_ACK go to ERROR

ldi r16, DATA

out TWDR, r16

TWDR = DATA;

TWCR = (1<<TWINT) |

(1<<TWEN);

Load DATA into TWDR Register.

Clear TWINT bit in TWCR to start

transmission of data

ldi r16, (1<<TWINT) |

(1<<TWEN)

out TWCR, r16

wait3:

while (!(TWCR & (1<<TWINT)))

Wait for TWINT Flag set. This

indicates that the DATA has been

transmitted, and ACK/NACK has

been received.

in

r16,TWCR

;

6

7

sbrs r16,TWINT

rjmp wait3

in

r16,TWSR

if ((TWSR & 0xF8) !=

MT_DATA_ACK)

Check value of TWI Status

Register. Mask prescaler bits. If

status different from

andi r16, 0xF8

cpi r16, MT_DATA_ACK

brne ERROR

ERROR();

MT_DATA_ACK go to ERROR

ldi r16,

(1<<TWINT)|(1<<TWEN)|

TWCR = (1<<TWINT)|(1<<TWEN)|

(1<<TWSTO);

Transmit STOP condition

(1<<TWSTO)

out TWCR, r16

232

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AT90USB64/128

20.8 Transmission Modes

The TWI can operate in one of four major modes. These are named Master Transmitter (MT),

Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these

modes can be used in the same application. As an example, the TWI can use MT mode to write

data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters

are present in the system, some of these might transmit data to the TWI, and then SR mode

would be used. It is the application software that decides which modes are legal.

The following sections describe each of these modes. Possible status codes are described

along with figures detailing data transmission in each of the modes. These figures contain the

following abbreviations:

S: START condition

Rs: REPEATED START condition

R: Read bit (high level at SDA)

W: Write bit (low level at SDA)

A: Acknowledge bit (low level at SDA)

A: Not acknowledge bit (high level at SDA)

Data: 8-bit data byte

P: STOP condition

SLA: Slave Address

In Figure 20-13 to Figure 20-19, circles are used to indicate that the TWINT Flag is set. The

numbers in the circles show the status code held in TWSR, with the prescaler bits masked to

zero. At these points, actions must be taken by the application to continue or complete the TWI

transfer. The TWI transfer is suspended until the TWINT Flag is cleared by software.

When the TWINT Flag is set, the status code in TWSR is used to determine the appropriate soft-

ware action. For each status code, the required software action and details of the following serial

transfer are given in Table 20-3 to Table 20-6. Note that the prescaler bits are masked to zero in

these tables.

20.8.1

Master Transmitter Mode

In the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver

(see Figure 20-12). In order to enter a Master mode, a START condition must be transmitted.

The format of the following address packet determines whether Master Transmitter or Master

Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is trans-

mitted, MR mode is entered. All the status codes mentioned in this section assume that the

prescaler bits are zero or are masked to zero.

233

7593D–AVR–07/06

Figure 20-12. Data Transfer in Master Transmitter Mode

V_CC

Device 1

MASTER

TRANSMITTER

Device 2

SLAVE

RECEIVER

Device 3

Device n

R1

R2

........

SDA

SCL

A START condition is sent by writing the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

1

0

X

1

0

X

TWEN must be set to enable the 2-wire Serial Interface, TWSTA must be written to one to trans-

mit a START condition and TWINT must be written to one to clear the TWINT Flag. The TWI will

then test the 2-wire Serial Bus and generate a START condition as soon as the bus becomes

free. After a START condition has been transmitted, the TWINT Flag is set by hardware, and the

status code in TWSR will be 0x08 (see Table 20-3). In order to enter MT mode, SLA+W must be

transmitted. This is done by writing SLA+W to TWDR. Thereafter the TWINT bit should be

cleared (by writing it to one) to continue the transfer. This is accomplished by writing the follow-

ing value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

0

X

1

0

X

When SLA+W have been transmitted and an acknowledgement bit has been received, TWINT is

set again and a number of status codes in TWSR are possible. Possible status codes in Master

mode are 0x18, 0x20, or 0x38. The appropriate action to be taken for each of these status codes

is detailed in Table 20-3.

When SLA+W has been successfully transmitted, a data packet should be transmitted. This is

done by writing the data byte to TWDR. TWDR must only be written when TWINT is high. If not,

the access will be discarded, and the Write Collision bit (TWWC) will be set in the TWCR Regis-

ter. After updating TWDR, the TWINT bit should be cleared (by writing it to one) to continue the

transfer. This is accomplished by writing the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

0

X

1

0

X

This scheme is repeated until the last byte has been sent and the transfer is ended by generat-

ing a STOP condition or a repeated START condition. A STOP condition is generated by writing

the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

0

1

X

1

0

X

A REPEATED START condition is generated by writing the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

1

0

X

1

0

X

234

AT90USB64/128

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AT90USB64/128

After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same

Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables

the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode with-

out losing control of the bus.

Table 20-3. Status codes for Master Transmitter Mode

Status Code

(TWSR)

Prescaler Bits

are 0

Application Software Response

To/from TWDR To TWCR

STO TWIN

Status of the 2-wire Serial Bus

and 2-wire Serial Interface

Hardware

STA

0

TWE

A

Next Action Taken by TWI Hardware

T

0x08

0x10

A START condition has been

transmitted

Load SLA+W

0

1

X

SLA+W will be transmitted;

ACK or NOT ACK will be received

A repeated START condition

has been transmitted

Load SLA+W or

Load SLA+R

0

1

X

SLA+W will be transmitted;

ACK or NOT ACK will be received

SLA+R will be transmitted;

Logic will switch to Master Receiver mode

0x18

0x20

0x28

0x30

0x38

SLA+W has been transmitted;

ACK has been received

Load data byte or

0

1

X

Data byte will be transmitted and ACK or NOT ACK will

be received

Repeated START will be transmitted

STOP condition will be transmitted and

TWSTO Flag will be reset

No TWDR action or

1

0

1

X

No TWDR action

Load data byte or

1

0

1

0

1

X

STOP condition followed by a START condition will be

transmitted and TWSTO Flag will be reset

SLA+W has been transmitted;

NOT ACK has been received

Data byte will be transmitted and ACK or NOT ACK will

be received

Repeated START will be transmitted

STOP condition will be transmitted and

TWSTO Flag will be reset

No TWDR action or

1

0

1

X

No TWDR action

Load data byte or

1

0

1

0

1

X

STOP condition followed by a START condition will be

transmitted and TWSTO Flag will be reset

Data byte has been transmit-

ted;

ACK has been received

Data byte will be transmitted and ACK or NOT ACK will

be received

Repeated START will be transmitted

STOP condition will be transmitted and

TWSTO Flag will be reset

No TWDR action or

1

0

1

X

No TWDR action

Load data byte or

1

0

1

0

1

X

STOP condition followed by a START condition will be

transmitted and TWSTO Flag will be reset

Data byte has been transmit-

ted;

NOT ACK has been received

Data byte will be transmitted and ACK or NOT ACK will

be received

Repeated START will be transmitted

STOP condition will be transmitted and

TWSTO Flag will be reset

No TWDR action or

1

0

1

X

No TWDR action

1

X

STOP condition followed by a START condition will be

transmitted and TWSTO Flag will be reset

Arbitration lost in SLA+W or

data bytes

No TWDR action or

No TWDR action

0

1

0

1

X

2-wire Serial Bus will be released and not addressed

Slave mode entered

A START condition will be transmitted when the bus

becomes free

235

7593D–AVR–07/06

Figure 20-13. Formats and States in the Master Transmitter Mode

MT

Successfull

S

SLA

W

A

DATA

A

P

transmission

to a slave

receiver

$08

$18

$28

Next transfer

started with a

repeated start

condition

R_S

SLA

W

R

$10

Not acknowledge

received after the

slave address

A

P

$20

MR

Not acknowledge

received after a data

byte

A

P

$30

Arbitration lost in slave

address or data byte

Other master

continues

Other master

continues

A or A

$38

A

$38

Arbitration lost and

addressed as slave

Other master

continues

To corresponding

states in slave mode

$68 $78 $B0

Any number of data bytes

and their associated acknowledge bits

From master to slave

From slave to master

DATA

A

This number (contained in TWSR) corresponds

to a defined state of the Two-Wire Serial Bus. The

prescaler bits are zero or masked to zero

n

20.8.2

Master Receiver Mode

In the Master Receiver mode, a number of data bytes are received from a Slave Transmitter

(Slave see Figure 20-14). In order to enter a Master mode, a START condition must be transmit-

ted. The format of the following address packet determines whether Master Transmitter or

Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R

is transmitted, MR mode is entered. All the status codes mentioned in this section assume that

the prescaler bits are zero or are masked to zero.

236

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

Figure 20-14. Data Transfer in Master Receiver Mode

V_CC

Device 1

MASTER

RECEIVER

Device 2

SLAVE

TRANSMITTER

Device 3

Device n

R1

R2

........

SDA

SCL

A START condition is sent by writing the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

1

0

X

1

0

X

TWEN must be written to one to enable the 2-wire Serial Interface, TWSTA must be written to

one to transmit a START condition and TWINT must be set to clear the TWINT Flag. The TWI

will then test the 2-wire Serial Bus and generate a START condition as soon as the bus

becomes free. After a START condition has been transmitted, the TWINT Flag is set by hard-

ware, and the status code in TWSR will be 0x08 (See Table 20-3). In order to enter MR mode,

SLA+R must be transmitted. This is done by writing SLA+R to TWDR. Thereafter the TWINT bit

should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing

the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

0

X

1

0

X

When SLA+R have been transmitted and an acknowledgement bit has been received, TWINT is

set again and a number of status codes in TWSR are possible. Possible status codes in Master

mode are 0x38, 0x40, or 0x48. The appropriate action to be taken for each of these status codes

is detailed in Table 20-4. Received data can be read from the TWDR Register when the TWINT

Flag is set high by hardware. This scheme is repeated until the last byte has been received.

After the last byte has been received, the MR should inform the ST by sending a NACK after the

last received data byte. The transfer is ended by generating a STOP condition or a repeated

START condition. A STOP condition is generated by writing the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

0

1

X

1

0

X

A REPEATED START condition is generated by writing the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

1

0

X

1

0

X

After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same

Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables

237

7593D–AVR–07/06

the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode with-

out losing control over the bus.

Table 20-4. Status codes for Master Receiver Mode

Status Code

(TWSR)

Prescaler Bits

are 0

Application Software Response

To TWCR

Status of the 2-wire Serial Bus

and 2-wire Serial Interface

Hardware

To/from TWDR

STA

STO

TWIN

T

TWE

A

Next Action Taken by TWI Hardware

0x08

0x10

A START condition has been

transmitted

Load SLA+R

0

1

X

SLA+R will be transmitted

ACK or NOT ACK will be received

A repeated START condition

has been transmitted

Load SLA+R or

Load SLA+W

0

1

X

SLA+R will be transmitted

ACK or NOT ACK will be received

SLA+W will be transmitted

Logic will switch to Master Transmitter mode

0x38

0x40

0x48

Arbitration lost in SLA+R or

NOT ACK bit

No TWDR action or

No TWDR action

0

1

0

1

X

2-wire Serial Bus will be released and not addressed

Slave mode will be entered

A START condition will be transmitted when the bus

becomes free

SLA+R has been transmitted;

ACK has been received

No TWDR action or

No TWDR action

0

1

0

1

Data byte will be received and NOT ACK will be

returned

Data byte will be received and ACK will be returned

SLA+R has been transmitted;

NOT ACK has been received

No TWDR action or

1

0

1

X

Repeated START will be transmitted

STOP condition will be transmitted and TWSTO Flag

will be reset

No TWDR action

1

X

STOP condition followed by a START condition will be

transmitted and TWSTO Flag will be reset

0x50

0x58

Data byte has been received;

ACK has been returned

Read data byte or

Read data byte

0

1

0

1

Data byte will be received and NOT ACK will be

returned

Data byte will be received and ACK will be returned

Data byte has been received;

NOT ACK has been returned

Read data byte or

1

0

1

X

Repeated START will be transmitted

STOP condition will be transmitted and TWSTO Flag

will be reset

Read data byte

1

X

STOP condition followed by a START condition will be

transmitted and TWSTO Flag will be reset

238

AT90USB64/128

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AT90USB64/128

Figure 20-15. Formats and States in the Master Receiver Mode

MR

Successfull

S

SLA

R

A

DATA

A

DATA

A

P

reception

from a slave

receiver

$08

$40

$50

$58

Next transfer

started with a

repeated start

condition

R_S

SLA

R

$10

Not acknowledge

received after the

slave address

W

A

P

$48

MT

Arbitration lost in slave

address or data byte

Other master

continues

Other master

continues

A or A

A

$38

A

$38

Arbitration lost and

addressed as slave

Other master

continues

To corresponding

states in slave mode

$68 $78 $B0

Any number of data bytes

and their associated acknowledge bits

From master to slave

From slave to master

DATA

A

This number (contained in TWSR) corresponds

to a defined state of the Two-Wire Serial Bus. The

prescaler bits are zero or masked to zero

n

20.8.3

Slave Receiver Mode

In the Slave Receiver mode, a number of data bytes are received from a Master Transmitter

(see Figure 20-16). All the status codes mentioned in this section assume that the prescaler bits

are zero or are masked to zero.

Figure 20-16. Data transfer in Slave Receiver mode

V_CC

Device 1

SLAVE

RECEIVER

Device 2

MASTER

TRANSMITTER

Device 3

Device n

R1

R2

........

SDA

SCL

To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows:

TWAR

TWA6

TWA5

TWA4

TWA3

TWA2

TWA1

TWA0

TWGCE

value

Device’s Own Slave Address

239

7593D–AVR–07/06

The upper 7 bits are the address to which the 2-wire Serial Interface will respond when

addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00),

otherwise it will ignore the general call address.

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

0

1

0

1

0

X

TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable

the acknowledgement of the device’s own slave address or the general call address. TWSTA

and TWSTO must be written to zero.

When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own

slave address (or the general call address if enabled) followed by the data direction bit. If the

direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST mode is entered. After

its own slave address and the write bit have been received, the TWINT Flag is set and a valid

status code can be read from TWSR. The status code is used to determine the appropriate soft-

ware action. The appropriate action to be taken for each status code is detailed in Table 20-5.

The Slave Receiver mode may also be entered if arbitration is lost while the TWI is in the Master

mode (see states 0x68 and 0x78).

If the TWEA bit is reset during a transfer, the TWI will return a “Not Acknowledge” (“1”) to SDA

after the next received data byte. This can be used to indicate that the Slave is not able to

receive any more bytes. While TWEA is zero, the TWI does not acknowledge its own slave

address. However, the 2-wire Serial Bus is still monitored and address recognition may resume

at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate

the TWI from the 2-wire Serial Bus.

In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA

bit is set, the interface can still acknowledge its own slave address or the general call address by

using the 2-wire Serial Bus clock as a clock source. The part will then wake up from sleep and

the TWI will hold the SCL clock low during the wake up and until the TWINT Flag is cleared (by

writing it to one). Further data reception will be carried out as normal, with the AVR clocks run-

ning as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be

held low for a long time, blocking other data transmissions.

Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the last byte present

on the bus when waking up from these Sleep modes.

240

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

Table 20-5. Status Codes for Slave Receiver Mode

Status Code

(TWSR)

Prescaler Bits

are 0

Application Software Response

To TWCR

STO TWIN

Status of the 2-wire Serial Bus

and 2-wire Serial Interface Hard-

ware

To/from TWDR

STA

X

TWE

A

Next Action Taken by TWI Hardware

T

0x60

0x68

0x70

0x78

Own SLA+W has been received;

ACK has been returned

No TWDR action or

0

1

0

Data byte will be received and NOT ACK will be

returned

No TWDR action

X

0

1

0

Data byte will be received and ACK will be returned

Arbitration lost in SLA+R/W as

Master; own SLA+W has been

received; ACK has been returned

No TWDR action or

Data byte will be received and NOT ACK will be

returned

No TWDR action

X

0

1

0

Data byte will be received and ACK will be returned

General call address has been

received; ACK has been returned

No TWDR action or

Data byte will be received and NOT ACK will be

returned

No TWDR action

X

0

1

0

Data byte will be received and ACK will be returned

Arbitration lost in SLA+R/W as

Master; General call address has

been received; ACK has been

returned

No TWDR action or

Data byte will be received and NOT ACK will be

returned

No TWDR action

Read data byte or

X

0

1

0

Data byte will be received and ACK will be returned

0x80

0x88

Previously addressed with own

SLA+W; data has been received;

ACK has been returned

Data byte will be received and NOT ACK will be

returned

Read data byte

X

0

1

0

Data byte will be received and ACK will be returned

Previously addressed with own

SLA+W; data has been received;

NOT ACK has been returned

Read data byte or

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitted when the bus

becomes free

Read data byte or

0

1

0

1

0

Read data byte

1

0

1

0

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitted when the bus

becomes free

0x90

0x98

Previously addressed with

general call; data has been re-

ceived; ACK has been returned

Read data byte or

X

Data byte will be received and NOT ACK will be

returned

Read data byte

X

0

1

0

Data byte will be received and ACK will be returned

Previously addressed with

general call; data has been

received; NOT ACK has been

returned

Read data byte or

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitted when the bus

becomes free

Read data byte or

0

1

0

1

0

Read data byte

No action

1

0

1

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitted when the bus

becomes free

0xA0

A STOP condition or repeated

START condition has been

received while still addressed as

Slave

0

1

0

1

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitted when the bus

becomes free

1

0

1

0

1

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitted when the bus

becomes free

241

7593D–AVR–07/06

Figure 20-17. Formats and States in the Slave Receiver Mode

Reception of the own

S

SLA

W

A

DATA

A

DATA

A

P or S

slave address and one or

more data bytes. All are

acknowledged

$60

$80

A

$A0

Last data byte received

is not acknowledged

P or S

$88

Arbitration lost as master

and addressed as slave

A

$68

A

Reception of the general call

address and one or more data

bytes

General Call

DATA

A

DATA

A

P or S

$70

$90

A

$A0

Last data byte received is

not acknowledged

P or S

$98

Arbitration lost as master and

addressed as slave by general call

A

$78

Any number of data bytes

and their associated acknowledge bits

From master to slave

From slave to master

DATA

A

This number (contained in TWSR) corresponds

to a defined state of the Two-Wire Serial Bus. The

prescaler bits are zero or masked to zero

n

20.8.4

Slave Transmitter Mode

In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver

(see Figure 20-18). All the status codes mentioned in this section assume that the prescaler bits

are zero or are masked to zero.

Figure 20-18. Data Transfer in Slave Transmitter Mode

V_CC

Device 1

SLAVE

TRANSMITTER

Device 2

MASTER

RECEIVER

Device 3

Device n

R1

R2

........

SDA

SCL

242

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AT90USB64/128

To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows:

TWAR

TWA6

TWA5

TWA4

TWA3

TWA2

TWA1

TWA0

TWGCE

value

Device’s Own Slave Address

The upper seven bits are the address to which the 2-wire Serial Interface will respond when

addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00),

otherwise it will ignore the general call address.

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

0

1

0

1

0

X

TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable

the acknowledgement of the device’s own slave address or the general call address. TWSTA

and TWSTO must be written to zero.

When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own

slave address (or the general call address if enabled) followed by the data direction bit. If the

direction bit is “1” (read), the TWI will operate in ST mode, otherwise SR mode is entered. After

its own slave address and the write bit have been received, the TWINT Flag is set and a valid

status code can be read from TWSR. The status code is used to determine the appropriate soft-

ware action. The appropriate action to be taken for each status code is detailed in Table 20-6.

The Slave Transmitter mode may also be entered if arbitration is lost while the TWI is in the

Master mode (see state 0xB0).

If the TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of the trans-

fer. State 0xC0 or state 0xC8 will be entered, depending on whether the Master Receiver

transmits a NACK or ACK after the final byte. The TWI is switched to the not addressed Slave

mode, and will ignore the Master if it continues the transfer. Thus the Master Receiver receives

all “1” as serial data. State 0xC8 is entered if the Master demands additional data bytes (by

transmitting ACK), even though the Slave has transmitted the last byte (TWEA zero and expect-

ing NACK from the Master).

While TWEA is zero, the TWI does not respond to its own slave address. However, the 2-wire

Serial Bus is still monitored and address recognition may resume at any time by setting TWEA.

This implies that the TWEA bit may be used to temporarily isolate the TWI from the 2-wire Serial

Bus.

In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA

bit is set, the interface can still acknowledge its own slave address or the general call address by

using the 2-wire Serial Bus clock as a clock source. The part will then wake up from sleep and

the TWI will hold the SCL clock will low during the wake up and until the TWINT Flag is cleared

(by writing it to one). Further data transmission will be carried out as normal, with the AVR clocks

running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may

be held low for a long time, blocking other data transmissions.

Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the last byte present

on the bus when waking up from these sleep modes.

Table 20-6. Status Codes for Slave Transmitter Mode

Status Code

(TWSR)

Prescaler

Bits

Application Software Response

To TWCR

Status of the 2-wire Serial Bus

and 2-wire Serial Interface Hard-

ware

To/from TWDR

STA

STO

TWIN

T

TWE

A

Next Action Taken by TWI Hardware

are 0

243

7593D–AVR–07/06

Table 20-6. Status Codes for Slave Transmitter Mode

0xA8

0xB0

0xB8

0xC0

Own SLA+R has been received;

ACK has been returned

Load data byte or

X

0

1

0

1

Last data byte will be transmitted and NOT ACK should

be received

Data byte will be transmitted and ACK should be re-

ceived

Load data byte

Arbitration lost in SLA+R/W as

Master; own SLA+R has been

received; ACK has been returned

Load data byte or

Load data byte

X

0

1

0

1

Last data byte will be transmitted and NOT ACK should

be received

Data byte will be transmitted and ACK should be re-

ceived

Data byte in TWDR has been

transmitted; ACK has been

received

Load data byte or

Load data byte

X

0

1

0

1

Last data byte will be transmitted and NOT ACK should

be received

Data byte will be transmitted and ACK should be re-

ceived

Data byte in TWDR has been

transmitted; NOT ACK has been

received

No TWDR action or

0

1

0

1

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitted when the bus

becomes free

No TWDR action or

No TWDR action

1

0

1

0

1

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitted when the bus

becomes free

0xC8

Last data byte in TWDR has been

transmitted (TWEA = “0”); ACK

has been received

No TWDR action or

0

1

0

1

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitted when the bus

becomes free

No TWDR action or

No TWDR action

1

0

1

0

1

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitted when the bus

becomes free

Figure 20-19. Formats and States in the Slave Transmitter Mode

Reception of the own

slave address and one or

more data bytes

S

SLA

R

A

DATA

A

DATA

A

P or S

$A8

A

$B8

$C0

Arbitration lost as master

and addressed as slave

$B0

Last data byte transmitted.

Switched to not addressed

slave (TWEA = '0')

A

All 1's

P or S

$C8

Any number of data bytes

and their associated acknowledge bits

From master to slave

From slave to master

DATA

A

This number (contained in TWSR) corresponds

to a defined state of the Two-Wire Serial Bus. The

prescaler bits are zero or masked to zero

n

20.8.5

244

Miscellaneous States

There are two status codes that do not correspond to a defined TWI state, see Table 20-7.

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

Status 0xF8 indicates that no relevant information is available because the TWINT Flag is not

set. This occurs between other states, and when the TWI is not involved in a serial transfer.

Status 0x00 indicates that a bus error has occurred during a 2-wire Serial Bus transfer. A bus

error occurs when a START or STOP condition occurs at an illegal position in the format frame.

Examples of such illegal positions are during the serial transfer of an address byte, a data byte,

or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the

TWSTO Flag must set and TWINT must be cleared by writing a logic one to it. This causes the

TWI to enter the not addressed Slave mode and to clear the TWSTO Flag (no other bits in

TWCR are affected). The SDA and SCL lines are released, and no STOP condition is

transmitted.

Table 20-7. Miscellaneous States

Status Code

(TWSR)

Prescaler Bits

are 0

Application Software Response

To TWCR

Status of the 2-wire Serial Bus

and 2-wire Serial Interface

Hardware

To/from TWDR

STA

STO

TWIN

T

TWE

A

Next Action Taken by TWI Hardware

Wait or proceed current transfer

0xF8

0x00

No relevant state information

available; TWINT = “0”

No TWDR action

No TWCR action

Bus error due to an illegal

START or STOP condition

0

1

X

Only the internal hardware is affected, no STOP condi-

tion is sent on the bus. In all cases, the bus is released

and TWSTO is cleared.

20.8.6

Combining Several TWI Modes

In some cases, several TWI modes must be combined in order to complete the desired action.

Consider for example reading data from a serial EEPROM. Typically, such a transfer involves

the following steps:

1. The transfer must be initiated.

2. The EEPROM must be instructed what location should be read.

3. The reading must be performed.

4. The transfer must be finished.

Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct

the Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data

must be read from the Slave, implying the use of the MR mode. Thus, the transfer direction must

be changed. The Master must keep control of the bus during all these steps, and the steps

should be carried out as an atomical operation. If this principle is violated in a multimaster sys-

tem, another Master can alter the data pointer in the EEPROM between steps 2 and 3, and the

Master will read the wrong data location. Such a change in transfer direction is accomplished by

transmitting a REPEATED START between the transmission of the address byte and reception

of the data. After a REPEATED START, the Master keeps ownership of the bus. The following

figure shows the flow in this transfer.

Figure 20-20. Combining Several TWI Modes to Access a Serial EEPROM

Master Transmitter

Master Receiver

S

SLA+W

A

ADDRESS

A

Rs

SLA+R

A

DATA

A

P

S = START

Transmitted from master to slave

Rs = REPEATED START

Transmitted from slave to master

P = STOP

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20.9 Multi-master Systems and Arbitration

If multiple masters are connected to the same bus, transmissions may be initiated simulta-

neously by one or more of them. The TWI standard ensures that such situations are handled in

such a way that one of the masters will be allowed to proceed with the transfer, and that no data

will be lost in the process. An example of an arbitration situation is depicted below, where two

masters are trying to transmit data to a Slave Receiver.

Figure 20-21. An Arbitration Example

V_CC

Device 1

MASTER

TRANSMITTER

Device 3

SLAVE

RECEIVER

Device 2

MASTER

TRANSMITTER

Device n

R1

R2

........

SDA

SCL

Several different scenarios may arise during arbitration, as described below:

• Two or more masters are performing identical communication with the same Slave. In this

case, neither the Slave nor any of the masters will know about the bus contention.

• Two or more masters are accessing the same Slave with different data or direction bit. In this

case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters

trying to output a one on SDA while another Master outputs a zero will lose the arbitration.

Losing masters will switch to not addressed Slave mode or wait until the bus is free and

transmit a new START condition, depending on application software action.

• Two or more masters are accessing different slaves. In this case, arbitration will occur in the

SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose

the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are

being addressed by the winning Master. If addressed, they will switch to SR or ST mode,

depending on the value of the READ/WRITE bit. If they are not being addressed, they will

switch to not addressed Slave mode or wait until the bus is free and transmit a new START

condition, depending on application software action.

This is summarized in Figure 20-22. Possible status values are given in circles.

246

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AT90USB64/128

Figure 20-22. Possible Status Codes Caused by Arbitration

START

SLA

Data

STOP

Arbitration lost in SLA

Arbitration lost in Data

Own

No

38

TWI bus will be released and not addressed slave mode will be entered

A START condition will be transmitted when the bus becomes free

Address / General Call

received

Yes

Write

68/78

B0

Data byte will be received and NOT ACK will be returned

Data byte will be received and ACK will be returned

Direction

Read

Last data byte will be transmitted and NOT ACK should be received

Data byte will be transmitted and ACK should be received

247

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21. USB controller

21.1 Features

• Support full-speed and low-speed.

• Support ping-pong mode (dual bank)

• 832 bytes of DPRAM.

• 1 endpoint 64 bytes max (default control endpoint),

• 1 endpoints of 256 bytes max, (one or two banks),

• 5 endpoints of 64 bytes max, (one or two banks)

21.2 Block Diagram

The USB controller provides the hardware to interface a USB link to a data flow stored in a dou-

ble port memory (DPRAM).

The USB controller requires a 48 MHz ±0.25% reference clock, which is the output of an internal

PLL. The PLL generates the internal high frequency (48 MHz) clock for USB interface, the PLL

input is generated from an external low-frequency (the crystal oscillator or external clock input

pin from XTAL1, to satisfy the USB frequency accuracy and jitter, only these sources clock allow

proper functionnality of the USB controller).

The 48MHz clock is used to generate a 12 MHz Full-speed (or 1.5 MHz Low-Speed bit clock

from the received USB differential data and to transmit data according to full or low speed USB

device tolerance. Clock recovery is done by a Digital Phase Locked Loop (DPLL) block, which is

compliant with the jitter specification of the USB bus.

To comply the USB DC characteristics, USB Pads (D+ or D-) should be powered within the 3.0

to 3.6V range. As AT90USB64/128 can be powered up to 5.5V, an internal regulator can insure

the USB pads power supply.

248

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AT90USB64/128

Figure 21-1. USB controller Block Diagram overview

UVCC

AVCC

XTAL1

clk

2MHz

PLL

24x

PLL clock

Prescaler

USB Regulator

UCAP

clk

48MHz

CPU

D-

DPLL

Clock

Recovery

D+

USB

Interface

VBUS

On-Chip

USB DPRAM

UID

21.3 Typical Application Implementation

Depending on the USB operating mode (Device only, Reduced Host or OTG mode) and target

application power supply, the AT90USB64/128 requires different hardware typical

implementations.

Figure 21-2. Operating modes versus frequency and power-supply

VCC (V)

Internal Regulator

Max

Functionnal operation

Operating Frequency (MHz)

5.5

4.5

16 MHz

USB operationnal

with internal regulator

Normal operation

3.6

3.4

8 MHz

USB operationnal

internal regulator not needed

3.0

2.7

Extra power consumption

USB not operationnal

2 MHz

VCC min

0

249

7593D–AVR–07/06

21.3.1

Device mode

21.3.1.1

Bus Powered device

Figure 21-3. Typical Bus powered application with 5V I/O

UVCC

AVCC

VCC

UCAP

1µF

VBUS

UDP

UDM

UVSS

UID

VBUS

D+

Rs=22

D-

UVSS

UID

XTAL1

XTAL2

AVSS

DVSS

Figure 21-4. Typical Bus powered application with 3V I/O

External

3V Regulator

UVCC

AVCC

VCC

UCAP

1µF

VBUS

UDP

UDM

UVSS

UID

VBUS

D+

Rs=22

D-

UVSS

UID

XTAL1

XTAL2

AVSS

DVSS

250

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

21.3.1.2

Self Powered device

Figure 21-5. Typical Self powered application with 3.4V to 5.5V I/O

External 3.4V - 5.5V

Power Supply

UVCC

AVCC

VCC

UCAP

1µF

VBUS

UDP

UDM

UVSS

UID

VBUS

D+

Rs=22

D-

UVSS

UID

XTAL1

XTAL2

AVSS

DVSS

Figure 21-6. Typical Self powered application with 3.0V to 3.4 I/O

External 3.0V - 3.4V

Power Supply

UVCC

AVCC

VCC

UCAP

1µF

VBUS

UDP

UDM

UVSS

UID

VBUS

D+

Rs=22

D-

UVSS

UID

XTAL1

XTAL2

AVSS

DVSS

251

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21.3.2

Host / OTG mode

Figure 21-7. Host/OTG powered application with 3.0V to 3.4 I/O

External 3.0V - 3.4V

Power Supply

UVCC

AVCC

VCC

5V

5V DC/DC

generator

UCAP

1µF

UVCON

VBUS

UDM

UDP

UVSS

UID

VBUS

D+

Rs=22

D-

UVSS

UID

XTAL1

XTAL2

AVSS

DVSS

Figure 21-8. Host/OTG powered application with 5V I/O

External 5.0V

Power Supply

5V

UVCC

AVCC

VCC

UCAP

1µF

UVCON

VBUS

UDP

UDM

UVSS

UID

VBUS

D+

Rs=22

D-

UVSS

UID

XTAL1

XTAL2

AVSS

DVSS

252

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

21.4 General Operating Modes

21.4.1

Introduction

After a hardware reset, the USB controller is disabled. When enabled, the USB controller has to

run the Device Controller or the Host Controller. This is performed using the ID detection.

• If the ID pin is not connected to ground, the ID bit is set by hardware (internal pull up on the

UID pad) and the USB Device controller is selected.

• The ID bit is cleared by hardware when a low level has been detected on the ID pin. The

Device controller is then disabled and the Host controller enabled.

The software anyway has to select the mode (Host, Device) in order to access to the Device

controller registers or to the Host controller registers, which are multiplexed. For example, even

if the USB controller has detected a Device mode (pin ID high), the software shall select the

device mode (bit HOST cleared), otherwise it will access to the host registers. This is also true

for the Host mode.

21.4.2

Power-on and reset

The next diagram explains the USB controller main states on power-on:

Figure 21-9. USB controller states after reset

Clockstopped

FRZCLK=1

Mac rooff

<anyother

state>

USBE=0

Reset

HW

RESET

USBE=1

ID=1

USBE=0

USBE=1

ID=0

USBE=0

Device

Host

USB Controller state after an hardware reset is ‘Reset’. In this state:

• USBE is not set

• the macro clock is stopped in order to minimize the power consumption (FRZCLK=1),

• the macro is disabled,

• the pad is in the suspend mode,

• the Host and Device USB controllers internal states are reset.

• The DPACC bit and the DPADD10:0 field can be set by software. The DPRAM is not cleared.

• The SPDCONF bits can be set by software.

After setting USBE, the USB Controller enters in the Host or in the Device state (according to the

IP pin). The selected controller is ‘Idle’.

The USB Controller can at any time be ‘stopped’ by clearing USBE. In fact, clearing USBE acts

as an hardware reset.

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7593D–AVR–07/06

21.4.3

Interrupts

Two interrupts vectors are assigned to USB interface.

Figure 21-10. USB Interrupt System

USB General

& OTG Interrupt

USB General

Interrupt Vector

USB Device

Interrupt

USB Host

Interrupt

Endpoint

Interrupt

USB Endpoint/Pipe

Interrupt Vector

Pipe

Interrupt

See Section 22.18, page 279 and Section 23.15, page 299 for more details on the Host and

Device interrupts.

254

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

Figure 21-11. USB General interrupt vector sources

IDTI

USBINT.1

IDTE

USBCON.1

VBUSTI

USBINT.0

VBUSTE

USBCON.0

STOI

OTGINT.5

STOE

OTGIEN.5

HNPERRI

OTGINT.4

HNPERRE

USB General

Interrupt Vector

OTGIEN.4

ROLEEXI

OTGINT.3

ROLEEXE

OTGIEN.3

BCERRI

OTGINT.2

BCERRE

OTGIEN.2

VBERRI

OTGINT.1

VBERRE

OTGIEN.1

SRPI

OTGINT.0

SRPE

OTGIEN.0

UPRSMI

UDINT.6

UPRSME

UDIEN.6

EORSMI

UDINT.5

EORSME

UDIEN.5

WAKEUPI

UDINT.4

USB General

Interrupt Vector

WAKEUPE

UDIEN.4

USB Device

Interrupt

EORSTI

UDINT.3

EORSTE

UDIEN.3

SOFI

UDINT.2

SOFE

UDIEN.2

SUSPI

UDINT.0

SUSPE

UDIEN.0

HWUPI

UHINT.6

HWUPE

UHIEN.6

HSOFI

UHINT.5

HSOFE

UHIEN.5

RXRSMI

UHINT.4

RXRSME

UHIEN.4

USB Host

Interrupt

RSMEDI

UHINT.3

RSMEDE

UHIEN.3

RSTI

UHINT.2

RSTE

UHIEN.2

DDISCI

UHINT.1

DDISCE

UHIEN.1

Asynchronous Interrupt source

(allows the CPU to wake up from power down mode)

DCONNI

UHINT.0

DCONNE

UHIEN.0

255

7593D–AVR–07/06

Figure 21-12. USB Endpoint/Pipe Interrupt vector sources

Endpoint 6

Endpoint 5

Endpoint 4

Endpoint 3

Endpoint 2

Endpoint 1

Endpoint 0

OVERFI

UESTAX.6

UNDERFI

UESTAX.5

FLERRE

UEIENX.7

NAKINI

UEINTX.6

NAKINE

UEIENX.6

NAKOUTI

UEINTX.4

TXSTPE

Endpoint Interrupt

UEIENX.4

RXSTPI

EPINT

UEINTX.3

UEINT.X

TXOUTE

UEIENX.3

RXOUTI

UEINTX.2

RXOUTE

UEIENX.2

STALLEDI

UEINTX.1

STALLEDE

UEIENX.1

TXINI

UEINTX.0

TXINE

UEIENX.0

USB Endpoint/P

Interrupt Vecto

PIPE 6

PIPE 5

PIPE 4

PIPE 3

PIPE 2

PIPE 1

PIPE 0

OVERFI

UPSTAX.6

UNDERFI

UPSTAX.5

FLERRE

UPIEN.7

NAKEDI

UPINTX.6

NAKEDE

UPIEN.6

PERRI

UPINTX.4

PERRE

UPIEN.4

Pipe Interrupt

TXSTPI

FLERRE

UPIEN.7

UPINTX.3

TXSTPE

UPIEN.3

TXOUTI

UPINTX.2

TXOUTE

UPIEN.2

RXSTALLI

UPINTX.1

RXSTALLE

UPIEN.1

RXINI

UPINTX.0

RXINE

UPIEN.0

256

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AT90USB64/128

Figure 21-13. USB General and OTG Controller Interrupt System

IDTI

USBINT.1

IDTE

USBCON.1

VBUSTI

USBINT.0

VBUSTE

USBCON.0

STOI

OTGINT.5

STOE

OTGIEN.5

HNPERRI

OTGINT.4

HNPERRE

USB General & OTG

Interrupt Vector

OTGIEN.4

ROLEEXI

OTGINT.3

ROLEEXE

OTGIEN.3

BCERRI

OTGINT.2

BCERRE

OTGIEN.2

VBERRI

OTGINT.1

VBERRE

Asynchronous Interrupt source

(allows the CPU to wake up from power down mode)

OTGIEN.1

SRPI

OTGINT.0

SRPE

OTGIEN.0

There are 2 kind of interrupts: processing (i.e. their generation are part of the normal processing)

and exception (errors).

Processing interrupts are generated when:

• ID Pad detection (insert, remove)(IDTI)

• VBUS plug-in detection (insert, remove) (VBUSTI)

• SRP detected(SRPI)

• Role Exchanged(ROLEEXI)

Exception Interrupts are generated when:

• Drop on VBus Detected(VBERRI)

• Error during the B-Connection(BCERRI)

• HNP Error(HNPERRI)

• Time-out detected during Suspend mode(STOII)

21.5 Power modes

21.5.1

Idle mode

In this mode, the CPU core is halted (CPU clock stopped). The Idle mode is taken whatever the

USB controller is running or not. The CPU “wakes up” on any USB interrupts.

21.5.2

Power down

In this mode, the oscillator is stopped and halts all the product (CPU and peripherals). The CPU

“wakes up” when:

• the WAKEUPI interrupt is triggered in the Peripheral mode (HOST cleared),

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7593D–AVR–07/06

• the HWUPI interrupt is triggered in the Host mode (HOST set).

• the IDTI interrupt is triggered

• the VBUSTI interrupt is triggered

21.5.3

Freeze clock

The firmware has the ability to reduce the power consumption by setting the FRZCLK bit, which

freeze the clock of USB controller. When FRZCLK is set, it is still possible to access to the fol-

lowing registers:

• USBCON, USBSTA, USBINT

• DPRAM direct access (DPADD10:0, UxDATX)

• UDCON (detach, ...)

• UDINT

• UDIEN

• UHCON

• UHINT

• UHIEN

Moreover, when FRZCLK is set, only the following interrupts may be triggered:

• WAKEUPI

• IDTI

• VBUSTI

• HWUPI

21.6 Speed Control

21.6.1

Device mode

When the USB interface is configured in device mode, the speed selection (Full Speed or Low

Speed) depends on the UDP/UDM pull-up. UDSS register allows to select an internal pull up on

UDM (Low Speed mode) or UDP(Full Speed mode) data lines. UDSS should be configure

before attaching the device.

Figure 21-14. Device mode Speed Selection

USB

Regulator

UCAP

DETACH

UDCON.0

LSM

UDCON.2

UDP

UDM

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21.6.2

Host mode

When the USB interface is configured in device mode, internal Pull Down resistors are activated

on both UDP UDM lines and the interface detects the type of device connected.

21.7 Memory management

The controller does only support the following memory allocation management:

The reservation of a Pipe or an Endpoint can only be made in the growing order (Pipe/Endpoint

0 to the last Pipe/Endpoint). The firmware shall thus configure them in the same order.

The reservation of a Pipe or an Endpoint “kⁱ” is done when its ALLOC bit is set. Then, the hard-

ware allocates the memory and insert it between the Pipe/Endpoints “k^i-1” and “kⁱ⁺¹”. The “kⁱ⁺¹

”

Pipe/Endpoint memory “slides” up and its data is lost. Note that the “kⁱ⁺²” and upper Pipe/End-

point memory does not slide.

Clearing a Pipe enable (PEN) or an Endpoint enable (EPEN) does not clear neither its ALLOC

bit, nor its configuration (EPSIZE/PSIZE, EPBK/PBK). To free its memory, the firmware should

clear ALLOC. Then, the “kⁱ⁺¹” Pipe/Endpoint memory automatically “slides” down. Note that the

“kⁱ⁺²” and upper Pipe/Endpoint memory does not slide.

The following figure illustrates the allocation and reorganization of the USB memory in a typical

example:

Table 21-1. Allocation and reorganization USB memory flow

Free memory

5

Free memory

5

Free memory

5

4

5

4

Conflict

4

3

Lost memory

4

EPEN=0

(ALLOC=1)

3 (bigger size)

2

1

0

1

0

1

0

1

0

EPEN=1

ALLOC=1

Pipe/Endpoints

activation

Pipe/Endpoint

Disable

Free its memory

(ALLOC=0)

Pipe/Endpoint

Activatation

• First, Pipe/Endpoint 0 to Pipe/Endpoint 5 are configured, in the growing order. The memory of

each is reserved in the DPRAM.

• Then, the Pipe/Endpoint 3 is disabled (EPEN=0), but its memory reservation is internally kept

by the controller.

• Its ALLOC bit is cleared: the Pipe/Endpoint 4 “slides” down, but the Pipe/Endpoint 5 does not

“slide”.

• Finally, if the firmware chooses to reconfigure the Pipe/Endpoint 3, with a bigger size. The

controller reserved the memory after the endpoint 2 memory and automatically “slide” the

Pipe/Endpoint 4. The Pipe/Endpoint 5 does not move and a memory conflict appear, in that

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both Pipe/Endpoint 4 and 5 use a common area. The data of those endpoints are potentially

lost.

Note that:

• the data of Pipe/Endpoint 0 are never lost whatever the activation or deactivation of the

higher Pipe/Endpoint. Its data is lost if it is deactivated.

• Deactivate and reactivate the same Pipe/Endpoint with the same parameters does not lead

to a “slide” of the higher endpoints. For those endpoints, the data are preserved.

• CFGOK is set by hardware even in the case that there is a “conflict” in the memory allocation.

21.8 PAD suspend

The next figures illustrates the pad behaviour:

• In the “idle” mode, the pad is put in low power consumption mode.

• In the “active” mode, the pad is working.

Figure 21-15. Pad behaviour

USBE=1

& DETACH=0

& suspend

Idle mode

USBE=0

| DETACH=1

| suspend

Active mode

The SUSPI flag indicated that a suspend state has been detected on the USB bus. This flag

automatically put the USB pad in Idle. The detection of a non-idle event sets the WAKEUPI flag

and wakes-up the USB pad.

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Suspend detected = USB pad power down

Clear Suspend by software

SUSPI

WAKEUPI

PAD status

Clear Resume by software

Resume = USB pad wake-up

Power Down

Active

Moreover, the pad can also be put in the “idle” mode if the DETACH bit is set. It come back in

the active mode when the DETACH bit is cleared.

21.9 OTG timers customizing

It is possible to refine some OTG timers thanks to the OTGTCON and OTGCON registers

• PAGE=00b: AWaitVrise time-out. [OTG] chapter 6.6.5.1

• VALUE=00bTime-out is set to 20 ms

• VALUE=01bTime-out is set to 50 ms

• VALUE=10bTime-out is set to 70ms

• VALUE=11bTime-out is set to 100 ms

• PAGE=01b: VbBusPulsing. [OTG] chapter 5.3.4

• VALUE=00bTime-out is set to 15 ms

• VALUE=01bTime-out is set to 23 ms

• VALUE=10bTime-out is set to 31 ms

• VALUE=11bTime-out is set to 40 ms

• PAGE=10b: PdTmOutCnt. [OTG] chapter 5.3.2

• VALUE=00bTime-out is set to 93 ms

• VALUE=01bTime-out is set to 105 ms

• VALUE=10bTime-out is set to 118 ms

• VALUE=11bTime-out is set to 131 ms

• PAGE=11b: SRPDetTmOut. [OTG] chapter 5.3.3

• VALUE=00bTime-out is set to 10 us

• VALUE=01bTime-out is set to 100 us

• VALUE=10bTime-out is set to 1 ms

• VALUE=11bTime-out is set to 11 ms

21.10 Plug-in detection

The USB connection is detected by the VBUS pad, thanks to the following architecture:

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Figure 21-16. Plug-in Detection Input Block Diagram

VDD

VBus_pulsing

Session_valid

UVBUS

Logic

VBUS

USBSTA.0

VBUSTI

USBINT.0

Va_Vbus_valid

VBus_discharge

VSS

Pad logic

The control logic of the UVBUS pad outputs 2 signals:

• The “session_valid” signal is active high when the voltage on the UVBUS pad is higher or

equal to 1.4V.

• The “Va_Vbus_valid” signal is active high when the voltage on the UVBUS pad is higher or

equal to 4.4V.

In the Host mode, the VBUS flag follows the next hysteresis rule:

• VBUS is set when the voltage on the UVBUS pad is higher or equal to 4.4 V.

• VBUS is cleared when the voltage on the UVBUS pad is lower than 1.4 V.

In the Peripheral mode, the VBUS flag follows the next rule:

• VBUS is set when the voltage on the UVBUS pad is higher or equal to 1.4 V.

• VBUS is cleared when the voltage on the UVBUS pad is lower than 1.4 V.

The VBUSTI interrupt is triggered at each transition of the VBUS flag.

21.11 ID detection

The ID pin transition is detected thanks to the following architecture:

Figure 21-17. ID Detection Input Block Diagram

VDD

Internal Pull Up

1

UID

ID

USBSTA.1

0

UIMOD

UHWCON.7

UIDE

UHWCON.6

The ID pin can be used to detect the USB mode (Peripheral or Host) or software selected. This

allows the UID pin to be used has general purpose I/O even when USB interface is enable.

When the UID pin is selected, by default, (no A-plug or B-plug), the macro is in the Peripheral

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mode (internal pull-up). The IDTI interrupt is triggered when a A-plug (Host) is plugged or

unplugged. The interrupt is not triggered when a B-plug (Periph) is plugged or unplugged.

ID detection is independant of USB global interface enable.

21.12 Registers description

21.12.1 USB general registers

Bit

7

UIMOD

R/W

1

6

UIDE

R/W

0

5

4

UVCONE

R/W

3

2

1

0

UVREGE

R/W

UHWCON

Read/Write

Initial Value

R

0

R

0

R

0

R

0

• 7 – UIMOD: USB Mode Bit

This bit has no effect when the UIDE bit is set (external UID pin activated). Set to enable the

USB device mode. Clear to enable the USB host mode

• 6 – UIDE: UID pin Enable

Set to enable the USB mode selection (peripheral/host) through the UID pin. Clear to enable the

USB mode selection (peripheral/host) with UIMOD bit register.

UIDE should be modified only when the USB interface is disabled (USBE bit cleared).

• 5 – Reserved

The value read from this bit is always 0. Do not set this bit.

• 4 – UVCONE: UVCON pin Enable

Set to enable the UVCON pin control. Clear to disable the UVCON pin control. This bit should be

set only when the USB interface is enable.

• 3-1 – Reserved

The value read from these bits is always 0. Do not set these bits.

• 0 – UVREGE: USB pad regulator Enable

Set to enable the USB pad regulator. Clear to disable the USB pad regulator.

Bit

7

USBE

R/W

0

6

HOST

R/W

0

5

FRZCLK

R/W

4

OTGPADE

R/W

3

-

2

-

1

IDTE

R/W

0

VBUSTE

R/W

USBCON

Read/Write

Initial Value

R

0

R

0

1

0

• 7 – USBE: USB macro Enable Bit

Set to enable the USB controller. Clear to disable and reset the USB controller, to disable the

USB transceiver and to disable the USB controller clock inputs.

• 6 – HOST: HOST Bit

Set to enable the Host mode. Clear to enable the device mode.

• 5 – FRZCLK: Freeze USB Clock Bit

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Set to disable the clock inputs (the ”Resume Detection” is still active). This reduces the power

consumption. Clear to enable the clock inputs.

• 4 – OTGPADE: OTG Pad Enable

Set to enable the OTG pad. Clear to disable the OTG pad.

Note that this bit can be set/cleared even if USBE=0 (this allows the VBUS detection even if the

USB macro is disable).

• 3-2 – Reserved

The value read from these bits is always 0. Do not set these bits.

• 1 – IDTE: ID Transition Interrupt Enable Bit

Set this bit to enable the ID Transition interrupt generation. Clear this bit to disable the ID Transi-

tion interrupt generation.

• 0 – VBUSTE: VBUS Transition Interrupt Enable Bit

Set this bit to enable the VBUS Transition interrupt generation.

Clear this bit to disable the VBUS Transition interrupt generation.

Bit

7

-

6

-

5

-

4

-

3

2

1

ID

R

1

0

VBUS

R

SPEED

USBSTA

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

1

R

0

• 7-4 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 3 – SPEED: Speed Status Flag

This should be read only when the USB controller operates in host mode, in device mode the

value read from this bit is underterminate.

Set by hardware when the controller is in FULL-SPEED mode. Cleared by hardware when the

controller is in LOW-SPEED mode.

• 2 – Reserved

The value read from this bit is always 0. Do not set this bit.

• 1 – ID: IUD pin Flag

The value read from this bit indicates the state of the UID pin.

• 0 – VBUS: VBus Flag

The value read from this bit indicates the state of the UVBUS pin. This bit can be used in device

mode to monitor the USB bus connection state of the appication. See Section 21.10, page 261

for more details.

Bit

7

-

6

-

5

-

4

-

3

-

2

-

1

0

IDTI

R/W

VBUSTI

R/W

USBINT

Read/Write

R

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Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Initial Value

7-2 - Reserved

The value read from these bits is always 0. Do not set these bits.

1 – IDTI: D Transition Interrupt Flag

Set by hardware when a transition (high to low, low to high) has been detected on the UID pin.

Shall be cleared by software.

• 0 – VBUSTI: IVBUS Transition Interrupt Flag

Set by hardware when a transition (high to low, low to high) has been detected on the VBUS

pad.

Shall be cleared by software.

Bit

7

-

6

-

5

HNPREQ

R/W

4

SRPREQ

R/W

3

SRPSEL

R/W

2

VBUSHWC

R/W

1

VBUSREQ

R/W

0

VBUSRQC

R/W

OTGCON

Read/Write

Initial Value

R

0

R

0

• 7-6 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 5 – HNPREQ: HNP Request Bit

Set to initiate the HNP when the controller is in the Device mode (B). Set to accept the HNP

when the controller is in the Host mode (A).

Clear otherwise.

• 4 – SRPREQ: SRP Request Bit

Set to initiate the SRP when the controller is in Device mode. Cleared by hardware when the

controller is initiating a SRP.

• 3 – SRPSEL: SRP Selection Bit

Set to choose VBUS pulsing as SRP method.

Clear to choose data line pulsing as SRP method.

• 2 – VBUSHWC: VBus Hardware Control Bit

Set to disable the hardware control over the UVCON pin.

Clear to enable the hardware control over the UVCON pin.

See for more details

• 1 – VBUSREQ: VBUS Request Bit

Set to assert the UVCON pin in order to enable the VBUS power supply generation. This bit

shall be used when the controller is in the Host mode.

Cleared by hardware when VBUSRQC is set.

• 0 – VBUSRQC: VBUS Request Clear Bit

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Set to deassert the UVCON pin in order to enable the VBUS power supply generation. This bit

shall be used when the controller is in the Host mode.

Cleared by hardware immediately after the set.

Bit

7

1

6

5

4

-

3

-

2

1

VALUE

R/W

0

PAGE

OTGTCON

Read/Write

Initial Value

R

1

R/W

0

R/W

0

R

0

R

0

R/W

0

R/W

0

• 7 – Reserved

This bit is reserved and always set.

• 6-5 – PAGE: Timer page access Bit

Set/clear to access a special timer register. See Section 21.9, page 261 for more details.

• 4-3 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 2-0 – VALUE: Value Bit

Set to initialize the new value of the timer. See Section 21.9, page 261 for more details.

Bit

7

-

6

-

5

STOE

R/W

0

4

HNPERRE

R/W

3

ROLEEXE

R/W

2

BCERRE

R/W

1

VBERRE

R/W

0

SRPE

R/W

0

OTGIEN

Read/Write

Initial Value

R

0

R

0

• 7-6 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 5 – STOE: Suspend Time-out Error Interrupt Enable Bit

Set to enable the STOI interrupt. Clear to disable the STOI interrupt.

• 4 – HNPERRE: HNP Error Interrupt Enable Bit

Set to enable the HNPERRI interrupt. Clear to disable the HNPERRI interrupt.

• 3 – ROLEEXE: Role Exchange Interrupt Enable Bit

Set to enable the ROLEEXI interrupt. Clear to disable the ROLEEXI interrupt.

• 2 – BCERRE: B-Connection Error Interrupt Enable Bit

Set to enable the BCERRI interrupt. Clear to disable the BCERRI interrupt.

• 1 – VBERRE: VBus Error Interrupt Enable Bit

Set to enable the VBERRI interrupt. Clear to disable the VBERRI interrupt.

• 0 – SRPE: SRP Interrupt Enable Bit

Set to enable the SRPI interrupt. Clear to disable the SRPI interrupt.

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Bit

7

-

6

-

5

STOI

R/W

0

4

HNPERRI

R/W

3

ROLEEXI

R/W

2

BCERRI

R/W

0

1

VBERRI

R/W

0

SRPI

R/W

0

OTGINT

Read/Write

Initial Value

R

0

R

0

• 7-6 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 5 – STOI: Suspend Time-out Error Interrupt Flag

Set by hardware when a time-out error (more than 150 ms) has been detected after a suspend.

Shall be cleared by software. See for more details.

• 4 – HNPERRI: HNP Error Interrupt Flag

Set by hardware when an error has been detected during the protocol.

Shall be cleared by software. See for more details.

• 3 – ROLEEXI: Role Exchange Interrupt Flag

Set by hardware when the USB controller has successfully swapped its mode, due to an HNP

negotiation: Host to Device or Device to Host. Shall be cleared by software. See for more

details.

• 2 – BCERRI: B-Connection Error Interrupt Flag

Set by hardware when an error occur during the B-Connection. Shall be cleared by software.

• 1 – VBERRI: V-Bus Error Interrupt Flag

Set by hardware when a drop on VBus has been detected. Shall be cleared by software.

• 0 – SRPI: SRP Interrupt Flag

Set by hardware when a SRP has been detected. Shall be used in the Host mode only Shall be

cleared by software.

21.13 USB Software Operating modes

Depending on the USB operating mode, the software should perform some the following

operations:

Power On the USB interface

• Power-On USB pads regulator

• Wait USB pads regulator ready state

• Configure PLL interface

• Enable PLL

• Check PLL lock

• Enable USB interface

• Configure USB interface (USB speed, Endpoints configuration...)

• Wait for USB VBUS information connection

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• Attach USB device

Power Off the USB interface

• Detach USB interface

• Disable USB interface

• Disable PLL

• Disable USB pad regulator

Suspending the USB interface

• Clear Suspend Bit

• Set USB suspend clock

• Disable PLL

• Be sure to have interrupts enable to exit sleep mode

• Make the MCU enter sleep mode

Resuming the USB interface

• Enable PLL

• Wait PLL lock

• Clear USB suspend clock

• Clear Resume information

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22. USB Device Operating modes

22.1 Introduction

The USB device controller supports full speed and low speed data transfers. In addition to the

default control endpoint, it provides six other endpoints, which can be configured in control, bulk,

interrupt or isochronous modes:

• Endpoint 0:programmable size FIFO up to 64 bytes, default control endpoint

• Endpoints 1 programmable size FIFO up to 256 bytes in ping-pong mode.

• Endpoints 2 to 6: programmable size FIFO up to 64 bytes in ping-pong mode.

The controller starts in the “idle” mode. In this mode, the pad consumption is reduced to the

minimum.

22.2 Power-on and reset

The next diagram explains the USB device controller main states on power-on:

Figure 22-1. USB device controller states after reset

<any

other

state>

USBE=0

Idle

USBE=1

UID=1

Reset

HW

RESET

The reset state of the Device controller is:

• the macro clock is stopped in order to minimize the power consumption (FRZCLK set),

• the USB device controller internal state is reset (all the registers are reset to their default

value. Note that DETACH is set.)

• the endpoint banks are reset

• the D+ or D- pull up are not activated (mode Detach)

The D+ or D- pull-up will be activated as soon as the DETACH bit is cleared and VBUS is

present.

The macro is in the ‘Idle’ state after reset with a minimum power consumption and does not

need to have the PLL activated to enter in this state.

The USB device controller can at any time be reset by clearing USBE (disable USB interface).

22.3 Speed identification on startup

The usb bus reset is managed by the hardware. At the connection, the host makes a reset that

can be:

At the end of the reset process (full speed or low speed mode), the end of reset interrupt

(EORSTI) is generated. Then the CPU can read the SPEED1 bit to know the speed mode of the

device.

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22.4 Endpoint reset

An endpoint can be reset at any time by setting in the UERST register the bit corresponding to

the endpoint (EPRSTx). This resets:

• the internal state machine on that endpoint,

• the Rx and Tx banks are cleared and their internal pointers are restored,

• the UEINTX, UESTA0X and UESTA1X are restored to their reset value.

The data toggle field remains unchanged.

The other registers remain unchanged.

The endpoint configuration remains active and the endpoint is still enabled.

The endpoint reset may be associated with a clear of the data toggle command (RSTDT bit) as

an answer to the CLEAR_FEATURE USB command.

22.5 USB reset

When an USB reset is detected on the USB line, the next operations are performed by the

controller:

• all the endpoints are disabled, except the default control endpoint,

• the default control endpoint is reset (see Section 22.4, page 270 for more details).

• The data toggle of the default control endpoint is cleared.

22.6 Endpoint selection

Prior to any operation performed by the CPU, the endpoint must first be selected. This is done

by:

• Clearing EPNUMS.

• Setting EPNUM with the endpoint number which will be managed by the CPU.

The CPU can then access to the various endpoint registers and data.

22.7 Endpoint activation

The endpoint is maintained under reset as long as the EPEN bit is not set.

The following flow must be respected in order to activate an endpoint:

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Figure 22-2. Endpoint activation flow:

Endpoint

Activation

Select the endpoint

UENUM

EPNUM=x

Activate the endpoint

EPEN=1

Configure:

UECFG0X

EPDIR

EPTYPE

...

- the endpoint direction

- the endpoint type

- the Not Yet Disable feature

Configure:

- the endpoint size

- the bank parametrization

Allocation and reorganization of

the memory is made on-the-fly

UECFG1X

ALLOC

EPSIZE

EPBK

Test the correct endpoint

configuration

CFGOK=1

No

Yes

Endpoint activated

ERROR

As long as the endpoint is not correctly configured (CFGOK cleared), the hardware does not

acknowledge the packets sent by the host.

CFGOK is will not be sent if the Endpoint size parameter is bigger than the DPRAM size.

A clear of EPEN acts as an endpoint reset (see Section 22.4, page 270 for more details). It also

performs the next operation:

• The configuration of the endpoint is kept (EPSIZE, EPBK, ALLOC kept)

• It resets the data toggle field.

• The DPRAM memory associated to the endpoint is still reserved.

See Section 21.7, page 259 for more details about the memory allocation/reorganization.

22.8 Address Setup

The USB device address is set up according to the USB protocol:

• the USB device, after power-up, responds at address 0

• the host sends a SETUP command (SET_ADDRESS(addr)),

• the firmware records that address in UADD, but keep ADDEN cleared,

• the USB device sends an IN command of 0 bytes (IN 0 Zero Length Packet),

• then, the firmware can enable the USB device address by setting ADDEN. The only accepted

address by the controller is the one stored in UADD.

ADDEN and UADD shall not be written at the same time.

UADD contains the default address 00h after a power-up or USB reset.

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ADDEN is cleared by hardware:

• after a power-up reset,

• when an USB reset is received,

• or when the macro is disabled (USBE cleared)

When this bit is cleared, the default device address 00h is used.

22.9 Suspend, Wake-up and Resume

After a period of 3 ms during which the USB line was inactive, the controller switches to the full-

speed mode and triggers (if enabled) the SUSPI (suspend) interrupt. The firmware may then set

the FRZCLK bit.

The CPU can also, depending on software architecture, enter in the idle mode to lower again the

power consumption.

There are two ways to recover from the “Suspend” mode:

• First one is to clear the FRZCLK bit. This is possible if the CPU is not in the Idle mode.

• Second way, if the CPU is “idle”, is to enable the WAKEUPI interrupt (WAKEUPE set). Then,

as soon as an non-idle signal is seen by the controller, the WAKEUPI interrupt is triggered.

The firmware shall then clear the FRZCLK bit to restart the transfer.

There are no relationship between the SUSPI interrupt and the WAKEUPI interrupt: the WAKE-

UPI interrupt is triggered as soon as there are non-idle patterns on the data lines. Thus, the

WAKEUPI interrupt can occurs even if the controller is not in the “suspend” mode.

When the WAKEUPI interrupt is triggered, if the SUSPI interrupt bit was already set, it is cleared

by hardware.

When the SUSPI interrupt is triggered, if the WAKEUPI interrupt bit was already set, it is cleared

by hardware.

22.10 Detach

The reset value of the DETACH bit is 1.

It is possible to re-enumerate a device, simply by setting and clearing the DETACH bit.

• If the USB device controller is in full-speed mode, setting DETACH will disconnect the pull-up

on the D+ or D- pad (depending on full or low speed mode selected). Then, clearing DETACH

will connect the pull-up on the D+ or D- pad.

Figure 22-3. Detach a device in Full-speed:

UVREF

D +

D -

D +

D -

Detach, then

Attach

EN=1

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22.11 Remote Wake-up

The “Remote Wake-up” (or “upstream resume”) request is the only operation allowed to be sent

by the device on its own initiative. Anyway, to do that, the device should first have received a

DEVICE_REMOTE_WAKEUP request from the host.

• First, the USB controller must have detected the “suspend” state of the line: the remote

wake-up can only be sent after a SUSPI interrupt has been triggered.

• The firmware has then the ability to set RMWKUP to send the “upstream resume” stream.

This will automatically be done by the controller after 5ms of inactivity on the USB line.

• When the controller starts to send the “upstream resume”, the UPRSMI interrupt is triggered

(if enabled). If SUSPI was set, SUSPI is cleared by hardware.

• RMWKUP is cleared by hardware at the end of the “upstream resume”.

• If the controller detects a good “End Of Resume” signal from the host, an EORSMI interrupt

is triggered (if enabled).

22.12 STALL request

For each endpoint, the STALL management is performed using 2 bits:

– STALLRQ (enable stall request)

– STALLRQC (disable stall request)

– STALLEDI (stall sent interrupt)

To send a STALL handshake at the next request, the STALLRQ request bit has to be set. All fol-

lowing requests will be handshak’ed with a STALL until the STALLRQC bit is set.

Setting STALLRQC automatically clears the STALLRQ bit. The STALLRQC bit is also immedi-

ately cleared by hardware after being set by software. Thus, the firmware will never read this bit

as set.

Each time the STALL handshake is sent, the STALLEDI flag is set by the USB controller and the

EPINTx interrupt will be triggered (if enabled).

The incoming packets will be discarded (RXOUTI and RWAL will not be set).

The host will then send a command to reset the STALL: the firmware just has to set the STALL-

RQC bit and to reset the endpoint.

22.12.1 Special consideration for Control Endpoints

A SETUP request is always ACK’ed.

If a STALL request is set for a Control Endpoint and if a SETUP request occurs, the SETUP

request has to be ACK’ed and the STALLRQ request and STALLEDI sent flags are automati-

cally reset (RXSETUPI set, TXIN cleared, STALLED cleared, TXINI cleared...).

This management simplifies the enumeration process management. If a command is not sup-

ported or contains an error, the firmware set the STALL request flag and can return to the main

task, waiting for the next SETUP request.

This function is compliant with the Chapter 8 test from PMTC that send extra status for a

GET_DESCRIPTOR. The firmware sets the STALL request just after receiving the status. All

extra status will be automatically STALL’ed until the next SETUP request.

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22.12.2 STALL handshake and Retry mechanism

The Retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the

STALLRQ request bit is set and if there is no retry required.

22.13 CONTROL endpoint management

A SETUP request is always ACK’ed. When a new setup packet is received, the RXSTPI inter-

rupt is triggered (if enabled). The RXOUTI interrupt is not triggered.

The FIFOCON and RWAL fields are irrelevant with CONTROL endpoints. The firmware shall

thus never use them on that endpoints. When read, their value is always 0.

CONTROL endpoints are managed by the following bits:

• RXSTPI is set when a new SETUP is received. It shall be cleared by firmware to

acknowledge the packet and to clear the endpoint bank.

• RXOUTI is set when a new OUT data is received. It shall be cleared by firmware to

acknowledge the packet and to clear the endpoint bank.

• TXINI is set when the bank is ready to accept a new IN packet. It shall be cleared by firmware

to send the packet and to clear the endpoint bank.

CONTROL endpoints should not be managed by interrupts, but only by polling the status bits.

22.13.1 Control Write

The next figure shows a control write transaction. During the status stage, the controller will not

necessary send a NAK at the first IN token:

• If the firmware knows the exact number of descriptor bytes that must be read, it can then

anticipate on the status stage and send a ZLP for the next IN token,

• or it can read the bytes and poll NAKINI, which tells that all the bytes have been sent by the

host, and the transaction is now in the status stage.

SETUP

DATA

STATUS

USB line

RXSTPI

RXOUTI

TXINI

SETUP

OUT

IN

NAK

HW

SW

HW

SW

HW

SW

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22.13.2 Control Read

The next figure shows a control read transaction. The USB controller has to manage the simulta-

neous write requests from the CPU and the USB host:

SETUP

HW

DATA

STATUS

USB line

RXSTPI

RXOUTI

TXINI

IN

OUT

NAK

OUT

SW

HW

SW

HW

SW

Wr Enable

HOST

Wr Enable

CPU

A NAK handshake is always generated at the first status stage command.

When the controller detect the status stage, all the data writen by the CPU are erased, and

clearing TXINI has no effects.

The firmware checks if the transmission is complete or if the reception is complete.

The OUT retry is always ack’ed. This reception:

- set the RXOUTI flag (received OUT data)

- set the TXINI flag (data sent, ready to accept new data)

software algorithm:

set transmit ready

wait (transmit complete OR Receive complete)

if receive complete, clear flag and return

if transmit complete, continue

Once the OUT status stage has been received, the USB controller waits for a SETUP request.

The SETUP request have priority over any other request and has to be ACK’ed. This means that

any other flag should be cleared and the fifo reset when a SETUP is received.

WARNING: the byte counter is reset when the OUT Zero Length Packet is received. The firm-

ware has to take care of this.

22.14 OUT endpoint management

OUT packets are sent by the host. All the data can be read by the CPU, which acknowledges or

not the bank when it is empty.

22.14.1 Overview

The Endpoint must be configured first.

Each time the current bank is full, the RXOUTI and the FIFOCON bits are set. This triggers an

interrupt if the RXOUTE bit is set. The firmware can acknowledge the USB interrupt by clearing

the RXOUTI bit. The Firmware read the data and clear the FIFOCON bit in order to free the cur-

rent bank. If the OUT Endpoint is composed of multiple banks, clearing the FIFOCON bit will

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switch to the next bank. The RXOUTI and FIFOCON bits are then updated by hardware in

accordance with the status of the new bank.

RXOUTI shall always be cleared before clearing FIFOCON.

The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can

read data from the bank, and cleared by hardware when the bank is empty.

Example with 1 OUT data bank

DATA

(to bank 0)

NAK

DATA

(to bank 0)

OUT

ACK

HW

OUT

ACK

HW

RXOUTI

SW

read data from CPU

BANK 0

FIFOCON

SW

read data from CPU

BANK 0

Example with 2 OUT data banks

DATA

OUT

DATA

(to bank 1)

ACK

HW

OUT

ACK

(to bank 0)

HW

RXOUTI

SW

read data from CPU

BANK 0

SW

FIFOCON

read data from CPU

BANK 1

22.14.2 Detailed description

22.14.2.1

The data are read by the CPU, following the next flow:

• When the bank is filled by the host, an endpoint interrupt (EPINTx) is triggered, if enabled

(RXOUTE set) and RXOUTI is set. The CPU can also poll RXOUTI or FIFOCON, depending

on the software architecture,

• The CPU acknowledges the interrupt by clearing RXOUTI,

• The CPU can read the number of byte (N) in the current bank (N=BYCT),

• The CPU can read the data from the current bank (“N” read of UEDATX),

• The CPU can free the bank by clearing FIFOCON when all the data is read, that is:

• after “N” read of UEDATX,

• as soon as RWAL is cleared by hardware.

If the endpoint uses 2 banks, the second one can be filled by the HOST while the current one is

being read by the CPU. Then, when the CPU clear FIFOCON, the next bank may be already

ready and RXOUTI is set immediately.

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22.15 IN endpoint management

IN packets are sent by the USB device controller, upon an IN request from the host. All the data

can be written by the CPU, which acknowledge or not the bank when it is full.Overview

The Endpoint must be configured first.

The TXINI bit is set by hardware when the current bank becomes free. This triggers an interrupt

if the TXINE bit is set. The FIFOCON bit is set at the same time. The CPU writes into the FIFO

and clears the FIFOCON bit to allow the USB controller to send the data. If the IN Endpoint is

composed of multiple banks, this also switches to the next data bank. The TXINI and FIFOCON

bits are automatically updated by hardware regarding the status of the next bank.

TXINI shall always be cleared before clearing FIFOCON.

The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can

write data to the bank, and cleared by hardware when the bank is full.

Example with 1 IN data bank

NAK

DATA

(bank 0)

IN

ACK

HW

IN

TXINI

SW

write data from CPU

BANK 0

FIFOCON

SW

write data from CPU

BANK 0

Example with 2 IN data banks

DATA

(bank 0)

DATA

(bank 1)

IN

ACK

HW

IN

ACK

TXINI

SW

write data from CPU

BANK0

write data from CPU

BANK 0

write data from CPU

BANK 1

FIFOCON

SW

22.15.1 Detailed description

The data are written by the CPU, following the next flow:

• When the bank is empty, an endpoint interrupt (EPINTx) is triggered, if enabled (TXINE set)

and TXINI is set. The CPU can also poll TXINI or FIFOCON, depending the software

architecture choice,

• The CPU acknowledges the interrupt by clearing TXINI,

• The CPU can write the data into the current bank (write in UEDATX),

• The CPU can free the bank by clearing FIFOCON when all the data are written, that is:

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• after “N” write into UEDATX

• as soon as RWAL is cleared by hardware.

If the endpoint uses 2 banks, the second one can be read by the HOST while the current is

being written by the CPU. Then, when the CPU clears FIFOCON, the next bank may be already

ready (free) and TXINI is set immediately.

22.15.1.1

Abort

An “abort” stage can be produced by the host in some situations:

• In a control transaction: ZLP data OUT received during a IN stage,

• In an isochronous IN transaction: ZLP data OUT received on the OUT endpoint during a IN

stage on the IN endpoint

• ...

The KILLBK bit is used to kill the last “written” bank. The best way to manage this abort is to per-

form the following operations:

Table 22-1. Abort flow

Endpoint

Abort

Clear

Disable the TXINI interrupt.

UEIENX.

TXINE

Abort is based on the fact

No

NBUSYBK

=0

that no banks are busy,

meaning that nothing has to

be sent.

Yes

Kill the last written

bank.

Endpoint

reset

KILLBK=1

Wait for the end of the

procedure.

Yes

KILLBK=1

No

Abort done

22.16 Isochronous mode

For Isochronous IN endpoints, it is possible to automatically switch the banks on each start of

frame (SOF). This is done by setting ISOSW. The CPU has to fill the bank of the endpoint; the

bank switching will be automatic as soon as a SOF is seen by the hardware.

A clear of FIFOCON does not have any effects in this mode.

In the case that a SOF is missing (noise on USB pad, ...), the controller will automatically build

internally a “pseudo” start of frame and the bank switching is made. The SOFI interrupt is trig-

gered and the frame number FNUM10:0 is increased.

22.16.1 Underflow

An underflow can occur during IN stage if the host attempts to read a bank which is empty. In

this situation, the UNDERFI interrupt is triggered.

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An underflow can also occur during OUT stage if the host send a packet while the banks are

already full. Typically, he CPU is not fast enough. The packet is lost.

It is not possible to have underflow error during OUT stage, in the CPU side, since the CPU

should read only if the bank is ready to give data (RXOUTI=1 or RWAL=1)

22.16.2 CRC Error

A CRC error can occur during OUT stage if the USB controller detects a bad received packet. In

this situation, the STALLEDI interrupt is triggered. This does not prevent the RXOUTI interrupt

from being triggered.

22.17 Overflow

In Control, Isochronous, Bulk or Interrupt Endpoint, an overflow can occur during OUT stage, if

the host attempts to write in a bank that is too small for the packet. In this situation, the OVERFI

interrupt is triggered (if enabled). The packet is hacknowledged and the RXOUTI interrupt is also

triggered (if enabled). The bank is filled with the first bytes of the packet.

It is not possible to have overflow error during IN stage, in the CPU side, since the CPU should

write only if the bank is ready to access data (TXINI=1 or RWAL=1).

22.18 Interrupts

The next figure shows all the interrupts sources:

Figure 22-4. USB Device Controller Interrupt System

UPRSMI

UDINT.6

UPRSME

UDIEN.6

EORSMI

UDINT.5

EORSME

UDIEN.5

WAKEUPI

UDINT.4

WAKEUPE

UDIEN.4

USB Device

Interrupt

EORSTI

UDINT.3

EORSTE

UDIEN.3

SOFI

UDINT.2

SOFE

UDIEN.2

SUSPI

UDINT.0

SUSPE

UDIEN.0

There are 2 kind of interrupts: processing (i.e. their generation are part of the normal processing)

and exception (errors).

Processing interrupts are generated when:

• VBUS plug-in detection (insert, remove)(VBUSTI)

• Upstream resume(UPRSMI)

• End of resume(EORSMI)

• Wake up(WAKEUPI)

• End of reset (Speed Initialization)(EORSTI)

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• Start of frame(SOFI, if FNCERR=0)

• Suspend detected after 3 ms of inactivity(SUSPI)

Exception Interrupts are generated when:

• CRC error in frame number of SOF(SOFI, FNCERR=1)

Figure 22-5. USB Device Controller Endpoint Interrupt System

Endpoint 6

Endpoint 5

Endpoint 4

Endpoint 3

Endpoint 2

Endpoint 1

Endpoint 0

OVERFI

UESTAX.6

UNDERFI

UESTAX.5

FLERRE

UEIENX.7

NAKINI

UEINTX.6

NAKINE

UEIENX.6

NAKOUTI

UEINTX.4

TXSTPE

Endpoint Interrupt

UEIENX.4

RXSTPI

EPINT

UEINTX.3

UEINT.X

TXOUTE

UEIENX.3

RXOUTI

UEINTX.2

RXOUTE

UEIENX.2

STALLEDI

UEINTX.1

STALLEDE

UEIENX.1

TXINI

UEINTX.0

TXINE

UEIENX.0

Processing interrupts are generated when:

• Ready to accept IN data(EPINTx, TXINI=1)

• Received OUT data(EPINTx, RXOUTI=1)

• Received SETUP(EPINTx, RXSTPI=1)

Exception Interrupts are generated when:

• Stalled packet(EPINTx, STALLEDI=1)

• CRC error on OUT in isochronous mode(EPINTx, STALLEDI=1)

• Overflow in isochronous mode(EPINTx, OVERFI=1)

• Underflow in isochronous mode(EPINTx, UNDERFI=1)

• NAK IN sent(EPINTx, NAKINI=1)

• NAK OUT sent(EPINTx, NAKOUTI=1)

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22.19 Registers

22.19.1 USB device general registers

Bit

7

-

6

-

5

-

4

-

3

-

2

1

0

LSM

R/W

0

RMWKUP DETACH

UDCON

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R/W

0

R/W

1

• 7-3 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 2 - LSM - USB Device Low Speed Mode Selection

When configured USB is configured in device mode, this bit allows to select the USB the USB

Low Speed or Full Speed Mod.

Clear to select full speed mode (D+ internal pull-up will be activate with the ATTACH bit will be

set) .

Set to select low speed mode (D- internal pull-up will be activate with the ATTACH bit will be

set). This bit has no effect when the USB interface is configured in HOST mode.

• 1- RMWKUP - Remote Wake-up Bit

Set to send an “upstream-resume” to the host for a remote wake-up.

Cleared by hardware. Clearing by software has no effect.

See Section 22.11, page 273 for more details.

• 0 - DETACH - Detach Bit

Set to physically detach de device (disconnect internal pull-up on D+ or D-).

Clear to reconnect the device. See Section 22.10, page 272 for more details.

Bit

7

-

6

5

4

3

2

1

0

UPRSMI

EORSMI WAKEUPI EORSTI

SOFI

-

SUSPI

UDINT

Read/Write

Initial Value

0

• 7 - Reserved

The value read from this bits is always 0. Do not set this bit.

• 6 - UPRSMI - Upstream Resume Interrupt Flag

Set by hardware when the USB controller is sending a resume signal called “Upstream

Resume”. This triggers an USB interrupt if UPRSME is set.

Shall be cleared by software (USB clocks must be enabled before). Setting by software has no

effect.

• 5 - EORSMI - End Of Resume Interrupt Flag

Set by hardware when the USB controller detects a good “End Of Resume” signal initiated by

the host. This triggers an USB interrupt if EORSME is set.

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Shall be cleared by software. Setting by software has no effect.

• 4 - WAKEUPI - Wake-up CPU Interrupt Flag

Set by hardware when the USB controller is re-activated by a filtered non-idle signal from the

lines (not by an upstream resume). This triggers an interrupt if WAKEUPE is set.

Shall be cleared by software (USB clock inputs must be enabled before). Setting by software

has no effect.

See Section 22.9, page 272 for more details.

• 3 - EORSTI - End Of Reset Interrupt Flag

Set by hardware when an “End Of Reset” has been detected by the USB controller. This triggers

an USB interrupt if EORSTE is set.

Shall be cleared by software. Setting by software has no effect.

• 2 - SOFI - Start Of Frame Interrupt Flag

Set by hardware when an USB “Start Of Frame” PID (SOF) has been detected (every 1 ms).

This triggers an USB interrupt if SOFE is set..

• 1 - Reserved

The value read from this bits is always 0. Do not set this bit

• 0 - SUSPI - Suspend Interrupt Flag

Set by hardware when an USB “Suspend” ‘idle bus for 3 frame periods: a J state for 3 ms) is detected. This

triggers an USB interrupt if SUSPE is set.

Shall be cleared by software. Setting by software has no effect.

See Section 22.9, page 272 for more details.

The interrupt bits are set even if their corresponding ‘Enable’ bits is not set.

Bit

7

6

5

4

3

2

1

0

-

UPRSME EORSME WAKEUPE EORSTE

SOFE

-

SUSPE

UDIEN

Read/Write

Initial Value

0

• 7 - Reserved

The value read from this bits is always 0. Do not set this bit.

• 6 - UPRSME - Upstream Resume Interrupt Enable Bit

Set to enable the UPRSMI interrupt.

Clear to disable the UPRSMI interrupt.

• 5 - EORSME - End Of Resume Interrupt Enable Bit

Set to enable the EORSMI interrupt.

Clear to disable the EORSMI interrupt.

• 4 - WAKEUPE - Wake-up CPU Interrupt Enable Bit

Set to enable the WAKEUPI interrupt.

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Clear to disable the WAKEUPI interrupt.

• 3 - EORSTE - End Of Reset Interrupt Enable Bit

Set to enable the EORSTI interrupt. This bit is set after a reset.

Clear to disable the EORSTI interrupt.

• 2 - SOFE - Start Of Frame Interrupt Enable Bit

Set to enable the SOFI interrupt.

Clear to disable the SOFI interrupt.

• 1 - Reserved

The value read from this bits is always 0. Do not set this bit

• 0 - SUSPE - Suspend Interrupt Enable Bit

Set to enable the SUSPI interrupt.

Clear to disable the SUSPI interrupt.

Bit

7

6

5

4

3

UADD6:0

R/W

2

1

0

ADDEN

UDADDR

Read/Write

W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Initial Val-

ue

0

• 7 - ADDEN - Address Enable Bit

Set to activate the UADD (USB address).

Cleared by hardware. Clearing by software has no effect.

See Section 22.8, page 271 for more details.

• 6-0 - UADD6:0 - USB Address Bits

Load by software to configure the device address.

.

Bit

7

-

6

-

5

-

4

-

3

-

2

1

0

FNUM10:8

UDFNUMH

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

• 7-3 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 2-0 - FNUM10:8 - Frame Number Upper Flag

Set by hardware. These bits are the 3 MSB of the 11-bits Frame Number information. They are

provided in the last received SOF packet. FNUM is updated if a corrupted SOF is received.

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Bit

7

6

5

4

3

2

1

0

FNUM7:0

UDFNUML

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

• Frame Number Lower Flag

Set by hardware. These bits are the 8 LSB of the 11-bits Frame Number information.

Bit

7

6

5

4

FNCERR

R

3

2

1

0

-

UDMFN

Read/W

rite

Initial

Value

0

• 7-5 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 4 - FNCERR -Frame Number CRC Error Flag

Set by hardware when a corrupted Frame Number in start of frame packet is received.

This bit and the SOFI interrupt are updated at the same time.

• 3-0 - Reserved

The value read from these bits is always 0. Do not set these bits.

22.19.2 USB device endpoint registers

Bit

7

-

6

-

5

-

4

-

3

-

2

1

EPNUM2:0

R/W

0

UENUM

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R/W

0

R/W

0

• 7-3 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 2-0 - EPNUM2:0 Endpoint Number Bits

Load by software to select the number of the endpoint which shall be accessed by the CPU. See

Section 22.6, page 270 for more details.

EPNUM = 111b is forbidden.

Bit

7

-

6

EPRST6

R/W

5

EPRST5

R/W

4

EPRST4

R/W

3

EPRST3

R/W

2

EPRST2

R/W

1

EPRST1

R/W

0

EPRST0

R/W

UERST

Read/Write

Initial Value

R

0

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• 7 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 6-0 - EPRST6:0 - Endpoint FIFO Reset Bits

Set to reset the selected endpoint FIFO prior to any other operation, upon hardware reset or

when an USB bus reset has been received. See Section 22.4, page 270 for more information

Then, cleared by software to complete the reset operation and start using the endpoint.

Bit

7

-

6

-

5

4

3

RSTDT

W

2

-

1

-

0

EPEN

R/W

0

STALLRQ STALLRQC

UECONX

Read/Write

Initial Value

R

0

R

0

W

0

W

0

R

0

R

0

• 7-6 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 5 - STALLRQ - STALL Request Handshake Bit

Set to request a STALL answer to the host for the next handshake.

Cleared by hardware when a new SETUP is received. Clearing by software has no effect.

See Section 22.12, page 273 for more details.

• 4 - STALLRQC - STALL Request Clear Handshake Bit

Set to disable the STALL handshake mechanism.

Cleared by hardware immediately after the set. Clearing by software has no effect.

See Section 22.12, page 273 for more details.

3

• RSTDT - Reset Data Toggle Bit

Set to automatically clear the data toggle sequence:

For OUT endpoint: the next received packet will have the data toggle 0.

For IN endpoint: the next packet to be sent will have the data toggle 0.

Cleared by hardware instantaneously. The firmware does not have to wait that the bit is cleared.

Clearing by software has no effect.

• 2 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 1 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 0 - EPEN - Endpoint Enable Bit

Set to enable the endpoint according to the device configuration. Endpoint 0 shall always be

enabled after a hardware or USB reset and participate in the device configuration.

Clear this bit to disable the endpoint. See Section 22.7, page 270 for more details.

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Bit

7

6

5

-

4

-

3

-

2

-

1

-

0

EPDIR

R/W

0

EPTYPE1:0

UECFG0X

Read/Write

Initial Value

R/W

0

R/W

0

R

0

R

0

R

0

R

0

R

0

• 7-6 - EPTYPE1:0 - Endpoint Type Bits

Set this bit according to the endpoint configuration:

00b: Control10b: Bulk

01b: Isochronous11b: Interrupt

• 5-4 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 3-2 - Reserved for test purpose

The value read from these bits is always 0. Do not set these bits.

• 1 - Reserved

The value read from this bits is always 0. Do not set this bit.

• 0 - EPDIR - Endpoint Direction Bit

Set to configure an IN direction for bulk, interrupt or isochronous endpoints.

Clear to configure an OUT direction for bulk, interrupt, isochronous or control endpoints.

Bit

7

-

6

5

EPSIZE2:0

R/W

4

3

2

1

ALLOC

R/W

0

-

EPBK1:0

UECFG1X

Read/Write

Initial Value

R

0

R/W

0

R/W

0

R/W

0

R/W

0

R

0

• 7 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 6-4 - EPSIZE2:0 - Endpoint Size Bits

Set this bit according to the endpoint size:

000b: 8 bytes100b: 128 bytes

001b: 16 bytes101b: 256 bytes

010b: 32 bytes110b: 512 bytes

011b: 64 bytes111b: Reserved. Do not use this configuration.

• 3-2 - EPBK1:0 - Endpoint Bank Bits

Set this field according to the endpoint size:

00b: One bank

01b: Double bank

1xb: Reserved. Do not use this configuration.

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• 1 - ALLOC - Endpoint Allocation Bit

Set this bit to allocate the endpoint memory.

Clear to free the endpoint memory.

See Section 22.7, page 270 for more details.

• 0 - Reserved

The value read from these bits is always 0. Do not set these bits.

Bit

7

6

OVERFI

R/W

0

5

4

3

2

1

0

CFGOK

UNDERFI ZLPSEEN

DTSEQ1:0

NBUSYBK1:0

UESTA0X

Read/Write

Initial Value

R

0

R/W

0

R/W

0

R

0

R

0

R

0

R

0

• 7 - CFGOK - Configuration Status Flag

Set by hardware when the endpoint X size parameter (EPSIZE) and the bank parametrization

(EPBK) are correct compared to the max FIFO capacity and the max number of allowed bank.

This bit is updated when the bit ALLOC is set.

If this bit is cleared, the user should reprogram the UECFG1X register with correct EPSIZE and

EPBK values.

• 6 - OVERFI - Overflow Error Interrupt Flag

Set by hardware when an overflow error occurs in an isochronous endpoint. An interrupt

(EPINTx) is triggered (if enabled).

See Section 22.16, page 278 for more details.

Shall be cleared by software. Setting by software has no effect.

• 5 - UNDERFI - Flow Error Interrupt Flag

Set by hardware when an underflow error occurs in an isochronous endpoint. An interrupt

(EPINTx) is triggered (if enabled).

See Section 22.16, page 278 for more details.

Shall be cleared by software. Setting by software has no effect.

• 4 - ZLPSEEN - Zero Length Packet Seen (bit / Flag)

Set by hardware, as soon as a ZLP has been filtered during a transfer.

Shall be cleared by the software. Setting by software has no effect.

• 3-2 - DTSEQ1:0 - Data Toggle Sequencing Flag

Set by hardware to indicate the PID data of the current bank:

00b Data0

01b Data1

1xb Reserved.

For OUT transfer, this value indicates the last data toggle received on the current bank.

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For IN transfer, it indicates the Toggle that will be used for the next packet to be sent. This is not

relative to the current bank.

• 1-0 - NBUSYBK1:0 - Busy Bank Flag

Set by hardware to indicate the number of busy bank.

For IN endpoint, it indicates the number of busy bank(s), filled by the user, ready for IN transfer.

For OUT endpoint, it indicates the number of busy bank(s) filled by OUT transaction from the

host.

00b All banks are free

01b 1 busy bank

10b 2 busy banks

11b Reserved.

Bit

7

-

6

-

5

-

4

-

3

-

2

1

0

CTRLDIR

CURRBK1:0

UESTA1X

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

R

0

• 7-3 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 2 - CTRLDIR - Control Direction (Flag, and bit for debug purpose)

Set by hardware after a SETUP packet, and gives the direction of the following packet:

- 1 for IN endpoint

- 0 for OUT endpoint.

Can not be set or cleared by software.

• 1-0 - CURRBK1:0 - Current Bank (all endpoints except Control endpoint) Flag

Set by hardware to indicate the number of the current bank:

00b Bank0

01b Bank1

1xb Reserved.

Can not be set or cleared by software.

Bit

7

FIFOCON

R/W

6

NAKINI

R/W

0

5

4

3

RXSTPI

R/W

0

2

1

0

TXINI

R/W

0

RWAL NAKOUTI

RXOUTI STALLEDI

UEINTX

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

• 7 - FIFOCON - FIFO Control Bit

For OUT and SETUP Endpoint:

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Set by hardware when a new OUT message is stored in the current bank, at the same time than

RXOUT or RXSTP.

Clear to free the current bank and to switch to the following bank. Setting by software has no

effect.

For IN Endpoint:

Set by hardware when the current bank is free, at the same time than TXIN.

Clear to send the FIFO data and to switch the bank. Setting by software has no effect.

• 6 - NAKINI - NAK IN Received Interrupt Flag

Set by hardware when a NAK handshake has been sent in response of a IN request from the

host. This triggers an USB interrupt if NAKINE is sent.

Shall be cleared by software. Setting by software has no effect.

• 5 - RWAL - Read/Write Allowed Flag

Set by hardware to signal:

- for an IN endpoint: the current bank is not full i.e. the firmware can push data into the FIFO,

- for an OUT endpoint: the current bank is not empty, i.e. the firmware can read data from the

FIFO.

The bit is never set if STALLRQ is set, or in case of error.

Cleared by hardware otherwise.

This bit shall not be used for the control endpoint.

• 4 - NAKOUTI - NAK OUT Received Interrupt Flag

Set by hardware when a NAK handshake has been sent in response of a OUT/PING request

from the host. This triggers an USB interrupt if NAKOUTE is sent.

Shall be cleared by software. Setting by software has no effect.

• 3 - RXSTPI - Received SETUP Interrupt Flag

Set by hardware to signal that the current bank contains a new valid SETUP packet. An inter-

rupt (EPINTx) is triggered (if enabled).

Shall be cleared by software to handshake the interrupt. Setting by software has no effect.

This bit is inactive (cleared) if the endpoint is an IN endpoint.

• 2 - RXOUTI / KILLBK - Received OUT Data Interrupt Flag

Set by hardware to signal that the current bank contains a new packet. An interrupt (EPINTx) is

triggered (if enabled).

Shall be cleared by software to handshake the interrupt. Setting by software has no effect.

Kill Bank IN Bit

Set this bit to kill the last written bank.

Cleared by hardware when the bank is killed. Clearing by software has no effect.

See page 278 for more details on the Abort.

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• 1 - STALLEDI - STALLEDI Interrupt Flag

Set by hardware to signal that a STALL handshake has been sent, or that a CRC error has been

detected in a OUT isochronous endpoint.

Shall be cleared by software. Setting by software has no effect.

• 0 - TXINI - Transmitter Ready Interrupt Flag

Set by hardware to signal that the current bank is free and can be filled. An interrupt (EPINTx) is

triggered (if enabled).

Shall be cleared by software to handshake the interrupt. Setting by software has no effect.

This bit is inactive (cleared) if the endpoint is an OUT endpoint.

Bit

7

6

5

-

4

3

2

1

0

TXINE

R/W

0

FLERRE NAKINE

NAKOUTE RXSTPE

RXOUTE STALLEDE

UEIENX

Read/Write

Initial Value

R/W

0

R/W

0

R

0

R/W

0

R/W

0

R/W

0

R/W

0

• 7 - FLERRE - Flow Error Interrupt Enable Flag

Set to enable an endpoint interrupt (EPINTx) when OVERFI or UNDERFI are sent.

Clear to disable an endpoint interrupt (EPINTx) when OVERFI or UNDERFI are sent.

• 6 - NAKINE - NAK IN Interrupt Enable Bit

Set to enable an endpoint interrupt (EPINTx) when NAKINI is set.

Clear to disable an endpoint interrupt (EPINTx) when NAKINI is set.

• 5 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 4 - NAKOUTE - NAK OUT Interrupt Enable Bit

Set to enable an endpoint interrupt (EPINTx) when NAKOUTI is set.

Clear to disable an endpoint interrupt (EPINTx) when NAKOUTI is set.

• 3 - RXSTPE - Received SETUP Interrupt Enable Flag

Set to enable an endpoint interrupt (EPINTx) when RXSTPI is sent.

Clear to disable an endpoint interrupt (EPINTx) when RXSTPI is sent.

• 2 - RXOUTE - Received OUT Data Interrupt Enable Flag

Set to enable an endpoint interrupt (EPINTx) when RXOUTI is sent.

Clear to disable an endpoint interrupt (EPINTx) when RXOUTI is sent.

• 1 - STALLEDE - Stalled Interrupt Enable Flag

Set to enable an endpoint interrupt (EPINTx) when STALLEDI is sent.

Clear to disable an endpoint interrupt (EPINTx) when STALLEDI is sent.

• 0 - TXINE - Transmitter Ready Interrupt Enable Flag

Set to enable an endpoint interrupt (EPINTx) when TXINI is sent.

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Clear to disable an endpoint interrupt (EPINTx) when TXINI is sent.

Bit

7

DAT D7

R/W

0

6

DAT D6

R/W

0

5

DAT D5

R/W

0

4

DAT D4

R/W

0

3

DAT D3

R/W

0

2

DAT D2

R/W

0

1

DAT D1

R/W

0

DAT D0

R/W

0

UEDATX

Read/Write

Initial Value

• 7-0 - DAT7:0 -Data Bits

Set by the software to read/write a byte from/to the endpoint FIFO selected by EPNUM.

Bit

7

6

5

4

3

2

1

0

-

BYCT D10 BYCT D9 BYCT D8 UEBCHX

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

• 7-3 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 2-0 - BYCT10:8 - Byte count (high) Bits

Set by hardware. This field is the MSB of the byte count of the FIFO endpoint. The LSB part is

provided by the UEBCLX register.

Bit

7

6

5

4

3

2

1

0

BYCT D7 BYCT D6 BYCT D5 BYCT D4 BYCT D3 BYCT D2 BYCT D1 BYCT D0 UEBCLX

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

• 7-0 - BYCT7:0 - Byte Count (low) Bits

Set by the hardware. BYCT10:0 is:

- (for IN endpoint) increased after each writing into the endpoint and decremented after each

byte sent,

- (for OUT endpoint) increased after each byte sent by the host, and decremented after each

byte read by the software.

Bit

7

-

6

5

4

3

2

1

0

EPINT D6 EPINT D5 EPINT D4 EPINT D3 EPINT D2 EPINT D1 EPINT D0 UEINT

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

• 7 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 6-0 - EPINT6:0 - Endpoint Interrupts Bits

Set by hardware when an interrupt is triggered by the UEINTX register and if the corresponding

endpoint interrupt enable bit is set.

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Cleared by hardware when the interrupt source is served.

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23. USB Host Operating Modes

23.1 Pipe description

For the USB Host controller, the term of Pipe is used instead of Endpoint for the USB Device

controller. A Host Pipe corresponds to a Device Endpoint, as described in the USB specification:

Figure 23-1. Pipes and Endpoints in a USB system

In the USB Host controller, a Pipe will be associated to a Device Endpoint, considering the

Device Configuration Descriptors.

23.2 Detach

The reset value of the DETACH bit is 1. Thus, the firmware has the responsibility of clearing this

bit before switching to the Host mode (HOST set).

23.3 Power-on and Reset

The next diagram explains the USB host controller main states on power-on:

Figure 23-2. USB host controller states after reset

<any

other

state>

Device

Clock stopped

disconnection

Macro off

Host

Idle

Device

connection

Device

disconnection

Host

Ready

SOFE=0

Host

SOFE=1

Suspend

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USB host controller state after an hardware reset is ‘Reset’. When the USB controller is enabled

and the USB Host controller is selected, the USB controller is in ‘Idle’ state. In this state, the

USB Host controller waits for the Device connection, with a minimum power consumption.

The USB Pad should be in Idle mode. The macro does not need to have the PLL activated to

enter in ‘Host Ready’ state.

The Host controller enters in Suspend state when the USB bus is in Suspend state, i.e. when the

Host controller doesn’t generate the Start of Frame. In this state, the USB consumption is mini-

mum. The Host controller exits to the Suspend state when starting to generate the SOF over the

USB line.

23.4 Device Detection

A Device is detected by the USB controller when the USB bus if different from D+ and D- low. In

other words, when the USB Host Controller detects the Device pull-up on the D+ line. To enable

this detection, the Host Controller has to provide the Vbus power supply to the Device.

The Device Disconnection is detected by the USB Host controller when the USB Idle correspond

to D+ and D- low on the USB line.

23.5 Pipe Selection

Prior to any operation performed by the CPU, the Pipe must first be selected. This is done by:

• Clearing PNUMS.

• Setting PNUM with the Pipe number which will be managed by the CPU.

The CPU can then access to the various Pipe registers and data.

23.6 Pipe Configuration

The following flow must be respected in order to activate a Pipe:

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Figure 23-3. Pipe activation flow:

Pipe

Activ ation

UPCONX

PENABLE=1

Enablethepipe

SelectthePipetype:

UPCFG0X

PTYPE

PTOKEN

*Type(Control,Bulk,Interrupt)

*Token(IN,OUT ,SETUP)

*Endpointnumber

PEPNUM

UPCFG1X

ConfigurethePipememory:

*Pipesize

*Numberofbanks

PSIZE

PBK

CFGMEM

No

CFGOK=1

Yes

ERROR

UPCFG2X

INTFRQ

(interruptonly)

Configurethepollinginterval

forInterruptpipe

Pipeactiv ated

and f reezed

Once the Pipe is activated (EPEN set) and, the hardware is ready to send requests to the

Device.

When configured (CFGOK = 1), only the Pipe Token (PTOKEN) and the polling interval for Inter-

rupt pipe can be modified.

A Control type pipe supports only 1 bank. Any other value will lead to a configuration error

(CFGOK = 0).

A clear of PEN will reset the configuration of the Pipe. All the corresponding Pipe registers are

reset to there reset values. Please refers to the Memory Management chapter for more details.

Note: The firmware has to configure the Default Control Pipe with the following parameters:

• Type: Control

• Token: SETUP

• Data bank: 1

• Size: 64 Bytes

The firmware asks for 8 bytes of the Device Descriptor sending a GET_DESCRIPTOR request.

These bytes contains the MaxPacketSize of the Device default control endpoint and the firm-

ware re-configures the size of the Default Control Pipe with this size parameter.

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23.7 USB Reset

The USB controller sends a USB Reset when the firmware set the RESET bit. The RSTI bit is

set by hardware when the USB Reset has been sent. This triggers an interrupt if the RSTE has

been set.

When a USB Reset has been sent, all the Pipe configuration and the memory allocation are

reset. The General Host interrupt enable register is left unchanged.

If the bus was previously in suspend mode (SOFEN = 0), the USB controller automatically

switches to the resume mode (HWUPI is set) and the SOFEN bit is set by hardware in order to

generate SOF immediately after the USB Reset.

23.8 Address Setup

Once the Device has answer to the first Host requests with the default address (0), the Host

assigns a new address to the device. The Host controller has to send a USB reset to the device

and perform a SET ADDRESS control request, with the new address to be used by the Device.

This control request ended, the firmware write the new address into the UHADDR register. All

following requests, on every Pipes, will be performed using this new address.

When the Host controller send a USB reset, the UHADDR register is reset by hardware and the

following Host requests will be performed using the default address (0).

23.9 Remote Wake-Up detection

The Host Controller enters in Suspend mode when clearing the SOFEN bit. No more Start Of

Frame is sent on the USB bus and the USB Device enters in Suspend mode 3ms later.

The Device awakes the Host Controller by sending an Upstream Resume (Remote Wake-Up

feature). The Host Controller detects a non-idle state on the USB bus and set the HWUPI bit. If

the non-Idle correspond to an Upstream Resume (K state), the RXRSMI bit is set by hardware.

The firmware has to generate a downstream resume within 1ms and for at least 20ms by setting

the RESUME bit.

Once the downstream Resume has been generated, the SOFEN bit is automatically set by hard-

ware in order to generate SOF immediately after the USB resume.

Host

Ready

SOFE=0

SOFE=1

or HWUP=1

Host

Suspend

23.10 USB Pipe Reset

The firmware can reset a Pipe using the pipe reset register. The configuration of the pipe and

the data toggle remains unchanged. Only the bank management and the status bits are reset to

their initial values.

To completely reset a Pipe, the firmware has to disable and then enable the pipe.

23.11 Pipe Data Access

In order to read or to write into the Pipe Fifo, the CPU selects the Pipe number with the UPNUM

register and performs read or write action on the UPDATX register.

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23.12 Control Pipe management

A Control transaction is composed of 3 phases:

• SETUP

• Data (IN or OUT)

• Status (OUT or IN)

The firmware has to change the Token for each phase.

The initial data toggle is set for the corresponding token (ONLY for Control Pipe):

• SETUP: Data0

• OUT: Data1

• IN: Data1 (expected data toggle)

23.13 OUT Pipe management

The Pipe must be configured and not frozen first.

Note: if the firmware decides to switch to suspend mode (clear SOFEN) even if a bank is ready

to be sent, the USB controller will automatically exit from Suspend mode and the bank will be

sent.

The TXOUT bit is set by hardware when the current bank becomes free. This triggers an inter-

rupt if the TXOUTE bit is set. The FIFOCON bit is set at the same time. The CPU writes into the

FIFO and clears the FIFOCON bit to allow the USB controller to send the data.

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If the OUT Pipe is composed of multiple banks, this also switches to the next data bank. The

TXOUT and FIFOCON bits are automatically updated by hardware regarding the status of the

next bank.

Example with 1 OUT data bank

DATA

(bank 0)

OUT

ACK

HW

OUT

TXOUT

SW

FIFOCON

SW

write data from CPU

BANK 0

write data from CPU

BANK 0

Example with 2 OUT data banks

DATA

(bank 0)

DATA

(bank 1)

OUT

ACK

HW

OUT

ACK

TXOUT

SW

FIFOCON

SW

write data from CPU

BANK 0

write data from CPU

BANK 1

write data from CPU

BANK0

Example with 2 OUT data banks

DATA

ACK

DATA

ACK

OUT

(bank 0)

(bank 1)

HW

TXOUT

SW

FIFOCON

SW

write data from CPU

BANK 0

write data from CPU

BANK 1

write data from CPU

BANK0

23.14 IN Pipe management

The Pipe must be configured first.

When the Host requires data from the device, the firmware has to determine first the IN mode to

use using the INMODE bit:

• INMODE = 0. The INRQX register is taken in account. The Host controller will perform

(INRQX+1) IN requests on the selected Pipe before freezing the Pipe. This mode avoids to

have extra IN requests on a Pipe.

• INMODE = 1. The USB controller will perform infinite IN request until the firmware freezes the

Pipe.

The IN request generation will start when the firmware clear the PFREEZE bit.

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Each time the current bank is full, the RXIN and the FIFOCON bits are set. This triggers an inter-

rupt if the RXINE bit is set. The firmware can acknowledge the USB interrupt by clearing the

RXIN bit. The Firmware read the data and clear the FIFOCON bit in order to free the current

bank. If the IN Pipe is composed of multiple banks, clearing the FIFOCON bit will switch to the

next bank. The RXIN and FIFOCON bits are then updated by hardware in accordance with the

status of the new bank.

Example with 1 IN data bank

DATA

(to bank 0)

DATA

(to bank 0)

IN

ACK

HW

IN

ACK

HW

RXIN

SW

FIFOCON

SW

read data from CPU

BANK 0

read data from CPU

BANK 0

Example with 2 IN data banks

DATA

(to bank 0)

DATA

(to bank 1)

IN

ACK

HW

IN

ACK

HW

RXIN

SW

FIFOCON

SW

read data from CPU

BANK 0

read data from CPU

BANK 1

23.14.1 CRC Error (isochronous only)

A CRC error can occur during IN stage if the USB controller detects a bad received packet. In

this situation, the STALLEDI/CRCERRI interrupt is triggered. This does not prevent the RXINI

interrupt from being triggered.

23.15 Interrupt system

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Figure 23-4. USB Host Controller Interrupt System

HWUPI

UHINT.6

HWUPE

UHIEN.6

HSOFI

UHINT.5

HSOFE

UHIEN.5

RXRSMI

UHINT.4

RXRSME

UHIEN.4

RSMEDI

USB Host

Interrupt

UHINT.3

RSMEDE

UHIEN.3

RSTI

UHINT.2

RSTE

UHIEN.2

DDISCI

UHINT.1

DDISCE

UHIEN.1

DCONNI

UHINT.0

DCONNE

UHIEN.0

Figure 23-5. USB Device Controller Pipe Interrupt System

PIPE 6

PIPE 5

PIPE 4

PIPE 3

PIPE 2

PIPE 1

PIPE 0

OVERFI

UPSTAX.6

UNDERFI

UPSTAX.5

FLERRE

UPIEN.7

NAKEDI

UPINTX.6

NAKEDE

UPIEN.6

PERRI

UPINTX.4

PERRE

Pipe Interrupt

UPIEN.4

TXSTPI

FLERRE

UPIEN.7

UPINTX.3

TXSTPE

UPIEN.3

TXOUTI

UPINTX.2

TXOUTE

UPIEN.2

RXSTALLI

UPINTX.1

RXSTALLE

UPIEN.1

RXINI

UPINTX.0

RXINE

UPIEN.0

23.16 Registers

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23.16.1 General USB Host registers

Bit

7

-

6

-

5

-

4

-

3

-

2

RESUME

R/W

1

RESET

R/W

0

SOFEN

R/W

0

UHCON

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

• 7-3 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 2 - RESUME - Send USB Resume

Set this bit to generate a USB Resume on the USB bus.

Cleared by hardware when the USB Resume has been sent. Clearing by software has no effect.

This bit should be set only when the start of frame generation is enable (SOFEN bit set).

• 1 - RESET - Send USB Reset

Set this bit to generate a USB Reset on the USB bus.

Cleared by hardware when the USB Reset has been sent. Clearing by software has no effect.

Refer to the USB reset section for more details.

• 0 - SOFEN - Start Of Frame Generation Enable

Set this bit to generate SOF on the USB bus in full speed mode and keep-alive in low speed

mode.

Clear this bit to disable the SOF generation and to leave the USB bus in Idle state.

Bit

7

-

6

HWUP

R/W

0

5

HSOF

R/W

0

4

RXRSMI

R/W

3

RSMEDI

R/W

2

RSTI

R/W

0

1

DDISCI

R/W

0

DCONNI

R/W

UHINT

Read/Write

Initial Value

R

0

• 7 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 6 - HWUP

Host Wake-Up Interrupt

Set by hardware when a non-idle state is detected on the USB bus.

Shall be clear by software to acknowledge the interrupt. Setting by software has no effect.

• 5 - HSOFI - Host Start Of Frame Interrupt

Set by hardware when a SOF is issued by the Host controller. This triggers a USB interrupt

when HSOFE is set. When using the host controller in low speed mode, this bit is also set when

a keep-alive is sent.

Shall be cleared by software to acknowledge the interrupt. Setting by software has no effect.

• 4 - RXRSMI - Upstream Resume Received Interrupt

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Set by hardware when an Upstream Resume has been received from the Device.

Shall be cleared by software. Setting by software has no effect.

• 3 - RSMEDI - Downstream Resume Sent Interrupt

Set by hardware when a Downstream Resume has been sent to the Device.

Shall be cleared by software. Setting by software has no effect.

• 2 - RSTI - USB Reset Sent Interrupt

Set by hardware when a USB Reset has been sent to the Device.

Shall be cleared by software. Setting by software has no effect.

• 1 - DDISCI Device Disconnection Interrupt

Set by hardware when the device has been removed from the USB bus.

Shall be cleared by software. Setting by software has no effect.

• 0 - DCONNI - Device Connection Interrupt

Set by hardware when a new device has been connected to the USB bus.

Shall be cleared by software. Setting by software has no effect.

Bit

7

6

HWUPE

R/W

0

5

HSOFE

R/W

0

4

3

2

RSTE

R/W

0

1

DDISCE

R/W

0

DCONNE

R/W

RXRSME RSMEDE

UHIEN

Read/Write

Initial Value

R

0

R/W

0

R/W

0

• 7 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 6 - HWUPE - Host Wake-Up Interrupt Enable

Set this bit to enable HWUP interrupt.

Clear this bit to disable HWUP interrupt.

• 5 - HSOFE - Host Start Of frame Interrupt Enable

Set this bit to enable HSOF interrupt.

Clear this bit to disable HSOF interrupt.

• 4 - RXRSME -Upstream Resume Received Interrupt Enable

Set this bit to enable the RXRSMI interrupt.

Clear this bit to disable the RXRSMI interrupt.

• 3 - RSMEDE - Downstream Resume Sent Interrupt Enable

Set this bit to enable the RSMEDI interrupt.

Clear this bit to disable the RSMEDI interrupt.

• 2 - RSTE - USB Reset Sent Interrupt Enable

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Set this bit to enable the RSTI interrupt.

Clear this bit to disable the RSTI interrupt.

• 1 - DDISCE - Device Disconnection Interrupt Enable

Set this bit to enable the DDISCI interrupt.

Clear this bit to disable the DDISCI interrupt.

• 0 - DCONNE - Device Connection Interrupt Enable

Set this bit to enable the DCONNI interrupt.

Clear this bit to disable the DCONNI interrupt.

Bit

7

6

5

4

3

2

1

0

HADDR6 HADDR5 HADDR4 HADDR3 HADDR2 HADDR1 HADDR0 HADDR6 UHADDR

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• 7 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 6-0 - HADDR6:0 - USB Host Address

These bits contain the address of the USB Device.

Bit

7

-

6

-

5

-

4

-

3

-

2

1

0

FNUM10

FNUM9

FNUM8

UHFNUMH

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

• 7-4 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 3-0 - FNUM10:8 - Frame Number

The value contained in this register is the current SOF number.

This value can be modified by software.

Bit

7

6

5

4

3

2

1

0

FNUM7

FNUM6

FNUM5

FNUM4

FNUM3

FNUM2

FNUM1

FNUM0 UHFNUML

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

• 7-0 - FNUM7:0 - Frame Number

The value contained in this register is the current SOF number.

This value can be modified by software.

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Bit

7

6

5

4

3

2

1

0

FLEN7

FLEN6

FLEN5

FLEN4

FLEN3

FLEN2

FLEN1

FLEN0

UHFLEN

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

• 7-0 - FLEN7:0 - Frame Length

The value contained the data frame length transmited.

23.16.2 USB Host Pipe registers

Bit

7

0

6

0

5

0

4

0

3

0

2

PNUM2

RW

1

PNUM1

RW

0

PNUM0

RW

UPNUM

Read/Write

Initial Value

0

• 7-3 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 2-0 - PNUM2:0 - Pipe Number

Select the pipe using this register. The USB Host registers ended by a X correspond then to this

number.

This number is used for the USB controller following the value of the PNUMD bit.

Bit

7

6

P6RST

RW

5

P5RST

RW

4

P4RST

RW

0

3

P3RST

RW

0

2

P2RST

RW

1

P1RST

RW

0

P0RST

RW

-

UPRST

Read/Write

Initial Value

0

• 7 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 6 - P6RST - Pipe 6 Reset

Set this bit to 1 and reset this bit to 0 to reset the Pipe 6.

• 5 - P5RST - Pipe 5 Reset

Set this bit to 1 and reset this bit to 0 to reset the Pipe 5.

• 4 - P4RST - Pipe 4 Reset

Set this bit to 1 and reset this bit to 0 to reset the Pipe 4.

• 3 - P3RST - Pipe 3 Reset

Set this bit to 1 and reset this bit to 0 to reset the Pipe 3.

• 2 - P2RST - Pipe 2 Reset

Set this bit to 1 and reset this bit to 0 to reset the Pipe 2.

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• 1 - P1RST - Pipe 1 Reset

Set this bit to 1 and reset this bit to 0 to reset the Pipe 1.

• 0 - P0RST - Pipe 0 Reset

Set this bit to 1 and reset this bit to 0 to reset the Pipe 0.

Bit

7

6

5

4

3

RSTDT

RW

2

1

0

PEN

RW

0

-

PFREEZE INMODE

-

UPCONX

Read/Write

Initial Value

RW

0

RW

0

• 7 - Reserved

The value read from this bit is always 0. Do not set this bit.

• 6 - PFREEZE - Pipe Freeze

Set this bit to Freeze the Pipe requests generation.

Clear this bit to enable the Pipe request generation.

This bit is set by hardware when:

- the pipe is not configured

- a STALL handshake has been received on this Pipe

- An error occurs on the Pipe (PERR = 1)

- (INRQ+1) In requests have been processed

This bit is set at 1 by hardware after a Pipe reset or a Pipe enable.

• 5 - INMODE - IN Request mode

Set this bit to allow the USB controller to perform infinite IN requests when the Pipe is not frozen.

Clear this bit to perform a pre-defined number of IN requests. This number is stored in the UIN-

RQX register.

• 4 - Reserved

The value read from this bit is always 0. Do not set this bit.

• 3 - RSTDT - Reset Data Toggle

Set this bit to reset the Data Toggle to its initial value for the current Pipe.

Cleared by hardware when proceed. Clearing by software has no effect.

• 2 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 1 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 0 - PEN - Pipe Enable

Set to enable the Pipe.

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Clear to disable and reset the Pipe.

Bit

7

6

5

4

3

2

1

0

PTYPE1 PTYPE0 PTOKEN1 PTOKEN0 PEPNUM3 PEPNUM2 PEPNUM1 PEPNUM0 UPCFG0X

Read/Write

Initial Value

RW

0

RW

0

RW

0

RW

0

RW

0

RW

0

RW

0

RW

0

• 7-6 - PTYPE1:0 - Pipe Type

Select the type of the Pipe:

- 00: Control

- 01: Isochronous

- 10: Bulk

- 11: Interrupt

• 5-4 - PTOKEN1:0 - Pipe Token

Select the Token to associate to the Pipe

- 00: SETUP

- 01: IN

- 10: OUT

- 11: reserved

• 3-0 - PEPNUM3:0 - Pipe Endpoint Number

Set this field according to the Pipe configuration. Set the number of the Endpoint targeted by the

Pipe. This value is from 0 and 15.

Bit

7

-

6

5

PSIZE2:0

RW

4

3

2

1

ALLOC

RW

0

PBK1:0

-

UPCFG1X

Read/Write

Initial Value

R

0

RW

0

RW

0

RW

0

RW

0

• 7 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 6-4 - PSIZE2:0 - Pipe Size

Select the size of the Pipe:

- 000: 8

- 001: 16

- 010: 32

- 011: 64

- 100: 128

- 101: 256

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- 110: 512

- 111: 1024

• 3-2 - PBK1:0 - Pipe Bank

Select the number of bank to declare for the current Pipe.

- 00: 1 bank

- 01: 2 banks

- 10: invalid

- 11: invalid

• ALLOC

Configure Pipe Memory

Set to configure the pipe memory with the characteristics.

Clear to update the memory allocation. Refer to the Memory Management chapter for more

details.

7 - Reserved

The value read from these bits is always 0. Do not set these bits.

Bit

7

6

5

4

3

2

1

0

INTFRQ7 INTFRQ6 INTFRQ5 INTFRQ4 INTFRQ3 INTFRQ2 INTFRQ1 INTFRQ0 UPCFG2X

Read/Write

Initial Value

RW

0

RW

0

RW

0

RW

0

RW

0

RW

0

RW

0

RW

0

• 7 - INTFRQ7:0 - Interrupt Pipe Request Frequency

These bits are the maximum value in millisecond of the polling period for an Interrupt Pipe.

This value has no effect for a non-Interrupt Pipe.

Bit

7

6

5

4

3

2

1

0

CFGOK

OVERFI UNDERFI

-

DTSEQ1:0

NBUSYBK

UPSTAX

Read/Write

Initial Value

R

0

RW

0

RW

0

R

0

R

0

R

0

R

0

• 7 - CFGOK - Configure Pipe Memory OK

Set by hardware if the required memory configuration has been successfully performed.

Cleared by hardware when the pipe is disabled. The USB reset and the reset pipe have no effect

on the configuration of the pipe.

• 6 - OVERFI - Overflow

Set by hardware when a the current Pipe has received more data than the maximum length of

the current Pipe. An interrupt is triggered if the FLERRE bit is set.

Shall be cleared by software. Setting by software has no effect.

• 5 - UNDERFI - Underflow

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Set by hardware when a transaction underflow occurs in the current isochronous or interrupt

Pipe. The Pipe can’t send the data flow required by the device. A ZLP will be sent instead. An

interrupt is triggered if the FLERRE bit is set.

Shall be cleared by software. Setting by software has no effect.

Note: the Host controller has to send a OUT packet, but the bank is empty. A ZLP will be sent

and the UNDERFI bit is set

underflow for interrupt Pipe:

• 4 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 3-2 - DTSEQ1:0 - Toggle Sequencing Flag

Set by hardware to indicate the PID data of the current bank:

00b Data0

01b Data1

1xb Reserved.

For OUT Pipe, this value indicates the next data toggle that will be sent. This is not relative to the

current bank.

For IN Pipe, this value indicates the last data toggle received on the current bank.

• 1-0 - NBUSYBK1:0 - Busy Bank Flag

Set by hardware to indicate the number of busy bank.

For OUT Pipe, it indicates the number of busy bank(s), filled by the user, ready for OUT transfer.

For IN Pipe, it indicates the number of busy bank(s) filled by IN transaction from the Device.

00b All banks are free

01b 1 busy bank

10b 2 busy banks

11b Reserved.

Bit

7

INRQ7

RW

0

6

INRQ6

RW

0

5

INRQ5

RW

0

4

INRQ4

RW

0

3

INRQ3

RW

0

2

INRQ2

RW

0

1

INRQ1

RW

0

INRQ0

RW

0

UPINRQX

Read/Write

Initial Value

• 7-0 - INRQ7:0 - IN Request Number Before Freeze

Enter the number of IN transactions before the USB controller freezes the pipe. The USB con-

troller will perform (INRQ+1) IN requests before to freeze the Pipe. This counter is automatically

decreased by 1 each time a IN request has been successfully performed.

This register has no effect when the INMODE bit is set (infinite IN requests generation till the

pipe is not frozen).

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Bit

7

6

5

4

CRC16

RW

3

TIMEOUT

RW

2

1

0

-

COUNTER1:0

PID

RW

0

DATAPID DATATGL UPERRX

Read/Write

Initial Value

RW

0

RW

0

RW

0

RW

0

• 7-6 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 5 - COUNTER1:0 - Error counter

This counter is increased by the USB controller each time an error occurs on the Pipe. When this

value reaches 3, the Pipe is automatically frozen.

Clear these bits by software.

• 4 - CRC16 - CRC16 Error

Set by hardware when a CRC16 error has been detected.

Shall be cleared by software. Setting by software has no effect.

• 3 - TIMEOUT - Time-out Error

Set by hardware when a time-out error has been detected.

Shall be cleared by software. Setting by software has no effect.

• 2 - PID - PID Error

Set by hardware when a PID error has been detected.

Shall be cleared by software. Setting by software has no effect.

• 1 - DATAPID - Data PID Error

Set by hardware when a data PID error has been detected.

Shall be cleared by software. Setting by software has no effect.

• 0 - DATATGL - Bad Data Toggle

Set by hardware when a data toggle error has been detected.

Shall be cleared by software. Setting by software has no effect.

Bit

7

6

5

RWAL

RW

0

4

PERRI

RW

0

3

TXSTPI

RW

2

1

0

RXINI

RW

0

FIFOCON NAKEDI

TXOUTI RXSTALLI

UPINTX

Read/Write

Initial Value

RW

0

RW

0

RW

0

RW

0

• 7 - FIFOCON - FIFO Control

For OUT and SETUP Pipe:

Set by hardware when the current bank is free, at the same time than TXOUT or TXSTP.

Clear to send the FIFO data and to switch the bank. Setting by software has no effect.

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For IN Pipe:

Set by hardware when a new IN message is stored in the current bank, at the same time than

RXIN.

Clear to free the current bank and to switch to the following bank. Setting by software has no

effect.

• 6 - NAKEDI - NAK Handshake received

Set by hardware when a NAK has been received on the current bank of the Pipe. This triggers

an interrupt if the NAKEDE bit is set in the UPIENX register.

Shall be clear to handshake the interrupt. Setting by software has no effect.

• 5 - RWAL - Read/Write Allowed

OUT Pipe:

Set by hardware when the firmware can write a new data into the Pipe FIFO.

Cleared by hardware when the current Pipe FIFO is full.

IN Pipe:

Set by hardware when the firmware can read a new data into the Pipe FIFO.

Cleared by hardware when the current Pipe FIFO is empty.

This bit is also cleared by hardware when the RXSTALL or the PERR bit is set

• 4 - PERRI -PIPE Error

Set by hardware when an error occurs on the current bank of the Pipe. This triggers an interrupt

if the PERRE bit is set in the UPIENX register. Refers to the UPERRX register to determine the

source of the error.

Automatically cleared by hardware when the error source bit is cleared.

• 3 - TXSTPI - SETUP Bank ready

Set by hardware when the current SETUP bank is free and can be filled. This triggers an inter-

rupt if the TXSTPE bit is set in the UPIENX register.

Shall be cleared to handshake the interrupt. Setting by software has no effect.

• 2 - TXOUTI -OUT Bank ready

Set by hardware when the current OUT bank is free and can be filled. This triggers an interrupt if

the TXOUTE bit is set in the UPIENX register.

Shall be cleared to handshake the interrupt. Setting by software has no effect.

• 1 - RXSTALLI / CRCERR - STALL Received / Isochronous CRC Error

Set by hardware when a STALL handshake has been received on the current bank of the Pipe.

The Pipe is automatically frozen. This triggers an interrupt if the RXSTALLE bit is set in the UPI-

ENX register.

Shall be cleared to handshake the interrupt. Setting by software has no effect.

For Isochronous Pipe:

Set by hardware when a CRC error occurs on the current bank of the Pipe. This triggers an inter-

rupt if the TXSTPE bit is set in the UPIENX register.

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Shall be cleared to handshake the interrupt. Setting by software has no effect.

• 0 - RXINI - IN Data received

Set by hardware when a new USB message is stored in the current bank of the Pipe. This trig-

gers an interrupt if the RXINE bit is set in the UPIENX register.

Shall be cleared to handshake the interrupt. Setting by software has no effect.

Bit

7

6

5

4

PERRE

RW

3

TXSTPE

RW

2

1

0

RXINE

RW

0

FLERRE NAKEDE

-

TXOUTE RXSTALLE

UPIENX

Read/Write

Initial Value

RW

0

RW

0

RW

0

RW

0

• 7 - FLERRE - Flow Error Interrupt enable

Set to enable the OVERFI and UNDERFI interrupts.

Clear to disable the OVERFI and UNDERFI interrupts.

• 6 - NAKEDE -NAK Handshake Received Interrupt Enable

Set to enable the NAKEDI interrupt.

Clear to disable the NAKEDI interrupt.

• 5 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 4 - PERRE -PIPE Error Interrupt Enable

Set to enable the PERRI interrupt.

Clear to disable the PERRI interrupt.

• 3 - TXSTPE - SETUP Bank ready Interrupt Enable

Set to enable the TXSTPI interrupt.

Clear to disable the TXSTPI interrupt.

• 2 - TXOUTE - OUT Bank ready Interrupt Enable

Set to enable the TXOUTI interrupt.

Clear to disable the TXOUTI interrupt.

• 1 - RXSTALLE - STALL Received Interrupt Enable

Set to enable the RXSTALLI interrupt.

Clear to disable the RXSTALLI interrupt.

• 0 - RXINE - IN Data received Interrupt Enable

Set to enable the RXINI interrupt.

Clear to disable the RXINI interrupt.

Bit

7

6

5

4

3

2

1

0

PDAT7

PDAT6

PDAT5

PDAT4

PDAT3

PDAT2

PDAT1

PDAT0

UPDATX

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Bit

7

RW

0

6

RW

0

5

RW

0

4

RW

0

3

RW

0

2

RW

0

1

RW

0

RW

0

Read/Write

Initial Value

• 7-0 - PDAT7:0 - Pipe Data Bits

Set by the software to read/write a byte from/to the Pipe FIFO selected by PNUM.

Bit

7

6

5

4

3

2

1

0

-

PBYCT10 PBYCT9

PBYCT8

UPBCHX

Read/Write

Initial Value

R

0

R

0

R

0

• 7-3 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 2-0 - PBYCT10:8 - Byte count (high) Bits

Set by hardware. This field is the MSB of the byte count of the FIFO endpoint. The LSB part is

provided by the UPBCLX register.

Bit

7

6

5

4

3

2

1

0

PBYCT7

PBYCT6

PBYCT5

PBYCT4

PBYCT3

PBYCT2

PBYCT1

PBYCT0 UPBCLX

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

• 7-0 - PBYCT7:0 - Byte Count (low) Bits

Set by the hardware. PBYCT10:0 is:

- (for OUT Pipe) increased after each writing into the Pipe and decremented after each byte

sent,

- (for IN Pipe) increased after each byte received by the host, and decremented after each byte

read by the software.

Bit

7

6

5

4

3

2

1

0

-

PINT6

PINT5

PINT4

PINT3

PINT2

PINT1

PINT0

UPINT

Read/Write

Initial Value

0

• 7 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 6-0 - PINT6:0 - Pipe Interrupts Bits

Set by hardware when an interrupt is triggered by the UPINTX register and if the corresponding

endpoint interrupt enable bit is set.

Cleared by hardware when the interrupt source is served.

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24. Analog Comparator

The Analog Comparator compares the input values on the positive pin AIN0 and negative pin

AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin

AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger

the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate

interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on com-

parator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is

shown in Figure 24-1.

The Power Reduction ADC bit, PRADC, in “Power Reduction Register 0 - PRR0” on page 56

must be disabled by writing a logical zero to be able to use the ADC input MUX.

Figure 24-1. Analog Comparator Block Diagram⁽²⁾

BANDGAP

REFERENCE

ACBG

ACME

ADEN

ADC MULTIPLEXER

OUTPUT⁽¹⁾

Notes: 1. See Table 24-2 on page 315.

2. Refer to Figure 1-1 on page 3 and Table 10-6 on page 82 for Analog Comparator pin

placement.

24.0.1

ADC Control and Status Register B – ADCSRB

Bit

7

6

5

4

–

R

0

3

-

2

1

0

–

ACME

–

ADTS2

R/W

0

ADTS1

R/W

0

ADTS0

R/W

0

ADCSRB

Read/Write

Initial Value

R

0

R/W

0

R

0

R

0

• Bit 6 – ACME: Analog Comparator Multiplexer Enable

When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the

ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written

logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed

description of this bit, see “Analog Comparator Multiplexed Input” on page 315.

24.0.2

Analog Comparator Control and Status Register – ACSR

Bit

7

6

5

4

3

2

1

0

ACD

ACBG

ACO

ACI

ACIE

R/W

0

ACIC

R/W

0

ACIS1

R/W

0

ACIS0

R/W

0

ACSR

Read/Write

Initial Value

R/W

0

R/W

0

R

R/W

0

N/A

• Bit 7 – ACD: Analog Comparator Disable

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When this bit is written logic one, the power to the Analog Comparator is switched off. This bit

can be set at any time to turn off the Analog Comparator. This will reduce power consumption in

Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be

disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is

changed.

• Bit 6 – ACBG: Analog Comparator Bandgap Select

When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog

Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Compar-

ator. See “Internal Voltage Reference” on page 64.

• Bit 5 – ACO: Analog Comparator Output

The output of the Analog Comparator is synchronized and then directly connected to ACO. The

synchronization introduces a delay of 1 - 2 clock cycles.

• Bit 4 – ACI: Analog Comparator Interrupt Flag

This bit is set by hardware when a comparator output event triggers the interrupt mode defined

by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set

and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding inter-

rupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Com-

parator interrupt is activated. When written logic zero, the interrupt is disabled.

• Bit 2 – ACIC: Analog Comparator Input Capture Enable

When written logic one, this bit enables the input capture function in Timer/Counter1 to be trig-

gered by the Analog Comparator. The comparator output is in this case directly connected to the

input capture front-end logic, making the comparator utilize the noise canceler and edge select

features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection

between the Analog Comparator and the input capture function exists. To make the comparator

trigger the Timer/Counter1 Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask

Register (TIMSK1) must be set.

• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which comparator events that trigger the Analog Comparator interrupt. The

different settings are shown in Table 24-1.

Table 24-1. ACIS1/ACIS0 Settings

ACIS1

ACIS0

Interrupt Mode

0

1

0

1

0

1

Comparator Interrupt on Output Toggle.

Reserved

Comparator Interrupt on Falling Output Edge.

Comparator Interrupt on Rising Output Edge.

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by

clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the

bits are changed.

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24.1 Analog Comparator Multiplexed Input

It is possible to select any of the ADC15..0 pins to replace the negative input to the Analog Com-

parator. The ADC multiplexer is used to select this input, and consequently, the ADC must be

switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in

ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), and MUX2..0 in

ADMUX select the input pin to replace the negative input to the Analog Comparator, as shown in

Table 24-2. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Ana-

log Comparator.

Table 24-2. Analog Comparator Mulitiplexed Input

ACME

ADEN

MUX2..0

xxx

Analog Comparator Negative Input

0

1

x

1

0

AIN1

xxx

AIN1

000

001

010

011

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

100

101

110

111

24.1.1

Digital Input Disable Register 1 – DIDR1

Bit

7

–

R

0

6

–

R

0

5

–

R

0

4

–

R

0

3

–

R

0

2

–

R

0

1

0

AIN1D

R/W

0

AIN0D

R/W

0

DIDR1

Read/Write

Initial Value

• Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable

When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corre-

sponding PIN Register bit will always read as zero when this bit is set. When an analog signal is

applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ-

ten logic one to reduce power consumption in the digital input buffer.

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25. Analog to Digital Converter - ADC

25.1 Features

• 10-bit Resolution

• 0.5 LSB Integral Non-linearity

• ± 2 LSB Absolute Accuracy

• 65 - 260 µs Conversion Time

• Up to 15 kSPS at Maximum Resolution

• Eight Multiplexed Single Ended Input Channels

• Seven Differential input channels

• Optional Left Adjustment for ADC Result Readout

• 0 - V_CCADC Input Voltage Range

• Selectable 2.56 V ADC Reference Voltage

• Free Running or Single Conversion Mode

• ADC Start Conversion by Auto Triggering on Interrupt Sources

• Interrupt on ADC Conversion Complete

• Sleep Mode Noise Canceler

The AT90USB64/128 features a 10-bit successive approximation ADC. The ADC is connected

to an 8-channel Analog Multiplexer which allows eight single-ended voltage inputs constructed

from the pins of Port A. The single-ended voltage inputs refer to 0V (GND).

The device also supports 16 differential voltage input combinations. Two of the differential inputs

(ADC1, ADC0 and ADC3, ADC2) are equipped with a programmable gain stage, providing

amplification steps of 0 dB (1x), 20 dB (10x), or 46 dB (200x) on the differential input voltage

before the A/D conversion. Seven differential analog input channels share a common negative

terminal (ADC1), while any other ADC input can be selected as the positive input terminal. If 1x

or 10x gain is used, 8-bit resolution can be expected. If 200x gain is used, 7-bit resolution can be

expected.

The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is

held at a constant level during conversion. A block diagram of the ADC is shown in Figure 25-1.

The ADC has a separate analog supply voltage pin, AV_CC. AV_CCmust not differ more than ±

0.3V from V_CC. See the paragraph “ADC Noise Canceler” on page 323 on how to connect this

pin.

Internal reference voltages of nominally 2.56V or AV_CCare provided On-chip. The voltage refer-

ence may be externally decoupled at the AREF pin by a capacitor for better noise performance.

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Figure 25-1. Analog to Digital Converter Block Schematic

ADC CONVERSION

COMPLETE IRQ

INTERRUPT

FLAGS

ADTS[2:0]

8-BIT DATA BUS

15

0

ADC MULTIPLEXER

SELECT (ADMUX)

ADC CTRL. & STATUS

REGISTER (ADCSRA)

ADC DATA REGISTER

(ADCH/ADCL)

TRIGGER

SELECT

MUX DECODER

PRESCALER

START

CONVERSION LOGIC

AVCC

INTERNAL

SAMPLE & HOLD

COMPARATOR

REFERENCE

AREF

GND

10-BIT DAC

-

+

ADHSM

BANDGAP

REFERENCE

ADC7

SINGLE ENDED / DIFFERENTIAL SELECTION

ADC6

POS.

INPUT

ADC MULTIPLEXER

OUTPUT

ADC5

MUX

ADC4

DIFFERENTIAL

AMPLIFIER

ADC3

+

ADC2

-

ADC1

ADC0

NEG.

INPUT

MUX

25.2 Operation

The ADC converts an analog input voltage to a 10-bit digital value through successive approxi-

mation. The minimum value represents GND and the maximum value represents the voltage on

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the AREF pin minus 1 LSB. Optionally, AV_CCor an internal 2.56V reference voltage may be con-

nected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal

voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve

noise immunity.

The analog input channel and differential gain are selected by writing to the MUX bits in

ADMUX. Any of the ADC input pins, as well as GND and a fixed bandgap voltage reference, can

be selected as single ended inputs to the ADC. A selection of ADC input pins can be selected as

positive and negative inputs to the differential amplifier.

The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and

input channel selections will not go into effect until ADEN is set. The ADC does not consume

power when ADEN is cleared, so it is recommended to switch off the ADC before entering power

saving sleep modes.

The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and

ADCL. By default, the result is presented right adjusted, but can optionally be presented left

adjusted by setting the ADLAR bit in ADMUX.

If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read

ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data

Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers

is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is

read, neither register is updated and the result from the conversion is lost. When ADCH is read,

ADC access to the ADCH and ADCL Registers is re-enabled.

The ADC has its own interrupt which can be triggered when a conversion completes. The ADC

access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt

will trigger even if the result is lost.

25.3 Starting a Conversion

A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.

This bit stays high as long as the conversion is in progress and will be cleared by hardware

when the conversion is completed. If a different data channel is selected while a conversion is in

progress, the ADC will finish the current conversion before performing the channel change.

Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is

enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is

selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (See description of the ADTS

bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal,

the ADC prescaler is reset and a conversion is started. This provides a method of starting con-

versions at fixed intervals. If the trigger signal is still set when the conversion completes, a new

conversion will not be started. If another positive edge occurs on the trigger signal during con-

version, the edge will be ignored. Note that an interrupt flag will be set even if the specific

interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus

be triggered without causing an interrupt. However, the interrupt flag must be cleared in order to

trigger a new conversion at the next interrupt event.

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Figure 25-2. ADC Auto Trigger Logic

ADTS[2:0]

PRESCALER

CLK_ADC

START

ADATE

ADIF

SOURCE 1

.

CONVERSION

LOGIC

EDGE

DETECTOR

SOURCE n

ADSC

Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon

as the ongoing conversion has finished. The ADC then operates in Free Running mode, con-

stantly sampling and updating the ADC Data Register. The first conversion must be started by

writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive

conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.

If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to

one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be

read as one during a conversion, independently of how the conversion was started.

25.4 Prescaling and Conversion Timing

Figure 25-3. ADC Prescaler

ADEN

START

Reset

7-BIT ADC PRESCALER

CK

ADPS0

ADPS1

ADPS2

ADC CLOCK SOURCE

By default, the successive approximation circuitry requires an input clock frequency between 50

kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the

input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate. Alter-

natively, setting the ADHSM bit in ADCSRB allows an increased ADC clock frequency at the

expense of higher power consumption.

The ADC module contains a prescaler, which generates an acceptable ADC clock frequency

from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA.

The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit

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in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously

reset when ADEN is low.

When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion

starts at the following rising edge of the ADC clock cycle. See “Differential Channels” on page

321 for details on differential conversion timing.

A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched

on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.

The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conver-

sion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is

complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion

mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new

conversion will be initiated on the first rising ADC clock edge.

When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures

a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold

takes place two ADC clock cycles after the rising edge on the trigger source signal. Three addi-

tional CPU clock cycles are used for synchronization logic.

In Free Running mode, a new conversion will be started immediately after the conversion com-

pletes, while ADSC remains high. For a summary of conversion times, see Table 25-1.

Figure 25-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)

Conversion

Cycle Number

1

2

12

13

14

15

16

17

18

19

20

21

22

23

24

25

1

2

3

ADC Clock

ADEN

ADSC

ADIF

Sign and MSB of Result

ADCH

ADCL

LSB of Result

MUX

MUX and REFS

Update

Conversion

Complete

and REFS

Update

Sample & Hold

Figure 25-5. ADC Timing Diagram, Single Conversion

One Conversion

Next Conversion

1

2

3

4

5

6

7

8

9

10

11

12

13

1

2

3

Cycle Number

ADC Clock

ADSC

ADIF

ADCH

Sign and MSB of Result

LSB of Result

ADCL

Sample & Hold

Conversion

Complete

MUX and REFS

Update

MUX and REFS

Update

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Figure 25-6. ADC Timing Diagram, Auto Triggered Conversion

One Conversion

Next Conversion

1

2

3

4

5

6

7

8

9

10

11

12

13

1

2

Cycle Number

ADC Clock

Trigger

Source

ADATE

ADIF

ADCH

ADCL

Sign and MSB of Result

LSB of Result

Sample &

Hold

Prescaler

Reset

Conversion

Complete

Prescaler

Reset

MUX and REFS

Update

Figure 25-7. ADC Timing Diagram, Free Running Conversion

One Conversion

Next Conversion

11

12

13

1

2

3

4

Cycle Number

ADC Clock

ADSC

ADIF

ADCH

ADCL

Sign and MSB of Result

LSB of Result

Sample & Hold

Conversion

Complete

MUX and REFS

Update

Table 25-1. ADC Conversion Time

Normal

First

Conversion

Conversion,

Single Ended

Auto Triggered

Convertion

Condition

Sample & Hold

(Cycles from Start of Convertion)

14.5

1.5

13

2

Conversion Time

(Cycles)

25

13.5

25.4.1

Differential Channels

When using differential channels, certain aspects of the conversion need to be taken into

consideration.

Differential conversions are synchronized to the internal clock CK_ADC2equal to half the ADC

clock frequency. This synchronization is done automatically by the ADC interface in such a way

that the sample-and-hold occurs at a specific phase of CK_ADC2. A conversion initiated by the

user (i.e., all single conversions, and the first free running conversion) when CK_ADC2is low will

take the same amount of time as a single ended conversion (13 ADC clock cycles from the next

prescaled clock cycle). A conversion initiated by the user when CK_ADC2is high will take 14 ADC

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clock cycles due to the synchronization mechanism. In Free Running mode, a new conversion is

initiated immediately after the previous conversion completes, and since CK_ADC2is high at this

time, all automatically started (i.e., all but the first) Free Running conversions will take 14 ADC

clock cycles.

If differential channels are used and conversions are started by Auto Triggering, the ADC must

be switched off between conversions. When Auto Triggering is used, the ADC prescaler is reset

before the conversion is started. Since the stage is dependent of a stable ADC clock prior to the

conversion, this conversion will not be valid. By disabling and then re-enabling the ADC between

each conversion (writing ADEN in ADCSRA to “0” then to “1”), only extended conversions are

performed. The result from the extended conversions will be valid. See “Prescaling and Conver-

sion Timing” on page 319 for timing details.

The gain stage is optimized for a bandwidth of 4 kHz at all gain settings. Higher frequencies may

be subjected to non-linear amplification. An external low-pass filter should be used if the input

signal contains higher frequency components than the gain stage bandwidth. Note that the ADC

clock frequency is independent of the gain stage bandwidth limitation. E.g. the ADC clock period

may be 6 µs, allowing a channel to be sampled at 12 kSPS, regardless of the bandwidth of this

channel.

25.5 Changing Channel or Reference Selection

The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary

register to which the CPU has random access. This ensures that the channels and reference

selection only takes place at a safe point during the conversion. The channel and reference

selection is continuously updated until a conversion is started. Once the conversion starts, the

channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Con-

tinuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in

ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after

ADSC is written. The user is thus advised not to write new channel or reference selection values

to ADMUX until one ADC clock cycle after ADSC is written.

If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special

care must be taken when updating the ADMUX Register, in order to control which conversion

will be affected by the new settings.

If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the

ADMUX Register is changed in this period, the user cannot tell if the next conversion is based

on the old or the new settings. ADMUX can be safely updated in the following ways:

a. When ADATE or ADEN is cleared.

b. During conversion, minimum one ADC clock cycle after the trigger event.

c. After a conversion, before the interrupt flag used as trigger source is cleared.

When updating ADMUX in one of these conditions, the new settings will affect the next ADC

conversion.

Special care should be taken when changing differential channels. Once a differential channel

has been selected, the stage may take as much as 125 µs to stabilize to the new value. Thus

conversions should not be started within the first 125 µs after selecting a new differential chan-

nel. Alternatively, conversion results obtained within this period should be discarded.

The same settling time should be observed for the first differential conversion after changing

ADC reference (by changing the REFS1:0 bits in ADMUX).

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The settling time and gain stage bandwidth is independent of the ADHSM bit setting.

25.5.1

ADC Input Channels

When changing channel selections, the user should observe the following guidelines to ensure

that the correct channel is selected:

• In Single Conversion mode, always select the channel before starting the conversion. The

channel selection may be changed one ADC clock cycle after writing one to ADSC. However,

the simplest method is to wait for the conversion to complete before changing the channel

selection.

• In Free Running mode, always select the channel before starting the first conversion. The

channel selection may be changed one ADC clock cycle after writing one to ADSC. However,

the simplest method is to wait for the first conversion to complete, and then change the

channel selection. Since the next conversion has already started automatically, the next

result will reflect the previous channel selection. Subsequent conversions will reflect the new

channel selection.

When switching to a differential gain channel, the first conversion result may have a poor accu-

racy due to the required settling time for the automatic offset cancellation circuitry. The user

should preferably disregard the first conversion result.

25.5.2

ADC Voltage Reference

The reference voltage for the ADC (V_REF) indicates the conversion range for the ADC. Single

ended channels that exceed V_REFwill result in codes close to 0x3FF. V_REFcan be selected as

either AV_CC, internal 2.56V reference, or external AREF pin.

AV_CCis connected to the ADC through a passive switch. The internal 2.56V reference is gener-

ated from the internal bandgap reference (V_BG) through an internal amplifier. In either case, the

external AREF pin is directly connected to the ADC, and the reference voltage can be made

more immune to noise by connecting a capacitor between the AREF pin and ground. V_REFcan

also be measured at the AREF pin with a high impedant voltmeter. Note that V_REFis a high

impedant source, and only a capacitive load should be connected in a system.

If the user has a fixed voltage source connected to the AREF pin, the user may not use the other

reference voltage options in the application, as they will be shorted to the external voltage. If no

external voltage is applied to the AREF pin, the user may switch between AV_CCand 2.56V as

reference selection. The first ADC conversion result after switching reference voltage source

may be inaccurate, and the user is advised to discard this result.

If differential channels are used, the selected reference should not be closer to AV_CCthan indi-

cated in Table 30-5 on page 407.

25.6 ADC Noise Canceler

The ADC features a noise canceler that enables conversion during sleep mode to reduce noise

induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC

Noise Reduction and Idle mode. To make use of this feature, the following procedure should be

used:

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a. Make sure that the ADC is enabled and is not busy converting. Single Conversion

mode must be selected and the ADC conversion complete interrupt must be

enabled.

b. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion

once the CPU has been halted.

c. If no other interrupts occur before the ADC conversion completes, the ADC inter-

rupt will wake up the CPU and execute the ADC Conversion Complete interrupt

routine. If another interrupt wakes up the CPU before the ADC conversion is com-

plete, that interrupt will be executed, and an ADC Conversion Complete interrupt

request will be generated when the ADC conversion completes. The CPU will

remain in active mode until a new sleep command is executed.

Note that the ADC will not be automatically turned off when entering other sleep modes than Idle

mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before enter-

ing such sleep modes to avoid excessive power consumption.

If the ADC is enabled in such sleep modes and the user wants to perform differential conver-

sions, the user is advised to switch the ADC off and on after waking up from sleep to prompt an

extended conversion to get a valid result.

25.6.1

Analog Input Circuitry

The analog input circuitry for single ended channels is illustrated in Figure 25-8. An analog

source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regard-

less of whether that channel is selected as input for the ADC. When the channel is selected, the

source must drive the S/H capacitor through the series resistance (combined resistance in the

input path).

The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or

less. If such a source is used, the sampling time will be negligible. If a source with higher imped-

ance is used, the sampling time will depend on how long time the source needs to charge the

S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources

with slowly varying signals, since this minimizes the required charge transfer to the S/H

capacitor.

If differential gain channels are used, the input circuitry looks somewhat different, although

source impedances of a few hundred kΩ or less is recommended.

Signal components higher than the Nyquist frequency (f_ADC/2) should not be present for either

kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised

to remove high frequency components with a low-pass filter before applying the signals as

inputs to the ADC.

Figure 25-8. Analog Input Circuitry

I

IH

ADCn

1..100 kΩ

C

= 14 pF

V

S/H

I

IL

/2

CC

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25.6.2

Analog Noise Canceling Techniques

Digital circuitry inside and outside the device generates EMI which might affect the accuracy of

analog measurements. If conversion accuracy is critical, the noise level can be reduced by

applying the following techniques:

a. Keep analog signal paths as short as possible. Make sure analog tracks run over

the analog ground plane, and keep them well away from high-speed switching digi-

tal tracks.

b. The AV_CCpin on the device should be connected to the digital V_CCsupply voltage

via an LC network as shown in Figure 25-9.

c. Use the ADC noise canceler function to reduce induced noise from the CPU.

d. If any ADC port pins are used as digital outputs, it is essential that these do not

switch while a conversion is in progress.

Figure 25-9. ADC Power Connections

(AD0) PA0 51

VCC

52

GND 53

(ADC7) PF7 54

(ADC6) PF6 55

(ADC5) PF5 56

(ADC4) PF4 57

(ADC3) PF3 58

(ADC2) PF2 59

(ADC1) PF1

(ADC0) PF0

60

61

10μH

62

63

64

AREF

GND

AVCC

100nF

1

Analog Ground Plane

25.6.3

25.6.4

Offset Compensation Schemes

The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential mea-

surements as much as possible. The remaining offset in the analog path can be measured

directly by selecting the same channel for both differential inputs. This offset residue can be then

subtracted in software from the measurement results. Using this kind of software based offset

correction, offset on any channel can be reduced below one LSB.

ADC Accuracy Definitions

An n-bit single-ended ADC converts a voltage linearly between GND and V_REFin 2ⁿsteps

(LSBs). The lowest code is read as 0, and the highest code is read as 2ⁿ-1.

Several parameters describe the deviation from the ideal behavior:

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• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition

(at 0.5 LSB). Ideal value: 0 LSB.

Figure 25-10. Offset Error

Output Code

Ideal ADC

Actual ADC

Offset

Error

V

Input Voltage

REF

• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last

transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum).

Ideal value: 0 LSB

Figure 25-11. Gain Error

Gain

Error

Output Code

Ideal ADC

Actual ADC

V_REF

Input Voltage

• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum

deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0

LSB.

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Figure 25-12. Integral Non-linearity (INL)

Output Code

Ideal ADC

Actual ADC

V_REFInput Voltage

• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval

between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.

Figure 25-13. Differential Non-linearity (DNL)

Output Code

0x3FF

1 LSB

DNL

0x000

0

V

Input Voltage

REF

• Quantization Error: Due to the quantization of the input voltage into a finite number of codes,

a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB.

• Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to

an ideal transition for any code. This is the compound effect of offset, gain error, differential

error, non-linearity, and quantization error. Ideal value: ± 0.5 LSB.

25.7 ADC Conversion Result

After the conversion is complete (ADIF is high), the conversion result can be found in the ADC

Result Registers (ADCL, ADCH).

For single ended conversion, the result is:

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V

⋅ 1023

IN

ADC = --------------------------

V

REF

where V_INis the voltage on the selected input pin and V_REFthe selected voltage reference (see

Table 25-3 on page 330 and Table 25-4 on page 330). 0x000 represents analog ground, and

0x3FF represents the selected reference voltage minus one LSB.

If differential channels are used, the result is:

(V

– V

) ⋅ GAIN ⋅ 512

NEG

POS

ADC = ------------------------------------------------------------------------

V

REF

where V_POSis the voltage on the positive input pin, V_NEGthe voltage on the negative input pin,

GAIN the selected gain factor and V_REFthe selected voltage reference. The result is presented

in two’s complement form, from 0x200 (-512d) through 0x1FF (+511d). Note that if the user

wants to perform a quick polarity check of the result, it is sufficient to read the MSB of the result

(ADC9 in ADCH). If the bit is one, the result is negative, and if this bit is zero, the result is posi-

tive. Figure 25-14 shows the decoding of the differential input range.

Table 82 shows the resulting output codes if the differential input channel pair (ADCn - ADCm) is

selected with a reference voltage of V_REF

.

Figure 25-14. Differential Measurement Range

Output Code

0x1FF

0x000

0

Differential Input

Voltage (Volts)

- V_REF

V_REF

0x3FF

0x200

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Table 25-2. Correlation Between Input Voltage and Output Codes

V_ADCn

Read code

0x1FF

0x1FE

...

Corresponding decimal value

V_ADCm+ V_REF/GAIN

511

510

...

V_ADCm+ 0.999 V_REF/GAIN

V_ADCm+ 0.998 V_REF/GAIN

...

V

_ADCm+ 0.001 V_REF/GAIN

V_ADCm

_ADCm- 0.001 V_REF/GAIN

0x001

0x000

0x3FF

...

1

0

V

-1

...

V_ADCm- 0.999 V_REF/GAIN

0x201

0x200

-511

-512

V_ADCm- V_REF/GAIN

Example 1:

– ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.56V reference, left adjusted result)

– Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV.

– ADCR = 512 * 10 * (300 - 500) / 2560 = -400 = 0x270

– ADCL will thus read 0x00, and ADCH will read 0x9C.

Writing zero to ADLAR right adjusts the result: ADCL = 0x70, ADCH = 0x02.

Example 2:

– ADMUX = 0xFB (ADC3 - ADC2, 1x gain, 2.56V reference, left adjusted result)

– Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV.

– ADCR = 512 * 1 * (300 - 500) / 2560 = -41 = 0x029.

– ADCL will thus read 0x40, and ADCH will read 0x0A.

Writing zero to ADLAR right adjusts the result: ADCL = 0x00, ADCH = 0x29.

25.8 ADC Register Description

25.8.1

ADC Multiplexer Selection Register – ADMUX

Bit

7

REFS1

R/W

0

6

REFS0

R/W

0

5

ADLAR

R/W

0

4

MUX4

R/W

0

3

MUX3

R/W

0

2

MUX2

R/W

0

1

MUX1

R/W

0

MUX0

R/W

0

ADMUX

Read/Write

Initial Value

• Bit 7:6 – REFS1:0: Reference Selection Bits

These bits select the voltage reference for the ADC, as shown in Table 25-3. If these bits are

changed during a conversion, the change will not go in effect until this conversion is complete

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(ADIF in ADCSRA is set). The internal voltage reference options may not be used if an external

reference voltage is being applied to the AREF pin.

Table 25-3. Voltage Reference Selections for ADC

REFS1

REFS0 Voltage Reference Selection

0

1

0

1

0

1

AREF, Internal Vref turned off

AV_CCwith external capacitor on AREF pin

Reserved

Internal 2.56V Voltage Reference with external capacitor on AREF pin

•

Bit 5 – ADLAR: ADC Left Adjust Result

The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.

Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the

ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-

sions. For a complete description of this bit, see “The ADC Data Register – ADCL and ADCH” on

page 332.

• Bits 4:0 – MUX4:0: Analog Channel Selection Bits

The value of these bits selects which combination of analog inputs are connected to the ADC.

These bits also select the gain for the differential channels. See Table 25-4 for details. If these

bits are changed during a conversion, the change will not go in effect until this conversion is

complete (ADIF in ADCSRA is set).

Table 25-4. Input Channel and Gain Selections

Single Ended

MUX4..0 Input

Positive Differential

Input

Negative Differential

Input

Gain

00000

00001

00010

00011

00100

00101

00110

00111

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

N/A

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Table 25-4. Input Channel and Gain Selections (Continued)

Single Ended

MUX4..0 Input

Positive Differential

Input

Negative Differential

Input

ADC0

Gain

10x

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

(ADC0 / ADC0 / 10x)

ADC1

(ADC0 / ADC0 / 200x)

ADC1

200x

10x

(Reserved - ADC2 / ADC2 / 10x)

ADC3

ADC2

(ADC2 / ADC2 / 200x)

ADC3

ADC2

ADC1

200x

1x

ADC0

(ADC1 / ADC1 / 1x)

ADC2

ADC1

ADC2

1x

N/A

ADC3

ADC4

ADC5

ADC6

ADC7

ADC0

ADC1

(ADC2 / ADC2 / 1x)

ADC3

ADC2

1x

ADC4

ADC5

1.1V (V_{Band Gap}

0V (GND)

)

N/A

25.8.2

ADC Control and Status Register A – ADCSRA

Bit

7

ADEN

R/W

0

6

ADSC

R/W

0

5

ADATE

R/W

0

4

ADIF

R/W

0

3

ADIE

R/W

0

2

1

ADPS1

R/W

0

ADPS0

R/W

0

ADPS2

ADCSRA

Read/Write

Initial Value

R/W

0

• Bit 7 – ADEN: ADC Enable

Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the

ADC off while a conversion is in progress, will terminate this conversion.

• Bit 6 – ADSC: ADC Start Conversion

In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode,

write this bit to one to start the first conversion. The first conversion after ADSC has been written

after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled,

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will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initializa-

tion of the ADC.

ADSC will read as one as long as a conversion is in progress. When the conversion is complete,

it returns to zero. Writing zero to this bit has no effect.

• Bit 5 – ADATE: ADC Auto Trigger Enable

When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a con-

version on a positive edge of the selected trigger signal. The trigger source is selected by setting

the ADC Trigger Select bits, ADTS in ADCSRB.

• Bit 4 – ADIF: ADC Interrupt Flag

This bit is set when an ADC conversion completes and the Data Registers are updated. The

ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set.

ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alter-

natively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-

Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI

instructions are used.

• Bit 3 – ADIE: ADC Interrupt Enable

When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter-

rupt is activated.

• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits

These bits determine the division factor between the XTAL frequency and the input clock to the

ADC.

Table 25-5. ADC Prescaler Selections

ADPS2

ADPS1

ADPS0

Division Factor

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

16

32

64

128

25.8.3

The ADC Data Register – ADCL and ADCH

25.8.3.1

ADLAR = 0

Bit

15

14

13

12

11

10

9

8

–

ADC9

ADC8

ADCH

ADCL

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

Bit

7

R

0

6

R

0

5

R

0

4

R

0

3

R

0

2

R

0

1

R

0

R

0

Read/Write

Initial Value

0

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25.8.3.2

ADLAR = 1

Bit

15

14

13

12

11

10

9

8

ADC9

ADC8

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADCH

ADCL

ADC1

ADC0

–

5

–

4

–

3

–

2

–

1

–

0

Bit

7

R

0

6

R

0

Read/Write

R

0

R

0

R

0

R

0

R

0

R

0

Initial Value

0

When an ADC conversion is complete, the result is found in these two registers. If differential

channels are used, the result is presented in two’s complement form.

When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if

the result is left adjusted and no more than 8-bit precision (7 bit + sign bit for differential input

channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then

ADCH.

The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from

the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result

is right adjusted.

• ADC9:0: ADC Conversion Result

These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on

page 327.

25.8.4

ADC Control and Status Register B – ADCSRB

Bit

7

ADHSM

R/W

0

6

ACME

R/W

0

5

–

4

–

3

–

2

ADTS2

R/W

0

1

ADTS1

R/W

0

ADTS0

R/W

0

ADCSRB

Read/Write

Initial Value

R

0

R

0

R

0

• Bit 7 – ADHSM: ADC High Speed Mode

Writing this bit to one enables the ADC High Speed mode. This mode enables higher conversion

rate at the expense of higher power consumption.

• Bit 2:0 – ADTS2:0: ADC Auto Trigger Source

If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger

an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion

will be triggered by the rising edge of the selected interrupt flag. Note that switching from a trig-

ger source that is cleared to a trigger source that is set, will generate a positive edge on the

trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running

mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set.

Table 25-6. ADC Auto Trigger Source Selections

ADTS2

ADTS1

ADTS0

Trigger Source

0

1

0

1

0

1

Free Running mode

Analog Comparator

External Interrupt Request 0

Timer/Counter0 Compare Match

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Table 25-6. ADC Auto Trigger Source Selections

ADTS2

ADTS1

ADTS0

Trigger Source

1

0

1

0

1

0

1

Timer/Counter0 Overflow

Timer/Counter1 Compare Match B

Timer/Counter1 Overflow

Timer/Counter1 Capture Event

25.8.5

Digital Input Disable Register 0 – DIDR0

Bit

7

ADC7D

R/W

0

6

ADC6D

R/W

0

5

ADC5D

R/W

0

4

ADC4D

R/W

0

3

ADC3D

R/W

0

2

ADC2D

R/W

0

1

ADC1D

R/W

0

ADC0D

R/W

0

DIDR0

Read/Write

Initial Value

• Bit 7:0 – ADC7D..ADC0D: ADC7:0 Digital Input Disable

When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-

abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an

analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this

bit should be written logic one to reduce power consumption in the digital input buffer.

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26. JTAG Interface and On-chip Debug System

26.0.1

Features

• JTAG (IEEE std. 1149.1 Compliant) Interface

• Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard

• Debugger Access to:

– All Internal Peripheral Units

– Internal and External RAM

– The Internal Register File

– Program Counter

– EEPROM and Flash Memories

• Extensive On-chip Debug Support for Break Conditions, Including

– AVR Break Instruction

– Break on Change of Program Memory Flow

– Single Step Break

– Program Memory Break Points on Single Address or Address Range

– Data Memory Break Points on Single Address or Address Range

• Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• On-chip Debugging Supported by AVR Studio^®

26.1 Overview

The AVR IEEE std. 1149.1 compliant JTAG interface can be used for

• Testing PCBs by using the JTAG Boundary-scan capability

• Programming the non-volatile memories, Fuses and Lock bits

• On-chip debugging

A brief description is given in the following sections. Detailed descriptions for Programming via

the JTAG interface, and using the Boundary-scan Chain can be found in the sections “Program-

ming via the JTAG Interface” on page 387 and “IEEE 1149.1 (JTAG) Boundary-scan” on page

341, respectively. The On-chip Debug support is considered being private JTAG instructions,

and distributed within ATMEL and to selected third party vendors only.

Figure 26-1 shows a block diagram of the JTAG interface and the On-chip Debug system. The

TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller

selects either the JTAG Instruction Register or one of several Data Registers as the scan chain

(Shift Register) between the TDI – input and TDO – output. The Instruction Register holds JTAG

instructions controlling the behavior of a Data Register.

The ID-Register, Bypass Register, and the Boundary-scan Chain are the Data Registers used

for board-level testing. The JTAG Programming Interface (actually consisting of several physical

and virtual Data Registers) is used for serial programming via the JTAG interface. The Internal

Scan Chain and Break Point Scan Chain are used for On-chip debugging only.

26.2 Test Access Port – TAP

The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins

constitute the Test Access Port – TAP. These pins are:

• TMS: Test mode select. This pin is used for navigating through the TAP-controller state

machine.

• TCK: Test Clock. JTAG operation is synchronous to TCK.

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• TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register

(Scan Chains).

• TDO: Test Data Out. Serial output data from Instruction Register or Data Register.

The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not

provided.

When the JTAGEN Fuse is unprogrammed, these four TAP pins are normal port pins, and the

TAP controller is in reset. When programmed, the input TAP signals are internally pulled high

and the JTAG is enabled for Boundary-scan and programming. The device is shipped with this

fuse programmed.

For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is moni-

tored by the debugger to be able to detect external reset sources. The debugger can also pull

the RESET pin low to reset the whole system, assuming only open collectors on the reset line

are used in the application.

Figure 26-1. Block Diagram

I/O PORT 0

DEVICE BOUNDARY

BOUNDARY SCAN CHAIN

TDI

JTAG PROGRAMMING

INTERFACE

TDO

TCK

TMS

TAP

CONTROLLER

AVR CPU

INTERNAL

SCAN

CHAIN

FLASH

MEMORY

Address

Data

PC

Instruction

INSTRUCTION

REGISTER

ID

REGISTER

BREAKPOINT

UNIT

M

U

X

FLOW CONTROL

UNIT

BYPASS

REGISTER

DIGITAL

PERIPHERAL

UNITS

ANALOG

PERIPHERIAL

UNITS

Analog inputs

BREAKPOINT

SCAN CHAIN

JTAG / AVR CORE

COMMUNICATION

INTERFACE

ADDRESS

DECODER

OCD STATUS

AND CONTROL

Control & Clock lines

I/O PORT n

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Figure 26-2. TAP Controller State Diagram

1

Test-Logic-Reset

0

1

0

Run-Test/Idle

Select-DR Scan

Select-IR Scan

0

1

Capture-DR

Capture-IR

0

Shift-DR

0

Shift-IR

0

1

Exit1-DR

0

1

Exit1-IR

0

Pause-IR

1

Pause-DR

1

0

Exit2-DR

1

Exit2-IR

1

Update-DR

Update-IR

1

0

26.3 TAP Controller

The TAP controller is a 16-state finite state machine that controls the operation of the Boundary-

scan circuitry, JTAG programming circuitry, or On-chip Debug system. The state transitions

depicted in Figure 26-2 depend on the signal present on TMS (shown adjacent to each state

transition) at the time of the rising edge at TCK. The initial state after a Power-on Reset is Test-

Logic-Reset.

As a definition in this document, the LSB is shifted in and out first for all Shift Registers.

Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is:

• At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift

Instruction Register – Shift-IR state. While in this state, shift the four bits of the JTAG

instructions into the JTAG Instruction Register from the TDI input at the rising edge of TCK.

The TMS input must be held low during input of the 3 LSBs in order to remain in the Shift-IR

state. The MSB of the instruction is shifted in when this state is left by setting TMS high.

While the instruction is shifted in from the TDI pin, the captured IR-state 0x01 is shifted out on

the TDO pin. The JTAG Instruction selects a particular Data Register as path between TDI

and TDO and controls the circuitry surrounding the selected Data Register.

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• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched

onto the parallel output from the Shift Register path in the Update-IR state. The Exit-IR,

Pause-IR, and Exit2-IR states are only used for navigating the state machine.

• At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift

Data Register – Shift-DR state. While in this state, upload the selected Data Register

(selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI input

at the rising edge of TCK. In order to remain in the Shift-DR state, the TMS input must be

held low during input of all bits except the MSB. The MSB of the data is shifted in when this

state is left by setting TMS high. While the Data Register is shifted in from the TDI pin, the

parallel inputs to the Data Register captured in the Capture-DR state is shifted out on the

TDO pin.

• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data

Register has a latched parallel-output, the latching takes place in the Update-DR state. The

Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating the state machine.

As shown in the state diagram, the Run-Test/Idle state need not be entered between selecting

JTAG instruction and using Data Registers, and some JTAG instructions may select certain

functions to be performed in the Run-Test/Idle, making it unsuitable as an Idle state.

Note:

Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be

entered by holding TMS high for five TCK clock periods.

For detailed information on the JTAG specification, refer to the literature listed in “Bibliography”

on page 340.

26.4 Using the Boundary-scan Chain

A complete description of the Boundary-scan capabilities are given in the section “IEEE 1149.1

(JTAG) Boundary-scan” on page 341.

26.5 Using the On-chip Debug System

As shown in Figure 26-1, the hardware support for On-chip Debugging consists mainly of

• A scan chain on the interface between the internal AVR CPU and the internal peripheral

units.

• Break Point unit.

• Communication interface between the CPU and JTAG system.

All read or modify/write operations needed for implementing the Debugger are done by applying

AVR instructions via the internal AVR CPU Scan Chain. The CPU sends the result to an I/O

memory mapped location which is part of the communication interface between the CPU and the

JTAG system.

The Break Point Unit implements Break on Change of Program Flow, Single Step Break, two

Program Memory Break Points, and two combined Break Points. Together, the four Break

Points can be configured as either:

• 4 single Program Memory Break Points.

• 3 Single Program Memory Break Point + 1 single Data Memory Break Point.

• 2 single Program Memory Break Points + 2 single Data Memory Break Points.

• 2 single Program Memory Break Points + 1 Program Memory Break Point with mask (“range

Break Point”).

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• 2 single Program Memory Break Points + 1 Data Memory Break Point with mask (“range

Break Point”).

A debugger, like the AVR Studio, may however use one or more of these resources for its inter-

nal purpose, leaving less flexibility to the end-user.

A list of the On-chip Debug specific JTAG instructions is given in “On-chip Debug Specific JTAG

Instructions” on page 339.

The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the

OCDEN Fuse must be programmed and no Lock bits must be set for the On-chip debug system

to work. As a security feature, the On-chip debug system is disabled when either of the LB1 or

LB2 Lock bits are set. Otherwise, the On-chip debug system would have provided a back-door

into a secured device.

The AVR Studio enables the user to fully control execution of programs on an AVR device with

On-chip Debug capability, AVR In-Circuit Emulator, or the built-in AVR Instruction Set Simulator.

AVR Studio^®supports source level execution of Assembly programs assembled with Atmel Cor-

poration’s AVR Assembler and C programs compiled with third party vendors’ compilers.

AVR Studio runs under Microsoft^®Windows^®95/98/2000 and Microsoft Windows NT^®.

For a full description of the AVR Studio, please refer to the AVR Studio User Guide. Only high-

lights are presented in this document.

All necessary execution commands are available in AVR Studio, both on source level and on

disassembly level. The user can execute the program, single step through the code either by

tracing into or stepping over functions, step out of functions, place the cursor on a statement and

execute until the statement is reached, stop the execution, and reset the execution target. In

addition, the user can have an unlimited number of code Break Points (using the BREAK

instruction) and up to two data memory Break Points, alternatively combined as a mask (range)

Break Point.

26.6 On-chip Debug Specific JTAG Instructions

The On-chip debug support is considered being private JTAG instructions, and distributed within

ATMEL and to selected third party vendors only. Instruction opcodes are listed for reference.

26.6.1

26.6.2

26.6.3

26.6.4

PRIVATE0; 0x8

PRIVATE1; 0x9

PRIVATE2; 0xA

PRIVATE3; 0xB

Private JTAG instruction for accessing On-chip debug system.

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26.7 On-chip Debug Related Register in I/O Memory

26.7.1

On-chip Debug Register – OCDR

Bit

7

6

5

4

3

2

1

0

MSB/IDRD

LSB

R/W

0

OCDR

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The OCDR Register provides a communication channel from the running program in the micro-

controller to the debugger. The CPU can transfer a byte to the debugger by writing to this

location. At the same time, an internal flag; I/O Debug Register Dirty – IDRD – is set to indicate

to the debugger that the register has been written. When the CPU reads the OCDR Register the

7 LSB will be from the OCDR Register, while the MSB is the IDRD bit. The debugger clears the

IDRD bit when it has read the information.

In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR

Register can only be accessed if the OCDEN Fuse is programmed, and the debugger enables

access to the OCDR Register. In all other cases, the standard I/O location is accessed.

Refer to the debugger documentation for further information on how to use this register.

26.8 Using the JTAG Programming Capabilities

Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS, TDI, and

TDO. These are the only pins that need to be controlled/observed to perform JTAG program-

ming (in addition to power pins). It is not required to apply 12V externally. The JTAGEN Fuse

must be programmed and the JTD bit in the MCUCR Register must be cleared to enable the

JTAG Test Access Port.

The JTAG programming capability supports:

• Flash programming and verifying.

• EEPROM programming and verifying.

• Fuse programming and verifying.

• Lock bit programming and verifying.

The Lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or LB2 are

programmed, the OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a

security feature that ensures no back-door exists for reading out the content of a secured

device.

The details on programming through the JTAG interface and programming specific JTAG

instructions are given in the section “Programming via the JTAG Interface” on page 387.

26.9 Bibliography

For more information about general Boundary-scan, the following literature can be consulted:

• IEEE: IEEE Std. 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan

Architecture, IEEE, 1993.

• Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-Wesley,

1992.

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27. IEEE 1149.1 (JTAG) Boundary-scan

27.1 Features

• JTAG (IEEE std. 1149.1 compliant) Interface

• Boundary-scan Capabilities According to the JTAG Standard

• Full Scan of all Port Functions as well as Analog Circuitry having Off-chip Connections

• Supports the Optional IDCODE Instruction

• Additional Public AVR_RESET Instruction to Reset the AVR

27.2 System Overview

The Boundary-scan chain has the capability of driving and observing the logic levels on the digi-

tal I/O pins, as well as the boundary between digital and analog logic for analog circuitry having

off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by

the TDI/TDO signals to form a long Shift Register. An external controller sets up the devices to

drive values at their output pins, and observe the input values received from other devices. The

controller compares the received data with the expected result. In this way, Boundary-scan pro-

vides a mechanism for testing interconnections and integrity of components on Printed Circuits

Boards by using the four TAP signals only.

The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRE-

LOAD, and EXTEST, as well as the AVR specific public JTAG instruction AVR_RESET can be

used for testing the Printed Circuit Board. Initial scanning of the Data Register path will show the

ID-Code of the device, since IDCODE is the default JTAG instruction. It may be desirable to

have the AVR device in reset during test mode. If not reset, inputs to the device may be deter-

mined by the scan operations, and the internal software may be in an undetermined state when

exiting the test mode. Entering reset, the outputs of any port pin will instantly enter the high

impedance state, making the HIGHZ instruction redundant. If needed, the BYPASS instruction

can be issued to make the shortest possible scan chain through the device. The device can be

set in the reset state either by pulling the external RESET pin low, or issuing the AVR_RESET

instruction with appropriate setting of the Reset Data Register.

The EXTEST instruction is used for sampling external pins and loading output pins with data.

The data from the output latch will be driven out on the pins as soon as the EXTEST instruction

is loaded into the JTAG IR-Register. Therefore, the SAMPLE/PRELOAD should also be used for

setting initial values to the scan ring, to avoid damaging the board when issuing the EXTEST

instruction for the first time. SAMPLE/PRELOAD can also be used for taking a snapshot of the

external pins during normal operation of the part.

The JTAGEN Fuse must be programmed and the JTD bit in the I/O Register MCUCR must be

cleared to enable the JTAG Test Access Port.

When using the JTAG interface for Boundary-scan, using a JTAG TCK clock frequency higher

than the internal chip frequency is possible. The chip clock is not required to run.

27.3 Data Registers

The Data Registers relevant for Boundary-scan operations are:

• Bypass Register

• Device Identification Register

• Reset Register

• Boundary-scan Chain

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7593D–AVR–07/06

27.3.1

27.3.2

Bypass Register

The Bypass Register consists of a single Shift Register stage. When the Bypass Register is

selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR

controller state. The Bypass Register can be used to shorten the scan chain on a system when

the other devices are to be tested.

Device Identification Register

Figure 27-1 shows the structure of the Device Identification Register.

Figure 27-1. The Format of the Device Identification Register

LSB

MSB

Bit

Device ID

31

28

27

12

11

1

0

Version

Part Number

Manufacturer ID

1

4 bits

16 bits

11 bits

1-bit

27.3.2.1

27.3.2.2

Version

Version is a 4-bit number identifying the revision of the component. The JTAG version number

follows the revision of the device. Revision A is 0x0, revision B is 0x1 and so on.

Part Number

The part number is a 16-bit code identifying the component. The JTAG Part Number for

AT90USB64/128 is listed in Table 27-1.

Table 27-1. AVR JTAG Part Number

Part Number

JTAG Part Number (Hex)

AVR USB

0x9782

27.3.2.3

Manufacturer ID

The Manufacturer ID is a 11-bit code identifying the manufacturer. The JTAG manufacturer ID

for ATMEL is listed in Table 27-2.

Table 27-2. Manufacturer ID

Manufacturer

JTAG Manufactor ID (Hex)

ATMEL

0x01F

27.3.3

Reset Register

The Reset Register is a test Data Register used to reset the part. Since the AVR tri-states Port

Pins when reset, the Reset Register can also replace the function of the unimplemented optional

JTAG instruction HIGHZ.

A high value in the Reset Register corresponds to pulling the external Reset low. The part is

reset as long as there is a high value present in the Reset Register. Depending on the fuse set-

tings for the clock options, the part will remain reset for a reset time-out period (refer to “Clock

Sources” on page 40) after releasing the Reset Register. The output from this Data Register is

not latched, so the reset will take place immediately, as shown in Figure 27-2.

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Figure 27-2. Reset Register

To

TDO

From Other Internal and

External Reset Sources

From

TDI

Internal reset

D

Q

ClockDR · AVR_RESET

27.3.4

Boundary-scan Chain

The Boundary-scan Chain has the capability of driving and observing the logic levels on the dig-

ital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having

off-chip connections.

See “Boundary-scan Chain” on page 345 for a complete description.

27.4 Boundary-scan Specific JTAG Instructions

The Instruction Register is 4-bit wide, supporting up to 16 instructions. Listed below are the

JTAG instructions useful for Boundary-scan operation. Note that the optional HIGHZ instruction

is not implemented, but all outputs with tri-state capability can be set in high-impedant state by

using the AVR_RESET instruction, since the initial state for all port pins is tri-state.

As a definition in this datasheet, the LSB is shifted in and out first for all Shift Registers.

The OPCODE for each instruction is shown behind the instruction name in hex format. The text

describes which Data Register is selected as path between TDI and TDO for each instruction.

27.4.1

EXTEST; 0x0

Mandatory JTAG instruction for selecting the Boundary-scan Chain as Data Register for testing

circuitry external to the AVR package. For port-pins, Pull-up Disable, Output Control, Output

Data, and Input Data are all accessible in the scan chain. For Analog circuits having off-chip

connections, the interface between the analog and the digital logic is in the scan chain. The con-

tents of the latched outputs of the Boundary-scan chain is driven out as soon as the JTAG IR-

Register is loaded with the EXTEST instruction.

The active states are:

• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.

• Shift-DR: The Internal Scan Chain is shifted by the TCK input.

• Update-DR: Data from the scan chain is applied to output pins.

27.4.2

IDCODE; 0x1

Optional JTAG instruction selecting the 32 bit ID-Register as Data Register. The ID-Register

consists of a version number, a device number and the manufacturer code chosen by JEDEC.

This is the default instruction after power-up.

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The active states are:

• Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain.

• Shift-DR: The IDCODE scan chain is shifted by the TCK input.

27.4.3

SAMPLE_PRELOAD; 0x2

Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the

input/output pins without affecting the system operation. However, the output latches are not

connected to the pins. The Boundary-scan Chain is selected as Data Register.

The active states are:

• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.

• Shift-DR: The Boundary-scan Chain is shifted by the TCK input.

• Update-DR: Data from the Boundary-scan chain is applied to the output latches. However,

the output latches are not connected to the pins.

27.4.4

AVR_RESET; 0xC

The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or

releasing the JTAG reset source. The TAP controller is not reset by this instruction. The one bit

Reset Register is selected as Data Register. Note that the reset will be active as long as there is

a logic “one” in the Reset Chain. The output from this chain is not latched.

The active states are:

• Shift-DR: The Reset Register is shifted by the TCK input.

27.4.5

BYPASS; 0xF

Mandatory JTAG instruction selecting the Bypass Register for Data Register.

The active states are:

• Capture-DR: Loads a logic “0” into the Bypass Register.

• Shift-DR: The Bypass Register cell between TDI and TDO is shifted.

27.5 Boundary-scan Related Register in I/O Memory

27.5.1

MCU Control Register – MCUCR

The MCU Control Register contains control bits for general MCU functions.

Bit

7

6

–

R

0

5

–

R

0

4

3

–

R

0

2

–

R

0

1

0

JTD

R/W

0

PUD

R/W

0

IVSEL

R/W

0

IVCE

R/W

0

MCUCR

Read/Write

Initial Value

• Bits 7 – JTD: JTAG Interface Disable

When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this

bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of

the JTAG interface, a timed sequence must be followed when changing this bit: The application

software must write this bit to the desired value twice within four cycles to change its value. Note

that this bit must not be altered when using the On-chip Debug system.

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27.5.2

MCU Status Register – MCUSR

The MCU Status Register provides information on which reset source caused an MCU reset.

Bit

7

–

R

0

6

–

R

0

5

–

R

0

4

3

2

1

0

JTRF

R/W

WDRF

R/W

BORF

R/W

EXTRF

R/W

PORF

R/W

MCUSR

Read/Write

Initial Value

See Bit Description

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by

the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic

zero to the flag.

27.6 Boundary-scan Chain

The Boundary-scan chain has the capability of driving and observing the logic levels on the digi-

tal I/O pins, as well as the boundary between digital and analog logic for analog circuitry having

off-chip connection.

27.6.1

Scanning the Digital Port Pins

Figure 27-3 shows the Boundary-scan Cell for a bi-directional port pin. The pull-up function is

disabled during Boundary-scan when the JTAG IC contains EXTEST or SAMPLE_PRELOAD.

The cell consists of a bi-directional pin cell that combines the three signals Output Control -

OCxn, Output Data - ODxn, and Input Data - IDxn, into only a two-stage Shift Register. The port

and pin indexes are not used in the following description

The Boundary-scan logic is not included in the figures in the datasheet. Figure 27-4 shows a

simple digital port pin as described in the section “I/O-Ports” on page 74. The Boundary-scan

details from Figure 27-3 replaces the dashed box in Figure 27-4.

When no alternate port function is present, the Input Data - ID - corresponds to the PINxn Regis-

ter value (but ID has no synchronizer), Output Data corresponds to the PORT Register, Output

Control corresponds to the Data Direction - DD Register, and the Pull-up Enable - PUExn - cor-

responds to logic expression PUD · DDxn · PORTxn.

Digital alternate port functions are connected outside the dotted box in Figure 27-4 to make the

scan chain read the actual pin value. For analog function, there is a direct connection from the

external pin to the analog circuit. There is no scan chain on the interface between the digital and

the analog circuitry, but some digital control signal to analog circuitry are turned off to avoid driv-

ing contention on the pads.

When JTAG IR contains EXTEST or SAMPLE_PRELOAD the clock is not sent out on the port

pins even if the CKOUT fuse is programmed. Even though the clock is output when the JTAG IR

contains SAMPLE_PRELOAD, the clock is not sampled by the boundary scan.

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Figure 27-3. Boundary-scan Cell for Bi-directional Port Pin with Pull-up Function.

To Next Cell

ShiftDR

EXTEST

Vcc

Pull-up Enable (PUE)

0

1

Output Control (OC)

FF1

Q

LD1

0

1

0

1

D

Q

G

Output Data (OD)

0

1

FF0

Q

LD0

0

1

0

1

D

G

Q

Input Data (ID)

From Last Cell

ClockDR

UpdateDR

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Figure 27-4. General Port Pin Schematic Diagram

See Boundary-scan

Description for Details!

PUExn

PUD

Q

D

DDxn

Q _CLR

WDx

RDx

RESET

OCxn

Q

D

Pxn

PORTxn

ODxn

Q _CLR

WRx

RRx

IDxn

RESET

SLEEP

SYNCHRONIZER

RPx

D

Q

D

L

Q

PINxn

Q

CLK _I/O

PUD:

PULLUP DISABLE

WDx:

RDx:

WRITE DDRx

PUExn:

OCxn:

ODxn:

IDxn:

PULLUP ENABLE for pin Pxn

OUTPUT CONTROL for pin Pxn

OUTPUT DATA to pin Pxn

INPUT DATA from pin Pxn

SLEEP CONTROL

READ DDRx

WRx:

RRx:

WRITE PORTx

READ PORTx REGISTER

READ PORTx PIN

I/O CLOCK

RPx:

SLEEP:

CLK _I/O:

27.6.2

Scanning the RESET Pin

The RESET pin accepts 5V active low logic for standard reset operation, and 12V active high

logic for High Voltage Parallel programming. An observe-only cell as shown in Figure 27-5 is

inserted for the 5V reset signal.

Figure 27-5. Observe-only Cell

To

Cell

From System Pin

To System Logic

FF1

0

1

D

Q

From

ClockDR

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27.7 AT90USB64/128 Boundary-scan Order

Table 27-3 shows the Scan order between TDI and TDO when the Boundary-scan chain is

selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The

scan order follows the pin-out order as far as possible. Therefore, the bits of Port A and Port Fis

scanned in the opposite bit order of the other ports. Exceptions from the rules are the Scan

chains for the analog circuits, which constitute the most significant bits of the scan chain regard-

less of which physical pin they are connected to. In Figure 27-3, PXn. Data corresponds to FF0,

PXn. Control corresponds to FF1, PXn. Bit 4, 5, 6 and 7 of Port F is not in the scan chain, since

these pins constitute the TAP pins when the JTAG is enabled. The USB pads are not included in

the boundary-scan.

Table 27-3. AT90USB64/128 Boundary-scan Order

Bit Number Signal Name

Module

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

PE6.Data

PE6.Control

PE7.Data

Port E

PE7.Control

PE3.Data

PE3.Control

PB0.Data

PB0.Control

PB1.Data

PB1.Control

PB2.Data

PB2.Control

PB3.Data

PB3.Control

PB4.Data

Port B

PB4.Control

PB5.Data

PB5.Control

PB6.Data

PB6.Control

PB7.Data

PB7.Control

PE4.Data

PE4.Control

PE5.Data

PORTE

PE5.Control

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Table 27-3. AT90USB64/128 Boundary-scan Order (Continued)

Bit Number Signal Name Module

Reset Logic (Observe Only)

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

RSTT

PD0.Data

PD0.Control

PD1.Data

PD1.Control

PD2.Data

PD2.Control

PD3.Data

PD3.Control

PD4.Data

Port D

PD4.Control

PD5.Data

PD5.Control

PD6.Data

PD6.Control

PD7.Data

PD7.Control

PE0.Data

PE0.Control

PE1.Data

Port E

PE1.Control

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Table 27-3. AT90USB64/128 Boundary-scan Order (Continued)

Bit Number Signal Name

Module

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

PC0.Data

PC0.Control

PC1.Data

PC1.Control

PC2.Data

PC2.Control

PC3.Data

PC3.Control

PC4.Data

Port C

PC4.Control

PC5.Data

PC5.Control

PC6.Data

PC6.Control

PC7.Data

PC7.Control

PE2.Data

Port E

PE2.Control

PA7.Data

PA7.Control

PA6.Data

PA6.Control

PA5.Data

PA5.Control

PA4.Data

PA4.Control

PA3.Data

Port A

PA3.Control

PA2.Data

PA2.Control

PA1.Data

PA1.Control

PA0.Data

8

PA0.Control

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Table 27-3. AT90USB64/128 Boundary-scan Order (Continued)

Bit Number Signal Name

Module

7

6

5

4

3

2

1

0

PF3.Data

PF3.Control

PF2.Data

PF2.Control

PF1.Data

Port F

PF1.Control

PF0.Data

PF0.Control

27.8 Boundary-scan Description Language Files

Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in

a standard format used by automated test-generation software. The order and function of bits in

the Boundary-scan Data Register are included in this description. BSDL files are available for

AT90USB64/128.

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28. Boot Loader Support – Read-While-Write Self-Programming

The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for

downloading and uploading program code by the MCU itself. This feature allows flexible applica-

tion software updates controlled by the MCU using a Flash-resident Boot Loader program. The

Boot Loader program can use any available data interface and associated protocol to read code

and write (program) that code into the Flash memory, or read the code from the program mem-

ory. The program code within the Boot Loader section has the capability to write into the entire

Flash, including the Boot Loader memory. The Boot Loader can thus even modify itself, and it

can also erase itself from the code if the feature is not needed anymore. The size of the Boot

Loader memory is configurable with fuses and the Boot Loader has two separate sets of Boot

Lock bits which can be set independently. This gives the user a unique flexibility to select differ-

ent levels of protection. General information on SPM and ELPM is provided in See “AVR CPU

Core” on page 10.

28.1 Boot Loader Features

• Read-While-Write Self-Programming

• Flexible Boot Memory Size

• High Security (Separate Boot Lock Bits for a Flexible Protection)

• Separate Fuse to Select Reset Vector

• Optimized Page⁽¹⁾Size

• Code Efficient Algorithm

• Efficient Read-Modify-Write Support

Note:

1. A page is a section in the Flash consisting of several bytes (see Table 29-11 on page 373)

used during programming. The page organization does not affect normal operation.

28.2 Application and Boot Loader Flash Sections

The Flash memory is organized in two main sections, the Application section and the Boot

Loader section (see Figure 28-2). The size of the different sections is configured by the

BOOTSZ Fuses as shown in Table 28-8 on page 366 and Figure 28-2. These two sections can

have different level of protection since they have different sets of Lock bits.

28.2.1

28.2.2

Application Section

The Application section is the section of the Flash that is used for storing the application code.

The protection level for the Application section can be selected by the application Boot Lock bits

(Boot Lock bits 0), see Table 28-2 on page 356. The Application section can never store any

Boot Loader code since the SPM instruction is disabled when executed from the Application

section.

BLS – Boot Loader Section

While the Application section is used for storing the application code, the The Boot Loader soft-

ware must be located in the BLS since the SPM instruction can initiate a programming when

executing from the BLS only. The SPM instruction can access the entire Flash, including the

BLS itself. The protection level for the Boot Loader section can be selected by the Boot Loader

Lock bits (Boot Lock bits 1), see Table 28-3 on page 356.

28.3 Read-While-Write and No Read-While-Write Flash Sections

Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader soft-

ware update is dependent on which address that is being programmed. In addition to the two

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sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also

divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-While-

Write (NRWW) section. The limit between the RWW- and NRWW sections is given in Table 28-

1 and Figure 28-1 on page 354. The main difference between the two sections is:

• When erasing or writing a page located inside the RWW section, the NRWW section can be

read during the operation.

• When erasing or writing a page located inside the NRWW section, the CPU is halted during

the entire operation.

Note that the user software can never read any code that is located inside the RWW section dur-

ing a Boot Loader software operation. The syntax “Read-While-Write section” refers to which

section that is being programmed (erased or written), not which section that actually is being

read during a Boot Loader software update.

28.3.1

RWW – Read-While-Write Section

If a Boot Loader software update is programming a page inside the RWW section, it is possible

to read code from the Flash, but only code that is located in the NRWW section. During an on-

going programming, the software must ensure that the RWW section never is being read. If the

user software is trying to read code that is located inside the RWW section (i.e., by load program

memory, call, or jump instructions or an interrupt) during programming, the software might end

up in an unknown state. To avoid this, the interrupts should either be disabled or moved to the

Boot Loader section. The Boot Loader section is always located in the NRWW section. The

RWW Section Busy bit (RWWSB) in the Store Program Memory Control and Status Register

(SPMCSR) will be read as logical one as long as the RWW section is blocked for reading. After

a programming is completed, the RWWSB must be cleared by software before reading code

located in the RWW section. See “Store Program Memory Control and Status Register –

SPMCSR” on page 358. for details on how to clear RWWSB.

28.3.2

NRWW – No Read-While-Write Section

The code located in the NRWW section can be read when the Boot Loader software is updating

a page in the RWW section. When the Boot Loader code updates the NRWW section, the CPU

is halted during the entire Page Erase or Page Write operation.

Table 28-1. Read-While-Write Features

Which Section does the Z-

pointer Address During the

Programming?

Which Section Can

be Read During

Programming?

Is the CPU

Halted?

Read-While-Write

Supported?

RWW Section

NRWW Section

None

No

Yes

No

NRWW Section

Yes

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Figure 28-1. Read-While-Write vs. No Read-While-Write

Read-While-Write

(RWW) Section

Z-pointer

Addresses NRWW

Section

Z-pointer

No Read-While-Write

(NRWW) Section

Addresses RWW

Section

CPU is Halted

During the Operation

Code Located in

NRWW Section

Can be Read During

the Operation

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Figure 28-2. Memory Sections

Program Memory

BOOTSZ = '10'

Program Memory

BOOTSZ = '11'

0x0000

Application Flash Section

End RWW

Start NRWW

Application Flash Section

Boot Loader Flash Section

Application Flash Section

Boot Loader Flash Section

End Application

Start Boot Loader

Flashend

Start Boot Loader

Flashend

0x0000

Program Memory

BOOTSZ = '01'

Program Memory

BOOTSZ = '00'

0x0000

Application Flash Section

End RWW, End Application

End RWW

Start NRWW, Start Boot Loader

Start NRWW

Application Flash Section

Boot Loader Flash Section

End Application

Boot Loader Flash Section

Start Boot Loader

Flashend

Note:

1. The parameters in the figure above are given in Table 28-8 on page 366.

28.4 Boot Loader Lock Bits

If no Boot Loader capability is needed, the entire Flash is available for application code. The

Boot Loader has two separate sets of Boot Lock bits which can be set independently. This gives

the user a unique flexibility to select different levels of protection.

The user can select:

• To protect the entire Flash from a software update by the MCU.

• To protect only the Boot Loader Flash section from a software update by the MCU.

• To protect only the Application Flash section from a software update by the MCU.

• Allow software update in the entire Flash.

See Table 28-2 and Table 28-3 for further details. The Boot Lock bits can be set by software and

in Serial or in Parallel Programming mode. They can only be cleared by a Chip Erase command

only. The general Write Lock (Lock Bit mode 2) does not control the programming of the Flash

memory by SPM instruction. Similarly, the general Read/Write Lock (Lock Bit mode 1) does not

control reading nor writing by (E)LPM/SPM, if it is attempted.

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Table 28-2. Boot Lock Bit0 Protection Modes (Application Section)⁽¹⁾

BLB0 Mode BLB02 BLB01 Protection

No restrictions for SPM or (E)LPM accessing the

Application section.

1

2

1

0

SPM is not allowed to write to the Application section.

SPM is not allowed to write to the Application section, and

(E)LPM executing from the Boot Loader section is not

allowed to read from the Application section. If Interrupt

Vectors are placed in the Boot Loader section, interrupts

are disabled while executing from the Application section.

3

4

0

1

(E)LPM executing from the Boot Loader section is not

allowed to read from the Application section. If Interrupt

Vectors are placed in the Boot Loader section, interrupts

are disabled while executing from the Application section.

Note:

1. “1” means unprogrammed, “0” means programmed

Table 28-3. Boot Lock Bit1 Protection Modes (Boot Loader Section)⁽¹⁾

BLB1 Mode BLB12 BLB11 Protection

No restrictions for SPM or (E)LPM accessing the Boot

Loader section.

1

2

1

0

SPM is not allowed to write to the Boot Loader section.

SPM is not allowed to write to the Boot Loader section,

and (E)LPM executing from the Application section is not

allowed to read from the Boot Loader section. If Interrupt

Vectors are placed in the Application section, interrupts

are disabled while executing from the Boot Loader

section.

3

4

0

(E)LPM executing from the Application section is not

allowed to read from the Boot Loader section. If Interrupt

Vectors are placed in the Application section, interrupts

are disabled while executing from the Boot Loader

section.

1

Note:

1. “1” means unprogrammed, “0” means programmed

28.5 Entering the Boot Loader Program

The bootloader can be executed with three different conditions:

28.5.1

28.5.2

Regular application conditions.

A jump or call from the application program. This may be initiated by a trigger such as a com-

mand received via USART, SPI or USB.

Boot Reset Fuse

The Boot Reset Fuse (BOOTRST) can be programmed so that the Reset Vector is pointing to

the Boot Flash start address after a reset. In this case, the Boot Loader is started after a reset.

After the application code is loaded, the program can start executing the application code. Note

that the fuses cannot be changed by the MCU itself. This means that once the Boot Reset Fuse

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is programmed, the Reset Vector will always point to the Boot Loader Reset and the fuse can

only be changed through the serial or parallel programming interface.

Table 28-4. Boot Reset Fuse⁽¹⁾

BOOTRST

Reset Address

1

0

Reset Vector = Application Reset (address 0x0000)

Reset Vector = Boot Loader Reset (see Table 28-8 on page 366)

Note:

1. “1” means unprogrammed, “0” means programmed

28.5.3

External Hardware conditions

The Hardware Boot Enable Fuse (HWBE) can be programmed (See Table 28-5) so that upon

special hardware conditions under reset, the bootloader execution is forced after reset.

Table 28-5. Hardware Boot Enable Fuse⁽¹⁾

HWBE

Reset Address

1

0

ALE/HWB pin can not be used to force Boot Loader execution after reset

ALE/HWB pin is used during reset to force bootloader execution after reset

Note:

1. “1” means unprogrammed, “0” means programmed

When the HWBE fuse is enable the ALE/HWB pin is configured as input during reset and sam-

pled during reset rising edge. When ALE/HWB pin is ‘0’ during reset rising edge, the reset vector

will be set as the Boot Loader Reset address and the Boot Loader will be executed (See Figures

28-3).

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Figure 28-3. Boot Process Description

RESET

t_SHRH

t_HHRH

ALE/HWB

HWBE ?

Ext. Hardware

Conditions ?

BOOTRST ?

Reset Vector = Application Reset

Reset Vector =Boot Lhoader Reset

28.5.4

Store Program Memory Control and Status Register – SPMCSR

The Store Program Memory Control and Status Register contains the control bits needed to con-

trol the Boot Loader operations.

Bit

7

6

5

4

3

2

1

0

SPMIE

R/W

0

RWWSB

SIGRD

R/W

0

RWWSRE

BLBSET

PGWRT

R/W

0

PGERS

R/W

0

SPMEN

R/W

0

SPMCSR

Read/Write

Initial Value

R

0

R/W

0

R/W

0

• Bit 7 – SPMIE: SPM Interrupt Enable

When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM

ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN

bit in the SPMCSR Register is cleared.

• Bit 6 – RWWSB: Read-While-Write Section Busy

When a Self-Programming (Page Erase or Page Write) operation to the RWW section is initi-

ated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section

cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a

Self-Programming operation is completed. Alternatively the RWWSB bit will automatically be

cleared if a page load operation is initiated.

• Bit 5 – SIGRD: Signature Row Read

If this bit is written to one at the same time as SPMEN, the next LPM instruction within three

clock cycles will read a byte from the signature row into the destination register. see “Reading

the Signature Row from Software” on page 363 for details. An SPM instruction within four cycles

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after SIGRD and SPMEN are set will have no effect. This operation is reserved for future use

and should not be used.

• Bit 4 – RWWSRE: Read-While-Write Section Read Enable

When programming (Page Erase or Page Write) to the RWW section, the RWW section is

blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the

user software must wait until the programming is completed (SPMEN will be cleared). Then, if

the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within

four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while

the Flash is busy with a Page Erase or a Page Write (SPMEN is set). If the RWWSRE bit is writ-

ten while the Flash is being loaded, the Flash load operation will abort and the data loaded will

be lost.

• Bit 3 – BLBSET: Boot Lock Bit Set

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock

cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z-

pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the Lock

bit set, or if no SPM instruction is executed within four clock cycles.

An (E)LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCSR

Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the

destination register. See “Reading the Fuse and Lock Bits from Software” on page 363 for

details.

• Bit 2 – PGWRT: Page Write

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock

cycles executes Page Write, with the data stored in the temporary buffer. The page address is

taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit

will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four

clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is

addressed.

• Bit 1 – PGERS: Page Erase

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock

cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The

data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase,

or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire

Page Write operation if the NRWW section is addressed.

• Bit 0 – SPMEN: Store Program Memory Enable

This bit enables the SPM instruction for the next four clock cycles. If written to one together with

either RWWSRE, BLBSET, PGWRT’ or PGERS, the following SPM instruction will have a spe-

cial meaning, see description above. If only SPMEN is written, the following SPM instruction will

store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of

the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction,

or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write,

the SPMEN bit remains high until the operation is completed.

Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower

five bits will have no effect.

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Note:

Only one SPM instruction should be active at any time.

28.6 Addressing the Flash During Self-Programming

The Z-pointer is used to address the SPM commands. The Z pointer consists of the Z-registers

ZL and ZH in the register file, and RAMPZ in the I/O space. The number of bits actually used is

implementation dependent. Note that the RAMPZ register is only implemented when the pro-

gram space is larger than 64K bytes.

Bit

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

RAMPZ

ZH (R31)

ZL (R30)

RAMPZ7

RAMPZ6

RAMPZ5

RAMPZ4

RAMPZ3

RAMPZ2

RAMPZ1

RAMPZ0

Z15

Z7

7

Z14

Z6

6

Z13

Z5

5

Z12

Z4

4

Z11

Z3

3

Z10

Z2

2

Z9

Z1

1

Z8

Z0

0

Since the Flash is organized in pages (see Table 29-11 on page 373), the Program Counter can

be treated as having two different sections. One section, consisting of the least significant bits, is

addressing the words within a page, while the most significant bits are addressing the pages.

This is shown in Figure 28-4. Note that the Page Erase and Page Write operations are

addressed independently. Therefore it is of major importance that the Boot Loader software

addresses the same page in both the Page Erase and Page Write operation. Once a program-

ming operation is initiated, the address is latched and the Z-pointer can be used for other

operations.

The (E)LPM instruction use the Z-pointer to store the address. Since this instruction addresses

the Flash byte-by-byte, also bit Z0 of the Z-pointer is used.

Figure 28-4. Addressing the Flash During SPM⁽¹⁾

BIT 23

ZPCMSB

PCMSB

ZPAGEMSB

1

0

Z - POINTER

PAGEMSB

PROGRAM COUNTER

PCPAGE

PCWORD

PAGE ADDRESS

WITHIN THE FLASH

WORD ADDRESS

WITHIN A PAGE

PROGRAM MEMORY

PAGE

INSTRUCTION WORD

PCWORD[PAGEMSB:0]:

00

01

02

PAGEEND

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Note:

1. The different variables used in Figure 28-4 are listed in Table 28-10 on page 367.

28.7 Self-Programming the Flash

The program memory is updated in a page by page fashion. Before programming a page with

the data stored in the temporary page buffer, the page must be erased. The temporary page

buffer is filled one word at a time using SPM and the buffer can be filled either before the Page

Erase command or between a Page Erase and a Page Write operation:

Alternative 1, fill the buffer before a Page Erase

• Fill temporary page buffer

• Perform a Page Erase

• Perform a Page Write

Alternative 2, fill the buffer after Page Erase

• Perform a Page Erase

• Fill temporary page buffer

• Perform a Page Write

If only a part of the page needs to be changed, the rest of the page must be stored (for example

in the temporary page buffer) before the erase, and then be rewritten. When using alternative 1,

the Boot Loader provides an effective Read-Modify-Write feature which allows the user software

to first read the page, do the necessary changes, and then write back the modified data. If alter-

native 2 is used, it is not possible to read the old data while loading since the page is already

erased. The temporary page buffer can be accessed in a random sequence. It is essential that

the page address used in both the Page Erase and Page Write operation is addressing the

same page. See “Simple Assembly Code Example for a Boot Loader” on page 364 for an

assembly code example.

28.7.1

Performing Page Erase by SPM

To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and

execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.

The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will

be ignored during this operation.

• Page Erase to the RWW section: The NRWW section can be read during the Page Erase.

• Page Erase to the NRWW section: The CPU is halted during the operation.

28.7.2

Filling the Temporary Buffer (Page Loading)

To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write

“00000001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The

content of PCWORD in the Z-register is used to address the data in the temporary buffer. The

temporary buffer will auto-erase after a Page Write operation or by writing the RWWSRE bit in

SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than

one time to each address without erasing the temporary buffer.

If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be

lost.

28.7.3

Performing a Page Write

To execute Page Write, set up the address in the Z-pointer, write “X0000101” to SPMCSR and

execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.

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The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to

zero during this operation.

• Page Write to the RWW section: The NRWW section can be read during the Page Write.

• Page Write to the NRWW section: The CPU is halted during the operation.

28.7.4

28.7.5

28.7.6

Using the SPM Interrupt

If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the

SPMEN bit in SPMCSR is cleared. This means that the interrupt can be used instead of polling

the SPMCSR Register in software. When using the SPM interrupt, the Interrupt Vectors should

be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is

blocked for reading. How to move the interrupts is described in “Interrupts” on page 70.

Consideration While Updating BLS

Special care must be taken if the user allows the Boot Loader section to be updated by leaving

Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the

entire Boot Loader, and further software updates might be impossible. If it is not necessary to

change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to

protect the Boot Loader software from any internal software changes.

Prevent Reading the RWW Section During Self-Programming

During Self-Programming (either Page Erase or Page Write), the RWW section is always

blocked for reading. The user software itself must prevent that this section is addressed during

the self programming operation. The RWWSB in the SPMCSR will be set as long as the RWW

section is busy. During Self-Programming the Interrupt Vector table should be moved to the BLS

as described in “Interrupts” on page 70, or the interrupts must be disabled. Before addressing

the RWW section after the programming is completed, the user software must clear the

RWWSB by writing the RWWSRE. See “Simple Assembly Code Example for a Boot Loader” on

page 364 for an example.

28.7.7

Setting the Boot Loader Lock Bits by SPM

To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR

and execute SPM within four clock cycles after writing SPMCSR. The only accessible Lock bits

are the Boot Lock bits that may prevent the Application and Boot Loader section from any soft-

ware update by the MCU.

Bit

7

6

5

4

3

2

1

0

R0

1

BLB12

BLB11

BLB02

BLB01

1

See Table 28-2 and Table 28-3 for how the different settings of the Boot Loader bits affect the

Flash access.

If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an

SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCSR.

The Z-pointer is don’t care during this operation, but for future compatibility it is recommended to

load the Z-pointer with 0x0001 (same as used for reading the lO_ckbits). For future compatibility it

is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing the Lock bits. When pro-

gramming the Lock bits the entire Flash can be read during the operation.

28.7.8

362

EEPROM Write Prevents Writing to SPMCSR

Note that an EEPROM write operation will block all software programming to Flash. Reading the

Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It

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AT90USB64/128

is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies

that the bit is cleared before writing to the SPMCSR Register.

28.7.9

Reading the Fuse and Lock Bits from Software

It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the

Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR. When an (E)LPM

instruction is executed within three CPU cycles after the BLBSET and SPMEN bits are set in

SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET and

SPMEN bits will auto-clear upon completion of reading the Lock bits or if no (E)LPM instruction

is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles.

When BLBSET and SPMEN are cleared, (E)LPM will work as described in the Instruction set

Manual.

Bit

Rd

7

6

5

4

3

2

1

0

–

BLB12

BLB11

BLB02

BLB01

LB2

LB1

The algorithm for reading the Fuse Low byte is similar to the one described above for reading

the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET

and SPMEN bits in SPMCSR. When an (E)LPM instruction is executed within three cycles after

the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will

be loaded in the destination register as shown below. Refer to Table 29-5 on page 370 for a

detailed description and mapping of the Fuse Low byte.

Bit

Rd

7

6

5

4

3

2

1

0

FLB7

FLB6

FLB5

FLB4

FLB3

FLB2

FLB1

FLB0

Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an (E)LPM

instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the

SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination register as

shown below. Refer to Table 29-4 on page 370 for detailed description and mapping of the Fuse

High byte.

Bit

Rd

7

6

5

4

3

2

1

0

FHB7

FHB6

FHB5

FHB4

FHB3

FHB2

FHB1

FHB0

When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an (E)LPM instruc-

tion is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR,

the value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown

below. Refer to Table 29-3 on page 369 for detailed description and mapping of the Extended

Fuse byte.

Bit

Rd

7

6

5

4

3

2

1

0

–

EFB2

EFB1

EFB0

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are

unprogrammed, will be read as one.

28.7.10 Reading the Signature Row from Software

To read the Signature Row from software, load the Z-pointer with the signature byte address

given in Table 28-6 on page 364 and set the SIGRD and SPMEN bits in SPMCSR. When an

LPM instruction is executed within three CPU cycles after the SIGRD and SPMEN bits are set in

SPMCSR, the signature byte value will be loaded in the destination register. The SIGRD and

SPMEN bits will auto-clear upon completion of reading the Signature Row Lock bits or if no LPM

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instruction is executed within three CPU cycles. When SIGRD and SPMEN are cleared, LPM will

work as described in the Instruction set Manual.

Table 28-6. Signature Row Addressing

Signature Byte

Z-Pointer Address

0x0000

Device Signature Byte 1

Device Signature Byte 2

Device Signature Byte 3

RC Oscillator Calibration Byte

0x0002

0x0004

0x0001

Note:

All other addresses are reserved for future use.

28.7.11 Preventing Flash Corruption

During periods of low V_CC, the Flash program can be corrupted because the supply voltage is

too low for the CPU and the Flash to operate properly. These issues are the same as for board

level systems using the Flash, and the same design solutions should be applied.

A Flash program corruption can be caused by two situations when the voltage is too low. First, a

regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,

the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions

is too low.

Flash corruption can easily be avoided by following these design recommendations (one is

sufficient):

1. If there is no need for a Boot Loader update in the system, program the Boot Loader

Lock bits to prevent any Boot Loader software updates.

2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.

This can be done by enabling the internal Brown-out Detector (BOD) if the operating

voltage matches the detection level. If not, an external low V_CCreset protection circuit

can be used. If a reset occurs while a write operation is in progress, the write operation

will be completed provided that the power supply voltage is sufficient.

3. Keep the AVR core in Power-down sleep mode during periods of low V_CC. This will pre-

vent the CPU from attempting to decode and execute instructions, effectively protecting

the SPMCSR Register and thus the Flash from unintentional writes.

28.7.12 Programming Time for Flash when Using SPM

The calibrated RC Oscillator is used to time Flash accesses. Table 28-7 shows the typical pro-

gramming time for Flash accesses from the CPU.

Table 28-7. SPM Programming Time

Symbol

Min Programming Time Max Programming Time

Flash write (Page Erase, Page Write,

and write Lock bits by SPM)

3.7 ms 4.5 ms

28.7.13 Simple Assembly Code Example for a Boot Loader

;-the routine writes one page of data from RAM to Flash

; the first data location in RAM is pointed to by the Y pointer

; the first data location in Flash is pointed to by the Z-pointer

;-error handling is not included

;-the routine must be placed inside the Boot space

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; (at least the Do_spm sub routine). Only code inside NRWW section can

; be read during Self-Programming (Page Erase and Page Write).

;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),

; loophi (r25), spmcrval (r20)

; storing and restoring of registers is not included in the routine

; register usage can be optimized at the expense of code size

;-It is assumed that either the interrupt table is moved to the Boot

; loader section or that the interrupts are disabled.

.equ PAGESIZEB = PAGESIZE*2

.org SMALLBOOTSTART

Write_page:

;PAGESIZEB is page size in BYTES, not words

; Page Erase

ldi spmcrval, (1<<PGERS) | (1<<SPMEN)

call Do_spm

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)

call Do_spm

; transfer data from RAM to Flash page buffer

ldi looplo, low(PAGESIZEB)

;init loop variable

ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256

Wrloop:

ld

r0, Y+

r1, Y+

ldi spmcrval, (1<<SPMEN)

call Do_spm

adiw ZH:ZL, 2

sbiw loophi:looplo, 2

brne Wrloop

;use subi for PAGESIZEB<=256

; execute Page Write

subi ZL, low(PAGESIZEB)

sbci ZH, high(PAGESIZEB)

;restore pointer

;not required for PAGESIZEB<=256

ldi spmcrval, (1<<PGWRT) | (1<<SPMEN)

call Do_spm

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)

call Do_spm

; read back and check, optional

ldi looplo, low(PAGESIZEB)

;init loop variable

ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256

subi YL, low(PAGESIZEB)

sbci YH, high(PAGESIZEB)

Rdloop:

;restore pointer

elpm r0, Z+

ld

r1, Y+

cpse r0, r1

jmp Error

sbiw loophi:looplo, 1

brne Rdloop

;use subi for PAGESIZEB<=256

; return to RWW section

; verify that RWW section is safe to read

Return:

in

temp1, SPMCSR

sbrs temp1, RWWSB

; If RWWSB is set, the RWW section is not ready yet

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ret

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)

call Do_spm

rjmp Return

Do_spm:

; check for previous SPM complete

Wait_spm:

in

temp1, SPMCSR

sbrc temp1, SPMEN

rjmp Wait_spm

; input: spmcrval determines SPM action

; disable interrupts if enabled, store status

in

temp2, SREG

cli

; check that no EEPROM write access is present

Wait_ee:

sbic EECR, EEPE

rjmp Wait_ee

; SPM timed sequence

out SPMCSR, spmcrval

spm

; restore SREG (to enable interrupts if originally enabled)

out SREG, temp2

ret

28.7.14 AT90USB64/128 Boot Loader Parameters

In Table 28-8 through Table 28-10, the parameters used in the description of the Self-Program-

ming are given.

Table 28-8. Boot Size Configuration (Word Addresses)⁽¹⁾

1

0

1

0

1

0

1

0

1

0

1

0

512 words

1024 words

2048 words

4096 words

512 words

1024 words

2048 words

4096 words

4

8

0x0000 - 0x7DFF

0x0000 - 0x7BFF

0x7E00 - 0x7FFF

0x7C00 - 0x7FFF

0x7800 - 0x7FFF

0x7000 - 0x7FFF

0xFE00 - 0xFFFF

0xFC00 - 0xFFFF

0xF800 - 0xFFFF

0xF000 - 0xFFFF

0x7DFF

0x7BFF

0x77FF

0x6FFF

0xFDFF

0xFBFF

0xF7FF

0xEFFF

0x7E00

0x7C00

0x7800

0x7000

0xFE00

0xFC00

0xF800

0xF000

16 0x0000 - 0x77FF

32 0x0000 - 0x6FFF

4

8

0x0000 - 0xFDFF

0x0000 - 0xFBFF

16 0x0000 - 0xF7FF

32 0x0000 - 0xEFFF

Note:

1. The different BOOTSZ Fuse configurations are shown in Figure 28-2

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Table 28-9. Read-While-Write Limit (Word Addresses)⁽¹⁾

Device

Section

Pages

224

32

Address

Read-While-Write section (RWW)

No Read-While-Write section (NRWW)

Read-While-Write section (RWW)

No Read-While-Write section (NRWW)

0x0000 - 0x6FFF

0x7000 - 0x7FFF

0x0000 - 0xEFFF

0xF000 - 0xFFFF

AT90USB64

480

32

AT90USB28

Note:

1. For details about these two section, see “NRWW – No Read-While-Write Section” on page

353 and “RWW – Read-While-Write Section” on page 353.

Table 28-10.

Explanation of different variables used in Figure 28-4 and the mapping to the Z-

pointer

Corresponding

Variable

Z-value

Description⁽¹⁾

Most significant bit in the Program Counter. (The

Program Counter is 17 bits PC[16:0])

PCMSB

16

6

Most significant bit which is used to address the

words within one page (128 words in a page requires

seven bits PC [6:0]).

PAGEMSB

ZPCMSB

Bit in Z-pointer that is mapped to PCMSB. Because

Z0 is not used, the ZPCMSB equals PCMSB + 1.

Z17

Z7

Bit in Z-pointer that is mapped to PCMSB. Because

Z0 is not used, the ZPAGEMSB equals PAGEMSB +

1.

ZPAGEMSB

PCPAGE

Program Counter page address: Page select, for

Page Erase and Page Write

PC[16:7]

PC[6:0]

Z17:Z8

Z7:Z1

Program Counter word address: Word select, for

filling temporary buffer (must be zero during Page

Write operation)

PCWORD

Most significant bit in the program counter. (The program

counter is 16 bits PC[15:0])

PCMSB

15

6

Most significant bit which is used to address the words

within one page (128 words in a page requires 7 bits PC

[6:0]).

PAGEMSB

Bit in Z-register that is mapped to PCMSB. Because Z0 is

not used, the ZPCMSB equals PCMSB + 1.

ZPCMSB

ZPAGEMSB

PCPAGE

Z16

Z7

Bit in Z-register that is mapped to PAGEMSB. Because Z0

is not used, the ZPAGEMSB equals PAGEMSB + 1.

Program counter page address: Page select, for Page

Erase and Page Write.

PC[15:7]

PC[6:0]

Z16:Z7

Program counter word address: Word select, for filling

temporary buffer (must be zero during PAGE WRITE

operation).

PCWORD

Z7:Z1

Note:

1. Z0: should be zero for all SPM commands, byte select for the (E)LPM instruction.

See “Addressing the Flash During Self-Programming” on page 360 for details about the use of

Z-pointer during Self-Programming.

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29. Memory Programming

29.1 Program And Data Memory Lock Bits

The AT90USB64/128 provides six Lock bits which can be left unprogrammed (“1”) or can be pro-

grammed (“0”) to obtain the additional features listed in Table 29-2. The Lock bits can only be

erased to “1” with the Chip Erase command.

Table 29-1. Lock Bit Byte⁽¹⁾

Lock Bit Byte

Bit No

Description

–

Default Value

7

6

5

4

3

2

1

0

1 (unprogrammed)

0 (programmed)

1 (unprogrammed)

0 (programmed)

–

BLB12

Boot Lock bit

Lock bit

BLB11

BLB02

BLB01

LB2

LB1

Lock bit

Note:

Table 29-2. Lock Bit Protection Modes⁽¹⁾⁽²⁾

Memory Lock Bits Protection Type

1. “1” means unprogrammed, “0” means programmed

LB Mode

LB2

LB1

1

No memory lock features enabled.

Further programming of the Flash and EEPROM is

disabled in Parallel and Serial Programming mode. The

Fuse bits are locked in both Serial and Parallel

Programming mode.⁽¹⁾

2

1

0

Further programming and verification of the Flash and

EEPROM is disabled in Parallel and Serial Programming

mode. The Boot Lock bits and Fuse bits are locked in both

Serial and Parallel Programming mode.⁽¹⁾

3

BLB0 Mode BLB02 BLB01

No restrictions for SPM or (E)LPM accessing the

Application section.

1

2

1

0

SPM is not allowed to write to the Application section.

SPM is not allowed to write to the Application section, and

(E)LPM executing from the Boot Loader section is not

allowed to read from the Application section. If Interrupt

Vectors are placed in the Boot Loader section, interrupts

are disabled while executing from the Application section.

3

4

0

1

(E)LPM executing from the Boot Loader section is not

allowed to read from the Application section. If Interrupt

Vectors are placed in the Boot Loader section, interrupts

are disabled while executing from the Application section.

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Table 29-2. Lock Bit Protection Modes⁽¹⁾⁽²⁾(Continued)

Memory Lock Bits

Protection Type

BLB1 Mode BLB12 BLB11

No restrictions for SPM or (E)LPM accessing the Boot

Loader section.

1

2

1

0

SPM is not allowed to write to the Boot Loader section.

SPM is not allowed to write to the Boot Loader section,

and (E)LPM executing from the Application section is not

allowed to read from the Boot Loader section. If Interrupt

Vectors are placed in the Application section, interrupts

are disabled while executing from the Boot Loader

section.

3

0

(E)LPM executing from the Application section is not

allowed to read from the Boot Loader section. If Interrupt

Vectors are placed in the Application section, interrupts

are disabled while executing from the Boot Loader

section.

4

0

1

Notes: 1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.

2. “1” means unprogrammed, “0” means programmed

29.2 Fuse Bits

The AT90USB64/128 has four Fuse bytes. Table 29-3 - Table 29-5 describe briefly the function-

ality of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read

as logical zero, “0”, if they are programmed.

Table 29-3. Extended Fuse Byte

Fuse Low Byte

Bit No

Description

Default Value

–

7

–

1

6

5

4

3

2

1

0

–

1

–

1

–

1

HWBE

Hardware Boot Enable

Brown-out Detector trigger level

0 (programmed)

1 (unprogrammed)

BODLEVEL2⁽¹⁾

BODLEVEL1⁽¹⁾

BODLEVEL0⁽¹⁾

Note:

1. See Table 8-2 on page 62 for BODLEVEL Fuse decoding.

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Table 29-4. Fuse High Byte

Fuse High Byte Bit No Description

Default Value

1 (unprogrammed, OCD

disabled)

OCDEN⁽⁴⁾

7

6

Enable OCD

Enable JTAG

0 (programmed, JTAG

enabled)

JTAGEN

Enable Serial Program and Data

Downloading

0 (programmed, SPI prog.

enabled)

SPIEN⁽¹⁾

WDTON⁽³⁾

EESAVE

5

4

3

Watchdog Timer always on

1 (unprogrammed)

EEPROM memory is preserved

through the Chip Erase

1 (unprogrammed,

EEPROM not preserved)

Select Boot Size (see Table 29-6

for details)

BOOTSZ1

2

0 (programmed)⁽²⁾

Select Boot Size (see Table 29-6

for details)

BOOTSZ0

BOOTRST

1

0

0 (programmed)⁽²⁾

1 (unprogrammed)

Select Reset Vector

Note:

1. The SPIEN Fuse is not accessible in serial programming mode.

2. The default value of BOOTSZ1..0 results in maximum Boot Size. See Table 28-8 on page 366

for details.

3. See “Watchdog Timer Control Register - WDTCSR” on page 67 for details.

4. Never ship a product with the OCDEN Fuse programmed regardless of the setting of Lock bits

and JTAGEN Fuse. A programmed OCDEN Fuse enables some parts of the clock system to

be running in all sleep modes. This may increase the power consumption.

Table 29-5. Fuse Low Byte

Fuse Low Byte

CKDIV8⁽⁴⁾

CKOUT⁽³⁾

SUT1

Bit No

Description

Default Value

7

6

5

4

3

2

1

0

Divide clock by 8

Clock output

0 (programmed)

1 (unprogrammed)

1 (unprogrammed)⁽¹⁾

0 (programmed)⁽¹⁾

0 (programmed)⁽²⁾

1 (unprogrammed)⁽²⁾

0 (programmed)⁽²⁾

Select start-up time

Select Clock source

SUT0

CKSEL3

CKSEL2

CKSEL1

CKSEL0

Note:

1. The default value of SUT1..0 results in maximum start-up time for the default clock source.

See Table 8-1 on page 60 for details.

2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz. See Table 6-1 on

page 40 for details.

3. The CKOUT Fuse allow the system clock to be output on PORTC7. See “Clock Output Buffer”

on page 48 for details.

4. See “System Clock Prescaler” on page 48 for details.

The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if

Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.

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29.2.1

Latching of Fuses

The fuse values are latched when the device enters programming mode and changes of the

fuse values will have no effect until the part leaves Programming mode. This does not apply to

the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on

Power-up in Normal mode.

29.3 Signature Bytes

All Atmel microcontrollers have a three-byte signature code which identifies the device. This

code can be read in both serial and parallel mode, also when the device is locked. The three

bytes reside in a separate address space.

AT90USB64/128 Signature Bytes:

1. 0x000: 0x1E (indicates manufactured by Atmel).

2. 0x001: 0x97 (indicates 128KB Flash memory).

3. 0x002: 0x82 (indicates AT90USBxxxdevice).

29.4 Calibration Byte

The AT90USB64/128 has a byte calibration value for the internal RC Oscillator. This byte

resides in the high byte of address 0x000 in the signature address space. During reset, this byte

is automatically written into the OSCCAL Register to ensure correct frequency of the calibrated

RC Oscillator.

29.5 Parallel Programming Parameters, Pin Mapping, and Commands

This section describes how to parallel program and verify Flash Program memory, EEPROM

Data memory, Memory Lock bits, and Fuse bits in the AT90USB64/128. Pulses are assumed to

be at least 250 ns unless otherwise noted.

29.5.1

Signal Names

In this section, some pins of the AT90USB64/128 are referenced by signal names describing

their functionality during parallel programming, see Figure 29-1 and Table 29-6. Pins not

described in the following table are referenced by pin names.

The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse.

The bit coding is shown in Table 29-9.

When pulsing WR or OE, the command loaded determines the action executed. The different

commands are shown in Table 29-10.

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Figure 29-1. Parallel Programming⁽¹⁾

+5V

RDY/BSY

OE

PD1

PD2

PD3

PD4

PD5

PD6

PD7

VCC

WR

AVCC

BS1

PB7 - PB0

DATA

XA0

XA1

PAGEL

+12 V

BS2

RESET

PA0

XTAL1

GND

Note:

1. Unused Pins should be left floating.

Table 29-6. Pin Name Mapping

Signal Name in

Programming Mode Pin Name

I/O

Function

0: Device is busy programming, 1: Device is

ready for new command.

RDY/BSY

PD1

O

OE

WR

PD2

PD3

PD4

PD5

PD6

PD7

PA0

I

Output Enable (Active low).

Write Pulse (Active low).

Byte Select 1.

I

BS1

I

XA0

I

XTAL Action Bit 0

XA1

I

XTAL Action Bit 1

PAGEL

BS2

Program Memory and EEPROM data Page Load.

Byte Select 2.

I

DATA

PB7-0

I/O

Bi-directional Data bus (Output when OE is low).

Table 29-7. BS2 and BS1 Encoding

Flash /

Flash Data

EEPROM

Address

Loading /

Reading

Fuse

Programming

Reading Fuse

and Lock Bits

BS2

0

BS1

0

Low Byte

High Byte

Low Byte

High Byte

Low Byte

High Byte

Fuse Low Byte

Lockbits

0

1

Extended High

Byte

Extended Fuse

Byte

1

0

1

Reserved

Extended Byte

Reserved

Fuse High Byte

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,

Table 29-8. Pin Values Used to Enter Programming Mode

PAGEL

XA1

Symbol

Value

Prog_enable[3]

Prog_enable[2]

Prog_enable[1]

Prog_enable[0]

0

XA0

BS1

Table 29-9. XA1 and XA0 Enoding

XA1

XA0

Action when XTAL1 is Pulsed

Load Flash or EEPROM Address (High or low address byte

determined by BS2 and BS1).

0

1

0

1

Load Data (High or Low data byte for Flash determined by BS1).

Load Command

No Action, Idle

Table 29-10. Command Byte Bit Encoding

Command Byte

1000 0000

0100 0000

0010 0000

0001 0000

0001 0001

0000 1000

0000 0100

0000 0010

0000 0011

Command Executed

Chip Erase

Write Fuse bits

Write Lock bits

Write Flash

Write EEPROM

Read Signature Bytes and Calibration byte

Read Fuse and Lock bits

Read Flash

Read EEPROM

Table 29-11. No. of Words in a Page and No. of Pages in the Flash

No. of

Flash Size

Page Size PCWORD

PC[6:0]

Pages

PCPAGE

PCMSB

128K words (256K bytes) 128 words

1024

PC[16:7]

16

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Table 29-12. No. of Words in a Page and No. of Pages in the EEPROM

No. of

EEPROM Size

Page Size PCWORD

8 bytes EEA[2:0]

Pages

PCPAGE

EEAMSB

4K bytes

512

EEA[11:3]

11

29.6 Parallel Programming

29.6.1

Enter Programming Mode

The following algorithm puts the device in parallel programming mode:

1. Apply 4.5 - 5.5V between V_CCand GND.

2. Set RESET to “0” and toggle XTAL1 at least six times.

3. Set the Prog_enable pins listed in Table 29-8 on page 373 to “0000” and wait at least

100 ns.

4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after

+12V has been applied to RESET, will cause the device to fail entering programming

mode.

5. Wait at least 50 µs before sending a new command.

29.6.2

Considerations for Efficient Programming

The loaded command and address are retained in the device during programming. For efficient

programming, the following should be considered.

• The command needs only be loaded once when writing or reading multiple memory

locations.

• Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the

EESAVE Fuse is programmed) and Flash after a Chip Erase.

• Address high byte needs only be loaded before programming or reading a new 256 word

window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes

reading.

29.6.3

Chip Erase

The Chip Erase will erase the Flash and EEPROM⁽¹⁾memories plus Lock bits. The Lock bits are

not reset until the program memory has been completely erased. The Fuse bits are not

changed. A Chip Erase must be performed before the Flash and/or EEPROM are

reprogrammed.

Note:

1. The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is programmed.

Load Command “Chip Erase”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “1000 0000”. This is the command for Chip Erase.

4. Give XTAL1 a positive pulse. This loads the command.

5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low.

6. Wait until RDY/BSY goes high before loading a new command.

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29.6.4

Programming the Flash

The Flash is organized in pages, see Table 29-11 on page 373. When programming the Flash,

the program data is latched into a page buffer. This allows one page of program data to be pro-

grammed simultaneously. The following procedure describes how to program the entire Flash

memory:

A. Load Command “Write Flash”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “0001 0000”. This is the command for Write Flash.

4. Give XTAL1 a positive pulse. This loads the command.

B. Load Address Low byte (Address bits 7..0)

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS2, BS1 to “00”. This selects the address low byte.

3. Set DATA = Address low byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the address low byte.

C. Load Data Low Byte

1. Set XA1, XA0 to “01”. This enables data loading.

2. Set DATA = Data low byte (0x00 - 0xFF).

3. Give XTAL1 a positive pulse. This loads the data byte.

D. Load Data High Byte

1. Set BS1 to “1”. This selects high data byte.

2. Set XA1, XA0 to “01”. This enables data loading.

3. Set DATA = Data high byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the data byte.

E. Latch Data

1. Set BS1 to “1”. This selects high data byte.

2. Give PAGEL a positive pulse. This latches the data bytes. (See Figure 29-3 for signal

waveforms)

F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded.

While the lower bits in the address are mapped to words within the page, the higher bits address

the pages within the FLASH. This is illustrated in Figure 29-2 on page 376. Note that if less than

eight bits are required to address words in the page (pagesize < 256), the most significant bit(s)

in the address low byte are used to address the page when performing a Page Write.

G. Load Address High byte (Address bits15..8)

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS2, BS1 to “01”. This selects the address high byte.

3. Set DATA = Address high byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the address high byte.

H. Load Address Extended High byte (Address bits 23..16)

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS2, BS1 to “10”. This selects the address extended high byte.

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3. Set DATA = Address extended high byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the address high byte.

I. Program Page

1. Set BS2, BS1 to “00”

2. Give WR a negative pulse. This starts programming of the entire page of data.

RDY/BSY goes low.

3. Wait until RDY/BSY goes high (See Figure 29-3 for signal waveforms).

J. Repeat B through I until the entire Flash is programmed or until all data has been

programmed.

K. End Page Programming

1. 1. Set XA1, XA0 to “10”. This enables command loading.

2. Set DATA to “0000 0000”. This is the command for No Operation.

3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals

are reset.

Figure 29-2. Addressing the Flash Which is Organized in Pages⁽¹⁾

PCMSB

PAGEMSB

PCWORD

PROGRAM

COUNTER

PCPAGE

PAGE ADDRESS

WITHIN THE FLASH

WORD ADDRESS

WITHIN A PAGE

PROGRAM MEMORY

PAGE

INSTRUCTION WORD

PCWORD[PAGEMSB:0]:

00

01

02

PAGEEND

Note:

1. PCPAGE and PCWORD are listed in Table 29-11 on page 373.

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Figure 29-3. Programming the Flash Waveforms⁽¹⁾

F

A

B

C

D

E

B

C

D

E

G

I

H

0x10

ADDR. LOW

DATA LOW

DATA HIGH

ADDR. LOW DATA LOW

DATA HIGH

ADDR. HIGH

ADDR. EXT.H

XX

DATA

XA1

XA0

BS1

BS2

XTAL1

WR

RDY/BSY

RESET +12V

OE

PAGEL

Note:

1. “XX” is don’t care. The letters refer to the programming description above.

29.6.5

Programming the EEPROM

The EEPROM is organized in pages, see Table 29-12 on page 374. When programming the

EEPROM, the program data is latched into a page buffer. This allows one page of data to be

programmed simultaneously. The programming algorithm for the EEPROM data memory is as

follows (refer to “Programming the Flash” on page 375 for details on Command, Address and

Data loading):

1. A: Load Command “0001 0001”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. C: Load Data (0x00 - 0xFF).

5. E: Latch data (give PAGEL a positive pulse).

K: Repeat 3 through 5 until the entire buffer is filled.

L: Program EEPROM page

1. Set BS2, BS1 to “00”.

2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY

goes low.

3. Wait until to RDY/BSY goes high before programming the next page (See Figure 29-4

for signal waveforms).

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Figure 29-4. Programming the EEPROM Waveforms

K

A

G

B

C

E

B

C

E

L

0x11

ADDR. HIGH

ADDR. LOW

DATA

ADDR. LOW

DATA

XX

DATA

XA1

XA0

BS1

XTAL1

WR

RDY/BSY

RESET +12V

OE

PAGEL

BS2

29.6.6

Reading the Flash

The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on

page 375 for details on Command and Address loading):

1. A: Load Command “0000 0010”.

2. H: Load Address Extended Byte (0x00- 0xFF).

3. G: Load Address High Byte (0x00 - 0xFF).

4. B: Load Address Low Byte (0x00 - 0xFF).

5. Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA.

6. Set BS to “1”. The Flash word high byte can now be read at DATA.

7. Set OE to “1”.

29.6.7

Reading the EEPROM

The algorithm for reading the EEPROM memory is as follows (refer to “Programming the Flash”

on page 375 for details on Command and Address loading):

1. A: Load Command “0000 0011”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA.

5. Set OE to “1”.

29.6.8

Programming the Fuse Low Bits

The algorithm for programming the Fuse Low bits is as follows (refer to “Programming the Flash”

on page 375 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Give WR a negative pulse and wait for RDY/BSY to go high.

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29.6.9

Programming the Fuse High Bits

The algorithm for programming the Fuse High bits is as follows (refer to “Programming the

Flash” on page 375 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Set BS2, BS1 to “01”. This selects high data byte.

4. Give WR a negative pulse and wait for RDY/BSY to go high.

5. Set BS2, BS1 to “00”. This selects low data byte.

29.6.10 Programming the Extended Fuse Bits

The algorithm for programming the Extended Fuse bits is as follows (refer to “Programming the

Flash” on page 375 for details on Command and Data loading):

1. 1. A: Load Command “0100 0000”.

2. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. 3. Set BS2, BS1 to “10”. This selects extended data byte.

4. 4. Give WR a negative pulse and wait for RDY/BSY to go high.

5. 5. Set BS2, BS1 to “00”. This selects low data byte.

Figure 29-5. Programming the FUSES Waveforms

Write Fuse Low byte

Write Fuse high byte

Write Extended Fuse byte

A

C

A

C

A

C

0x40

DATA

XX

0x40

DATA

XX

0x40

DATA

XX

DATA

XA1

XA0

BS1

BS2

XTAL1

WR

RDY/BSY

RESET +12V

OE

PAGEL

29.6.11 Programming the Lock Bits

The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on

page 375 for details on Command and Data loading):

1. A: Load Command “0010 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed

(LB1 and LB2 is programmed), it is not possible to program the Boot Lock bits by any

External Programming mode.

3. Give WR a negative pulse and wait for RDY/BSY to go high.

The Lock bits can only be cleared by executing Chip Erase.

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29.6.12 Reading the Fuse and Lock Bits

The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the Flash”

on page 375 for details on Command loading):

1. A: Load Command “0000 0100”.

2. Set OE to “0”, and BS2, BS1 to “00”. The status of the Fuse Low bits can now be read

at DATA (“0” means programmed).

3. Set OE to “0”, and BS2, BS1 to “11”. The status of the Fuse High bits can now be read

at DATA (“0” means programmed).

4. Set OE to “0”, and BS2, BS1 to “10”. The status of the Extended Fuse bits can now be

read at DATA (“0” means programmed).

5. Set OE to “0”, and BS2, BS1 to “01”. The status of the Lock bits can now be read at

DATA (“0” means programmed).

6. Set OE to “1”.

Figure 29-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read

0

Fuse Low Byte

Extended Fuse Byte

Lock Bits

0

1

0

DATA

BS2

BS1

Fuse High Byte

1

BS2

29.6.13 Reading the Signature Bytes

The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash” on

page 375 for details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte (0x00 - 0x02).

3. Set OE to “0”, and BS to “0”. The selected Signature byte can now be read at DATA.

4. Set OE to “1”.

29.6.14 Reading the Calibration Byte

The algorithm for reading the Calibration byte is as follows (refer to “Programming the Flash” on

page 375 for details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte, 0x00.

3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.

4. Set OE to “1”.

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29.6.15 Parallel Programming Characteristics

Figure 29-7. Parallel Programming Timing, Including some General Timing Requirements

t_XLWL

t_XHXL

XTAL1

t_DVXH

t_XLDX

Data & Contol

(DATA, XA0/1, BS1, BS2)

t_BVPH

t_PLBXt_BVWL

t_WLBX

PAGEL

t_PHPL

t_WLWH

WR

t_PLWL

WLRL

RDY/BSY

t_WLRH

Figure 29-8. Parallel Programming Timing, Loading Sequence with Timing Requirements⁽¹⁾

LOAD DATA

LOAD ADDRESS

(LOW BYTE)

LOAD DATA

(LOW BYTE)

LOAD DATA

(HIGH BYTE)

LOAD ADDRESS

(LOW BYTE)

t_XLPH

t_XLXH

t_PLXH

XTAL1

BS1

PAGEL

DATA

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

XA0

XA1

Note:

1. The timing requirements shown in Figure 29-7 (i.e., t_DVXH, t_XHXL, and t_XLDX) also apply to load-

ing operation.

Figure 29-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with

Timing Requirements⁽¹⁾

LOAD ADDRESS

(LOW BYTE)

READ DATA

(LOW BYTE)

READ DATA

(HIGH BYTE)

LOAD ADDRESS

(LOW BYTE)

t_XLOL

XTAL1

BS1

t_BVDV

t_OLDV

OE

t_OHDZ

ADDR1 (Low Byte)

DATA (High Byte)

DATA

ADDR0 (Low Byte)

DATA (Low Byte)

XA0

XA1

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Note:

1. The timing requirements shown in Figure 29-7 (i.e., t_DVXH, t_XHXL, and t_XLDX) also apply to read-

ing operation.

Table 29-13. Parallel Programming Characteristics, V_CC= 5V ± 10%

Symbol

V_PP

Parameter

Min

Typ

Max

12.5

250

Units

V

Programming Enable Voltage

Programming Enable Current

Data and Control Valid before XTAL1 High

XTAL1 Low to XTAL1 High

XTAL1 Pulse Width High

11.5

I_PP

μA

ns

μs

ms

ns

t_DVXH

t_XLXH

t_XHXL

t_XLDX

t_XLWL

t_XLPH

t_PLXH

t_BVPH

t_PHPL

t_PLBX

t_WLBX

t_PLWL

t_BVWL

t_WLWH

t_WLRL

t_WLRH

t_{WLRH_CE}

t_XLOL

t_BVDV

t_OLDV

t_OHDZ

67

200

150

67

0

Data and Control Hold after XTAL1 Low

XTAL1 Low to WR Low

XTAL1 Low to PAGEL high

PAGEL low to XTAL1 high

BS1 Valid before PAGEL High

PAGEL Pulse Width High

BS1 Hold after PAGEL Low

BS2/1 Hold after WR Low

PAGEL Low to WR Low

0

150

67

150

67

150

0

BS2/1 Valid to WR Low

WR Pulse Width Low

WR Low to RDY/BSY Low

WR Low to RDY/BSY High⁽¹⁾

WR Low to RDY/BSY High for Chip Erase⁽²⁾

XTAL1 Low to OE Low

1

4.5

9

3.7

7.5

0

BS1 Valid to DATA valid

0

250

OE Low to DATA Valid

OE High to DATA Tri-stated

Notes: 1. t_WLRHis valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits

commands.

2.

t_{WLRH_CE}is valid for the Chip Erase command.

29.7 Serial Downloading

Both the Flash and EEPROM memory arrays can be programmed using a serial programming

bus while RESET is pulled to GND. The serial programming interface consists of pins SCK, PDI

(input) and PDO (output). After RESET is set low, the Programming Enable instruction needs to

be executed first before program/erase operations can be executed. NOTE, in Table 29-14 on

page 383, the pin mapping for serial programming is listed. Not all packages use the SPI pins

dedicated for the internal Serial Peripheral Interface - SPI.

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29.8 Serial Programming Pin Mapping

Table 29-14. Pin Mapping Serial Programming

Pins

Symbol

PDI

(TQFP-64)

I/O

Description

PB2

PB3

PB1

I

O

I

Serial Data in

Serial Data out

Serial Clock

PDO

SCK

Figure 29-10. Serial Programming and Verify⁽¹⁾

+1.8 - 5.5V

VCC

+1.8 - 5.5V⁽²⁾

PDI

AVCC

PDO

SCK

XTAL1

RESET

GND

Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the

XTAL1 pin.

2. V_CC- 0.3V < AVCC < V_CC+ 0.3V, however, AVCC should always be within 1.8 - 5.5V

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming

operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase

instruction. The Chip Erase operation turns the content of every memory location in both the

Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods

for the serial clock (SCK) input are defined as follows:

Low: > 2 CPU clock cycles for f_ck< 12 MHz, 3 CPU clock cycles for f_ck>= 12 MHz

High: > 2 CPU clock cycles for f_ck< 12 MHz, 3 CPU clock cycles for f_ck>= 12 MHz

29.8.1

Serial Programming Algorithm

When writing serial data to the AT90USB64/128, data is clocked on the rising edge of SCK.

When reading data from the AT90USB64/128, data is clocked on the falling edge of SCK. See

Figure 29-11 for timing details.

To program and verify the AT90USB64/128 in the serial programming mode, the following

sequence is recommended (See four byte instruction formats in Table 29-16):

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1. Power-up sequence:

Apply power between V_CCand GND while RESET and SCK are set to “0”. In some sys-

tems, the programmer can not guarantee that SCK is held low during power-up. In this

case, RESET must be given a positive pulse of at least two CPU clock cycles duration

after SCK has been set to “0”.

2. Wait for at least 20 ms and enable serial programming by sending the Programming

Enable serial instruction to pin PDI.

3. The serial programming instructions will not work if the communication is out of syn-

chronization. When in sync. the second byte (0x53), will echo back when issuing the

third byte of the Programming Enable instruction. Whether the echo is correct or not, all

four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give

RESET a positive pulse and issue a new Programming Enable command.

4. The Flash is programmed one page at a time. The memory page is loaded one byte at

a time by supplying the 7 LSB of the address and data together with the Load Program

Memory Page instruction. To ensure correct loading of the page, the data low byte must

be loaded before data high byte is applied for a given address. The Program Memory

Page is stored by loading the Write Program Memory Page instruction with the address

lines 15..8. Before issuing this command, make sure the instruction Load Extended

Address Byte has been used to define the MSB of the address. The extended address

byte is stored until the command is re-issued, i.e., the command needs only be issued

for the first page, and when crossing the 64KWord boundary. If polling (RDY/BSY) is not

used, the user must wait at least t_{WD_FLASH}before issuing the next page. (See Table 29-

15.) Accessing the serial programming interface before the Flash write operation com-

pletes can result in incorrect programming.

5. The EEPROM array is programmed one byte at a time by supplying the address and

data together with the appropriate Write instruction. An EEPROM memory location is

first automatically erased before new data is written. If polling is not used, the user must

wait at least t_{WD_EEPROM}before issuing the next byte. (See Table 29-15.) In a chip

erased device, no 0xFFs in the data file(s) need to be programmed.

6. Any memory location can be verified by using the Read instruction which returns the

content at the selected address at serial output PDO. When reading the Flash memory,

use the instruction Load Extended Address Byte to define the upper address byte,

which is not included in the Read Program Memory instruction. The extended address

byte is stored until the command is re-issued, i.e., the command needs only be issued

for the first page, and when crossing the 64KWord boundary.

7. At the end of the programming session, RESET can be set high to commence normal

operation.

8. Power-off sequence (if needed):

Set RESET to “1”.

Turn V_CCpower off.

Table 29-15. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location

Symbol

Minimum Wait Delay

4.5 ms

t_{WD_FLASH}

t_{WD_EEPROM}

t_{WD_ERASE}

9.0 ms

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Figure 29-11. Serial Programming Waveforms

SERIAL DATA INPUT

MSB

LSB

(MOSI)

SERIAL DATA OUTPUT

MSB

(MISO)

SERIAL CLOCK INPUT

(SCK)

SAMPLE

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Table 29-16. Serial Programming Instruction Set

Instruction Format

Byte 2 Byte 3

Instruction

Byte 1

Byte4

Operation

1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after

Programming Enable

Chip Erase

RESET goes low.

1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash.

0100 1101 0000 0000 cccc cccc xxxx xxxx Defines Extended Address Byte for

Read Program Memory and Write

Load Extended Address Byte

Read Program Memory

Program Memory Page.

0010 H000 aaaa aaaa bbbb bbbb oooo oooo Read H (high or low) data o from

Program memory at word address

c:a:b.

0100 H000 xxxx xxxx xxbb bbbb iiii iiii Write H (high or low) data i to Program

Memory page at word address b. Data

low byte must be loaded before Data

high byte is applied within the same

address.

Load Program Memory Page

0100 1100 aaaa aaaa bbxx xxxx xxxx xxxx Write Program Memory Page at

address c:a:b.

Write Program Memory Page

Read EEPROM Memory

Write EEPROM Memory

1010 0000 0000 aaaa bbbb bbbb oooo oooo Read data o from EEPROM memory at

address a:b.

1100 0000 0000 aaaa bbbb bbbb iiii iiii Write data i to EEPROM memory at

address a:b.

1100 0001 0000 0000 0000 00bb iiii iiii Load data i to EEPROM memory page

Load EEPROM Memory

Page (page access)

buffer. After data is loaded, program

EEPROM page.

Write EEPROM Memory

Page (page access)

1100 0010 0000 aaaa bbbb bb00 xxxx xxxx

Write EEPROM page at address a:b.

0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock bits. “0” = programmed, “1”

Read Lock bits

Write Lock bits

= unprogrammed. See Table 29-1 on

page 368 for details.

1010 1100 111x xxxx xxxx xxxx 11ii iiii Write Lock bits. Set bits = “0” to

program Lock bits. See Table 29-1 on

page 368 for details.

Read Signature Byte

Write Fuse bits

0011 0000 000x xxxx xxxx xxbb oooo oooo Read Signature Byte o at address b.

1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to

unprogram.

1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to

Write Fuse High bits

unprogram.

1010 1100 1010 0100 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to

Write Extended Fuse Bits

unprogram. See Table 29-3 on page

369 for details.

0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fuse bits. “0” = programmed, “1”

Read Fuse bits

= unprogrammed.

0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fuse High bits. “0” = pro-

Read Fuse High bits

grammed, “1” = unprogrammed.

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Table 29-16. Serial Programming Instruction Set (Continued)

Instruction Format

Instruction

Byte 1

Byte 2

Byte 3

Byte4

Operation

0101 0000 0000 1000 xxxx xxxx oooo oooo Read Extended Fuse bits. “0” = pro-

grammed, “1” = unprogrammed. See

Read Extended Fuse Bits

Read Calibration Byte

Poll RDY/BSY

Table 29-3 on page 369 for details.

0011 1000 000x xxxx 0000 0000 oooo oooo Read Calibration Byte

1111 0000 0000 0000 xxxx xxxx xxxx xxxo If o = “1”, a programming operation is

still busy. Wait until this bit returns to

“0” before applying another command.

Note:

a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in,

x = don’t care

29.8.2

Serial Programming Characteristics

For characteristics of the Serial Programming module see “SPI Timing Characteristics” on page

405.

29.9 Programming via the JTAG Interface

Programming through the JTAG interface requires control of the four JTAG specific pins: TCK,

TMS, TDI, and TDO. Control of the reset and clock pins is not required.

To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is

default shipped with the fuse programmed. In addition, the JTD bit in MCUCSR must be cleared.

Alternatively, if the JTD bit is set, the external reset can be forced low. Then, the JTD bit will be

cleared after two chip clocks, and the JTAG pins are available for programming. This provides a

means of using the JTAG pins as normal port pins in Running mode while still allowing In-Sys-

tem Programming via the JTAG interface. Note that this technique can not be used when using

the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must be ded-

icated for this purpose.

During programming the clock frequency of the TCK Input must be less than the maximum fre-

quency of the chip. The System Clock Prescaler can not be used to divide the TCK Clock Input

into a sufficiently low frequency.

As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers.

29.9.1

Programming Specific JTAG Instructions

The Instruction Register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions

useful for programming are listed below.

The OPCODE for each instruction is shown behind the instruction name in hex format. The text

describes which Data Register is selected as path between TDI and TDO for each instruction.

The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be

used as an idle state between JTAG sequences. The state machine sequence for changing the

instruction word is shown in Figure 29-12.

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Figure 29-12. State Machine Sequence for Changing the Instruction Word

1

Test-Logic-Reset

0

1

0

Run-Test/Idle

Select-DR Scan

Select-IR Scan

0

1

Capture-DR

Capture-IR

0

Shift-DR

0

Shift-IR

0

1

Exit1-DR

0

1

Exit1-IR

0

1

Pause-DR

1

0

Pause-IR

1

0

Exit2-DR

1

Exit2-IR

1

Update-DR

Update-IR

1

0

29.9.2

AVR_RESET (0xC)

The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking

the device out from the Reset mode. The TAP controller is not reset by this instruction. The one

bit Reset Register is selected as Data Register. Note that the reset will be active as long as there

is a logic “one” in the Reset Chain. The output from this chain is not latched.

The active states are:

• Shift-DR: The Reset Register is shifted by the TCK input.

29.9.3

PROG_ENABLE (0x4)

The AVR specific public JTAG instruction for enabling programming via the JTAG port. The 16-

bit Programming Enable Register is selected as Data Register. The active states are the

following:

• Shift-DR: The programming enable signature is shifted into the Data Register.

• Update-DR: The programming enable signature is compared to the correct value, and

Programming mode is entered if the signature is valid.

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29.9.4

PROG_COMMANDS (0x5)

The AVR specific public JTAG instruction for entering programming commands via the JTAG

port. The 15-bit Programming Command Register is selected as Data Register. The active

states are the following:

• Capture-DR: The result of the previous command is loaded into the Data Register.

• Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous

command and shifting in the new command.

• Update-DR: The programming command is applied to the Flash inputs

• Run-Test/Idle: One clock cycle is generated, executing the applied command

29.9.5

PROG_PAGELOAD (0x6)

The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port.

An 8-bit Flash Data Byte Register is selected as the Data Register. This is physically the 8 LSBs

of the Programming Command Register. The active states are the following:

• Shift-DR: The Flash Data Byte Register is shifted by the TCK input.

• Update-DR: The content of the Flash Data Byte Register is copied into a temporary register.

A write sequence is initiated that within 11 TCK cycles loads the content of the temporary

register into the Flash page buffer. The AVR automatically alternates between writing the low

and the high byte for each new Update-DR state, starting with the low byte for the first

Update-DR encountered after entering the PROG_PAGELOAD command. The Program

Counter is pre-incremented before writing the low byte, except for the first written byte. This

ensures that the first data is written to the address set up by PROG_COMMANDS, and

loading the last location in the page buffer does not make the program counter increment into

the next page.

29.9.6

PROG_PAGEREAD (0x7)

The AVR specific public JTAG instruction to directly capture the Flash content via the JTAG port.

An 8-bit Flash Data Byte Register is selected as the Data Register. This is physically the 8 LSBs

of the Programming Command Register. The active states are the following:

• Capture-DR: The content of the selected Flash byte is captured into the Flash Data Byte

Register. The AVR automatically alternates between reading the low and the high byte for

each new Capture-DR state, starting with the low byte for the first Capture-DR encountered

after entering the PROG_PAGEREAD command. The Program Counter is post-incremented

after reading each high byte, including the first read byte. This ensures that the first data is

captured from the first address set up by PROG_COMMANDS, and reading the last location

in the page makes the program counter increment into the next page.

• Shift-DR: The Flash Data Byte Register is shifted by the TCK input.

29.9.7

Data Registers

The Data Registers are selected by the JTAG instruction registers described in section “Pro-

gramming Specific JTAG Instructions” on page 387. The Data Registers relevant for

programming operations are:

• Reset Register

• Programming Enable Register

• Programming Command Register

• Flash Data Byte Register

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29.9.8

Reset Register

The Reset Register is a Test Data Register used to reset the part during programming. It is

required to reset the part before entering Programming mode.

A high value in the Reset Register corresponds to pulling the external reset low. The part is reset

as long as there is a high value present in the Reset Register. Depending on the Fuse settings

for the clock options, the part will remain reset for a Reset Time-out period (refer to “Clock

Sources” on page 40) after releasing the Reset Register. The output from this Data Register is

not latched, so the reset will take place immediately, as shown in Figure 8-1 on page 60.

29.9.9

Programming Enable Register

The Programming Enable Register is a 16-bit register. The contents of this register is compared

to the programming enable signature, binary code 0b1010_0011_0111_0000. When the con-

tents of the register is equal to the programming enable signature, programming via the JTAG

port is enabled. The register is reset to 0 on Power-on Reset, and should always be reset when

leaving Programming mode.

Figure 29-13. Programming Enable Register

TDI

0xA370

D

Q

A

T

A

Programming Enable

=

ClockDR & PROG_ENABLE

TDO

29.9.10 Programming Command Register

The Programming Command Register is a 15-bit register. This register is used to serially shift in

programming commands, and to serially shift out the result of the previous command, if any. The

JTAG Programming Instruction Set is shown in Table 29-17. The state sequence when shifting

in the programming commands is illustrated in Figure 29-15.

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Figure 29-14. Programming Command Register

TDI

S

T

R

O

B

E

S

Flash

EEPROM

Fuses

A

D

R

E

S

/

Lock Bits

D

A

T

A

TDO

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Table 29-17. JTAG Programming Instruction

Set a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out,

i = data in, x = don’t care

Instruction

TDI Sequence

TDO Sequence

Notes

0100011_10000000

0110001_10000000

0110011_10000000

xxxxxxx_xxxxxxxx

1a. Chip Erase

1b. Poll for Chip Erase Complete

2a. Enter Flash Write

0110011_10000000

0100011_00010000

0001011_cccccccc

0000111_aaaaaaaa

0000011_bbbbbbbb

0010011_iiiiiiii

xxxxxox_xxxxxxxx

xxxxxxx_xxxxxxxx

(2)

2b. Load Address Extended High Byte

2c. Load Address High Byte

2d. Load Address Low Byte

2e. Load Data Low Byte

(10)

2f. Load Data High Byte

0010111_iiiiiiii

0110111_00000000

1110111_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

2g. Latch Data

(1)

0110111_00000000

0110101_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

2h. Write Flash Page

2i. Poll for Page Write Complete

3a. Enter Flash Read

0110111_00000000

0100011_00000010

0001011_cccccccc

0000111_aaaaaaaa

0000011_bbbbbbbb

xxxxxox_xxxxxxxx

xxxxxxx_xxxxxxxx

(2)

3b. Load Address Extended High Byte

3c. Load Address High Byte

3d. Load Address Low Byte

(10)

0110010_00000000

0110110_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

3e. Read Data Low and High Byte

Low byte

High byte

4a. Enter EEPROM Write

4b. Load Address High Byte

4c. Load Address Low Byte

4d. Load Data Byte

0100011_00010001

0000111_aaaaaaaa

0000011_bbbbbbbb

0010011_iiiiiiii

xxxxxxx_xxxxxxxx

(10)

0110111_00000000

1110111_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

4e. Latch Data

(1)

0110011_00000000

0110001_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

4f. Write EEPROM Page

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Table 29-17. JTAG Programming Instruction (Continued)

Set (Continued) a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte,

o = data out, i = data in, x = don’t care

Instruction

TDI Sequence

TDO Sequence

Notes

4g. Poll for Page Write Complete

5a. Enter EEPROM Read

5b. Load Address High Byte

5c. Load Address Low Byte

0110011_00000000

0100011_00000011

0000111_aaaaaaaa

0000011_bbbbbbbb

xxxxxox_xxxxxxxx

xxxxxxx_xxxxxxxx

(2)

(10)

0110011_bbbbbbbb

0110010_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

5d. Read Data Byte

6a. Enter Fuse Write

0100011_01000000

xxxxxxx_xxxxxxxx

6b. Load Data Low Byte⁽⁶⁾

0010011_iiiiiiii

(3)

(1)

0111011_00000000

0111001_00000000

0111011_00000000

xxxxxxx_xxxxxxxx

6c. Write Fuse Extended Byte

6d. Poll for Fuse Write Complete

6e. Load Data Low Byte⁽⁷⁾

0110111_00000000

xxxxxox_xxxxxxxx

(2)

(3)

0010011_iiiiiiii

xxxxxxx_xxxxxxxx

0110111_00000000

0110101_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

6f. Write Fuse High Byte

(1)

6g. Poll for Fuse Write Complete

6h. Load Data Low Byte⁽⁷⁾

0110111_00000000

xxxxxox_xxxxxxxx

(2)

(3)

0010011_iiiiiiii

xxxxxxx_xxxxxxxx

0110011_00000000

0110001_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

6i. Write Fuse Low Byte

(1)

6j. Poll for Fuse Write Complete

7a. Enter Lock Bit Write

7b. Load Data Byte⁽⁹⁾

0110011_00000000

0100011_00100000

0010011_11iiiiii

xxxxxox_xxxxxxxx

xxxxxxx_xxxxxxxx

(2)

(4)

0110011_00000000

0110001_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

7c. Write Lock Bits

(1)

(2)

7d. Poll for Lock Bit Write complete

8a. Enter Fuse/Lock Bit Read

0110011_00000000

0100011_00000100

xxxxxox_xxxxxxxx

xxxxxxx_xxxxxxxx

0111010_00000000

0111011_00000000

xxxxxxx_xxxxxxxx

8b. Read Extended Fuse Byte⁽⁶⁾

8c. Read Fuse High Byte⁽⁷⁾

xxxxxxx_oooooooo

0111110_00000000

0111111_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

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Table 29-17. JTAG Programming Instruction (Continued)

Set (Continued) a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte,

o = data out, i = data in, x = don’t care

Instruction

TDI Sequence

TDO Sequence

Notes

0110010_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

8d. Read Fuse Low Byte⁽⁸⁾

xxxxxxx_oooooooo

0110110_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

8e. Read Lock Bits⁽⁹⁾

(5)

xxxxxxx_xxoooooo

0111010_00000000

0111110_00000000

0110010_00000000

0110110_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

(5)

Fuse Ext. byte

Fuse High byte

Fuse Low byte

Lock bits

8f. Read Fuses and Lock Bits

9a. Enter Signature Byte Read

9b. Load Address Byte

0100011_00001000

xxxxxxx_xxxxxxxx

0000011_bbbbbbbb

0110010_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

9c. Read Signature Byte

xxxxxxx_oooooooo

10a. Enter Calibration Byte Read

10b. Load Address Byte

0100011_00001000

xxxxxxx_xxxxxxxx

0000011_bbbbbbbb

0110110_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

10c. Read Calibration Byte

xxxxxxx_oooooooo

0100011_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

11a. Load No Operation Command

Notes: 1. This command sequence is not required if the seven MSB are correctly set by the previous command sequence (which is

normally the case).

2. Repeat until o = “1”.

3. Set bits to “0” to program the corresponding Fuse, “1” to unprogram the Fuse.

4. Set bits to “0” to program the corresponding Lock bit, “1” to leave the Lock bit unchanged.

5. “0” = programmed, “1” = unprogrammed.

6. The bit mapping for Fuses Extended byte is listed in Table 29-3 on page 369

7. The bit mapping for Fuses High byte is listed in Table 29-4 on page 370

8. The bit mapping for Fuses Low byte is listed in Table 29-5 on page 370

9. The bit mapping for Lock bits byte is listed in Table 29-1 on page 368

10. Address bits exceeding PCMSB and EEAMSB (Table 29-11 and Table 29-12) are don’t care

11. All TDI and TDO sequences are represented by binary digits (0b...).

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Figure 29-15. State Machine Sequence for Changing/Reading the Data Word

1

Test-Logic-Reset

0

1

0

Run-Test/Idle

Select-DR Scan

Select-IR Scan

0

1

Capture-DR

Capture-IR

0

Shift-DR

0

Shift-IR

0

1

Exit1-DR

0

1

Exit1-IR

0

Pause-IR

1

Pause-DR

1

0

Exit2-DR

1

Exit2-IR

1

Update-DR

Update-IR

1

0

29.9.11 Flash Data Byte Register

The Flash Data Byte Register provides an efficient way to load the entire Flash page buffer

before executing Page Write, or to read out/verify the content of the Flash. A state machine sets

up the control signals to the Flash and senses the strobe signals from the Flash, thus only the

data words need to be shifted in/out.

The Flash Data Byte Register actually consists of the 8-bit scan chain and a 8-bit temporary reg-

ister. During page load, the Update-DR state copies the content of the scan chain over to the

temporary register and initiates a write sequence that within 11 TCK cycles loads the content of

the temporary register into the Flash page buffer. The AVR automatically alternates between

writing the low and the high byte for each new Update-DR state, starting with the low byte for the

first Update-DR encountered after entering the PROG_PAGELOAD command. The Program

Counter is pre-incremented before writing the low byte, except for the first written byte. This

ensures that the first data is written to the address set up by PROG_COMMANDS, and loading

the last location in the page buffer does not make the Program Counter increment into the next

page.

During Page Read, the content of the selected Flash byte is captured into the Flash Data Byte

Register during the Capture-DR state. The AVR automatically alternates between reading the

low and the high byte for each new Capture-DR state, starting with the low byte for the first Cap-

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ture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is

post-incremented after reading each high byte, including the first read byte. This ensures that

the first data is captured from the first address set up by PROG_COMMANDS, and reading the

last location in the page makes the program counter increment into the next page.

Figure 29-16. Flash Data Byte Register

STROBES

State

Machine

TDI

ADDRESS

Flash

EEPROM

Fuses

Lock Bits

D

A

T

A

TDO

The state machine controlling the Flash Data Byte Register is clocked by TCK. During normal

operation in which eight bits are shifted for each Flash byte, the clock cycles needed to navigate

through the TAP controller automatically feeds the state machine for the Flash Data Byte Regis-

ter with sufficient number of clock pulses to complete its operation transparently for the user.

However, if too few bits are shifted between each Update-DR state during page load, the TAP

controller should stay in the Run-Test/Idle state for some TCK cycles to ensure that there are at

least 11 TCK cycles between each Update-DR state.

29.9.12 Programming Algorithm

All references below of type “1a”, “1b”, and so on, refer to Table 29-17.

29.9.13 Entering Programming Mode

1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register.

2. Enter instruction PROG_ENABLE and shift 0b1010_0011_0111_0000 in the Program-

ming Enable Register.

29.9.14 Leaving Programming Mode

1. Enter JTAG instruction PROG_COMMANDS.

2. Disable all programming instructions by using no operation instruction 11a.

3. Enter instruction PROG_ENABLE and shift 0b0000_0000_0000_0000 in the program-

ming Enable Register.

4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register.

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29.9.15 Performing Chip Erase

1. Enter JTAG instruction PROG_COMMANDS.

2. Start Chip Erase using programming instruction 1a.

3. Poll for Chip Erase complete using programming instruction 1b, or wait for t_{WLRH_CE}

(refer to Table 29-13 on page 382).

29.9.16 Programming the Flash

Before programming the Flash a Chip Erase must be performed, see “Performing Chip Erase”

on page 397.

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash write using programming instruction 2a.

3. Load address Extended High byte using programming instruction 2b.

4. Load address High byte using programming instruction 2c.

5. Load address Low byte using programming instruction 2d.

6. Load data using programming instructions 2e, 2f and 2g.

7. Repeat steps 5 and 6 for all instruction words in the page.

8. Write the page using programming instruction 2h.

9. Poll for Flash write complete using programming instruction 2i, or wait for t_WLRH(refer to

Table 29-13 on page 382).

10. Repeat steps 3 to 9 until all data have been programmed.

A more efficient data transfer can be achieved using the PROG_PAGELOAD instruction:

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash write using programming instruction 2a.

3. Load the page address using programming instructions 2b, 2c and 2d. PCWORD (refer

to Table 29-11 on page 373) is used to address within one page and must be written as

0.

4. Enter JTAG instruction PROG_PAGELOAD.

5. Load the entire page by shifting in all instruction words in the page byte-by-byte, start-

ing with the LSB of the first instruction in the page and ending with the MSB of the last

instruction in the page. Use Update-DR to copy the contents of the Flash Data Byte

Register into the Flash page location and to auto-increment the Program Counter

before each new word.

6. Enter JTAG instruction PROG_COMMANDS.

7. Write the page using programming instruction 2h.

8. Poll for Flash write complete using programming instruction 2i, or wait for t_WLRH(refer to

Table 29-13 on page 382).

9. Repeat steps 3 to 8 until all data have been programmed.

29.9.17 Reading the Flash

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash read using programming instruction 3a.

3. Load address using programming instructions 3b, 3c and 3d.

4. Read data using programming instruction 3e.

5. Repeat steps 3 and 4 until all data have been read.

A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction:

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1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash read using programming instruction 3a.

3. Load the page address using programming instructions 3b, 3c and 3d. PCWORD (refer

to Table 29-11 on page 373) is used to address within one page and must be written as

0.

4. Enter JTAG instruction PROG_PAGEREAD.

5. Read the entire page (or Flash) by shifting out all instruction words in the page (or

Flash), starting with the LSB of the first instruction in the page (Flash) and ending with

the MSB of the last instruction in the page (Flash). The Capture-DR state both captures

the data from the Flash, and also auto-increments the program counter after each word

is read. Note that Capture-DR comes before the shift-DR state. Hence, the first byte

which is shifted out contains valid data.

6. Enter JTAG instruction PROG_COMMANDS.

7. Repeat steps 3 to 6 until all data have been read.

29.9.18 Programming the EEPROM

Before programming the EEPROM a Chip Erase must be performed, see “Performing Chip

Erase” on page 397.

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable EEPROM write using programming instruction 4a.

3. Load address High byte using programming instruction 4b.

4. Load address Low byte using programming instruction 4c.

5. Load data using programming instructions 4d and 4e.

6. Repeat steps 4 and 5 for all data bytes in the page.

7. Write the data using programming instruction 4f.

8. Poll for EEPROM write complete using programming instruction 4g, or wait for t_WLRH

(refer to Table 29-13 on page 382).

9. Repeat steps 3 to 8 until all data have been programmed.

Note that the PROG_PAGELOAD instruction can not be used when programming the EEPROM.

29.9.19 Reading the EEPROM

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable EEPROM read using programming instruction 5a.

3. Load address using programming instructions 5b and 5c.

4. Read data using programming instruction 5d.

5. Repeat steps 3 and 4 until all data have been read.

Note that the PROG_PAGEREAD instruction can not be used when reading the EEPROM.

29.9.20 Programming the Fuses

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Fuse write using programming instruction 6a.

3. Load data high byte using programming instructions 6b. A bit value of “0” will program

the corresponding fuse, a “1” will unprogram the fuse.

4. Write Fuse High byte using programming instruction 6c.

5. Poll for Fuse write complete using programming instruction 6d, or wait for t_WLRH(refer to

Table 29-13 on page 382).

398

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

6. Load data low byte using programming instructions 6e. A “0” will program the fuse, a

“1” will unprogram the fuse.

7. Write Fuse low byte using programming instruction 6f.

8. Poll for Fuse write complete using programming instruction 6g, or wait for t_WLRH(refer to

Table 29-13 on page 382).

29.9.21 Programming the Lock Bits

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Lock bit write using programming instruction 7a.

3. Load data using programming instructions 7b. A bit value of “0” will program the corre-

sponding lock bit, a “1” will leave the lock bit unchanged.

4. Write Lock bits using programming instruction 7c.

5. Poll for Lock bit write complete using programming instruction 7d, or wait for t_WLRH

(refer to Table 29-13 on page 382).

29.9.22 Reading the Fuses and Lock Bits

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Fuse/Lock bit read using programming instruction 8a.

3. To read all Fuses and Lock bits, use programming instruction 8e.

To only read Fuse High byte, use programming instruction 8b.

To only read Fuse Low byte, use programming instruction 8c.

To only read Lock bits, use programming instruction 8d.

29.9.23 Reading the Signature Bytes

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Signature byte read using programming instruction 9a.

3. Load address 0x00 using programming instruction 9b.

4. Read first signature byte using programming instruction 9c.

5. Repeat steps 3 and 4 with address 0x01 and address 0x02 to read the second and third

signature bytes, respectively.

29.9.24 Reading the Calibration Byte

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Calibration byte read using programming instruction 10a.

3. Load address 0x00 using programming instruction 10b.

4. Read the calibration byte using programming instruction 10c.

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7593D–AVR–07/06

30. Electrical Characteristics

30.1 Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Operating Temperature.................................... -40°C to +85°C

Storage Temperature..................................... -65°C to +150°C

Voltage on any Pin except RESET

with respect to Ground ................................-0.5V to V_CC+0.5V

Voltage on RESET with respect to Ground......-0.5V to +13.0V

Maximum Operating Voltage ............................................ 6.0V

DC Current per I/O Pin ............................................... 40.0 mA

DC Current V_CCand GND Pins................................ 200.0 mA

30.2 DC Characteristics

T_A= -40°C to 85°C, V_CC= 1.8V to 5.5V (unless otherwise noted)

Symbol

Parameter

Condition

Min.⁽⁵⁾

Typ.

Max.⁽⁵⁾

Units

(1)

Input Low Voltage,Except

XTAL1 and Reset pin

V_CC= 1.8V - 2.4V

V_CC= 2.4V - 5.5V

-0.5

0.2V_CC

0.3V_CC

V_IL

V

(1)

Input Low Voltage,

XTAL1 pin

V_IL1

V_IL2

V_CC= 1.8V - 5.5V

-0.5

0.1V_CC

V

Input Low Voltage,

RESET pin

(1)

Input High Voltage,

Except XTAL1 and

RESET pins

(2)

V_CC= 1.8V - 2.4V

V_CC= 2.4V - 5.5V

0.7V_CC

0.6V_CC

V_CC+ 0.5

V_IH

V

(2)

Input High Voltage,

XTAL1 pin

V_CC= 1.8V - 2.4V

V_CC= 2.4V - 5.5V

0.8V_CC

0.7V_CC

V_CC+ 0.5

V_IH1

V_IH2

V_OL

V_OH

I_IL

V

Input High Voltage,

RESET pin

(2)

V_CC= 1.8V - 5.5V

0.9V_CC

V_CC+ 0.5

I_OL= 10mA, V_CC= 5V

I_OL= 5mA, V_CC= 3V

0.7

0.5

Output Low Voltage⁽³⁾,

Output High Voltage⁽⁴⁾,

V

I_OH= -20mA, V_CC= 5V

I_OH= -10mA, V_CC= 3V

4.2

2.3

V

Input Leakage

Current I/O Pin

V_CC= 5.5V, pin low

(absolute value)

1

µA

Input Leakage

Current I/O Pin

V_CC= 5.5V, pin high

(absolute value)

I_IH

R_RST

R_PU

Reset Pull-up Resistor

I/O Pin Pull-up Resistor

30

20

60

50

kΩ

400

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

T_A= -40°C to 85°C, V_CC= 1.8V to 5.5V (unless otherwise noted) (Continued)

Symbol

Parameter

Condition

Min.⁽⁵⁾

Typ.

Max.⁽⁵⁾

Units

Active 1MHz, V_CC= 2V

(AT90USB64/128)

0.8

mA

Active 4MHz, V_CC= 3V

(AT90USB64/128)

5

18

mA

Active 8MHz, V_CC= 5V

(AT90USB64/128)

Power Supply Current⁽⁶⁾

Idle 1MHz, V_CC= 2V

(AT90USB64/128)

0.4

0.75

2.2

8

I_CC

Idle 4MHz, V_CC= 3V

(AT90USB64/128)

Idle 8MHz, V_CC= 5V

(AT90USB64/128)

WDT enabled, V_CC= 3V

WDT disabled, V_CC= 3V

<10

<1

20

3

µA

Power-down mode

V_CC= 5V

Analog Comparator

Input Offset Voltage

V_ACIO

I_ACLK

t_ACID

<10

40

50

mV

nA

ns

V_in= V_CC/2

Analog Comparator

Input Leakage Current

V_CC= 5V

V_in= V_CC/2

-50

Analog Comparator

Propagation Delay

V_CC= 2.7V

V_CC= 4.0V

750

500

Note:

1. "Max" means the highest value where the pin is guaranteed to be read as low

2. "Min" means the lowest value where the pin is guaranteed to be read as high

3. Although each I/O port can sink more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state

conditions (non-transient), the following must be observed:

AT90USB64/128:

1.)The sum of all IOL, for ports A0-A7, G2, C4-C7 should not exceed 100 mA.

2.)The sum of all IOL, for ports C0-C3, G0-G1, D0-D7 should not exceed 100 mA.

3.)The sum of all IOL, for ports G3-G5, B0-B7, E0-E7 should not exceed 100 mA.

4.)The sum of all IOL, for ports F0-F7 should not exceed 100 mA.

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test condition.

4. Although each I/O port can source more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady

state conditions (non-transient), the following must be observed:

AT90USB64/128:

1)The sum of all IOH, for ports A0-A7, G2, C4-C7 should not exceed 100 mA.

2)The sum of all IOH, for ports C0-C3, G0-G1, D0-D7 should not exceed 100 mA.

3)The sum of all IOH, for ports G3-G5, B0-B7, E0-E7 should not exceed 100 mA.

4)The sum of all IOH, for ports F0-F7 should not exceed 100 mA.

5. All DC Characteristics contained in this datasheet are based on simulation and characterization of other AVR microcontrol-

lers manufactured in the same process technology. These values are preliminary values representing design targets, and

will be updated after characterization of actual silicon

6. Values with “Power Reduction Register 1 - PRR1” disabled (0x00).

401

7593D–AVR–07/06

30.3 External Clock Drive Waveforms

Figure 30-1. External Clock Drive Waveforms

V_IH1

V_IL1

30.4 External Clock Drive

Table 30-1. External Clock Drive

V_CC=1.8-5.5V

V_CC=2.7-5.5V

V_CC=4.5-5.5V

Symbol Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Units

Oscillator

1/t_CLCL

0

2

0

8

0

16

MHz

Frequency

t_CLCL

t_CHCX

t_CLCX

t_CLCH

t_CHCL

Clock Period

High Time

Low Time

Rise Time

Fall Time

500

200

125

50

62.5

25

ns

μs

50

25

2.0

1.6

0.5

Change in period

from one clock

cycle to the next

Δt_CLCL

2

%

Note:

All DC Characteristics contained in this datasheet are based on simulation and characterization of

other AVR microcontrollers manufactured in the same process technology. These values are pre-

liminary values representing design targets, and will be updated after characterization of actual

silicon.

30.5 Maximum speed vs. V_CC

Maximum frequency is depending on V_CC.As shown in Figure 30-2, the Maximum Frequency vs.

_CCcurve is linear between 2.7V < V_CC< 4.5V.

V

402

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

Figure 30-2. Maximum Frequency vs. V_CC, AT90USB64/128

30.6 2-wire Serial Interface Characteristics

Table 30-2 describes the requirements for devices connected to the 2-wire Serial Bus. The AT90USB64/128 2-wire Serial

Interface meets or exceeds these requirements under the noted conditions.

Timing symbols refer to Figure 30-3.

Table 30-2. 2-wire Serial Bus Requirements

Symbol Parameter

Condition

Min

-0.5

Max

0.3 V_CC

V_CC+ 0.5

–

Units

V

Input Low-voltage

VIL

Input High-voltage

0.7 V_CC

V

VIH

Vhys

(1)

(2)

Hysteresis of Schmitt Trigger Inputs

Output Low-voltage

0.05 V_CC

V

(1)

3 mA sink current

10 pF < C_b< 400 pF⁽³⁾

0.1V_CC< V_i< 0.9V_CC

0

0.4

V

VOL

(1)

tr

(3)(2)

Rise Time for both SDA and SCL

Output Fall Time from V_IHminto V_ILmax

Spikes Suppressed by Input Filter

Input Current each I/O Pin

Capacitance for each I/O Pin

SCL Clock Frequency

20 + 0.1C_b

300

ns

µA

pF

kHz

(1)

tof

20 + 0.1C_b

250

(1)

tSP

0

-10

–

50⁽²⁾

I_i

10

C_i⁽¹⁾

10

f_SCL

f_CK⁽⁴⁾> max(16f_SCL, 250kHz)⁽⁵⁾

0

400

V_CC– 0,4V

f_SCL≤ 100 kHz

1000ns

-------------------

C_b

----------------------------

Ω

3mA

Rp

Value of Pull-up resistor

V

_CC– 0,4V

f_SCL> 100 kHz

300ns

---------------

C_b

----------------------------

3mA

f_SCL≤ 100 kHz

_SCL> 100 kHz

4.0

0.6

4.7

1.3

–

µs

t_HD;STA

Hold Time (repeated) START Condition

Low Period of the SCL Clock

f

f_SCL≤ 100 kHz⁽⁶⁾

t_LOW

f_SCL> 100 kHz⁽⁷⁾

403

7593D–AVR–07/06

Table 30-2. 2-wire Serial Bus Requirements (Continued)

Symbol Parameter

Condition

Min

4.0

0.6

4.7

0.6

0

Max

–

Units

µs

ns

µs

f_SCL≤ 100 kHz

f_SCL> 100 kHz

f_SCL≤ 100 kHz

f_SCL> 100 kHz

f_SCL≤ 100 kHz

f_SCL> 100 kHz

f_SCL≤ 100 kHz

t_HIGH

High period of the SCL clock

Set-up time for a repeated START condition

Data hold time

–

t_SU;STA

t_HD;DAT

t_SU;DAT

t_SU;STO

t_BUF

–

3.45

0.9

–

0

250

100

4.0

0.6

4.7

1.3

Data setup time

f

_SCL> 100 kHz

–

f_SCL≤ 100 kHz

f_SCL> 100 kHz

f_SCL≤ 100 kHz

f_SCL> 100 kHz

–

Setup time for STOP condition

–

Bus free time between a STOP and START

condition

–

Notes: 1. In AT90USB64/128, this parameter is characterized and not 100% tested.

2. Required only for f_SCL> 100 kHz.

3. C_b= capacitance of one bus line in pF.

4. f_CK= CPU clock frequency

5. This requirement applies to all AT90USB64/128 2-wire Serial Interface operation. Other devices connected to the 2-wire

Serial Bus need only obey the general f_SCLrequirement.

6. The actual low period generated by the AT90USB64/128 2-wire Serial Interface is (1/f_SCL- 2/f_CK), thus f_CKmust be greater

than 6 MHz for the low time requirement to be strictly met at f_SCL= 100 kHz.

7. The actual low period generated by the AT90USB64/128 2-wire Serial Interface is (1/f_SCL- 2/f_CK), thus the low time require-

ment will not be strictly met for f_SCL> 308 kHz when f_CK= 8 MHz. Still, AT90USB64/128 devices connected to the bus may

communicate at full speed (400 kHz) with other AT90USB64/128 devices, as well as any other device with a proper t_LOW

acceptance margin.

Figure 30-3. 2-wire Serial Bus Timing

t

HIGH

t

r

of

t

LOW

SCL

SDA

t

HD;DAT

SU;STA

HD;STA

t

SU;DAT

t

SU;STO

t

BUF

404

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

30.7 SPI Timing Characteristics

See Figure 30-4 and Figure 30-5 for details.

Table 30-3. SPI Timing Parameters

Description

SCK period

SCK high/low

Rise/Fall time

Setup

Mode

Master

Slave

Min

Typ

Max

1

2

See Table 17-4

50% duty cycle

3

TBD

10

4

5

Hold

10

6

Out to SCK

SCK to out

SCK to out high

SS low to out

SCK period

SCK high/low⁽¹⁾

Rise/Fall time

Setup

0.5 • t_sck

10

7

8

10

9

15

ns

10

11

12

13

14

15

16

17

18

Slave

4 • t_ck

2 • t_ck

Slave

TBD

10

t_ck

Hold

SCK to out

SCK to SS high

SS high to tri-state

SS low to SCK

15

10

20

Slave

Note:

1. In SPI Programming mode the minimum SCK high/low period is:

- 2 t_CLCLfor f_CK< 12 MHz

- 3 t_CLCLfor f_CK> 12 MHz

Figure 30-4. SPI Interface Timing Requirements (Master Mode)

SS

6

1

SCK

(CPOL = 0)

2

SCK

(CPOL = 1)

4

5

3

MISO

(Data Input)

MSB

...

LSB

7

8

MOSI

(Data Output)

MSB

...

LSB

405

7593D–AVR–07/06

Figure 30-5. SPI Interface Timing Requirements (Slave Mode)

SS

10

16

9

SCK

(CPOL = 0)

11

SCK

(CPOL = 1)

13

14

12

MOSI

(Data Input)

MSB

...

LSB

15

17

MISO

(Data Output)

MSB

...

LSB

X

30.8 Hardware Boot EntranceTiming Characteristics

Figure 30-6. Hardware Boot Timing Requirements

RESET

t_SHRH

t_HHRH

ALE/HWB

Table 30-4. Hardware Boot Timings

Symbol Parameter

Min

Max

HWB low Setup before Reset High

0

tSHRH

StartUpTime(S

UT) + Time

Out

HWB low Hold after Reset High

tHHRH

Delay(TOUT)

406

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

30.9 ADC Characteristics – Preliminary Data

Table 30-5. ADC Characteristics

Symbol

Parameter

Condition

Min⁽¹⁾

Typ⁽¹⁾

Max⁽¹⁾

Units

Single Ended Conversion

10

Bits

Differential Conversion

Gain = 1x or 20x

8

7

Bits

Resolution

Differential Conversion

Gain = 200x

Single Ended Conversion

V_REF= 4V, V_CC= 4V,

ADC clock = 200 kHz

2

2.5

LSB

Single Ended Conversion

V_REF= 4V, V_CC= 4V,

4.5

ADC clock = 1 MHz

Absolute accuracy (Including

INL, DNL, quantization error,

gain and offset error)

Single Ended Conversion

V_REF= 4V, V_CC= 4V,

2

LSB

ADC clock = 200 kHz

Noise Reduction Mode

Single Ended Conversion

V_REF= 4V, V_CC= 4V,

ADC clock = 1 MHz

4.5

Noise Reduction Mode

Single Ended Conversion

V_REF= 4V, V_CC= 4V,

ADC clock = 200 kHz

Integral Non-Linearity (INL)

Differential Non-Linearity (DNL)

Gain Error

0.5

0.25

2

LSB

Single Ended Conversion

V_REF= 4V, V_CC= 4V,

ADC clock = 200 kHz

Single Ended Conversion

V_REF= 4V, V_CC= 4V,

ADC clock = 200 kHz

Single Ended Conversion

Offset Error

V_REF= 4V, V_CC= 4V,

2

ADC clock = 200 kHz

Conversion Time

Free Running Conversion

Single Ended Conversion

13

50

260

1000

µs

kHz

V

Clock Frequency

AVCC

V_REF

Analog Supply Voltage

V_CC- 0.3

1.0

V_CC+ 0.3

AVCC

Single Ended Conversion

Differential Conversion

Single ended channels

Differential Conversion

Single Ended Channels

Differential Channels

1.1V

V

Reference Voltage

Input Voltage

1.0

AVCC - 0.5

V_REF

V

GND

0

V

V_IN

AVCC

V

38,5

4

kHz

V

Input Bandwidth

V_INT1

Internal Voltage Reference

1.0

1.1

1.2

407

7593D–AVR–07/06

Table 30-5. ADC Characteristics (Continued)

Symbol

V_INT2

Parameter

Condition

Min⁽¹⁾

Typ⁽¹⁾

2.56

32

Max⁽¹⁾

Units

V

Internal Voltage Reference

Reference Input Resistance

Analog Input Resistance

2.56V

2.4

2.8

R_REF

kΩ

R_AIN

100

MΩ

Notes: 1. Values are guidelines only. Actual values are TBD

30.10 External Data Memory Timing

Table 30-6. External Data Memory Characteristics, 4.5 - 5.5 Volts, No Wait-state

8 MHz Oscillator

Variable Oscillator

Symbol

1/t_CLCL

t_LHLL

Parameter

Min

Max

Min

Max

Unit

0

1

2

Oscillator Frequency

ALE Pulse Width

0.0

16

MHz

ns

115

1.0t_CLCL-10

0.5t_CLCL-5⁽¹⁾

t_AVLL

Address Valid A to ALE Low

57.5

ns

Address Hold After ALE Low,

write access

3a

3b

t_{LLAX_ST}

t_{LLAX_LD}

5

ns

Address Hold after ALE Low,

read access

5

4

t_AVLLC

t_AVRL

t_AVWL

t_LLWL

t_LLRL

Address Valid C to ALE Low

Address Valid to RD Low

Address Valid to WR Low

ALE Low to WR Low

ALE Low to RD Low

57.5

115

47.5

40

0.5t_CLCL-5⁽¹⁾

1.0t_CLCL-10

0.5t_CLCL-15⁽²⁾

40

ns

5

6

7

67.5

0.5t_CLCL+5⁽²⁾

8

9

t_DVRH

t_RLDV

t_RHDX

t_RLRH

t_DVWL

t_WHDX

t_DVWH

t_WLWH

Data Setup to RD High

Read Low to Data Valid

Data Hold After RD High

RD Pulse Width

10

11

12

13

14

15

16

75

1.0t_CLCL-50

0

115

42.5

115

125

115

1.0t_CLCL-10

0.5t_CLCL-20⁽¹⁾

1.0t_CLCL-10

1.0t_CLCL

Data Setup to WR Low

Data Hold After WR High

Data Valid to WR High

WR Pulse Width

1.0t_CLCL-10

Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.

2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

408

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

Table 30-7. External Data Memory Characteristics, 4.5 - 5.5 Volts, 1 Cycle Wait-state

8 MHz Oscillator

Variable Oscillator

Symbol

Parameter

Min

Max

Min

Max

16

Unit

MHz

ns

0

1/t_CLCL

Oscillator Frequency

Read Low to Data Valid

RD Pulse Width

0.0

10 t_RLDV

12 t_RLRH

15 t_DVWH

16 t_WLWH

200

2.0t_CLCL-50

240

2.0t_CLCL-10

2.0t_CLCL

ns

Data Valid to WR High

WR Pulse Width

ns

2.0t_CLCL-10

ns

Table 30-8. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0

4 MHz Oscillator Variable Oscillator

Symbol

Parameter

Min

Max

Min

Max

16

Unit

MHz

ns

0

1/t_CLCL

Oscillator Frequency

Read Low to Data Valid

RD Pulse Width

0.0

10 t_RLDV

12 t_RLRH

15 t_DVWH

16 t_WLWH

325

3.0t_CLCL-50

365

375

365

3.0t_CLCL-10

3.0t_CLCL

ns

Data Valid to WR High

WR Pulse Width

ns

3.0t_CLCL-10

ns

Table 30-9. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1

4 MHz Oscillator Variable Oscillator

Symbol

Parameter

Min

Max

Min

Max

16

Unit

MHz

ns

0

1/t_CLCL

Oscillator Frequency

Read Low to Data Valid

RD Pulse Width

0.0

10 t_RLDV

12 t_RLRH

14 t_WHDX

15 t_DVWH

16 t_WLWH

325

3.0t_CLCL-50

365

240

375

365

3.0t_CLCL-10

2.0t_CLCL-10

3.0t_CLCL

ns

Data Hold After WR High

Data Valid to WR High

WR Pulse Width

ns

3.0t_CLCL-10

ns

Table 30-10. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait-state

4 MHz Oscillator

Variable Oscillator

Symbol

1/t_CLCL

t_LHLL

Parameter

Min

Max

Min

0.0

Max

Unit

MHz

ns

0

1

2

Oscillator Frequency

ALE Pulse Width

8

235

115

t_CLCL-15

0.5t_CLCL-10⁽¹⁾

t_AVLL

Address Valid A to ALE Low

ns

Address Hold After ALE Low,

write access

3a t_{LLAX_ST}

5

ns

409

7593D–AVR–07/06

Table 30-10. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait-state (Continued)

4 MHz Oscillator Variable Oscillator

Symbol

Parameter

Min

Max

Min

Max

Unit

Address Hold after ALE Low,

read access

3b t_{LLAX_LD}

5

ns

4

5

6

7

8

9

t_AVLLC

t_AVRL

t_AVWL

t_LLWL

t_LLRL

Address Valid C to ALE Low

Address Valid to RD Low

Address Valid to WR Low

ALE Low to WR Low

ALE Low to RD Low

115

235

115

45

0.5t_CLCL-10⁽¹⁾

1.0t_CLCL-15

0.5t_CLCL-10⁽²⁾

45

ns

130

0.5t_CLCL+5⁽²⁾

t_DVRH

Data Setup to RD High

Read Low to Data Valid

Data Hold After RD High

RD Pulse Width

10 t_RLDV

11 t_RHDX

12 t_RLRH

13 t_DVWL

14 t_WHDX

15 t_DVWH

16 t_WLWH

190

1.0t_CLCL-60

0

235

105

235

250

235

1.0t_CLCL-15

0.5t_CLCL-20⁽¹⁾

1.0t_CLCL-15

1.0t_CLCL

Data Setup to WR Low

Data Hold After WR High

Data Valid to WR High

WR Pulse Width

1.0t_CLCL-15

Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.

2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

Table 30-11. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 0, SRWn0 = 1

4 MHz Oscillator

Variable Oscillator

Min Max

Symbol

Parameter

Min

Max

Unit

MHz

ns

0

1/t_CLCL

Oscillator Frequency

Read Low to Data Valid

RD Pulse Width

0.0

8

10 t_RLDV

12 t_RLRH

15 t_DVWH

16 t_WLWH

440

2.0t_CLCL-60

485

500

485

2.0t_CLCL-15

2.0t_CLCL

ns

Data Valid to WR High

WR Pulse Width

ns

2.0t_CLCL-15

ns

Table 30-12. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0

4 MHz Oscillator Variable Oscillator

Symbol

Parameter

Min

Max

Min

Max

8

Unit

MHz

ns

0

1/t_CLCL

Oscillator Frequency

Read Low to Data Valid

RD Pulse Width

0.0

10 t_RLDV

12 t_RLRH

15 t_DVWH

16 t_WLWH

690

3.0t_CLCL-60

735

750

735

3.0t_CLCL-15

3.0t_CLCL

ns

Data Valid to WR High

WR Pulse Width

ns

3.0t_CLCL-15

ns

410

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

Table 30-13. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1

4 MHz Oscillator Variable Oscillator

Min Max

Symbol

Parameter

Min

Max

Unit

MHz

ns

0

1/t_CLCL

Oscillator Frequency

Read Low to Data Valid

RD Pulse Width

0.0

8

10 t_RLDV

12 t_RLRH

14 t_WHDX

15 t_DVWH

16 t_WLWH

690

3.0t_CLCL-60

735

485

750

735

3.0t_CLCL-15

2.0t_CLCL-15

3.0t_CLCL

ns

Data Hold After WR High

Data Valid to WR High

WR Pulse Width

ns

3.0t_CLCL-15

ns

Figure 30-7. External Memory Timing (SRWn1 = 0, SRWn0 = 0

T1

T2

T3

T4

System Clock (CLK_CPU

)

1

ALE

4

2

7

A15:8 Prev. addr.

Address

15

3a

3b

13

DA7:0 Prev. data

Address

6

XX

Data

16

14

WR

9

11

DA7:0 (XMBK = 0)

Address

5

Data

10

8

12

RD

411

7593D–AVR–07/06

Figure 30-8. External Memory Timing (SRWn1 = 0, SRWn0 = 1)

T1

T2

T3

T4

T5

System Clock (CLK_CPU

)

1

ALE

4

2

7

A15:8 Prev. addr.

Address

15

3a

3b

13

Data

16

DA7:0 Prev. data

Address

6

XX

14

WR

9

11

DA7:0 (XMBK = 0)

Address

5

Data

10

8

12

RD

Figure 30-9. External Memory Timing (SRWn1 = 1, SRWn0 = 0)

T1

T2

T3

T4

T5

T6

System Clock (CLK_CPU

)

1

ALE

4

2

7

Address

15

A15:8 Prev. addr.

3a

3b

13

DA7:0 Prev. data

Address

6

XX

Data

16

14

WR

9

11

DA7:0 (XMBK = 0)

Address

5

Data

10

8

12

RD

412

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

Figure 30-10. External Memory Timing (SRWn1 = 1, SRWn0 = 1)⁽⁾

T6

T1

T2

T3

T4

T5

T7

System Clock (CLK_CPU

)

1

ALE

4

2

7

Address

15

A15:8 Prev. addr.

3a

3b

13

DA7:0 Prev. data

Address

6

XX

Data

16

14

WR

9

11

DA7:0 (XMBK = 0)

Address

5

Data

10

8

12

RD

The ALE pulse in the last period (T4-T7) is only present if the next instruction accesses the RAM (internal

or external).

413

7593D–AVR–07/06

31. Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xFF)

(0xFE)

(0xFD)

(0xFC)

(0xFB)

(0xFA)

(0xF9)

(0xF8)

(0xF7)

(0xF6)

(0xF5)

(0xF4)

(0xF3)

(0xF2)

(0xF1)

(0xF0)

(0xEF)

(0xEE)

(0xED)

(0xEC)

(0xEB)

(0xEA)

(0xE9)

(0xE8)

(0xE7)

(0xE6)

(0xE5)

(0xE4)

(0xE3)

(0xE2)

(0xE1)

(0xE0)

(0xDF)

(0xDE)

(0xDD)

(0xDC)

(0xDB)

(0xDA)

(0xD9)

(0xD8)

(0xD7)

(0xD6)

(0xD5)

(0xD4)

(0xD3)

(0xD2)

(0xD1)

(0xD0)

(0xCF)

(0xCE)

(0xCD)

(0xCC)

(0xCB)

(0xCA)

(0xC9)

(0xC8)

(0xC7)

(0xC6)

(0xC5)

(0xC4)

(0xC3)

(0xC2)

(0xC1)

(0xC0)

(0xBF)

Reserved

OTGTCON

UPINT

-

1

PAGE

VALUE

PINT7:0

UPBCHX

UPBCLX

UPERRX

UEINT

-

PBYCT10:8

DATAPID

BYCT10:8

PBYCT7:0

TIMEOUT

COUNTER1:0

CRC16

-

PID

DATATGL

EPINT6:0

-

UEBCHX

UEBCLX

UEDATX

UEIENX

-

BYCT7:0

DAT7:0

RXSTPE

FLERRE

-

NAKINE

-

NAKOUTE

-

RXOUTE

CTRLDIR

STALLEDE

TXINE

UESTA1X

UESTA0X

UECFG1X

UECFG0X

UECONX

UERST

-

CURRBK1:0

NBUSYBK1:0

ALLOC

CFGOK

OVERFI

UNDERFI

EPSIZE2:0

ZLPSEEN

DTSEQ1:0

EPBK1:0

EPTYPE1:0

ISOSW

RSTDT

AUTOSW

NYETSDIS

EPDIR

EPEN

STALLRQ

STALLRQC

EPRST6:0

UENUM

EPNUM2:0

STALLEDI

UEINTX

FIFOCON

ADDEN

NAKINI

RWAL

NAKOUTI

TSTPCKT

FNCERR

RXSTPI

TSTK

RXOUTI

TSTJ

TXINI

UDTST

OPMODE2

UDMFN

UDFNUMH

UDFNUML

UDADDR

UDIEN

FNUM10:8

FNUM7:0

UADD6:0

EORSTE

EORSTI

UPRSME

UPRSMI

EORSME

EORSMI

WAKEUPE

WAKEUPI

SOFE

SOFI

MSOFE

MSOFI

SUSPE

SUSPI

UDINT

UDCON

LSM

RMWKUP

VBERRI

DETACH

SRPI

OTGINT

OTGIEN

OTGCON

UDPADDH

UDPADDL

USBINT

STOI

STOE

HNPERRI

HNPERRE

SRPREQ

ROLEEXI

ROLEEXE

SRPSEL

BCERRI

BCERRE

VBUSHWC

VBERRE

VBUSREQ

DPADD10:8

SRPE

0

HNPREQ

VBUSRQC

DPACC

DPADD7:0

IDTI

ID

VBUSTI

VBUS

USBSTA

USBCON

UHWCON

Reserved

UDR1

SPEED

USBE

HOST

UIDE

FRZCLK

OTGPADE

UVCONE

IDTE

VBUSTE

UVREGE

UIMOD

-

USART1 I/O Data Register

- USART1 Baud Rate Register High Byte

UBRR1H

UBRR1L

Reserved

UCSR1C

UCSR1B

UCSR1A

Reserved

-

USART1 Baud Rate Register Low Byte

-

UMSEL11

UMSEL10

UPM11

UPM10

USBS1

UCSZ11

UCSZ10

UCPOL1

RXCIE1

TXCIE1

UDRIE1

RXEN1

TXEN1

UCSZ12

RXB81

TXB81

RXC1

TXC1

UDRE1

FE1

DOR1

PE1

U2X1

MPCM1

-

414

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xBE)

(0xBD)

(0xBC)

(0xBB)

(0xBA)

(0xB9)

(0xB8)

(0xB7)

(0xB6)

(0xB5)

(0xB4)

(0xB3)

(0xB2)

(0xB1)

(0xB0)

(0xAF)

(0xAE)

(0xAD)

(0xAC)

(0xAB)

(0xAA)

(0xA9)

(0xA8)

(0xA7)

(0xA6)

(0xA5)

(0xA4)

(0xA3)

(0xA2)

(0xA1)

(0xA0)

(0x9F)

(0x9E)

(0x9D)

(0x9C)

(0x9B)

(0x9A)

(0x99)

(0x98)

(0x97)

(0x96)

(0x95)

(0x94)

(0x93)

(0x92)

(0x91)

(0x90)

(0x8F)

(0x8E)

(0x8D)

(0x8C)

(0x8B)

(0x8A)

(0x89)

(0x88)

(0x87)

(0x86)

(0x85)

(0x84)

(0x83)

(0x82)

(0x81)

(0x80)

(0x7F)

(0x7E)

(0x7D)

Reserved

TWAMR

TWCR

-

TWAM6

TWINT

TWAM5

TWEA

TWAM4

TWSTA

TWAM3

TWSTO

TWAM2

TWWC

TWAM1

TWEN

TWAM0

-

TWIE

TWDR

2-wire Serial Interface Data Register

TWAR

TWA6

TWS7

TWA5

TWS6

TWA4

TWS5

TWA3

TWS4

TWA2

TWS3

TWA1

-

TWA0

TWGCE

TWPS0

TWSR

TWPS1

TWBR

2-wire Serial Interface Bit Rate Register

Reserved

ASSR

-

AS2

-

EXCLK

-

TCN2UB

-

OCR2AUB

-

OCR2BUB

-

TCR2AUB

-

TCR2BUB

-

Reserved

OCR2B

Timer/Counter2 Output Compare Register B

Timer/Counter2 Output Compare Register A

Timer/Counter2 (8 Bit)

OCR2A

TCNT2

TCCR2B

TCCR2A

UPDATX

UPIENX

UPCFG2X

UPSTAX

UPCFG1X

UPCFG0X

UPCONX

UPRST

FOC2A

FOC2B

-

WGM22

-

CS22

-

CS21

CS20

COM2A1

COM2A0

COM2B1

COM2B0

WGM21

WGM20

PDAT7:0

TXSTPE

INTFRQ7:0

FLERRE

CFGOK

NAKEDE

OVERFI

-

PERRE

TXOUTE

RXSTALLE

RXINE

UNDERFI

PSIZE2:0

DTSEQ1:0

PBK1:0

NBUSYBK1:0

ALLOC

PEPNUM3:0

PTYPE1:0

PTOKEN1:0

PFREEZE

NAKEDI

INMODE

AUTOSW

RSTDT

PEN

PRST6:0

UPNUM

UPINTX

UPINRQX

UHFLEN

UHFNUMH

UHFNUML

UHADDR

UHIEN

PNUM2:0

RXSTALLI

FIFOCON

RWAL

PERRI

TXSTPI

TXOUTI

RXINI

INRQ7:0

FLEN7:0

FNUM10:8

FNUM7:0

HADD6:0

EORSTE

RSMEDI

UPRSME

HWUPI

EORSME

HSOFI

WAKEUPE

RXRSMI

SOFE

RSTI

MSOFE

DDISCI

RESET

SUSPE

DCONNI

SOFEN

UHINT

UHCON

OCR3CH

OCR3CL

OCR3BH

OCR3BL

OCR3AH

OCR3AL

ICR3H

RESUME

Timer/Counter3 - Output Compare Register C High Byte

Timer/Counter3 - Output Compare Register C Low Byte

Timer/Counter3 - Output Compare Register B High Byte

Timer/Counter3 - Output Compare Register B Low Byte

Timer/Counter3 - Output Compare Register A High Byte

Timer/Counter3 - Output Compare Register A Low Byte

Timer/Counter3 - Input Capture Register High Byte

Timer/Counter3 - Input Capture Register Low Byte

Timer/Counter3 - Counter Register High Byte

ICR3L

TCNT3H

TCNT3L

Reserved

TCCR3C

TCCR3B

TCCR3A

Reserved

OCR1CH

OCR1CL

OCR1BH

OCR1BL

OCR1AH

OCR1AL

ICR1H

Timer/Counter3 - Counter Register Low Byte

-

FOC3A

FOC3B

FOC3C

-

ICNC3

ICES3

-

WGM33

WGM32

CS32

CS31

CS30

COM3A1

COM3A0

COM3B1

COM3B0

COM3C1

COM3C0

WGM31

WGM30

-

Timer/Counter1 - Output Compare Register C High Byte

Timer/Counter1 - Output Compare Register C Low Byte

Timer/Counter1 - Output Compare Register B High Byte

Timer/Counter1 - Output Compare Register B Low Byte

Timer/Counter1 - Output Compare Register A High Byte

Timer/Counter1 - Output Compare Register A Low Byte

Timer/Counter1 - Input Capture Register High Byte

Timer/Counter1 - Input Capture Register Low Byte

Timer/Counter1 - Counter Register High Byte

ICR1L

TCNT1H

TCNT1L

Reserved

TCCR1C

TCCR1B

TCCR1A

DIDR1

Timer/Counter1 - Counter Register Low Byte

-

FOC1A

ICNC1

COM1A1

-

FOC1B

ICES1

COM1A0

-

FOC1C

-

WGM13

WGM12

CS12

CS11

WGM11

AIN1D

ADC1D

-

CS10

WGM10

AIN0D

ADC0D

-

COM1B1

COM1B0

COM1C1

COM1C0

-

DIDR0

ADC7D

-

ADC6D

-

ADC5D

-

ADC4D

-

ADC3D

-

ADC2D

-

415

7593D–AVR–07/06

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0x7C)

(0x7B)

ADMUX

ADCSRB

ADCSRA

ADCH

REFS1

-

REFS0

ACME

ADSC

ADLAR

-

MUX4

-

MUX3

MUX5

ADIE

MUX2

ADTS2

ADPS2

MUX1

ADTS1

ADPS1

MUX0

ADTS0

ADPS0

(0x7A)

ADEN

ADATE

ADIF

(0x79)

ADC Data Register High byte

ADC Data Register Low byte

(0x78)

ADCL

(0x77)

Reserved

XMCRB

XMCRA

Reserved

TIMSK3

TIMSK2

TIMSK1

TIMSK0

Reserved

PCMSK0

EICRB

-

(0x76)

-

(0x75)

XMBK

-

XMM2

XMM1

XMM0

SRW00

-

(0x74)

SRE

SRL2

SRL1

SRL0

SRW11

SRW10

SRW01

(0x73)

-

(0x72)

-

(0x71)

-

ICIE3

-

OCIE3C

OCIE3B

OCIE2B

OCIE1B

OCIE0B

-

OCIE3A

OCIE2A

OCIE1A

OCIE0A

-

TOIE3

TOIE2

TOIE1

TOIE0

-

(0x70)

-

(0x6F)

-

ICIE1

-

OCIE1C

(0x6E)

-

(0x6D)

-

(0x6C)

-

PCINT7

ISC71

ISC31

-

PCINT6

ISC70

ISC30

-

PCINT5

ISC61

ISC21

-

PCINT4

ISC60

ISC20

-

PCINT3

ISC51

ISC11

-

(0x6B)

PCINT2

ISC50

ISC10

-

PCINT1

ISC41

ISC01

-

PCINT0

ISC40

ISC00

PCIE0

-

(0x6A)

(0x69)

EICRA

(0x68)

PCICR

(0x67)

Reserved

OSCCAL

PRR1

-

(0x66)

Oscillator Calibration Register

(0x65)

PRUSB

-

PRTIM3

-

PRUSART1

(0x64)

PRR0

PRTWI

PRTIM2

PRTIM0

-

PRTIM1

PRSPI

-

PRADC

(0x63)

Reserved

CLKPR

-

(0x62)

-

(0x61)

CLKPCE

-

CLKPS3

CLKPS2

CLKPS1

CLKPS0

(0x60)

WDTCSR

SREG

WDIF

WDIE

WDP3

WDCE

WDE

WDP2

WDP1

WDP0

0x3F (0x5F)

0x3E (0x5E)

0x3D (0x5D)

0x3C (0x5C)

0x3B (0x5B)

0x3A (0x5A)

0x39 (0x59)

0x38 (0x58)

0x37 (0x57)

0x36 (0x56)

0x35 (0x55)

0x34 (0x54)

0x33 (0x53)

0x32 (0x52)

I

T

H

S

V

N

Z

C

SPH

SP15

SP14

SP13

SP12

SP11

SP10

SP9

SP8

SPL

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

Reserved

RAMPZ

Reserved

SPMCSR

Reserved

MCUCR

MCUSR

SMCR

-

RAMPZ1

RAMPZ0

-

SPMEN

-

SPMIE

RWWSB

SIGRD

RWWSRE

BLBSET

PGWRT

PGERS

-

PUD

JTRF

-

JTD

-

IVSEL

EXTRF

SM0

-

IVCE

PORF

SE

-

WDRF

SM2

-

BORF

SM1

-

Reserved

-

OCDR/

MONDR

OCDR7

OCDR6

OCDR5

OCDR4

OCDR3

OCDR2

OCDR1

OCDR0

0x31 (0x51)

Monitor Data Register

0x30 (0x50)

0x2F (0x4F)

0x2E (0x4E)

0x2D (0x4D)

0x2C (0x4C)

0x2B (0x4B)

0x2A (0x4A)

0x29 (0x49)

0x28 (0x48)

0x27 (0x47)

0x26 (0x46)

0x25 (0x45)

0x24 (0x44)

0x23 (0x43)

0x22 (0x42)

0x21 (0x41)

0x20 (0x40)

0x1F (0x3F)

0x1E (0x3E)

0x1D (0x3D)

0x1C (0x3C)

ACSR

Reserved

SPDR

ACD

-

ACBG

-

ACO

-

ACI

-

ACIE

-

ACIC

-

ACIS1

-

ACIS0

-

SPI Data Register

-

SPSR

SPIF

SPIE

WCOL

SPE

-

SPI2X

SPR0

SPCR

DORD

MSTR

CPOL

CPHA

SPR1

GPIOR2

GPIOR1

PLLCSR

OCR0B

OCR0A

TCNT0

TCCR0B

TCCR0A

GTCCR

EEARH

EEARL

EEDR

General Purpose I/O Register 2

General Purpose I/O Register 1

-

PLLP2

PLLP1

PLLP0

PLLE

PLOCK

Timer/Counter0 Output Compare Register B

Timer/Counter0 Output Compare Register A

Timer/Counter0 (8 Bit)

FOC0A

COM0A1

TSM

FOC0B

-

WGM02

CS02

CS01

CS00

COM0A0

COM0B1

COM0B0

-

WGM01

PSRASY

WGM00

-

PSRSYNC

-

EEPROM Address Register High Byte

EEPROM Address Register Low Byte

EEPROM Data Register

EECR

-

EEPM1

EEPM0

EERIE

EEMPE

EEPE

EERE

GPIOR0

EIMSK

EIFR

General Purpose I/O Register 0

INT7

INT6

INT5

INT4

INT3

INT2

INT1

INT0

INTF7

INTF6

INTF5

INTF4

INTF3

INTF2

INTF1

INTF0

416

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

0x1B (0x3B)

0x1A (0x3A)

0x19 (0x39)

0x18 (0x38)

0x17 (0x37)

0x16 (0x36)

0x15 (0x35)

0x14 (0x34)

0x13 (0x33)

0x12 (0x32)

0x11 (0x31)

0x10 (0x30)

0x0F (0x2F)

0x0E (0x2E)

0x0D (0x2D)

0x0C (0x2C)

0x0B (0x2B)

0x0A (0x2A)

0x09 (0x29)

0x08 (0x28)

0x07 (0x27)

0x06 (0x26)

0x05 (0x25)

0x04 (0x24)

0x03 (0x23)

0x02 (0x22)

0x01 (0x21)

0x00 (0x20)

PCIFR

Reserved

TIFR3

-

PCIF0

-

ICF3

-

OCF3C

-

OCF3B

OCF2B

OCF1B

OCF0B

-

OCF3A

OCF2A

OCF1A

OCF0A

-

TOV3

TOV2

TOV1

TOV0

-

TIFR2

-

TIFR1

-

ICF1

-

OCF1C

-

TIFR0

-

Reserved

PORTF

DDRF

-

PORTF7

DDF7

PINF7

PORTE7

DDE7

PINE7

PORTD7

DDD7

PIND7

PORTC7

DDC7

PINC7

PORTB7

DDB7

PINB7

PORTA7

DDA7

PINA7

PORTF6

DDF6

PINF6

PORTE6

DDE6

PINE6

PORTD6

DDD6

PIND6

PORTC6

DDC6

PINC6

PORTB6

DDB6

PINB6

PORTA6

DDA6

PINA6

PORTF5

DDF5

PINF5

PORTE5

DDE5

PINE5

PORTD5

DDD5

PIND5

PORTC5

DDC5

PINC5

PORTB5

DDB5

PINB5

PORTA5

DDA5

PINA5

PORTF4

DDF4

PINF4

PORTE4

DDE4

PINE4

PORTD4

DDD4

PIND4

PORTC4

DDC4

PINC4

PORTB4

DDB4

PINB4

PORTA4

DDA4

PINA4

PORTF3

DDF3

PINF3

PORTE3

DDE3

PINE3

PORTD3

DDD3

PIND3

PORTC3

DDC3

PINC3

PORTB3

DDB3

PINB3

PORTA3

DDA3

PINA3

PORTF2

DDF2

PINF2

PORTE2

DDE2

PINE2

PORTD2

DDD2

PIND2

PORTC2

DDC2

PINC2

PORTB2

DDB2

PINB2

PORTA2

DDA2

PINA2

PORTF1

DDF1

PINF1

PORTE1

DDE1

PINE1

PORTD1

DDD1

PIND1

PORTC1

DDC1

PINC1

PORTB1

DDB1

PINB1

PORTA1

DDA1

PINA1

PORTF0

DDF0

PINF0

PORTE0

DDE0

PINE0

PORTD0

DDD0

PIND0

PORTC0

DDC0

PINC0

PORTB0

DDB0

PINB0

PORTA0

DDA0

PINA0

PINF

PORTE

DDRE

PINE

PORTD

DDRD

PIND

PORTC

DDRC

PINC

PORTB

DDRB

PINB

PORTA

DDRA

PINA

Note:

1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these reg-

isters, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on

all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions

work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O reg-

isters as data space using LD and ST instructions, $20 must be added to these addresses. The AT90USB64/128 is a

complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the

IN and OUT instructions. For the Extended I/O space from $60 - $1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD

instructions can be used.

417

7593D–AVR–07/06

32. Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

ADC

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd + Rr

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

2

ADIW

SUB

SUBI

SBC

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

SBCI

SBIW

AND

ANDI

OR

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd v K

Z,N,V

EOR

COM

NEG

SBR

Rd ← Rd ⊕ Rr

Z,N,V

Rd ← 0xFF − Rd

Rd ← 0x00 − Rd

Rd ← Rd v K

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd,K

Rd

Set Bit(s) in Register

CBR

Clear Bit(s) in Register

Increment

Rd ← Rd • (0xFF - K)

Rd ← Rd + 1

Z,N,V

INC

Z,N,V

DEC

Rd

Decrement

Rd ← Rd − 1

Z,N,V

TST

Rd

Test for Zero or Minus

Rd ← Rd • Rd

Z,N,V

CLR

Rd

Clear Register

Rd ← Rd ⊕ Rd

Rd ← 0xFF

Z,N,V

SER

Rd

Set Register

None

MUL

Rd, Rr

Multiply Unsigned

R1:R0 ← Rd x Rr

^{R1:R0 ← (Rd x Rr)}<< 1

R1:R0 ← (Rd x Rr) << 1

Z,C

MULS

MULSU

FMUL

FMULS

FMULSU

Multiply Signed

Z,C

Multiply Signed with Unsigned

Fractional Multiply Unsigned

Fractional Multiply Signed

Fractional Multiply Signed with Unsigned

Z,C

BRANCH INSTRUCTIONS

RJMP

IJMP

k

Relative Jump

Indirect Jump to (Z)

PC ← PC + k + 1

PC ← Z

None

I

2

PC ←(EIND:Z)

EIJMP

JMP

Extended Indirect Jump to (Z)

Direct Jump

2

k

PC ← k

PC ← PC + k + 1

PC ← Z

3

RCALL

ICALL

EICALL

CALL

RET

Relative Subroutine Call

Indirect Call to (Z)

4

PC ←(EIND:Z)

Extended Indirect Call to (Z)

Direct Subroutine Call

Subroutine Return

4

k

PC ← k

5

PC ← STACK

5

RETI

Interrupt Return

PC ← STACK

5

CPSE

CP

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

None

Z, N,V,C,H

None

1/2/3

1

Rd,Rr

CPC

Rd,Rr

Compare with Carry

Rd − Rr − C

1

CPI

Rd,K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd − K

1

SBRC

SBRS

SBIC

Rr, b

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (P(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC+k + 1

if (SREG(s) = 0) then PC←PC+k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V= 0) then PC ← PC + k + 1

if (N ⊕ V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

1/2/3

1/2

Rr, b

P, b

s, k

k

SBIS

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

k

Branch if T Flag Cleared

Branch if Overflow Flag is Set

k

418

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

Mnemonics

Operands

Description

Operation

Flags

#Clocks

BRVC

BRIE

BRID

k

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

if (V = 0) then PC ← PC + k + 1

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

None

1/2

BIT AND BIT-TEST INSTRUCTIONS

SBI

CBI

P,b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

I/O(P,b) ← 0

None

LSL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Logical Shift Right

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Z,C,N,V

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Z,C,N,V

Rd(n) ← Rd(n+1), n=0..6

Z,C,N,V

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

T

None

C

N

Z

Clear Carry

C ← 0

Set Negative Flag

N ← 1

Clear Negative Flag

Set Zero Flag

N ← 0

Z ← 1

Clear Zero Flag

Z ← 0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

I

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

S ← 1

S

S ← 0

S

V ← 1

V

V ← 0

V

T ← 1

T

Clear T in SREG

T ← 0

T

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

H ← 1

H

H ← 0

DATA TRANSFER INSTRUCTIONS

MOV

MOVW

LDI

Rd, Rr

Rd, K

Move Between Registers

Copy Register Word

Rd ← Rr

None

1

2

3

Rd+1:Rd ← Rr+1:Rr

Load Immediate

Rd ← K

Rd ← (X)

LD

Rd, X

Load Indirect

LD

Rd, X+

Rd, - X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

LD

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

LD

LDD

LD

Rd ← (Z)

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

LD

LDD

LDS

ST

Rd ← (k)

X, Rr

(X) ← Rr

ST

X+, Rr

- X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

STD

ST

(Z) ← Rr

ST

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

ELPM

(k) ← Rr

Load Program Memory

Load Program Memory and Post-Inc

Extended Load Program Memory

R0 ← (Z)

Rd, Z

Rd ← (Z)

Rd, Z+

Rd ← (Z), Z ← Z+1

R0 ← (RAMPZ:Z)

Rd ← (Z)

Rd, Z

Rd, Z+

Rd ← (RAMPZ:Z), RAMPZ:Z ←RAMPZ:Z+1

419

7593D–AVR–07/06

Mnemonics

Operands

Description

Operation

Flags

#Clocks

SPM

IN

Store Program Memory

In Port

(Z) ← R1:R0

Rd ← P

None

-

Rd, P

P, Rr

Rr

1

2

OUT

PUSH

POP

Out Port

P ← Rr

Push Register on Stack

Pop Register from Stack

STACK ← Rr

Rd ← STACK

Rd

MCU CONTROL INSTRUCTIONS

NOP

SLEEP

WDR

No Operation

Sleep

None

1

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

For On-chip Debug Only

Watchdog Reset

Break

1

BREAK

N/A

420

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

33. Ordering Information

Table 33-1. Possible Order Entries

USB

interface

Speed

(MHz)

Power Supply

(V)

Ordering Code

Package

Operation Range

Product Marking

Industrial (-40° to +85°C)

Green

AT90USB1287-16AU

AT90USB1287-16MU

AT90USB1286-16MU

AT90USB647-16AU

AT90USB647-16MU

AT90USB646-16MU

OTG

8-16

2.7 - 5.5

TQFP64

QFN64

TQFP64

QFN64

90USB1287-16AU

90USB1287-16MU

90USB1286-16MU

90USB1287-16AU

90USB1287-16MU

90USB1286-16MU

Industrial (-40° to +85°C)

Green

Device

only

Industrial (-40° to +85°C)

Green

Industrial (-40° to +85°C)

Green

OTG

Industrial (-40° to +85°C)

Green

Device

only

Industrial (-40° to +85°C)

Green

421

7593D–AVR–07/06

33.1 TQFP64

422

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

33.2 QFN64

423

7593D–AVR–07/06

34. Errata

The revision letter in this section refers to the revision of the AT90USB64/128 device.

34.1 AT90USB1287/6 Rev B

• USB signal rate

• Spike on TWI pins when TWI is enabled

• High current consumption in sleep mode

• Async timer interrupt wake up from sleep generate multiple interrupts

4.

UBS signal rate

The average USB signal rate may sometime be measured out of the USB specifications

(12MHz ±30kHz) with short frames. When measured on a long period, the average signal

rate value complies with the specifications. This bit rate deviation does not generates com-

munication or functional errors.

Problem fix/workaround

None.

3. Spike on TWI pins when TWI is enabled

100 ns negative spike occurs on SDA and SCL pins when TWI is enabled.

Problem Fix/workaround

No known workaround, enable AT90USB64/128 TWI first versus the others nodes of the

TWI network.

2. High current consumption in sleep mode

If a pending interrupt cannot wake the part up from the selected mode, the current consump-

tion will increase during sleep when executing the SLEEP instruction directly after a SEI

instruction.

Problem Fix/workaround

Before entering sleep, interrupts not used to wake up the part from the sleep mode should

be disabled.

1. Asynchronous timer interrupt wake up from sleep generates multiple interrupts

If the CPU core is in sleep and wakes-up from an asynchronous timer interrupt and then go

back in sleep mode again it may wake up several times.

Problem Fix/workaround

A software workaround is to wait with performing the sleep instruction until

TCNT2>OCR2+1.

424

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

34.2 AT90USB1287/6 Rev A

• USB signal rate

• VBUS residual level

• Spike on TWI pins when TWI is enabled

• High current consumption in sleep mode

• Async timer interrupt wake up from sleep generate multiple interrupts

5.

UBS signal rate

The average USB signal rate may sometime be measured out of the USB specifications

(12MHz ±30kHz) with short frames. When measured on a long period, the average signal

rate value complies with the specifications. This bit rate deviation does not generates com-

munication or functional errors.

Problem fix/workaround

None.

4.

VBUS residual level

In USB device and host mode, once a 5V level has been detected to the VBUS pad, a resid-

ual level (about 3V) can be measured on the VBUS pin.

Problem fix/workaround

None.

3. Spike on TWI pins when TWI is enabled

100 ns negative spike occurs on SDA and SCL pins when TWI is enabled.

Problem Fix/workaround

No known workaround, enable AT90USB64/128 TWI first versus the others nodes of the

TWI network.

2. High current consumption in sleep mode

If a pending interrupt cannot wake the part up from the selected mode, the current consump-

tion will increase during sleep when executing the SLEEP instruction directly after a SEI

instruction.

Problem Fix/workaround

Before entering sleep, interrupts not used to wake up the part from the sleep mode should

be disabled.

1. Asyncrhonous timer interrupt wake up from sleep generates multiple interrupts

If the CPU core is in sleep and wakes-up from an asynchronous timer interrupt and then go

back in sleep again it may wake up multiple times.

Problem Fix/workaround

A software workaround is to wait with performing the sleep instruction until

TCNT2>OCR2+1.

425

7593D–AVR–07/06

35. Datasheet Revision History for AT90USB64/128

Please note that the referring page numbers in this section are referred to this document. The

referring revision in this section are referring to the document revision.

35.1 Changes from 7593A to 7593B

1. Changed default configuration for fuse bytes and security byte.

2. Suppression of timer 4,5 registers which does not exist.

Updated typical application schematics in USB section

35.2 Changes from 7593B to 7593C

1. Update to package drawings, MQFP64 and TQFP64.

35.3 Changes from 7593C to 7593D

1. For further product compatibility, changed USB PLL possible prescaler configurations.

Only 8MHz and 16MHz crystal frequencies allows USB operation (See Table 6-13 on

page 51).

426

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

1

2

Pin Configurations ................................................................................... 3

1.1Disclaimer ..................................................................................................................4

Overview ................................................................................................... 4

2.1Block Diagram ...........................................................................................................5

2.2Pin Descriptions .........................................................................................................6

3

4

About Code Examples ............................................................................. 8

AVR CPU Core ........................................................................................ 10

4.1Introduction ..............................................................................................................10

4.2Architectural Overview .............................................................................................10

4.3ALU – Arithmetic Logic Unit .....................................................................................11

4.4Status Register ........................................................................................................12

4.5General Purpose Register File ................................................................................13

4.6Stack Pointer ...........................................................................................................14

4.7Instruction Execution Timing ...................................................................................15

4.8Reset and Interrupt Handling ...................................................................................16

5

6

AVR AT90USB64/128 Memories ........................................................... 19

5.1In-System Reprogrammable Flash Program Memory .............................................19

5.2SRAM Data Memory ................................................................................................20

5.3EEPROM Data Memory ..........................................................................................23

5.4I/O Memory ..............................................................................................................29

5.5External Memory Interface ......................................................................................30

System Clock and Clock Options ......................................................... 39

6.1Clock Systems and their Distribution .......................................................................39

6.2Clock Sources .........................................................................................................40

6.3Low Power Crystal Oscillator ...................................................................................41

6.4Low Frequency Crystal Oscillator ............................................................................44

6.5Calibrated Internal RC Oscillator .............................................................................44

6.6128 kHz Internal Oscillator ......................................................................................46

6.7External Clock .........................................................................................................47

6.8Clock Output Buffer .................................................................................................48

6.9Timer/Counter Oscillator ..........................................................................................48

6.10System Clock Prescaler ........................................................................................48

6.11PLL ........................................................................................................................50

7

Power Management and Sleep Modes ................................................. 53

1

7593D–AVR–07/06

7.1Idle Mode .................................................................................................................54

7.2ADC Noise Reduction Mode ....................................................................................54

7.3Power-down Mode ...................................................................................................54

7.4Power-save Mode ....................................................................................................54

7.5Standby Mode .........................................................................................................55

7.6Extended Standby Mode .........................................................................................55

7.7Power Reduction Register .......................................................................................56

7.8Minimizing Power Consumption ..............................................................................57

8

9

System Control and Reset .................................................................... 59

8.1Internal Voltage Reference ......................................................................................64

8.2Watchdog Timer ......................................................................................................64

Interrupts ................................................................................................ 70

9.1Interrupt Vectors in AT90USB64/128 ......................................................................70

10 I/O-Ports .................................................................................................. 74

10.1Introduction ............................................................................................................74

10.2Ports as General Digital I/O ...................................................................................75

10.3Alternate Port Functions ........................................................................................79

10.4Register Description for I/O-Ports ..........................................................................92

11 External Interrupts ................................................................................. 96

12 Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers . 100

12.1Internal Clock Source ..........................................................................................100

12.2Prescaler Reset ...................................................................................................100

12.3External Clock Source .........................................................................................100

12.4General Timer/Counter Control Register – GTCCR ............................................101

13 8-bit Timer/Counter0 with PWM .......................................................... 102

13.1Overview ..............................................................................................................102

13.2Timer/Counter Clock Sources .............................................................................103

13.3Counter Unit ........................................................................................................103

13.4Output Compare Unit ...........................................................................................104

13.5Compare Match Output Unit ................................................................................106

13.6Modes of Operation .............................................................................................107

13.7Timer/Counter Timing Diagrams .........................................................................111

13.88-bit Timer/Counter Register Description ............................................................112

14 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3) ........... 119

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14.1Overview ..............................................................................................................119

14.2Accessing 16-bit Registers ..................................................................................121

14.3Timer/Counter Clock Sources .............................................................................124

14.4Counter Unit ........................................................................................................124

14.5Input Capture Unit ...............................................................................................126

14.6Output Compare Units .........................................................................................128

14.7Compare Match Output Unit ................................................................................129

14.8Modes of Operation .............................................................................................131

14.9Timer/Counter Timing Diagrams .........................................................................138

14.1016-bit Timer/Counter Register Description ........................................................140

15 8-bit Timer/Counter2 with PWM and Asynchronous Operation ...... 151

15.1Overview ..............................................................................................................151

15.2Timer/Counter Clock Sources .............................................................................152

15.3Counter Unit ........................................................................................................152

15.4Output Compare Unit ...........................................................................................153

15.5Compare Match Output Unit ................................................................................155

15.6Modes of Operation .............................................................................................156

15.7Timer/Counter Timing Diagrams .........................................................................160

15.88-bit Timer/Counter Register Description ............................................................162

15.9Asynchronous operation of the Timer/Counter ....................................................167

15.10Timer/Counter Prescaler ...................................................................................171

16 Output Compare Modulator (OCM1C0A) ........................................... 172

16.1Overview ..............................................................................................................172

16.2Description ...........................................................................................................172

17 Serial Peripheral Interface – SPI ......................................................... 174

17.1SS Pin Functionality ............................................................................................178

17.2Data Modes .........................................................................................................181

18 USART ................................................................................................... 183

18.1Overview ..............................................................................................................183

18.2Clock Generation .................................................................................................184

18.3Frame Formats ....................................................................................................187

18.4USART Initialization .............................................................................................189

18.5Data Transmission – The USART Transmitter ....................................................190

18.6Data Reception – The USART Receiver .............................................................192

18.7Asynchronous Data Reception ............................................................................196

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18.8Multi-processor Communication Mode ................................................................199

18.9USART Register Description ...............................................................................200

18.10Examples of Baud Rate Setting .........................................................................205

19 USART in SPI Mode ............................................................................. 208

19.1Overview ..............................................................................................................208

19.2Clock Generation .................................................................................................209

19.3SPI Data Modes and Timing ................................................................................209

19.4Frame Formats ....................................................................................................210

19.5Data Transfer .......................................................................................................212

19.6USART MSPIM Register Description ..................................................................214

19.7AVR USART MSPIM vs. AVR SPI ......................................................................216

20 2-wire Serial Interface .......................................................................... 218

20.1Features ..............................................................................................................218

20.22-wire Serial Interface Bus Definition ..................................................................218

20.3Data Transfer and Frame Format ........................................................................219

20.4Multi-master Bus Systems, Arbitration and Synchronization ...............................222

20.5Overview of the TWI Module ...............................................................................223

20.6TWI Register Description .....................................................................................226

20.7Using the TWI ......................................................................................................229

20.8Transmission Modes ...........................................................................................233

20.9Multi-master Systems and Arbitration ..................................................................246

21 USB controller ...................................................................................... 248

21.1Features ..............................................................................................................248

21.2Block Diagram .....................................................................................................248

21.3Typical Application Implementation .....................................................................249

21.4General Operating Modes ...................................................................................253

21.5Power modes .......................................................................................................257

21.6Speed Control ......................................................................................................258

21.7Memory management ..........................................................................................259

21.8PAD suspend .......................................................................................................260

21.9OTG timers customizing ......................................................................................261

21.10Plug-in detection ................................................................................................261

21.11ID detection .......................................................................................................262

21.12Registers description .........................................................................................263

21.13USB Software Operating modes .......................................................................267

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AT90USB64/128

22 USB Device Operating modes ............................................................ 269

22.1Introduction ..........................................................................................................269

22.2Power-on and reset .............................................................................................269

22.3Speed identification on startup ............................................................................269

22.4Endpoint reset .....................................................................................................270

22.5USB reset ............................................................................................................270

22.6Endpoint selection ...............................................................................................270

22.7Endpoint activation ..............................................................................................270

22.8Address Setup .....................................................................................................271

22.9Suspend, Wake-up and Resume .........................................................................272

22.10Detach ...............................................................................................................272

22.11Remote Wake-up ...............................................................................................273

22.12STALL request ...................................................................................................273

22.13CONTROL endpoint management ....................................................................274

22.14OUT endpoint management ..............................................................................275

22.15IN endpoint management ..................................................................................277

22.16Isochronous mode .............................................................................................278

22.17Overflow ............................................................................................................279

22.18Interrupts ...........................................................................................................279

22.19Registers ...........................................................................................................281

23 USB Host Operating Modes ................................................................ 293

23.1Pipe description ...................................................................................................293

23.2Detach .................................................................................................................293

23.3Power-on and Reset ............................................................................................293

23.4Device Detection .................................................................................................294

23.5Pipe Selection ......................................................................................................294

23.6Pipe Configuration ...............................................................................................294

23.7USB Reset ...........................................................................................................296

23.8Address Setup .....................................................................................................296

23.9Remote Wake-Up detection ................................................................................296

23.10USB Pipe Reset .................................................................................................296

23.11Pipe Data Access ..............................................................................................296

23.12Control Pipe management .................................................................................297

23.13OUT Pipe management .....................................................................................297

23.14IN Pipe management .........................................................................................298

23.15Interrupt system .................................................................................................299

5

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23.16Registers ...........................................................................................................300

24 Analog Comparator .............................................................................. 313

24.1Analog Comparator Multiplexed Input .................................................................315

25 Analog to Digital Converter - ADC ...................................................... 316

25.1Features ..............................................................................................................316

25.2Operation .............................................................................................................317

25.3Starting a Conversion ..........................................................................................318

25.4Prescaling and Conversion Timing ......................................................................319

25.5Changing Channel or Reference Selection .........................................................322

25.6ADC Noise Canceler ...........................................................................................323

25.7ADC Conversion Result .......................................................................................327

25.8ADC Register Description ....................................................................................329

26 JTAG Interface and On-chip Debug System ...................................... 335

26.1Overview ..............................................................................................................335

26.2Test Access Port – TAP ......................................................................................335

26.3TAP Controller .....................................................................................................337

26.4Using the Boundary-scan Chain ..........................................................................338

26.5Using the On-chip Debug System .......................................................................338

26.6On-chip Debug Specific JTAG Instructions .........................................................339

26.7On-chip Debug Related Register in I/O Memory .................................................340

26.8Using the JTAG Programming Capabilities .........................................................340

26.9Bibliography .........................................................................................................340

27 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 341

27.1Features ..............................................................................................................341

27.2System Overview .................................................................................................341

27.3Data Registers .....................................................................................................341

27.4Boundary-scan Specific JTAG Instructions .........................................................343

27.5Boundary-scan Related Register in I/O Memory .................................................344

27.6Boundary-scan Chain ..........................................................................................345

27.7AT90USB64/128 Boundary-scan Order ..............................................................348

27.8Boundary-scan Description Language Files ........................................................351

28 Boot Loader Support – Read-While-Write Self-Programming ......... 352

28.1Boot Loader Features ..........................................................................................352

28.2Application and Boot Loader Flash Sections .......................................................352

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28.3Read-While-Write and No Read-While-Write Flash Sections ..............................352

28.4Boot Loader Lock Bits .........................................................................................355

28.5Entering the Boot Loader Program ......................................................................356

28.6Addressing the Flash During Self-Programming .................................................360

28.7Self-Programming the Flash ................................................................................361

29 Memory Programming ......................................................................... 368

29.1Program And Data Memory Lock Bits .................................................................368

29.2Fuse Bits ..............................................................................................................369

29.3Signature Bytes ...................................................................................................371

29.4Calibration Byte ...................................................................................................371

29.5Parallel Programming Parameters, Pin Mapping, and Commands .....................371

29.6Parallel Programming ..........................................................................................374

29.7Serial Downloading ..............................................................................................382

29.8Serial Programming Pin Mapping ........................................................................383

29.9Programming via the JTAG Interface ..................................................................387

30 Electrical Characteristics .................................................................... 400

30.1Absolute Maximum Ratings* ...............................................................................400

30.2DC Characteristics ...............................................................................................400

30.3External Clock Drive Waveforms .........................................................................402

30.4External Clock Drive ............................................................................................402

30.5Maximum speed vs. V_{CC ..............................................................................................................................402}

30.62-wire Serial Interface Characteristics .................................................................403

30.7SPI Timing Characteristics ..................................................................................405

30.8Hardware Boot EntranceTiming Characteristics ..................................................406

30.9ADC Characteristics – Preliminary Data ..............................................................407

30.10External Data Memory Timing ...........................................................................408

31 Register Summary ............................................................................... 414

32 Instruction Set Summary ..................................................................... 418

33 Ordering Information ........................................................................... 421

33.1TQFP64 ...............................................................................................................422

33.2QFN64 .................................................................................................................423

34 Errata ..................................................................................................... 424

34.1Rev B ...................................................................................................................424

34.2Rev A ...................................................................................................................424

7

7593D–AVR–07/06

35 Datasheet Revision History for AT90USB64/128 .............................. 426

35.1Changes from 7593A to 7593B ...........................................................................426

35.2Changes from 7593B to 7593C ...........................................................................426

35.3Changes from 7593C to 7593D ...........................................................................426

8

AT90USB64/128

7593D–AVR–07/06

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Printed on recycled paper.

7593D–AVR–07/06


型号：	AT90USB646
厂家：	ATMEL
描述：	8-bit Microcontroller with 64/128K Bytes of ISP Flash and USB Controller 8位微控制器具有ISP功能的Flash和USB控制器64 / 128K字节微控制器
文件：	总435页 (文件大小：2724K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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