AT91RM9200-EK [ATMEL]
AT91RM9200-EK Evaluation Board User Guide; AT91RM9200 - EK评估板用户指南
| 型号： | AT91RM9200-EK |
| 厂家： | 
ATMEL |
| 描述： | AT91RM9200-EK Evaluation Board User Guide |
| 文件： | 总33页 (文件大小：777K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AT91RM9200-EK Evaluation Board
..............................................................................................
User Guide
Table of Contents
Section 1
Overview...............................................................................................1-1
1.1 Scope........................................................................................................1-1
1.2 Deliverables ..............................................................................................1-2
1.3 The AT91RM9200-EK Evaluation Board ..................................................1-3
Section 2
Setting Up the AT91RM9200-EK
Evaluation Board ..................................................................................2-1
2.1 Electrostatic Warning ................................................................................2-1
2.2 Requirements............................................................................................2-1
2.3 Powering Up the Board.............................................................................2-1
2.4 Getting Started with the AT91RM9200 .....................................................2-1
Section 3
Board Description .................................................................................3-1
3.1 AT91RM9200 Processor...........................................................................3-1
3.2 Memory .....................................................................................................3-2
3.3 Memory Card ............................................................................................3-2
3.4 Clock Circuitry and Analog Functions .......................................................3-2
3.5 Reset Circuitry...........................................................................................3-2
3.6 Power Supply Circuitry..............................................................................3-2
3.7 Remote Communication............................................................................3-2
3.8 User Interface ...........................................................................................3-2
3.9 Expansion Slot..........................................................................................3-3
3.10 Debug Interface ........................................................................................3-3
3.11 Wrapping User Area..................................................................................3-3
Section 4
Configuration Straps.............................................................................4-1
4.1 Configuration Straps and Jumper Settings ...............................................4-1
Section 5
Schematics ...........................................................................................5-1
5.1 Schematics ...............................................................................................5-1
Section 6
Errata....................................................................................................6-1
6.1 Errata ........................................................................................................6-1
6.1.1 SD/MMC Card slot communication problem ......................................6-1
AT91RM9200-EK Evaluation Board User Guide
1
6103C–ATARM–05-Jan-06
Table of Contents
2
AT91RM9200-EK Evaluation Board User Guide
6103C–ATARM–05-Jan-06
Overview
Section 1
Overview
1.1
Scope
The AT91RM9200-EK Evaluation Board enables real-time code development and eval-
uation. It supports the AT91RM9200 ARM9™-based 32-bit RISC microcontroller.
This guide focuses on the AT91RM9200-EK Evaluation Board as an evaluation and
demonstration platform:
! Section 1 is this overview.
! Section 2 gives information on setting up the installation.
! Section 3 contains a description of the development board.
! Section 4 details the configuration straps.
! Section 5 shows board schematics.
! Section 6 contains errata.
AT91RM9200-EK Evaluation Board User Guide
1-1
6103C–ATARM–05-Jan-06
Overview
1.2
Deliverables
The development kit is delivered with:
! One AC adapter 100 - 240V ~ 1.2A, 12V, 50 - 60 Hz with adapters
! One modem RS232 cable
! One RJ45 Ethernet crossed cable
! One A/B-type USB cable
! One AT91 DVD-ROM containing summary and full datasheets, datasheets with
electrical and mechanical characteristics, application notes and getting started
documents for all development boards and AT91 microcontrollers. An AT91 software
package with C and assembly listings is also provided. This allows the user to begin
evaluating the AT91 ARM® Thumb® 32-bit microcontroller quickly.
! CD ROMs from third parties, providing solutions for operating system evaluation
! DataFlash® Cards to provide demonstrations of operating systems when inserted in
the bootable slot
Note: To boot on a DataFlash Card:
- Ensure J15 (BMS) is set on position 1-2
- Insert the DataFlash Card in the J200 socket (bottom side)
- Reset the board
Further details are given on the AT91 DVD-ROM.
Note: These deliverables are subject to change without notice.
1-2
AT91RM9200-EK Evaluation Board User Guide
6103C–ATARM–05-Jan-06
Overview
1.3
The
The board consists of an AT91RM9200 together with the following:
! 8 Mbytes of parallel Flash memory
AT91RM9200-EK
Evaluation Board
! Four banks of 2M x 32-bit SDRAM
! DataFlash® or SD/MMC memory expansion socket
! Additional DataFlash memory expansion socket
! Digital-to-Analog Converter (DAC) for a stereo audio signal
! Four communication ports (USB host and device, Ethernet, serial and DBGU)
! Graphic controller with output to a standard VGA monitor
! JTAG/ICE, ETM and code test port interface
! Expansion connector
! Onboard prototype area
AT91RM9200-EK Evaluation Board User Guide
1-3
6103C–ATARM–05-Jan-06
Overview
Figure 1-1. AT91RM9200-EK Evaluation Board Block Diagram
LCD Panel
Slot
LCD Panel
Slot
VGA Connector
16
Flash
Graphic Display
Controller
Clock
Controller
32
25
Ethernet
Port
DataFlash Card
Socket
Ethernet
PHY
LED LED LED
Expansion Slot
SDRAM
ICE Debug Port
EBI
SPI
EMAC
JTAG
ETM
UHP
UDP
USB Host
Port
Trace Port
AT91RM9200
DBGU
USB Device
Port
RS232 Driver
NRST
MCI or
SPI
USART
TWI
Code Test Port
DataFlash Card/
SDCard
Oscillator, PLL
and Reset
RS232
Driver
Socket
DC
Input
Power
Supply
Digital-to-Analog
Converter
Stereo Output
1-4
AT91RM9200-EK Evaluation Board User Guide
6103C–ATARM–05-Jan-06
Section 2
Setting Up the AT91RM9200-EK
Evaluation Board
2.1
Electrostatic
Warning
The AT91RM9200-EK Evaluation Board is shipped in protective anti-static packaging.
The board must not be subjected to high electrostatic potentials. A grounding strap or
similar protective device should be worn when handling the board. Avoid touching the
component pins or any other metallic element.
2.2
2.3
Requirements
In order to connect the AT91RM9200-EK Evaluation Board, the following element is
required:
! The AT91RM9200-EK Evaluation Board itself
Powering Up the DC power is supplied to the board via the 2.1 mm socket (J1). The polarity of the power
Board
supply is not critical. The minimum voltage required is 7V.
The board has three voltage regulators providing 1.8V, 3.3V and 5V. The regulators
allow the input voltage range to be from 7V to 12V.
2.4
Getting Started
with the
AT91RM9200
The AT91RM9200-EK Evaluation Board is delivered with a DVD-ROM containing all
necessary information and step-by-step procedures for working with the most common
development tool chains. Please refer to this DVD-ROM, or to the AT91 web site,
http://www.atmel.com/products/AT91/ for the most up-to-date information on getting
started with the AT91RM9200.
AT91RM9200-EK Evaluation Board User Guide
2-1
Rev. 6103C–ATARM–05-Jan-06
Setting Up the AT91RM9200-EK Evaluation Board
2-2
AT91RM9200-EK Evaluation Board User Guide
6103C–ATARM–05-Jan-06
Section 3
Board Description
3.1
AT91RM9200
Processor
! Incorporates the ARM920T™ ARM® Thumb® Processor
– 200 MIPS at 180 MHz
– 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer
– Memory Management Unit
– In-circuit Emulator including Debug Communication Channel
– Mid-level Implementation Embedded Trace Macrocell™
! Additional Embedded Memories
– 16K Bytes of SRAM and 128K Bytes of ROM
! External Bus Interface (EBI)
– Supports SDRAM, Static Memory, Burst Flash, Glueless Connection to
CompactFlash®, SmartMedia® and NAND Flash
! System Peripherals:
– Enhanced Clock Generator and Power Management Controller
– Two On-chip Oscillators with Two PLLs
– Very Slow Clock Operating Mode and Software Power Optimization
Capabilities
– Four Programmable External Clock Signals
– System Timer Including Periodic Interrupt, Watchdog and Second Counter
– Real-time Clock with Alarm Interrupt
– Debug Unit, Two-wire UART and Support for Debug Communication Channel
– Advanced Interrupt Controller with 8-level Priority, Individually Maskable
Vectored Interrupt Sources, Spurious Interrupt Protected
– Seven External Interrupt Sources and One Fast Interrupt Source
– Four 32-bit PIO Controllers with Up to 122 Programmable I/O Lines, Input
Change Interrupt and Open-drain Capability on Each Line
– 20-channel Peripheral DMA Controller (PDC)
! Ethernet MAC 10/100 Base-T
! USB 2.0 Full Speed (12 M-bits per second) Host Double Port and Device Port
AT91RM9200-EK Evaluation Board User Guide
3-1
Rev. 6103C–ATARM–05-Jan-06
Board Description
! MultiMedia Card Interface (MCI)
! Three Synchronous Serial Controllers (SSC)
! Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
! Master/Slave Serial Peripheral Interface (SPI)
! Two 3-channel, 16-bit Timer/Counters (TC)
! Two-wire Interface (TWI)
! IEEE 1149.1 JTAG Boundary Scan on All Digital Pins
3.2
3.3
Memory
! 8-Mbyte parallel Flash memory
! Four banks of 2M x 32-bit SDRAM
Memory Card
! SD Card/MMC
– Supports MultiMedia and SD Card
– Analog switches provide support for DataFlash® Card
! Additional DataFlash Card Socket
3.4
Clock Circuitry
and Analog
Functions
! 32.768 kHz standard crystal for the AT91RM9200
! 18.432 MHz standard crystal for the AT91RM9200
! 50 MHz CMOS oscillator for the Display Controller and Ethernet PHY
3.5
3.6
Reset Circuitry
! Reset Controller
Power Supply
Circuitry
! 5V DC/DC converter
! 3.3V DC/DC converter
! 1.8V Linear regulator
3.7
Remote
Communication
! Fast Ethernet Physical Layer Single Chip Transceiver
! Host Interface via RS-232 DB9 male socket
! Debug Port via RS-232 DB9 connector
! Host and Device USB socket
3.8
User Interface
! Graphic Display Controller
! TFT/SNT panel socket
3-2
AT91RM9200-EK Evaluation Board User Guide
6103C–ATARM–05-Jan-06
Board Description
! 15-pin standard socket for an external VGA monitor
! Three LEDs managed via general PIO lines
! Stereo Audio Jack connected to a DAC
3.9
Expansion Slot
Debug Interface
! The expansion slot gives access to all the microcontroller’s signals.
3.10
! 38-pin trace Port socket (ETM)
! 38-pin Code Test port socket
! 20-pin JTAG ICE interface connector
! Serial Debug Unit
3.11
Wrapping User
Area
! Onboard prototype area allowing the developer to fit additional components.
AT91RM9200-EK Evaluation Board User Guide
3-3
6103C–ATARM–05-Jan-06
Board Description
3-4
AT91RM9200-EK Evaluation Board User Guide
6103C–ATARM–05-Jan-06
Section 4
Configuration Straps
4.1
Configuration
Straps and
Table 4-1 gives details on configuration straps and jumper settings on the
AT91RM9200-EK Evaluation Board and their default settings.
Jumper Settings
Table 4-1. Configuration Straps and Jumper Settings
Default
Designation
Setting
Closed
1 - 2
Feature
J13
Available for measuring VDDCORE current.
The AT91RM9200 boots from internal ROM and can also boot
from external SPI DataFlash® connected on NPCS0.
J15
2 - 3
The AT91RM9200 boots from Flash memory connected on NCS0.
AT91RM9200-EK Evaluation Board User Guide
4-1
Rev. 6103C–ATARM–05-Jan-06
Configuration Straps
4-2
AT91RM9200-EK Evaluation Board User Guide
6103C–ATARM–05-Jan-06
Section 5
Schematics
5.1
Schematics
This section contains the following schematics:
! AT91RM9200-EK Board Layout, Rev. 63PC042262A01 - Top View
! AT91RM9200-EK Board Layout, Rev. 63PC042262A01 - Bottom View
! Power Supply
! AT91RM9200 Chip
! Debug
! SDRAM and Flash
! RMII Ethernet
! Stereo Audio DAC
! Serial Interfaces
! VGA Display
! Expansion Connector
AT91RM9200-EK Evaluation Board User Guide
5-1
Rev. 6103C–ATARM–05-Jan-06
Schematics
Figure 5-1. AT91RM9200-EK Board Layout, Rev. 63PC042262A01 - Top View
5-2
AT91RM9200-EK Evaluation Board User Guide
6103C–ATARM–05-Jan-06
Schematics
Figure 5-2. AT91RM9200-EK Board Layout, Rev. 63PC042262A01 - Bottom View
AT91RM9200-EK Evaluation Board User Guide
5-3
6103C–ATARM–05-Jan-06
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Z11
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The Z reference designators
are not listed on the actual
board.
GUARD RING
TP2
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AT91RM9200-EK
AT91RM9200-EK
AT91RM9200-EK
1
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NORMALLY CLOSED
POWER SUPPLY
POWER SUPPLY
POWER SUPPLY
63SC042261
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PB[0..29]
PA[0..31]
PC[0..15]
D[0..31]
A[0..25]
PD[0..27]
D0
D1
D2
D3
D4
D5
D6
D7
R9
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
P10
N11
U9
D
C
B
A
D
C
B
A
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
E17
F15
F14
E16
D17
C17
D16
D6
A6
B6
C6
A5
B5
PD0/ETX0
PD1/ETX1
PD2/ETX2
PD3/ETX3
PD4/ETXEN
PD5/ETXER
PD6/DTXD
PD7/PCK0/TSYNC
PD8/PCK1/TCLK
PD9/PCK2/TPS0
PD10/PCK3/TPS1
PD11/TPS2
PD12/TPK0
PD13/TPK1
M11
P11
U10
U11
R11
T11
P12
U12
T12
R12
U13
P13
U14
R13
U15
T14
U16
T15
U17
T16
R15
T17
P14
P15
N13
R16
N15
N14
D8
D9
PD8
PD9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
B2
C3
C2
F1
PD14/TPK2
PC16/D16
PC17/D17
PC18/D18
PC19/D19
PC20/D20
PC21/D21
PC22/D22
PC23/D23
PC24/D24
PC25/D25
PC26/D26
PC27/D27
PC28/D28
PC29/D29
PC30/D30
PC31/D31
PD15/TD0/TPK3
PD16/TD1/TPK4
PD17/TD2/TPK5
PD18/NPCS1/TPK6
PD19/NPCS2/TPK7
PD20/NPCS3/TPK8
PD21/RTS0/TPK9
PD22/RTS1/TPK10
PD23/RTS2/TPK11
PD24/RTS3/TPK12
PD25/DTR1/TPK13
PD26/TPK14
G2
G5
G1
H2
H4
H3
H1
J3
J1
J4
J2
PD27/TPK15
K5
K2
DDP
DDM
DDP
DDM
A0
A1
A2
A3
A4
A5
A6
A7
N1
M4
M6
M3
N4
N2
L4
NBS0/A0
NWR2/NBS2/A1
K1
K3
HDPA
HDMA
HDPA
HDMA
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
L2
L3
3V3
HDPB
HDMB
HDPB
HDMB
P1
N7
N3
M5
P5
P3
P2
N5
T1
U3
T3
R3
U4
R4
N8
P6
T4
R5
P7
A8
A9
R38
47K
A1
C1
E5
TDI
TDI
TMS
TCK
TMS
TCK
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
AT91RM9200
B1
E2
A2
1
3
TDO
NTRST
TDO
NTRST
JTAGSEL
U11
R292
0R
PA31
J15
BOOT MODE SELECT
1-2: BMS=Hight=Internal Boot
1-3: BMS=Low=External Boot from NCS0
2
A15
VDDPLL
C31
100NF
H13
H15
F17
K17
VDDPLLB
GNDPLLB
PLLRCB
XOUT
BA0/A16
BA1/A17
A18
A19
A20
A21
A22
C292
4.7NF
R286
1K96
1%
R39
470R
C293
470pF
PC7/A23
PC8/A24
CFRNW/PC9/A25
R285
C273
10PF
0R
N10
U8
RAS
CAS
RAS
CAS
Y3
C287
10PF
18.4320MHz
J17
CR10
BAT54-7
NRST
3
T8
N6
P9
U7
SDWE
SDA10
SDCKE
SDCK
XIN
SDWE
SDA10
SDCKE
SDCK
VDDOSC
C280
100NF
J14
VDDOSC
J13
U6
M9
T6
R7
N9
BFCS_NCS0
SDCS
NCS2
SMCS_NCS3
CFOE_NOE_NRD
GNDOSC
XOUT32
BFCS/NCS0
SDCS/NCS1
NCS2
C288
10PF
C325
100NF
H17
3V3
SMCS/NCS3
CFOE/NOE/NRD
Y4
32.768 kHz
C291
10PF
P8
T7
R8
CFWE_NWE_NWR0
CFIOR_NBS1_NWR1
CFIOW_NBS3_NWR3
CFWE/NWE/NWR0
CFIOR/NBS1/NWR1
CFIOW/NBS3/NWR3
U10
GND
G17
J15
XIN32
1
2
4
3
RESET
VCC
MR
VDDPLL
C285
100NF
VDDPLLA
S1
J16
L17
E1
GNDPLLA
PLLRCA
NRST
RESET
R300
1%
C283
5.6NF
R284
1K27
1%
1K
1K
MAX6390XS29D4-T
D1
E4
TST1
TST0
1%
R291
R293
1K
1%
3V3
C284
680pF
1V8
NRST
J13
1
2
3V3
Monday, March 21, 2005
C302
10 uF
10V
C295
10 uF
10V
CR9
STPS1L30U
R290
R289
0R
0R
VDDOSC
VDDPLL
C301
100NF
A01101-3-05-106
ELX
MDZ
DES.
23/02/05 JPG
23/02/05
INIT EDIT
REV MODIF.
A
04/01/05
DATE
JPG 06/01/05
VER.
REV.
DATE
SHEET
2
SCALE1/1
AT91RM9200-EK
AT91RM9200
A01
63SC042261
9
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
PD[0..27]
PC[0..15]
D[0..31]
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D
C
B
A
D
C
B
A
CODETEST
PORT
PD7
PD8
PD9
J12
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
D0
D1
D2
D3
D4
D5
D6
D7
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
CT_CLK
A2
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
D8
D7
D6
D5
D4
D3
D2
D1
D8
D9
D10
D11
D12
D13
D14
D15
NCS7
A1
7
5
3
1
D0
PC13
R295
0R
PD8
6
4
2
R294
0R
A3
A4
A[0..25]
A1
A2
A3
A4
ETM
TRACE PORT
J16
PD9
PD20
PIPESTAT[0]
PIPESTAT[1]
PIPESTAT[2]
TRACESYNC
TRACEPKT[0]
TRACEPKT[1]
TRACEPKT[2]
TRACEPKT[3]
TRACEPKT[4]
TRACEPKT[5]
TRACEPKT[6]
TRACEPKT[7]
VSUPPLY
TRACEPKT[8]
TRACEPKT[9]
TRACEPKT[10]
TRACEPKT[11]
TRACEPKT[12]
TRACEPKT[13]
TRACEPKT[14]
TRACEPKT[15]
NTRST
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
PD10
PD11
PD7
PD21
PD22
PD23
PD24
PD25
PD26
PD27
3V3
R309
10K
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
3V3
J18
TDI
TMS
TCK
2
4
6
1
3
5
7
C323
100NF
R302
10K
NTRST
TDI
TMS
TCK
8
3V3
SYSTEM RESET
TDO
NSRST
DBGRQ
GND
10
12
14
16
18
20
9
R297
0R
EXTTRIG
11
13
15
17
19
NRST
7
5
TDO
NRST
PD8
R299
0R
TRACECLK
6
4
2
R298
10K
3
1
R310
0R
C320
100NF
C319
100NF
ICE INTERFACE
Monday, March 21, 2005
101-3-05-106
INIT EDIT
REV MODIF.
A01
A
ELX
MDZ
DES.
23/02/05 JPG
23/02/05
04/01/05
DATE
JPG 06/01/05
VER.
DATE
SHEET
3
SCALE1/1
REV.
AT91RM9200-EK
ETM - ICE - TEST
A01
63SC042261
9
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
EBI SDRAM INTERFACE
A[0..25]
D[0..31]
RAS
CAS
D
C
B
A
D
C
B
A
SDWE
SDA10
SDCKE
SDCK
CFIOR_NBS1_NWR1
CFIOW_NBS3_NWR3
U13
U200
A2
A3
A4
A5
A6
A7
A8
A9
D0
D1
D2
D3
D4
D5
D6
D7
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
23
24
25
26
29
30
31
32
33
34
22
35
2
4
5
7
23
24
25
26
29
30
31
32
33
34
22
35
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
SDCS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
MT48LC8M16A2
MT48LC8M16A2
8
10
11
13
42
44
45
47
48
50
51
53
A10
A11
D8
D9
DQ9
DQ9
SDA10
D10
D11
D12
D13
D14
D15
SDA10
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
A13
A13
A16
A17
A16
A17
BA0
BA1
BA0
BA1
20
21
20
21
BA0
BA1
BA0
BA1
A14
A14
36
40
36
40
3V3
3V3
N.C
N.C
N.C
N.C
1
1
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
14
27
3
9
43
49
14
27
3
9
43
49
SDCKE
SDCK
NBS0
SDCKE
SDCK
NBS2
37
38
37
38
CKE
CKE
CLK
CLK
A0
A1
15
39
15
39
DQML
DQMH
DQML
DQMH
CFIOR_NBS1_NWR1
CFIOW_NBS3_NWR3
28
41
54
6
12
46
52
28
41
54
6
12
46
52
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
CAS
RAS
CAS
RAS
17
18
17
18
CAS
RAS
CAS
RAS
C33
100NF
C312
100NF
SDWE
SDWE
16
19
16
19
WE
CS
WE
CS
C34
100NF
C298
100NF
128 Mbits
128 Mbits
D[0..31]
A[0..25]
U201
A1
A2
A3
A4
A5
A6
A7
A8
D0
D1
D2
D3
D4
D5
D6
D7
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16
15
10
9
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
A0
A1
A2
A3
A4
A5
A6
A7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
A9
D8
D9
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
DQ9
D10
D11
D12
D13
D14
D15
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
3V3
AT49BV6416-70TI
R32
47K
3V3
12
11
13
14
26
28
NRST
RESET
WE
VPP
WP
CE
OE
47
37
CFWE_NWE_NWR0
VCCQ
VCC
3V3
3V3
R31
10K
C28
100NF
C27
100NF
R33
0R
BFCS_NCS0
CFOE_NOE_NRD
46
27
GND
GND
Monday, March 21, 2005
101-3-05-106
INIT EDIT
REV MODIF.
A01
A
ELX
MDZ
DES.
23/02/05 JPG
23/02/05
04/01/05
JPG 06/01/05
VER.
DATE
DATE
REV.
SCALE1/1
S4HEET
9
AT91RM9200-EK
SDRAM & FLASH
A01
63SC042261
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
3V3
R20
3V3
Y1
10K
1
2
4
3
OE
VDD
OUT
C13
100NF
50 MHz
VSS
SG-8002JC-50.0000M-PCB
D
C
B
A
D
C
B
A
R15
0R
L201
742792093
1
2
PA[0..31]
PC[0..15]
VCCA
C228
100NF
C227
100NF
L200
742792093
1
2
VCCA
U3
R230
49R9
1%
C218
100NF
PA7
R231
49R9
1%
REFCK
42
43
7
REF_CLK/XT2
XT1
TX+
TX-
17
18
19
20
21
22
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK/ISOLATE
J2
TD+
CT
TX+
TX-
RX+
RX-
1
2
3
6
PA10
PA9
PA8
ETX1
1
3
2
ETX0
C217
100NF
100V
ETXEN
TD-
8
26
27
28
29
31
34
37
RXD3/ADR3
RXD2/ADR2
RXD1/ADR1
RXD0/ADR0
RX_EN
PA13
PA12
ERX1
ERX0
RD+
CT
R228
49R9
1%
3
7
6
8
RX+
RX-
R12
R14
10K
10K
C225
3V3
3V3
RX_CLK/SCRAMEN/10BTSER
PA11
PA14
ECRSDV
ERXER
RX_DV/TESTMODE
RD-
R229
49R9
1%
100NF
100V
4
16
38
TX_ER/TXD4
RX_ER/RXD4/RPTR
VCCA
C219
100NF
100V
75 75
C6
100NF
C5
100NF
C4
36
35
75
75
COL/RMII
DM9161E
4
5
7
8
1
2
9
4
5
CRS/ADR4
AVDD
AVDD
AVDD
PA15
PA16
PC4
R10
R11
0R
0R
EMDC
EMDIO
IRQ
24
25
32
MDC
MDIO
MDINTR
1nF
3V3
100NF
R13
C223
2K2
3V3
5
6
46
AGND
AGND
AGND
100NF
100NF
100NF
100NF
J0026D21
41
39
30
23
DVDD
DVDD
DVDD
DVDD
R212
10K
C224
C226
C229
R207
10K
R213
10K
47
BGRESG
R226
6K8
1%
DS1
OP0
OP1
OP2
RECEIVE STATUS
SUPER YELLOW
270R
270R
270R
R237
R214
R234
R211
R232
R208
3V3
48
BGRES
DNP
DNP
DNP
NOT INSTALLED
NOT INSTALLED
NOT INSTALLED
15
33
44
DGND
DGND
DGND
11
12
13
14
FDX/COLLED/OP0
SPEEDLED/OP1
LINK/ACTLED/OP2
CABLESTS/LINKSTS
DISPLAY SPEED STATUS
GREEN
= 100 Mb
R9
0R
DS3
10
40
PWRDWN
RESET
ACT LED
GREEN
45
NRST
SD
DS5
3V3
DNP
DNP
DNP
R3
47K
R242
10K
VCCA
VCCA
VCCA
3V3
L202
742792093
C230
OP2 OP1 OP0
100NF
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Dual speed 100/10 HDX
Reserved
1
1
2
2
C215
10 uF
10V
R209
R215
C220
10µF
R210
Reserved
Manually select 10TX HDX
Manually select 10TX FDX
NOT INSTALLED
L203
742792093
C231
100NF
Manually select 100TX HDX
Manually select 100TX FDX
VCCA
Auto negociation enables all capabilities (default)
R243
0R
Triple Light pipe, 5mm.
Install if putting board
into case.
LP2
LPF-C031304S
NOT INSTALLED
Monday, March 21, 2005
101-3-05-106
INIT EDIT
REV MODIF.
A01
A
ELX
MDZ
DES.
23/02/05 JPG
23/02/05
04/01/05
DATE
JPG 06/01/05
VER.
REV.
DATE
SHEET
5
SCALE1/1
AT91RM9200-EK
ETHERNET
A01
63SC042261
9
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
L2
742792093
1
2
3V3
3V3
D
C
B
A
D
C
B
A
C16
100NF
C15
100NF
C14
10 uF
10V
C10
10µF
C205
100NF
C204
100NF
C9
100NF
LINE OUT
J5
10
AVDD1
9
18
U2
5
4
3
2
1
AVDD0
VDD
C11
150uF
16V
C1
330PF
R203
R200
47R
47R
5
OUT_L
OUT_R
ST-3081-5N
R217
10K
21
7
DEECTRL
R204
15K
R218
15K
15K
TP4
DNP
TP7
DNP
C17
150uF
16V
37
38
39
35
34
FOUTL
FOPL
FINL
DEEMR
DEEML
R201
1K5
1%
R202
1K5
1%
R219
R220
10K
10K
20
19
16
15
MCS2
MCS1
SDA
R1
15K
R2
41
42
43
FOUTR
FOPR
FINR
TP8
DNP
TP9
DNP
C202
330PF
TWD
TWCK
SCL
DAC3550A
TP14
DNP
14
CLKOUT
32
31
AUX1R
AUX1L
DNP
TP6
DNP
TP12
30
29
AUX2R
AUX2L
DNP
PB[0..29]
TP13
DNP
TP15
27
25
24
23
TESTEN
WSI
DAI
TF1
TD1
TK1
PB6
PB8
PB7
R238
R240
R239
0R
0R
0R
4
6
8
11
22
28
33
36
40
CLI
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
26
NRST
PORQ
XTI
XTO
R241
10K
12
13
3V3
XTI
Triple Light pipe, 10mm.
Install if putting board
into case.
LP1
R221
10K
XTO
LPF-C031303S
VREF
44
AGNDC
AVSS1 AVSS0 VSS
17
NOT INSTALLED
1
2
3
3V3
3V3
3V3
C203
3.3µF
USER LED
1
USER LED
2
USER LED 3
PB[0..29]
DS2
GREEN
DS4
DS6
RED
SUPER YELLOW
PB0
PB1
PB2
R236
R235
R233
220R
R216
0R
220R
220R
GND AUDIO
Monday, March 21, 2005
A01 101-3-05-106
INIT EDIT
REV MODIF.
ELX
MDZ
DES.
23/02/05 JPG
23/02/05
A
04/01/05
DATE
JPG 06/01/05
VER.
REV.
DATE
SHEET
6
SCALE1/1
AT91RM9200-EK
I2S STEREO DAC
63SC042261
A01
9
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
3V3
U8
PA2
1
16
C1+
VCC
PA17
PA29
PA0
PB27
PB3
R304
0R
C257
100NF
C26
100NF
PA[0..31]
PB[0..29]
15
2
GND
V+
J17
3
4
PA[0..31]
C1-
C2+
12
11
10
8
7
6
5
4
3
2
J10
CD1 SW <2>
CD1 SW <1>
MCI8
PB4
C258
100NF
C260
U15
100NF
MCDA1
1
NO1
NC4
CO4
NO4
PB5
MCI7
C259
100NF
MCDA3
MISO
3
4
2
14
12
13
5
6
6
2
7
3
8
4
9
5
C2-
V-
SERIAL DEBUG PORT
RXD
TXD
CO1
NC1
MCI1
MCI7
MCI5
R259
4K7
11
14
T
T
3V3
D
C
B
A
D
C
B
A
PA6
R311 10K
MMC_CS
MCDA0
MCI2
MCI1
MCIA9
PA31
PA30
DBGU_TXD
10
12
9
7
1
9
IN
MCDA2
PB22
PA28
MMC_TYPE
MMC_CMD
1
DBGU_RXD
13
8
R
R
FPS009-2405-0
NO2
NC3
CO3
NO3
C321
100NF
R258
0R
SPCK
6
7
5
11
9
R260
3V3
4K7
CO2
NC2
MCI2
MCI5
PA1
MOSI
MMC_CLK
ADM3202ARN
10
SD CARD / MMC CARD OR
DATA FLASH INTERFACE
RIGHT ANGLE MALE SUBD
U14
16
8
15
V+
EN_B
5V
C318
100NF
28
26
C1+
VCC
C275
100NF
C42
100NF
R303
4K7
GND
25
27
GND
V+
PI5A100Q
24
1
C1-
C2+
J14
C276
C274
100NF
100NF
PB[0..29]
RS232 COM PORT
DCD
1
6
2
7
3
8
4
9
5
C297
100NF
DSR
RXD
RTS
TXD
CTS
DTR
RI
2
3
9
C2-
V-
PA27
T1IN
T1OUT
PB26
PB20
PB19
RTS1
TXD1
DTR1
14
T
T
T
T2IN
T3IN
T2OUT
T3OUT
J200
12
13
12
21
20
19
18
17
16
15
23
10
11
CD1 SW <2>
CD1 SW <1>
11
10
8
7
6
5
4
3
2
PB10
PA0
PA2
MISO
SPCK
R
R
SPCK
3V3
PA1
PA3
MOSI
NPCS0
MOSI
NPCS0
1
9
R1OUT
R2OUT
R3OUT
R4OUT
R5OUT
EN
R1IN
R
PB23
PB25
PB21
PB24
PB18
DCD1
DSR1
RXD1
CTS1
RI1
4
RIGHT ANGLE MALE SUBD
FPS009-2405-0
R2IN
R
C317
100NF
5
DATA FLASH
R3IN
R
6
INTERFACE ONLY
R4IN
R
7
3V3
R5IN
R
8
F2
0.20A
SHDN
R287
4K7
22
5V
C7
10 uF
10V
MAX3241ECW
R37
10K
C216
100NF
C214
10NF
PD[0..27]
R223
0R
R5
15K
F3
0.20A
PD4
PD5
USB_CNX
5V
R4
22K
3V3
C8
10 uF
10V
C210
100NF
C211
10NF
R222
47K
Q1
MMBT2222ALT1
J3
USB HOST INTERFACE
CCUSBA-32002-30X
R7
1K5
1%
USB_DP_PUP
A1
A2
A3
A4
B1
A
R17
R18
27R
27R
B2
B3
B4
HDMA
HDPA
CR6
BAT54-7
C207
33PF
3
B
NRST
R225
15K
R224
15K
C213
47pF
C212
47pF
1 2
3 4
J4
R6
R8
27R
27R
2
3
1
DDM
DDP
C209
100NF
4
C208
15PF
C206
15PF
5
6
R19
R16
27R
27R
HDMB
HDPB
Monday, March 21, 2005
USB DEVICE INTERFACE
C200
47pF
R206
15K
R205
15K
C201
47pF
A01 101-3-05-106
ELX
23/02/05 JPG
23/02/05
INIT EDIT
REV MODIF.
A
MDZ
DES.
04/01/05
DATE
JPG 06/01/05
VER.
DATE
SHEET
7
SCALE1/1
REV.
AT91RM9200-EK
SERIAL INTERFACES
A01
63SC042261
9
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
DNP
C252 C253
NOT INNSOTATLILNESDTALLED
DNP
DNP
J11
LUMINANCE 20% ..100%
C245
C244
C243
DNP
VR1
NOT IN2S0T%ALLED
100NF 100NF 100NF
1
L205
2
3
4
5
6
1
2
AVDDV
5V
742792093
1
3
R256
4K7
R270
4K7
CW
L206
742792093
2
1
A[0..25]
3V3
DNP
A21
C246
10µF
C250
10 uF
10V
U6
D
C
B
A
D
C
B
A
TWD
TWCK
6
5
13
12
14
D[0..31]
SDA RH/VH
SCL RW/VW
PC[0..15]
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
FDAT23
FDAT22
FDAT21
FDAT20
FDAT19
FDAT18
R0
6
7
8
107
106
105
104
103
102
101
100
98
97
96
95
94
93
91
90
87
86
85
84
83
10
4
11
AB20
FDAT23
A0
A2
A3
RL/VL
AB19
AB18
AB17
AB16
AB15
AB14
AB13
AB12
AB11
AB10
AB9
AB8
AB7
AB6
AB5
AB4
AB3
AB2
AB1
FDAT22
FDAT21
FDAT20
FDAT19
FDAT18
FDAT17
FDAT16
FDAT15
FDAT14
FDAT13
FDAT12
FDAT11
FDAT10
FDAT9
FDAT8
FDAT7
FDAT6
FDAT5
FDAT4
FDAT3
FDAT2
FDAT1
FDAT0
9
9
WP
3V3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
2
3
7
15
NC
NC
NC
NC
NC
16
8
3V3
VCC
VSS
B0
B1
B2
G0
G1
G2
R1
R2
B3
B4
B5
G3
G4
G5
R3
R4
C251
NOT INSTALLED
DNP
R278
2K7
R276
2K7
NOT INSTALLED
PA[0..31]
DNP
J9
DNP
J8
R277
0R
PA26
PA25
DOTCLK
VSYNC
R0
FDAT18
FDAT20
FDAT22
FDAT19
FDAT21
FDAT23
1
3
5
7
2
4
6
8
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2
4
6
8
HSYNC
R268
4K7
R1
R3
R5
G0
G2
G4
R2
R4
VMP0
VMP2
VMP4
VMP6
GPIO12
GPIO10
GPIO8
GPIO6
GPIO4
GPIO2
GPIO0
VMP1
VMP3
VMP5
VMP7
9
10
12
14
16
18
20
22
24
26
28
30
32
10
12
14
16
18
20
22
24
26
28
30
R279
0R
11
13
15
17
19
21
23
25
27
29
31
AB0
G1
G3
G5
B0
B2
B4
82
81
80
D15
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
R5
TWD
TWCK
GPIO11
GPIO9
GPIO7
GPIO5
GPIO3
GPIO1
VSYNC
HSYNC
DATAEN
B1
B3
B5
74
75
77
78
FPFRAME
FPLINE
DRDY
S1D13806
DISPLAY CONTROLLER
3V3
DOTCLK
DATAEN
FPSHIFT
PC6
U5
VMP7
VMP6
VMP5
VMP4
VMP3
VMP2
VMP1
VMP0
C235
131
130
129
128
127
126
125
124
VMP7
VMP6
VMP5
VMP4
VMP3
VMP2
VMP1
VMP0
NOT INSTALLED
NOT INSTALLED
DNP
R280
2K2
C222
DNP
C263
10 uF
10V
C261
100NF
DB4
DB3
DB2
DB1
C265
100NF
3V3
U7
1
24
3V3
VDDD
IREF
R265
47K
D0
DB0
CR200
CR201
BAV99-7
GPIO12
GPIO11
GPIO10
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
BAV99-7
2
23
22
39
35
34
33
32
31
30
29
28
134
135
136
137
57
61
63
65
67
68
69
3V3
VSSD
CLK/2+
CLK/2-
WAIT
RESET
RD/WR
WE1
WE0
RD
BS
M/R
CS
GPIO12
GPIO11
GPIO10
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
NRST
C267
10µF
AVDDV
3
4
SDA
SCL
CR202
BAV99-7
21
20
CFIOR_NBS1_NWR1
CFWE_NWE_NWR0
CFOE_NOE_NRD
CLK+
CLK-
C266
100NF
2
1
2
1
2
1
R266
5
6
7
PDEN
EXTFB
HSYNC
R261 10K
R262 10K
R264 10K
15K
19
SMCS_NCS3
3V3
VSSQ
3V3
R267
0R
3
3
3
3V3
C264
3.3NF
R269
47K
8
18
17
16
15
14
13
3V3
EXTFIL
VDDQ
CLK
C262
J6
60
66
64
62
BUSCLK
CLKI
CLKI2
150pF
9
R253
R254
10R
CA-15DHDSR-F-11
70
71
R263
6K8
1%
XFILRET
VDDA
L4
L5
L6
10R
6
1
7
2
8
3
9
4
10
5
CLK/2
FUNC
CLKI3
R
G
B
1
2
10
C237
100NF
11
112
115
117
119
120
113
11
12
13
14
15
3V3
RED
GREEN
BLUE
HRTC
VRTC
IREF
L204
742792093
R271
138
139
140
141
142
2
CNF7
CNF6
CNF5
CNF4
CNF3
CNF2
CNF1
CNF0
R272
R273
R274
R275
R283
R282
R281
C238
10µF
R255
10R
VSSA LOCK/REF
12
OSC
I2CADR
ICS1523
R246
150R
1%
R247
150R
1%
R252
150R
1%
3
4
4.6mA
Generic Little Indian
(Default)
3V3
C240
10 uF
10V
3V3
AVDDV
R251
1K5
1%
3V3
R21
10K
Y2
3V3
Q202
MMBT2222ALT1
Monday, March 21, 2005
1
2
4
3
OE
VDD
C239
100NF
50 MHz
VSS OUT
C236
100NF
R249
75R
1%
R250
1K
1%
SG-8002JC-50.0000M-PCB
A01101-3-05-106
INIT EDIT
REV MODIF.
ELX
23/02/05 JPG
23/02/05
JPG 06/01/05
A
MDZ
DES.
04/01/05
DATE
VER.
REV.
DATE
SHEET
8
SCALE1/1
AT91RM9200-EK
R22
0R
VGA TFT/CRT DISPLAY
63SC042261
A01
9
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
PD[0..27]
PC[0..15]
PB[0..29]
PA[0..31]
C324
100NF
3V3
3V3
3V3
3V3
3V3
3V3
5V
P1C
PA31
P15
1
P2
P1A
PA30
PA29
PA28
PA27
PA26
PA25
PA24
PA23
PA22
PA21
PA20
PA19
PA18
PA17
PA16
PA15
PA14
PA13
PA12
PA11
PA10
PA9
PA9
C1
C2
C3
C4
C5
C6
C7
C8
D
C
B
A
D
C
B
A
C1
C2
C3
C4
C5
C6
C7
C8
C9
1
PB29
PB28
PB27
PB26
PB25
PB24
PB23
PB22
PB21
PB20
PB19
PB18
PB17
PB16
PB15
PB14
PB13
PB12
PB11
PB10
PB9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
P39
1
P27
1
A1
A2
A3
A4
A5
A6
A7
A8
3V3
A1
A2
A3
A4
A5
A6
A7
A8
A9
D0
D1
D2
D3
D4
D5
D6
D7
D8
P16
1
P3
1
P40
1
P28
1
C9
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
P17
1
P5
A9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C41
C42
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C41
C42
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
1
P41
1
P29
1
D9
D10
D11
D12
D13
D14
D15
D16
P23
1
P4
PC15
1
PC14
PC13
PC12
PC11
PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
P42
1
P30
1
P24
1
P6
1
D17
D18
D19
D20
D21
D22
D23
D24
P43
1
P31
1
PB8
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PD6
P25
1
P7
TP16
PD5
PD4
PD3
PD2
PD1
PD0
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
1
P44
1
P32
1
P26
1
P10
1
PB0
PA0
D25
D26
D27
D28
D29
D30
D31
P45
1
P33
1
5V
P14
1
P11
1
PB9
PB10
PB11
PB12
PB13
PB14
PB15
P46
1
P34
1
5V
A0
A1
A2
A3
A4
NWR2
P18
1
P12
1
P47
1
P35
1
D[0..31]
A[0..25]
5V
P19
1
P13
1
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
P48
1
P36
1
P1B
P1D
5V
A5
A6
A7
A8
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
B1
B2
B3
B4
B5
B6
B7
B8
D1
D2
D3
D4
D5
D6
D7
D8
B1
B2
B3
B4
B5
B6
B7
B8
B9
D1
D2
D3
D4
D5
D6
D7
D8
D9
P20
1
P8
1
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
P49
1
P37
1
A9
5V
A10
A11
A12
P21
1
P9
1
P50
1
P38
1
B9
D9
3V3
A13
A14
A15
A16
A17
A18
A19
A20
PB24
PB25
PB26
PB27
PB28
PB29
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
P22
1
P51
1
R301
1K
1%
WAIT
PC0
PC1
PC2
PC3
PC4
PC5
PC6_R
A21
A22
A23
A24
A25
D8
D7
D6
D5
D4
D3
D2
D1
PC6
PC7 A23
PC8 A24
BFCS_NCS0
NCS2
SMCS_NCS3
R296
0R
PC9 A25
NRST
PC10
D0
A0
CFOE_NOE_NRD
CFWE_NWE_NWR0
CFIOR_NBS1_NWR1
CFIOW_NBS3_NWR3
PC11
PC12
PC13
PC14
PC15
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PD0
PD1
PD2
PD3
PD4
PD5
PD6
BFCS_NCS0
NCS2
SMCS_NCS3
NRST
CFOE_NOE_NRD
CFWE_NWE_NWR0
CFIOR_NBS1_NWR1
CFIOW_NBS3_NWR3
5V
C322
100NF
Monday, March 21, 2005
A01101-3-05-106
ELX
23/02/05 JPG
23/02/05
INIT EDIT
REV MODIF.
A
MDZ
DES.
04/01/05
DATE
JPG 06/01/05
VER.
DATE
SHEET
9
SCALE1/1
REV.
AT91RM9200-EK
EXPANSION CONNECTORS
63SC042261
A01
9
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
Schematics
5-4
AT91RM9200-EK Evaluation Board User Guide
6103C–ATARM–05-Jan-06
Errata
Section 6
Errata
6.1
Errata
6.1.1
SD/MMC Card Slot
Communication
Problem
On the AT91RM9200-EK Board, revision 700-20226 REV X5, a communication problem
may occur on the SD/MMC interface.
This issue has been corrected on all boards of revision 63PC042262A by adding a 10
kOhm pull-up resistor between the pin connectors J17-2 and J17-4.
AT91RM9200-EK Evaluation Board User Guide
6-1
6103C–ATARM–05-Jan-06
Errata
6-2
AT91RM9200-EK Evaluation Board User Guide
6103C–ATARM–05-Jan-06
Revision History
Doc. Rev.
6103A
Date
Comments
Change Request Ref.
24-Sep-04
02-Mar-05
First issue.
6103B
Section 1.2, “Deliverables” on page 2; List simplified
Table 4-1, Boot information modified
CSR 04-361,
CSR 05-028, CSR 05-246
19-Jul-05
New schematics added in Section 5.
6103C
07-Nov-05
Added Section 6, Errata.
CSR 05-478
1
6103C–ATARM–05-Jan-06
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