AT91SAM7S256_0504_技术文档

Features

• Incorporates the ARM7TDMI^®ARM^®Thumb^®Processor

– High-performance 32-bit RISC Architecture

– High-density 16-bit Instruction Set

– Leader in MIPS/Watt

– Embedded ICE In-circuit Emulation, Debug Communication Channel Support

• 256 Kbytes of Internal High-speed Flash, Organized in 1024 Pages of 256 Bytes

– Single Cycle Access at Up to 30 MHz in Worst Case Conditions

– Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed

– Page Programming Time: 4 ms, Including Page Auto-erase, Full Erase Time: 10 ms

– 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities,

Flash Security Bit

AT91 ARM^®

Thumb^®-based

Microcontrollers

– Fast Flash Programming Interface for High Volume Production

• 64 Kbytes of Internal High-speed SRAM, Single-cycle Access at Maximum Speed

• Memory Controller (MC)

– Embedded Flash Controller, Abort Status and Misalignment Detection

• Reset Controller (RSTC)

– Based on Power-on Reset and Low-power Factory-calibrated Brown-out Detector

– Provides External Reset Signal Shaping and Reset Source Status

• Clock Generator (CKGR)

AT91SAM7S256

Summary

Preliminary

– Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL

• Power Management Controller (PMC)

– Software Power Optimization Capabilities, Including Slow Clock Mode (Down to

500 Hz) and Idle Mode

– Three Programmable External Clock Signals

• Advanced Interrupt Controller (AIC)

– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources

– Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt

Protected

• Debug Unit (DBGU)

– 2-wire UART and Support for Debug Communication Channel interrupt,

Programmable ICE Access Prevention

• Periodic Interval Timer (PIT)

– 20-bit Programmable Counter plus 12-bit Interval Counter

• Windowed Watchdog (WDT)

– 12-bit key-protected Programmable Counter

– Provides Reset or Interrupt Signals to the System

– Counter May Be Stopped While the Processor is in Debug State or in Idle Mode

• Real-time Timer (RTT)

– 32-bit Free-running Counter with Alarm

– Runs Off the Internal RC Oscillator

• One Parallel Input/Output Controller (PIOA)

– Thirty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os

– Input Change Interrupt Capability on Each I/O Line

– Individually Programmable Open-drain, Pull-up resistor and Synchronous Output

• Eleven Peripheral DMA Controller (PDC) Channels

• One USB 2.0 Full Speed (12 Mbits per second) Device Port

– On-chip Transceiver, 328-byte Configurable Integrated FIFOs

6117BS–ATARM–07-Apr-05

• One Synchronous Serial Controller (SSC)

– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter

– I²S Analog Interface Support, Time Division Multiplex Support

– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer

• Two Universal Synchronous/Asynchronous Receiver Transmitters (USART)

– Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation

– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support

– Manchester Encoder/Decoder

– Full Modem Line Support on USART1

• One Master/Slave Serial Peripheral Interface (SPI)

– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects

• One Three-channel 16-bit Timer/Counter (TC)

– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel

– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability

• One Four-channel 16-bit PWM Controller (PWMC)

• One Two-wire Interface (TWI)

– Master Mode Support Only, All Two-wire Atmel EEPROMs Supported

• One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os

• IEEE 1149.1 JTAG Boundary Scan on All Digital Pins

• 5V-tolerant I/Os, including Four High-current Drive I/O lines, Up to 16 mA Each

• Power Supplies

– Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and External Components

– 3.3V VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply

– 1.8V VDDCORE Core Power Supply with Brown-out Detector

• Fully Static Operation: Up to 55 MHz at 1.65V and 85°C Worst Case Conditions

• Available in a 64-lead LQFP Green Package

1. Description

Atmel’s AT91SAM7S256 is a member of a series of low pincount Flash microcontrollers based

on the 32-bit ARM RISC processor. It features a 256 Kbyte high-speed Flash and a 64 Kbyte

SRAM, a large set of peripherals, including a USB 2.0 device, and a complete set of system

functions minimizing the number of external components. The device is an ideal migration

path for 8-bit microcontroller users looking for additional performance and extended memory.

The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or

via a parallel interface on a production programmer prior to mounting. Built-in lock bits and a

security bit protect the firmware from accidental overwrite and preserves its confidentiality.

The AT91SAM7S256 system controller includes a reset controller capable of managing the

power-on sequence of the microcontroller and the complete system. Correct device operation

can be monitored by a built-in brownout detector and a watchdog running off an integrated RC

oscillator.

The AT91SAM7S256 is a general-purpose microcontroller. Its integrated USB Device port

makes it an ideal device for peripheral applications requiring connectivity to a PC or cellular

phone. Its aggressive price point and high level of integration pushes its scope of use far into

the cost-sensitive, high-volume consumer market.

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AT91SAM7S256

2. Block Diagram

Figure 2-1. AT91SAM7S256 Block Diagram

TDI

TDO

ICE

ARM7TDMI

Processor

JTAG

TMS

SCAN

TCK

JTAGSEL

1.8 V

Voltage

VDDIN

GND

System Controller

AIC

Regulator

VDDOUT

TST

FIQ

VDDCORE

VDDIO

IRQ0-IRQ1

Memory Controller

SRAM

Embedded

Address

Decoder

64 Kbytes

Flash

PCK0-PCK2

PLLRC

Controller

PLL

PMC

Abort

Status

Misalignment

Detection

XIN

XOUT

OSC

VDDFLASH

ERASE

Flash

RCOSC

256 Kbytes

VDDCORE

BOD

POR

Peripheral Bridge

Reset

Controller

VDDCORE

NRST

PGMRDY

Peripheral Data

Controller

PGMNVALID

PGMNOE

PGMCK

PGMM0-PGMM3

PGMD0-PGMD15

PGMNCMD

Fast Flash

Programming

Interface

11 Channels

PIT

WDT

RTT

APB

PGMEN0-PGMEN2

PDC

DRXD

DTXD

DBGU

FIFO

DDM

DDP

USB Device

PIOA

PWM0

PWM1

PWM2

PWM3

TF

TK

TD

RD

RK

RF

TCLK0

TCLK1

TCLK2

TIOA0

TIOB0

TIOA1

TIOB1

RXD0

TXD0

SCK0

RTS0

CTS0

RXD1

TXD1

SCK1

RTS1

CTS1

DCD1

DSR1

DTR1

RI1

NPCS0

NPCS1

NPCS2

NPCS3

MISO

MOSI

SPCK

PDC

PWMC

USART0

PDC

SSC

PDC

USART1

Timer Counter

PDC

TC0

TC1

TC2

TWI

TIOA2

TIOB2

SPI

TWD

TWCK

PDC

ADTRG

AD0

AD1

AD2

AD3

ADC

AD4

AD5

AD6

AD7

ADVREF

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3. Signal Description

Table 3-1.

Signal Description List

Active

Level

Signal Name

Function

Type

Comments

Power

VDDIN

Voltage and ADC Regulator Power Supply Input

Voltage Regulator Output

Flash Power Supply

I/O Lines Power Supply

Core Power Supply

PLL

Power

Ground

3.0 to 3.6V

VDDOUT

VDDFLASH

VDDIO

1.85V nominal

3.0V to 3.6V

1.65V to 1.95V

VDDCORE

VDDPLL

GND

Ground

Clocks, Oscillators and PLLs

XIN

Main Oscillator Input

Main Oscillator Output

PLL Filter

Input

Output

XOUT

PLLRC

PCK0 - PCK2

Input

Programmable Clock Output

Output

ICE and JTAG

Input

TCK

Test Clock

No pull-up resistor

TDI

Test Data In

Input

TDO

Test Data Out

Test Mode Select

JTAG Selection

Output

TMS

Input

No pull-up resistor

Pull-down resistor

JTAGSEL

Input

Flash Memory

Flash and NVM Configuration Bits Erase

Command

ERASE

Input

High

Pull-down resistor

Reset/Test

NRST

TST

Microcontroller Reset

Test Mode Select

I/O

Low

Pull-Up resistor

Input

High

Pull-down resistor

Debug Unit

AIC

DRXD

DTXD

Debug Receive Data

Debug Transmit Data

Input

Output

IRQ0 - IRQ1

FIQ

External Interrupt Inputs

Fast Interrupt Input

Input

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AT91SAM7S256

Table 3-1.

Signal Description List (Continued)

Active

Level

Signal Name

Function

Type

Comments

PIO

PA0 - PA31

Parallel IO Controller A

I/O

Pulled-up input at reset

USB Device Port

Analog

DDM

DDP

USB Device Port Data -

USB Device Port Data +

Analog

USART

SCK0 - SCK1

TXD0 - TXD1

RXD0 - RXD1

RTS0 - RTS1

CTS0 - CTS1

DCD1

Serial Clock

I/O

Transmit Data

Receive Data

Input

Output

Input

Output

Input

Request To Send

Clear To Send

Data Carrier Detect

Data Terminal Ready

Data Set Ready

Ring Indicator

DTR1

DSR1

RI1

Synchronous Serial Controller

TD

RD

TK

RK

TF

RF

Transmit Data

Output

Receive Data

Input

Transmit Clock

I/O

Receive Clock

I/O

Transmit Frame Sync

Receive Frame Sync

I/O

Timer/Counter

TCLK0 - TCLK2

TIOA0 - TIOA2

TIOB0 - TIOB2

External Clock Inputs

I/O Line A

Input

I/O

I/O Line B

I/O

PWM Controller

PWM0 - PWM3

PWM Channels

Output

SPI

I/O

MISO

Master In Slave Out

Master Out Slave In

SPI Serial Clock

MOSI

SPCK

NPCS0

NPCS1-NPCS3

SPI Peripheral Chip Select 0

Low

SPI Peripheral Chip Select 1 to 3

Output

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Table 3-1.

Signal Description List (Continued)

Active

Level

Signal Name

Function

Type

Two-Wire Interface

Comments

TWD

Two-wire Serial Data

Two-wire Serial Clock

I/O

TWCK

Analog-to-Digital Converter

AD0-AD3

AD4-AD7

ADTRG

Analog Inputs

ADC Trigger

Analog

Digital pulled-up inputs at reset

Analog Inputs

Analog

Input

ADVREF

ADC Reference

Analog

Fast Flash Programming Interface

PGMEN0-PGMEN2 Programming Enabling

Input

I/O

PGMM0-PGMM3

PGMD0-PGMD15

PGMRDY

Programming Mode

Programming Data

Programming Ready

Data Direction

Output

Input

High

Low

PGMNVALID

PGMNOE

Programming Read

Programming Clock

Programming Command

PGMCK

PGMNCMD

Low

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AT91SAM7S256

4. Package and Pinout

The AT91SAM7S256 is available in a 64-lead LQFP package.

4.1

64-lead LQFP Mechanical Overview

Figure 4-1 shows the orientation of the 64-lead LQFP package. A detailed mechanical

description is given in the section Mechanical Characteristics of the full datasheet.

Figure 4-1. 64-lead LQFP Package Pinout (Top View)

33

48

49

64

32

17

16

1

4.2

Pinout

Table 4-1.

AT91SAM7S256 Pinout in 64-lead LQFP Package

1

2

3

4

5

6

7

8

ADVREF

GND

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

GND

33

TDI

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

TDO

JTAGSEL

TMS

VDDIO

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

PA6/PGMNOE

PA5/PGMRDY

AD4

PA16/PGMD4

PA15/PGMD3

PA14/PGMD2

PA13/PGMD1

PA24/PGMD12

VDDCORE

AD5

PA4/PGMNCMD

PA27/PGMD15

PA28

PA31

AD6

TCK

AD7

VDDCORE

ERASE

DDM

VDDIN

VDDOUT

NRST

TST

9

PA17/PGMD5/AD0

PA18/PGMD6/AD1

PA21/PGMD9

PA25/PGMD13

PA26/PGMD14

PA12/PGMD0

PA11/PGMM3

PA10/PGMM2

PA9/PGMM1

PA8/PGMM0

PA7/PGMNVALID

PA29

DDP

10

11

12

13

14

15

16

PA30

VDDIO

VDDFLASH

GND

PA3

VDDCORE

PA2/PGMEN2

VDDIO

PA19/PGMD7/AD2

PA22/PGMD10

PA23/PGMD11

PA20/PGMD8/AD3

XOUT

GND

XIN/PGMCK

PLLRC

VDDPLL

PA1/PGMEN1

PA0/PGMEN0

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5. Power Considerations

5.1

Power Supplies

The AT91SAM7S256 has six types of power supply pins and integrates a voltage regulator,

allowing the device to be supplied with only one voltage. The six power supply pin types are:

• VDDIN pin. It powers the voltage regulator and the ADC; voltage ranges from 3.0V to 3.6V,

3.3V nominal. If the voltage regulator is not used, VDDIN should be connected to GND.

• VDDOUT pin. It is the output of the 1.8V voltage regulator.

• VDDIO pin. It powers the I/O lines and the USB transceivers; dual voltage range is

supported. Ranges from 3.0V to 3.6V, 3.3V nominal. Note that supplying less than 3.0V to

VDDIO prevents any use of the USB transceivers.

• VDDFLASH pin. It powers a part of the Flash and is required for the Flash to operate

correctly; voltage ranges from 3.0V to 3.6V, 3.3V nominal.

• VDDCORE pins. They power the logic of the device; voltage ranges from 1.65V to 1.95V,

1.8V typical. It can be connected to the VDDOUT pin with decoupling capacitor.

VDDCORE is required for the device, including its embedded Flash, to operate correctly.

• VDDPLL pin. It powers the oscillator and the PLL. It can be connected directly to the

VDDOUT pin.

No separate ground pins are provided for the different power supplies. Only GND pins are pro-

vided and should be connected as shortly as possible to the system ground plane.

5.2

5.3

Power Consumption

The AT91SAM7S256 has a static current of less than 60 µA on VDDCORE at 25°C, including

the RC oscillator, the voltage regulator and the power-on reset when the brown-out detector is

deactivated. Activating the brown-out detector adds 20 µA static current.

The dynamic power consumption on VDDCORE is less than 50 mA at full speed when running

out of the Flash. Under the same conditions, the power consumption on VDDFLASH does not

exceed 10 mA.

Voltage Regulator

The AT91SAM7S256 embeds a voltage regulator that is managed by the System Controller.

In Normal Mode, the voltage regulator consumes less than 100 µA static current and draws

100 mA of output current.

The voltage regulator also has a Low-power Mode. In this mode, it consumes less than 25 µA

static current and draws 1 mA of output current.

Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid

oscillations. The best way to achieve this is to use two capacitors in parallel: one external 470

pF (or 1 nF) NPO capacitor must be connected between VDDOUT and GND as close to the

chip as possible. One external 2.2 µF (or 3.3 µF) X7R capacitor must be connected between

VDDOUT and GND.

Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability

and reduce source voltage drop. The input decoupling capacitor should be placed close to the

chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R.

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AT91SAM7S256

6117BS–ATARM–07-Apr-05

AT91SAM7S256

5.4

Typical Powering Schematics

The AT91SAM7S256 supports a 3.3V single supply mode. The internal regulator is connected

to the 3.3V source and its output feeds VDDCORE and the VDDPLL. Figure 5-1 shows the

power schematics to be used for USB bus-powered systems.

Figure 5-1.

3.3V System Single Power Supply Schematic

VDDFLASH

Power Source

VDDIO

ranges

from 4.5V (USB)

to 18V

DC/DC Converter

VDDIN

Voltage

Regulator

3.3V

VDDOUT

VDDCORE

VDDPLL

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6. I/O Lines Considerations

6.1

JTAG Port Pins

TMS, TDI and TCK are schmitt trigger inputs. TMS and TCK are 5-V tolerant, TDI is not. TMS,

TDI and TCK do not integrate a pull-up resistor.

TDO is an output, driven at up to VDDIO, and has no pull-up resistor.

The pin JTAGSEL is used to select the JTAG boundary scan when asserted at a high level.

The pin JTAGSEL integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it

can be left unconnected for normal operations.

6.2

Test Pin

The pin TST is used for manufacturing test or fast programming mode of the AT91SAM7S256

when asserted high. The pin TST integrates a permanent pull-down resistor of about 15 kΩ to

GND, so that it can be left unconnected for normal operations.

To enter fast programming mode, the pin TST and the pins PA0 and PA1 should be tied hig-

hand PA2 tied to low.

Driving the pin TST at a high level while PA0 or PA1 is driven at 0 leads to unpredictable

results.

6.3

Reset Pin

The pin NRST is bidirectional. It is handled by the on-chip reset controller and can be driven

low to provide a reset signal to the external components or asserted low externally to reset the

microcontroller. There is no constraint on the length of the reset pulse, and the reset controller

can guarantee a minimum pulse length. This allows connection of a simple push-button on the

pin NRST as system user reset, and the use of the signal NRST to reset all the components of

the system.

The pin NRST integrates a permanent pull-up resistor to VDDIO.

6.4

6.5

ERASE Pin

The pin ERASE is used to re-initialize the Flash content and some of its NVM bits. It integrates

a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for

normal operations.

PIO Controller A Lines

All the I/O lines PA0 to PA31 are 5V-tolerant and all integrate a programmable pull-up resistor.

Programming of this pull-up resistor is performed independently for each I/O line through the

PIO controllers.

5V-tolerant means that the I/O lines can drive voltage level according to VDDIO, but can be

driven with a voltage of up to 5.5V. However, driving an I/O line with a voltage over VDDIO

while the programmable pull-up resistor is enabled can lead to unpredictable results. Care

should be taken, in particular at reset, as all the I/O lines default to input with pull-up resistor

enabled at reset.

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AT91SAM7S256

6.6

I/O Line Drive Levels

The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive up

to 16 mA permanently.

The remaining I/O lines can draw only 8 mA.

However, the total current drawn by all the I/O lines cannot exceed 150 mA.

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7. Processor and Architecture

7.1

7.2

7.3

ARM7TDMI Processor

• RISC processor based on ARMv4T Von Neumann architecture

– Runs at up to 55 MHz, providing 0.9 MIPS/MHz

• Two instruction sets

– ARM^®high-performance 32-bit instruction set

– Thumb^®high code density 16-bit instruction set

• Three-stage pipeline architecture

– Instruction Fetch (F)

– Instruction Decode (D)

– Execute (E)

Debug and Test Features

• Integrated embedded in-circuit emulator

– Two watchpoint units

– Test access port accessible through a JTAG protocol

– Debug communication channel

• Debug Unit

– Two-pin UART

– Debug communication channel interrupt handling

– Chip ID Register

• IEEE1149.1 JTAG Boundary-scan on all digital pins

Memory Controller

• Bus Arbiter

– Handles requests from the ARM7TDMI and the Peripheral DMA Controller

• Address decoder provides selection signals for

– Three internal 1 Mbyte memory areas

– One 256 Mbyte embedded peripheral area

• Abort Status Registers

– Source, Type and all parameters of the access leading to an abort are saved

– Facilitates debug by detection of bad pointers

• Misalignment Detector

– Alignment checking of all data accesses

– Abort generation in case of misalignment

• Remap Command

– Remaps the SRAM in place of the embedded non-volatile memory

– Allows handling of dynamic exception vectors

• Embedded Flash Controller

– Embedded Flash interface, up to three programmable wait states

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6117BS–ATARM–07-Apr-05

AT91SAM7S256

– Prefetch buffer, bufferizing and anticipating the 16-bit requests, reducing the

required wait states

– Key-protected program, erase and lock/unlock sequencer

– Single command for erasing, programming and locking operations

– Interrupt generation in case of forbidden operation

7.4

Peripheral DMA Controller

• Handles data transfer between peripherals and memories

• Eleven channels

– Two for each USART

– Two for the Debug Unit

– Two for the Serial Synchronous Controller

– Two for the Serial Peripheral Interface

– One for the Analog-to-digital Converter

• Low bus arbitration overhead

– One Master Clock cycle needed for a transfer from memory to peripheral

– Two Master Clock cycles needed for a transfer from peripheral to memory

• Next Pointer management for reducing interrupt latency requirements

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8. Memory

• 256 Kbytes of Flash Memory

– 1024 pages of 256 bytes

– Fast access time, 30 MHz single-cycle access in worst case conditions

– Page programming time: 4 ms, including page auto-erase

– Page programming without auto-erase: 2 ms

– Full chip erase time: 10 ms

– 10,000 write cycles, 10-year data retention capability

– 16 lock bits, each protecting 16 sectors of 64 pages

– Protection Mode to secure contents of the Flash

• 64 Kbytes of Fast SRAM

– Single-cycle access at full speed

8.1

Memory Mapping

8.1.1

Internal SRAM

The AT91SAM7S256 embeds a high-speed 64-Kbyte SRAM bank. After reset and until the

Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After

Remap, the SRAM also becomes available at address 0x0.

8.1.2

Internal Flash

The AT91SAM77S256 features one bank of 256 Kbytes of Flash. At any time, the Flash is

mapped to address 0x0010 0000. It is also accessible at address 0x0 after the reset and

before the Remap Command.

Figure 8-1. Internal Memory Mapping

0x0000 0000

Flash Before Remap

1 M Bytes

SRAM After Remap

0x000F FFFF

0x0010 0000

Internal Flash

1 M Bytes

0x001F FFFF

0x0020 0000

Internal SRAM

256M Bytes

0x002F FFFF

0x0030 0000

Undefined Areas

(Abort)

253 M Bytes

0x0FFF FFFF

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6117BS–ATARM–07-Apr-05

AT91SAM7S256

8.2

Embedded Flash

8.2.1

Flash Overview

The Flash of the AT91SAM7S256 is organized in 1024 pages of 256 bytes. The 262,144 bytes

are organized in 32-bit words.

The Flash contains a 256-byte write buffer, accessible through a 32-bit interface.

The Flash benefits from the integration of a power reset cell and from the brownout detector.

This prevents code corruption during power supply changes, even in the worst conditions.

When Flash is not used (read or write access), it is automatically placed into standby mode.

8.2.2

Embedded Flash Controller

The Embedded Flash Controller (EFC) manages accesses performed by the masters of the

system. It enables reading the Flash and writing the write buffer. It also contains a User Inter-

face, mapped within the Memory Controller on the APB. The User Interface allows:

• programming of the access parameters of the Flash (number of wait states, timings, etc.)

• starting commands such as full erase, page erase, page program, NVM bit set, NVM bit

clear, etc.

• getting the end status of the last command

• getting error status

• programming interrupts on the end of the last commands or on errors

The Embedded Flash Controller also provides a dual 32-bit Prefetch Buffer that optimizes 16-

bit access to the Flash. This is particularly efficient when the processor is running in Thumb

mode.

8.2.3

Lock Regions

The Embedded Flash Controller manages 16 lock bits to protect 16 regions of the flash

against inadvertent flash erasing or programming commands. The AT91SAM7S256 contains

16 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a

size of 16 Kbytes.

If a locked-regions erase or program command occurs, the command is aborted and the EFC

trigs an interrupt.

The 16 NVM bits are software programmable through the EFC User Interface. The command

"Set Lock Bit" enables the protection. The command "Clear Lock Bit" unlocks the lock region.

Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.

8.2.4

Security Bit Feature

The AT91SAM7S256 features a security bit, based on a specific NVM-Bit. When the security

is enabled, any access to the Flash, either through the ICE interface or through the Fast Flash

Programming Interface, is forbidden. This ensures the confidentiality of the code programmed

in the Flash.

This security bit can only be enabled, through the Command "Set Security Bit" of the EFC

User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at

1, and after a full flash erase is performed. When the security bit is deactivated, all accesses to

the flash are permitted.

It is important to note that the assertion of the ERASE pin should always be longer than 50 ms.

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6117BS–ATARM–07-Apr-05

As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal

operation. However, it is safer to connect it directly to GND for the final application.

8.2.5

Non-volatile Brownout Detector Control

Two general purpose NVM (GPNVM) bits are used for controlling the brownout detector

(BOD), so that even after a power loss, the brownout detector operations remain in their state.

These two GPNVM bits can be cleared or set respectively through the commands "Clear Gen-

eral-purpose NVM Bit" and "Set General-purpose NVM Bit" of the EFC User Interface.

• GPNVM Bit 0 is used as a brownout detector enable bit. Setting the GPNVM Bit 0 enables

the BOD, clearing it disables the BOD. Asserting ERASE clears the GPNVM Bit 0 and thus

disables the brownout detector by default.

• The GPNVM Bit 1 is used as a brownout reset enable signal for the reset controller. Setting

the GPNVM Bit 1 enables the brownout reset when a brownout is detected, Clearing the

GPNVM Bit 1 disables the brownout reset. Asserting ERASE disables the brownout reset

by default.

8.2.6

Calibration Bits

Eight NVM bits are used to calibrate the brownout detector and the voltage regulator. These

bits are factory configured and cannot be changed by the user. The ERASE pin has no effect

on the calibration bits.

8.3

Fast Flash Programming Interface

The Fast Flash Programming Interface allows programming the device through either a serial

JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang-pro-

gramming with market-standard industrial programmers.

The FFPI supports read, page program, page erase, full erase, lock, unlock and protect

commands.

The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered

when the TST pin and the PA0 and PA1 pins are all tied high and PA2 is tied low.

16

AT91SAM7S256

6117BS–ATARM–07-Apr-05

AT91SAM7S256

9. System Controller

The System Controller manages all vital blocks of the microcontroller: interrupts, clocks,

power, time, debug and reset.

Figure 9-1. System Controller Block Diagram

jtag_nreset

Boundary Scan

TAP Controller

System Controller

nirq

nfiq

irq0-irq1

fiq

Advanced

Interrupt

Controller

proc_nreset

ARM7TDMI

periph_irq[2..14]

PCK

int

debug

pit_irq

rtt_irq

wdt_irq

dbgu_irq

pmc_irq

rstc_irq

ice_nreset

force_ntrst

MCK

periph_nreset

dbgu_irq

Debug

Unit

force_ntrst

dbgu_rxd

dbgu_txd

pit_irq

security_bit

MCK

debug

Periodic

Interval

Timer

periph_nreset

SLCK

flash_poe

Real-Time

Timer

Embedded

Flash

rtt_irq

periph_nreset

flash_wrdis

cal

SLCK

debug

Watchdog

Timer

wdt_irq

gpnvm[0..1]

idle

proc_nreset

cal

gpnvm[0]

wdt_fault

WDRPROC

gpnvm[1]

MCK

en

bod_rst_en

Memory

flash_wrdis

Controller

BOD

proc_nreset

ice_nreset

jtag_nreset

periph_nreset

proc_nreset

Reset

Controller

Voltage

Regulator

Mode

POR

flash_poe

standby

cal

Voltage

Controller

rstc_irq

Regulator

NRST

SLCK

RCOSC

periph_clk[2..14]

pck[0-2]

UDPCK

periph_clk[11]

USB Device

Port

XIN

Power

Management

Controller

MAINCK

OSC

PLL

periph_nreset

PCK

XOUT

UDPCK

MCK

periph_irq[11]

usb_suspend

PLLRC

PLLCK

int

pmc_irq

idle

periph_nreset

periph_clk[4..14]

periph_nreset

usb_suspend

Embedded

Peripherals

periph_nreset

periph_clk[2]

dbgu_rxd

periph_irq{2]

irq0-irq1

fiq

periph_irq[4..14]

PIO

Controller

dbgu_txd

in

PA0-PA31

out

enable

17

6117BS–ATARM–07-Apr-05

9.1

System Controller Mapping

The System Controller peripherals are all mapped to the highest 4 Kbytes of address space,

between addresses 0xFFFF F000 and 0xFFFF FFFF.

Figure 9-2 shows the mapping of the System Controller. Note that the Memory Controller con-

figuration user interface is also mapped within this address space.

Figure 9-2. System Controller Mapping

Address Peripheral

Peripheral Name

Size

0xFFFF F000

AIC

Advanced Interrupt Controller

512 Bytes/128 registers

0xFFFF F1FF

0xFFFF F200

DBGU

PIOA

Debug Unit

512 Bytes/128 registers

0xFFFF F3FF

0xFFFF F400

PIO Controller A

0xFFFF F5FF

0xFFFF F600

Reserved

PMC

0xFFFF FBFF

0xFFFF FC00

Power Management Controller

Reset Controller

256 Bytes/64 registers

16 Bytes/4 registers

0xFFFF FCFF

0xFFFF FD00

0xFFFF FD0F

RSTC

Reserved

RTT

0xFFFF FD20

0xFFFF FC2F

0xFFFF FD30

0xFFFF FC3F

0xFFFF FD40

0xFFFF FD4F

Real-time Timer

16 Bytes/4 registers

PIT

Periodic Interval Timer

Watchdog Timer

WDT

Reserved

VREG

0xFFFF FD60

0xFFFF FC6F

0xFFFF FD70

Voltage Regulator Mode Controller

4 Bytes/1 register

Reserved

0xFFFF FEFF

0xFFFF FF00

MC

Memory Controller

256 Bytes/64 registers

0xFFFF FFFF

18

AT91SAM7S256

6117BS–ATARM–07-Apr-05

AT91SAM7S256

9.2

Reset Controller

The Reset Controller is based on a power-on reset cell and one brownout detector. It gives the

status of the last reset, indicating whether it is a power-up reset, a software reset, a user reset,

a watchdog reset or a brownout reset. In addition, it controls the internal resets and the NRST

pin output. It allows to shape a signal on the NRST line, guaranteeing that the length of the

pulse meets any requirement.

Note that if NRST is used as a reset output signal for external devices during power-off, the

brownout detector must be activated.

9.2.1

Brownout Detector and Power-on Reset

The AT91SAM7S256 embeds a brownout detection circuit and a power-on reset cell. Both are

supplied with and monitor VDDCORE. Both signals are provided to the Flash to prevent any

code corruption during power-up or power-down sequences or if brownouts occur on the

VDDCORE power supply.

The power-on reset cell has a limited-accuracy threshold at around 1.5V. Its output remains

low during power-up until VDDCORE goes over this voltage level. This signal goes to the reset

controller and allows a full re-initialization of the device.

The brownout detector monitors the VDDCORE level during operation by comparing it to a

fixed trigger level. It secures system operations in the most difficult environments and prevents

code corruption in case of brownout on the VDDCORE.

Only VDDCORE is monitored, as a voltage drop on VDDFLASH or any other power supply of

the device cannot affect the Flash.

When the brownout detector is enabled and VDDCORE decreases to a value below the trigger

level (Vbot-, defined as Vbot - hyst/2), the brownout output is immediately activated.

When VDDCORE increases above the trigger level (Vbot+, defined as Vbot + hyst/2), the

reset is released. The brownout detector only detects a drop if the voltage on VDDCORE

stays below the threshold voltage for longer than about 1µs.

The threshold voltage has a hysteresis of about 50 mV, to ensure spike free brownout detec-

tion. The typical value of the brownout detector threshold is 1.68V with an accuracy of ± 2%

and is factory calibrated.

The brownout detector is low-power, as it consumes less than 20 µA static current. However, it

can be deactivated to save its static current. In this case, it consumes less than 1µA. The

deactivation is configured through the GPNVM bit 0 of the Flash.

19

6117BS–ATARM–07-Apr-05

9.3

Clock Generator

The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL

with the following characteristics:

• RC Oscillator ranges between 22 KHz and 42 KHz

• Main Oscillator frequency ranges between 3 and 20 MHz

• Main Oscillator can be bypassed

• PLL output ranges between 80 and 220 MHz

It provides SLCK, MAINCK and PLLCK.

Figure 9-3. Clock Generator Block Diagram

Clock Generator

Embedded

Slow Clock

RC

Oscillator

SLCK

XIN

Main

Oscillator

Main Clock

MAINCK

XOUT

PLL and

Divider

PLL Clock

PLLCK

PLLRC

Status

Power

Control

Management

Controller

20

AT91SAM7S256

6117BS–ATARM–07-Apr-05

AT91SAM7S256

9.4

Power Management Controller

The Power Management Controller uses the Clock Generator outputs to provide:

• the Processor Clock PCK

• the Master Clock MCK

• the USB Clock UDPCK

• all the peripheral clocks, independently controllable

• three programmable clock outputs

The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating

frequency of the device.

The Processor Clock (PCK) switches off when entering processor idle mode, thus allowing

reduced power consumption while waiting for an interrupt.

Figure 9-4. Power Management Controller Block Diagram

Processor

PCK

Clock

Controller

int

Master Clock Controller

Idle Mode

SLCK

Prescaler

MAINCK

MCK

/1,/2,/4,...,/64

PLLCK

Peripherals

Clock Controller

periph_clk[2..14]

ON/OFF

Programmable Clock Controller

SLCK

MAINCK

PLLCK

Prescaler

/1,/2,/4,...,/64

pck[0..2]

USB Clock Controller

ON/OFF

usb_suspend

UDPCK

Divider

/1,/2,/4

PLLCK

9.5

Advanced Interrupt Controller

• Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor

• Individually maskable and vectored interrupt sources

– Source 0 is reserved for the Fast Interrupt Input (FIQ)

– Source 1 is reserved for system peripherals RTT, PIT, EFC, PMC, DBGU, etc.)

– Other sources control the peripheral interrupts or external interrupts

– Programmable edge-triggered or level-sensitive internal sources

– Programmable positive/negative edge-triggered or high/low level-sensitive

external sources

• 8-level Priority Controller

– Drives the normal interrupt of the processor

– Handles priority of the interrupt sources

21

6117BS–ATARM–07-Apr-05

– Higher priority interrupts can be served during service of lower priority interrupt

• Vectoring

– Optimizes interrupt service routine branch and execution

– One 32-bit vector register per interrupt source

– Interrupt vector register reads the corresponding current interrupt vector

• Protect Mode

– Easy debugging by preventing automatic operations

• Fast Forcing

– Permits redirecting any interrupt source on the fast interrupt

• General Interrupt Mask

– Provides processor synchronization on events without triggering an interrupt

9.6

Debug Unit

• Comprises:

– One two-pin UART

– One Interface for the Debug Communication Channel (DCC) support

– One set of Chip ID Registers

– One Interface providing ICE Access Prevention

• Two-pin UART

– Implemented features are compatible with the USART

– Programmable Baud Rate Generator

– Parity, Framing and Overrun Error

– Automatic Echo, Local Loopback and Remote Loopback Channel Modes

• Debug Communication Channel Support

– Offers visibility of COMMRX and COMMTX signals from the ARM Processor

• Chip ID Registers

– Identification of the device revision, sizes of the embedded memories, set of

peripherals

– Chip ID is 0x270d0940 (VERSION 0)

9.7

9.8

Periodic Interval Timer

• 20-bit programmable counter plus 12-bit interval counter

Watchdog Timer

• 12-bit key-protected Programmable Counter running on prescaled SCLK

• Provides reset or interrupt signals to the system

• Counter may be stopped while the processor is in debug state or in idle mode

9.9

Real-time Timer

• 32-bit free-running counter with alarm running on prescaled SCLK

• Programmable 16-bit prescaler for SLCK accuracy compensation

22

AT91SAM7S256

6117BS–ATARM–07-Apr-05

AT91SAM7S256

9.10 PIO Controller

• One PIO Controller, controlling 32 I/O lines

• Fully programmable through set/clear registers

• Multiplexing of two peripheral functions per I/O line

• For each I/O line (whether assigned to a peripheral or used as general-purpose I/O)

– Input change interrupt

– Half a clock period glitch filter

– Multi-drive option enables driving in open drain

– Programmable pull-up on each I/O line

– Pin data status register, supplies visibility of the level on the pin at any time

• Synchronous output, provides Set and Clear of several I/O lines in a single write

9.11 Voltage Regulator Controller

The aim of this controller is to select the Power Mode of the Voltage Regulator between Nor-

mal Mode (bit 0 is cleared) or Standby Mode (bit 0 is set).

23

6117BS–ATARM–07-Apr-05

10. Peripherals

10.1 Peripheral Mapping

Each peripheral is allocated 16 Kbytes of address space.

Figure 10-1. User Peripheral Mapping

Peripheral Name

Size

0xF000 0000

Reserved

0xFFF9 FFFF

0xFFFA 0000

TC0, TC1, TC2

Timer/Counter 0, 1 and 2

16 Kbytes

0xFFFA 3FFF

0xFFFA 4000

Reserved

0xFFFA FFFF

0xFFFB 0000

UDP

USB Device Port

16 Kbytes

0xFFFB 3FFF

0xFFFB 4000

Reserved

0xFFFB 7FFF

0xFFFB 8000

TWI

Two-Wire Interface

0xFFFB BFFF

0xFFFB C000

Reserved

0xFFFB FFFF

0xFFFC 0000

USART0

Universal Synchronous Asynchronous

Receiver Transmitter 0

16 Kbytes

0xFFFC 3FFF

0xFFFC 4000

USART1

Universal Synchronous Asynchronous

Receiver Transmitter 1

0xFFFC 7FFF

0xFFFC 8000

Reserved

0xFFFC BFFF

0xFFFC C000

16 Kbytes

PWMC

PWM Controller

0xFFFC FFFF

0xFFFD 0000

Reserved

0xFFFD 3FFF

0xFFFD 4000

SSC

Serial Synchronous Controller

Analog-to-Digital Converter

16 Kbytes

0xFFFD 7FFF

0xFFFD 8000

ADC

0xFFFD BFFF

0xFFFD C000

Reserved

0xFFFD FFFF

0xFFFE 0000

SPI

Serial Peripheral Interface

16 Kbytes

0xFFFE 3FFF

0xFFFE 4000

Reserved

0xFFFE FFFF

24

AT91SAM7S256

6117BS–ATARM–07-Apr-05

AT91SAM7S256

10.2 Peripheral Multiplexing on PIO Lines

The AT91SAM7S256 features one PIO controller, PIOA, that multiplexes the I/O lines of the

peripheral set.

PIO Controller A controls 32 lines. Each line can be assigned to one of two peripheral func-

tions, A or B. Some of them can also be multiplexed with the analog inputs of the ADC

Controller.

Table 10-1 on page 26 defines how the I/O lines of the peripherals A, B or the analog inputs

are multiplexed on the PIO Controller A. The two columns “Function” and “Comments” have

been inserted for the user’s own comments; they may be used to track how pins are defined in

an application.

Note that some peripheral functions that are output only may be duplicated in the table.

All pins reset in their Parallel I/O lines function are configured in input with the programmable

pull-up enabled, so that the device is maintained in a static state as soon as a reset is

detected.

25

6117BS–ATARM–07-Apr-05

10.3 PIO Controller A Multiplexing

Table 10-1. Multiplexing on PIO Controller A

PIO Controller A

Application Usage

Function Comments

I/O Line

PA0

Peripheral A

PWM0

PWM1

PWM2

TWD

Peripheral B

TIOA0

TIOB0

SCK0

Comments

High-Drive

PA1

PA2

PA3

NPCS3

TCLK0

NPCS3

PCK0

PA4

TWCK

RXD0

TXD0

RTS0

CTS0

DRXD

DTXD

NPCS0

MISO

MOSI

SPCK

TF

PA5

PA6

PA7

PWM3

ADTRG

NPCS1

NPCS2

PWM0

PWM1

PWM2

PWM3

TIOA1

TIOB1

PCK1

PA8

PA9

PA10

PA11

PA12

PA13

PA14

PA15

PA16

PA17

PA18

PA19

PA20

PA21

PA22

PA23

PA24

PA25

PA26

PA27

PA28

PA29

PA30

PA31

TK

TD

AD0

AD1

AD2

AD3

RD

PCK2

RK

FIQ

RF

IRQ0

RXD1

TXD1

SCK1

RTS1

CTS1

DCD1

DTR1

DSR1

RI1

PCK1

NPCS3

PWM0

PWM1

PWM2

TIOA2

TIOB2

TCLK1

TCLK2

NPCS2

PCK2

IRQ1

NPCS1

26

AT91SAM7S256

6117BS–ATARM–07-Apr-05

AT91SAM7S256

10.4 Peripheral Identifiers

The AT91SAM7S256 embeds a wide range of peripherals. Table 10-2 defines the Peripheral

Identifiers of the AT91SAM7S256. A peripheral identifier is required for the control of the

peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral

clock with the Power Management Controller.

Table 10-2. Peripheral Identifiers

Peripheral

ID

Peripheral

Mnemonic

Peripheral

Name

External

Interrupt

0

AIC

Advanced Interrupt Controller

System Interrupt

FIQ

1

SYSIRQ⁽¹⁾

PIOA

Reserved

ADC⁽¹⁾

SPI

2

Parallel I/O Controller A

3

4

Analog-to Digital Converter

Serial Peripheral Interface

USART 0

5

6

US0

7

US1

USART 1

8

SSC

Synchronous Serial Controller

Two-wire Interface

PWM Controller

9

TWI

10

11

12

13

14

15 - 29

30

31

PWMC

UDP

USB Device Port

Timer/Counter 0

TC0

TC1

Timer/Counter 1

TC2

Timer/Counter 2

Reserved

AIC

Advanced Interrupt Controller

IRQ0

IRQ1

AIC

Note:

1. Setting SYSIRQ and ADC bits in the clock set/clear registers of the PMC has no effect. The

System Controller is continuously clocked. The ADC clock is automatically started for the

first conversion. In Sleep Mode the ADC clock is automatically stopped after each

conversion.

10.5 Serial Peripheral Interface

• Supports communication with external serial devices

– Four chip selects with external decoder allow communication with up to 15

peripherals

– Serial memories, such as DataFlash^®and 3-wire EEPROMs

– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and

Sensors

– External co-processors

• Master or slave serial peripheral bus interface

– 8- to 16-bit programmable data length per chip select

– Programmable phase and polarity per chip select

27

6117BS–ATARM–07-Apr-05

– Programmable transfer delays between consecutive transfers and between clock

and data per chip select

– Programmable delay between consecutive transfers

– Selectable mode fault detection

– Maximum frequency at up to Master Clock

10.6 Two-wire Interface

• Master Mode only

• Compatibility with standard two-wire serial memories

• One, two or three bytes for slave address

• Sequential read/write operations

10.7 USART

• Programmable Baud Rate Generator

• 5- to 9-bit full-duplex synchronous or asynchronous serial communications

– 1, 1.5 or 2 stop bits in Asynchronous Mode

– 1 or 2 stop bits in Synchronous Mode

– Parity generation and error detection

– Framing error detection, overrun error detection

– MSB or LSB first

– Optional break generation and detection

– By 8 or by 16 over-sampling receiver frequency

– Hardware handshaking RTS - CTS

– Modem Signals Management DTR-DSR-DCD-RI on USART1

– Receiver time-out and transmitter timeguard

– Multi-drop Mode with address generation and detection

• RS485 with driver control signal

• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards

– NACK handling, error counter with repetition and iteration limit

• IrDA modulation and demodulation

– Communication at up to 115.2 Kbps

• Test Modes

– Remote Loopback, Local Loopback, Automatic Echo

10.8 Serial Synchronous Controller

• Provides serial synchronous communication links used in audio and telecom applications

• Contains an independent receiver and transmitter and a common clock divider

• Offers a configurable frame sync and data length

• Receiver and transmitter can be programmed to start automatically or on detection of

different event on the frame sync signal

• Receiver and transmitter include a data signal, a clock signal and a frame synchronization

signal

28

AT91SAM7S256

6117BS–ATARM–07-Apr-05

AT91SAM7S256

10.9 Timer Counter

• Three 16-bit Timer Counter Channels

– Three output compare or two input capture

• Wide range of functions including:

– Frequency measurement

– Event counting

– Interval measurement

– Pulse generation

– Delay timing

– Pulse Width Modulation

– Up/down capabilities

• Each channel is user-configurable and contains:

– Three external clock inputs

– Five internal clock inputs, as defined in Table 10-3

Table 10-3. Timer Counter Clocks Assignment

TC Clock Input

TIMER_CLOCK1

Clock

MCK/2

TIMER_CLOCK2

TIMER_CLOCK3

TIMER_CLOCK4

TIMER_CLOCK5

MCK/8

MCK/32

MCK/128

MCK/1024

– Two multi-purpose input/output signals

– Two global registers that act on all three TC channels

10.10 PWM Controller

• Four channels, one 16-bit counter per channel

• Common clock generator, providing thirteen different clocks

– One Modulo n counter providing eleven clocks

– Two independent linear dividers working on modulo n counter outputs

• Independent channel programming

– Independent enable/disable commands

– Independent clock selection

– Independent period and duty cycle, with double bufferization

– Programmable selection of the output waveform polarity

– Programmable center or left aligned output waveform

10.11 USB Device Port

• USB V2.0 full-speed compliant,12 Mbits per second.

• Embedded USB V2.0 full-speed transceiver

29

6117BS–ATARM–07-Apr-05

• Embedded 328-byte dual-port RAM for endpoints

• Four endpoints

– Endpoint 0: 8 bytes

– Endpoint 1 and 2: 64 bytes ping-pong

– Endpoint 3: 64 bytes

– Ping-pong Mode (two memory banks) for bulk endpoints

• Suspend/resume logic

10.12 Analog-to-digital Converter

• 8-channel ADC

• 10-bit 384 Ksamples/sec. Successive Approximation Register ADC

• -3/+3 LSB Integral Non Linearity, -2/+2 LSB Differential Non Linearity

• Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs

• External voltage reference for better accuracy on low voltage inputs

• Individual enable and disable of each channel

• Multiple trigger source

– Hardware or software trigger

– External trigger pin

– Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger

• Sleep Mode and conversion sequencer

– Automatic wakeup on trigger and back to sleep mode after conversions of all

enabled channels

• Four of eight analog inputs shared with digital signals

30

AT91SAM7S256

6117BS–ATARM–07-Apr-05

AT91SAM7S256

11. AT91SAM7S256 Ordering Information

Table 11-1. Ordering Information

Temperature

Ordering Code

Package

Package Type

ROM Code Revision

Operating Range

Industrial

(-40° C to 85° C)

AT91SAM7S256-AU-001

LQFP 64

Green

001

31

6117BS–ATARM–07-Apr-05

Revision History

Doc. Rev.

6117AS

6117BS

Date

Comments

Change Request Ref.

20-Oct-05

07-Apr-05

First issue. Qualified on web

Update qualified on web.

CSR 04-432

Section 9.3 ”Clock Generator” on page 20, PLL output range chaged to

“between 80 and 220 MHz

Evolutions in full datasheet implemented

Datasheet Review

Cycle

Table 3-1, “Signal Description List,” on page 4 VDDIN, VDDIO, TST

Section 5.1 ”Power Supplies” on page 8 VDDIN

Section 5.3 ”Voltage Regulator” on page 8 “consumes less than 25 µA”

Section 8.2.1 ”Flash Overview” on page 15 text added

Section 9.2 ”Reset Controller” on page 19 text added

Section 10.12 ”Analog-to-digital Converter” on page 30 change to 2nd and

3rd lines

Global: font error kW to kΩ corrected

Global: PGMEN2 added.

32

AT91SAM7S256

6117BS–ATARM–07-Apr-05

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6117BS–ATARM–07-Apr-05


型号：	AT91SAM7S256_0504
厂家：	ATMEL
描述：	AT91 ARM Thumb-based Microcontrollers AT91 ARM的Thumb-基于微控制器微控制器
文件：	总33页 (文件大小：393K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT91SAM7S256_0504 [ATMEL]

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