AT91SAM9261-EK [ATMEL]
The AT91SAM9261-EK evaluation kit is an effective platform for evaluating chip performance and developing code for applications based on the AT91SAM92; 在AT91SAM9261 - EK评估套件是一个基于AT91SAM92评价芯片性能和开发代码的应用程序的有效平台
| 型号： | AT91SAM9261-EK |
| 厂家： | 
ATMEL |
| 描述： | The AT91SAM9261-EK evaluation kit is an effective platform for evaluating chip performance and developing code for applications based on the AT91SAM92 |
| 文件： | 总26页 (文件大小：692K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AT91SAM9261-EK Evaluation Board
..............................................................................................
User Guide
AT91SAM9261-EK Evaluation Board User Guide
6198A–ATARM–15-Nov-05
Table of Contents
Section 1
Overview...............................................................................................1-1
1.1 Scope........................................................................................................1-1
1.2 Deliverables ..............................................................................................1-1
1.3 The AT91SAM9261-EK Evaluation Board................................................1-1
Section 2
Setting Up the AT91SAM9261-EK Evaluation Board ...........................2-1
2.1 Electrostatic Warning................................................................................2-1
2.2 Requirements............................................................................................2-1
2.3 Layout .......................................................................................................2-2
2.4 Powering Up the Board.............................................................................2-3
2.5 Backup Power Supply...............................................................................2-4
2.6 Getting Started..........................................................................................2-4
2.7 AT91SAM9261-EK Block Diagram ...........................................................2-4
Section 3
Board Description .................................................................................3-1
3.1 AT91SAM9261 Microcontroller.................................................................3-1
3.2 AT91SAM9261 Block Diagram .................................................................3-4
3.3 Memory.....................................................................................................3-5
3.4 Clock Circuitry...........................................................................................3-5
3.5 Reset Circuitry ..........................................................................................3-5
3.6 Shutdown Controller .................................................................................3-5
3.7 Power Supply Circuitry..............................................................................3-5
3.8 Remote Communication ...........................................................................3-5
3.9 Audio Stereo Interface ..............................................................................3-5
3.10 User Interface ...........................................................................................3-5
3.11 Debug Interface ........................................................................................3-6
3.12 Expansion Slot..........................................................................................3-6
Section 4
Configuration Straps.............................................................................4-1
4.1 Configuration Straps .................................................................................4-1
Section 5
Schematics ...........................................................................................5-1
5.1 Schematics ...............................................................................................5-1
AT91SAM9261-EK Evaluation Board User Guide
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6198A–ATARM–15-Nov-05
-ii
AT91SAM9261-EK Evaluation Board User Guide
6198A–ATARM–15-Nov-05
Section 1
Overview
1.1
1.2
Scope
The AT91SAM9261-EK evaluation kit is an effective platform for evaluating chip perfor-
mance and developing code for applications based on the AT91SAM9261.
This guide is a description of the hardware included in the AT91SAM9261-EK evaluation
kit. Software files are available on the DVD-ROM included in the kit and described in
“Deliverables” below.
Deliverables
The AT91SAM9261-EK package contains the following items:
! an AT91SAM9261-EK board
! one A/B-type USB cable
! one serial RS232 cable
! one RJ45 crossed Ethernet cable
! one DataFlash® card
! universal input AC/DC power supply with US and EU plug adapter
! one DVD-ROM containing summary and full datasheets, datasheets with electrical
and mechanical characteristics, application notes and getting started documents for
all development boards and AT91 microcontrollers. An AT91 software package with C
and assembly listings is also provided. This allows the user to begin evaluating the
AT91 ARM® Thumb® 32-bit microcontroller quickly.
1.3
The
The board is equipped with an AT91SAM9261 (217-ball LFBGA package) together with
the following:
AT91SAM9261-
EK Evaluation
Board
! 64 Mbytes of SDRAM memory
! 256 Mbytes of NAND Flash memory
! one Atmel 32 Mbit serial DataFlash (AT45DB321C-CNC)
! one USB device port interface
! two USB host port interfaces
! one DBGU serial communication port
AT91SAM9261-EK Evaluation Board User Guide
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Overview
! JTAG/ICE debug interface
! one Ethernet 100-base TX with three status LEDs
! one Atmel AT73C213 Audio DAC
! one 3.5" 1/4 VGA TFT LCD Module with TouchScreen and backlight
! one Power LED and two general-purpose LEDs
! four user input pushbuttons
! one wakeup input pushbutton
! one reset pushbutton
! one DataFlash SD/MMC card slot
! two expansion footprint connectors (solder side)
! one Lithium Coin Cell Battery Retainer for 12 mm cell size
! dual pitch prototyping area
1-2
AT91SAM9261-EK Evaluation Board User Guide
6198A–ATARM–15-Nov-05
Section 2
Setting Up the AT91SAM9261-EK
Evaluation Board
2.1
2.2
Electrostatic
Warning
The AT91SAM9261-EK evaluation board is shipped in a protective anti-static package.
The board must not be subjected to high electrostatic potentials. A grounding strap or
similar protective device should be worn when handling the board. Avoid touching the
component pins or any other metallic element.
Requirements
In order to set up the AT91SAM9261-EK evaluation board, the following items are
required:
! the AT91SAM9261-EK evaluation board itself
! AC/DC power adapter (5V at 2A), 2.1 mm by 5.5 mm
AT91SAM9261-EK Evaluation Board User Guide
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6198A–ATARM–15-Nov-05
Setting Up the AT91SAM9261-EK Evaluation Board
2.3
Layout
Figure 2-1. AT91SAM9261-EK Layout - Top View
2-2
AT91SAM9261-EK Evaluation Board User Guide
6198A–ATARM–15-Nov-05
Setting Up the AT91SAM9261-EK Evaluation Board
Figure 2-2. AT91SAM9261-EK Layout - Bottom View
2.4
Powering Up the AT91SAM9261-EK requires 5V DC (±5%). DC power is supplied to the board via the 2.1
Board
mm by 5.5 mm socket (J1). The coaxial power plug center pin is positive polarity .
AT91SAM9261-EK Evaluation Board User Guide
2-3
6198A–ATARM–15-Nov-05
Setting Up the AT91SAM9261-EK Evaluation Board
2.5
Backup Power
Supply
The user has the possibility to add a battery (3V Lithium Battery CR1225 or equivalent)
in order to permanently power the backup part of the device. In this case, J9 configura-
tion must to be set in position 1, 2.
Refer to Table 4-1, “Configuration Jumpers and Straps”.
2.6
Getting Started
The AT91SAM9261-EK evaluation board is delivered with a DVD-ROM containing all
necessary information and step-by-step procedures for working with the most common
development tool chains. Please refer to this DVD-ROM, or to the AT91 web site,
http://www.atmel.com/products/AT91/, for the most up-to-date information on getting
started with the AT91SAM9261-EK.
2.7
AT91SAM9261-
EK Block
Diagram
Figure 2-3. Block Diagram
DBGU
RS232
TFT
320 x 240
HEADPHONE
OUT
ETHERNET 10/100
RJ45
1/4 VGA DISPLAY
WITH TOUCHSCREEN
JTAG/ICE
VUSB
ADM3202A
POWER SUPPLY
5 VDC
AT73C213
STEREO
AUDIO DAC
EMAC + PHY
LINEAR REGULATOR
3V3
VDD3V3
TRACE PORT
ETM
YELLOW POWER LED
5V
PIO
TOUCHSCREEN
CONTROLLER
NRST
1V2
REG
1V2
1V2
VDDCORE
LCD CONTROLLER
VDDPLL VDDOSC
VDDIO
SYSTEM CONTROLLER
AT91SAM9261-BGA217
XOUT
XIN
PIO
EXT CLK INPUT
1V2
3
2
1
3
2
1
32
3V
16
16
1.2V
16
+
32 Mbits
DATAFLASH
AT45D321C-CNC
SDRAM
256 Mb
SDRAM
256 Mb
NANDFLASH
512 Mb
3V3
USER'S GREEN LED
9
1
2
3
4
5
6
7
8
SD/MMC
DATAFLASH
CARD READER
2-4
AT91SAM9261-EK Evaluation Board User Guide
6198A–ATARM–15-Nov-05
Section 3
Board Description
3.1
AT91SAM9261
Microcontroller
! Incorporates the ARM926EJ-S™ ARM® Thumb® Processor
– DSP Instruction Extensions
– ARM Jazelle® Technology for Java™ Acceleration
– 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer
– 200 MIPS at 180 MHz
– Memory Management Unit
– EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support
– Mid-level implementation Embedded Trace Macrocell™
! Additional Embedded Memories
– 32K Bytes of Internal ROM, Single-cycle Access at Maximum Bus Speed
– 160K Bytes of Internal SRAM, Single-cycle Access at Maximum Processor or
Bus Speed
! External Bus Interface (EBI)
– Supports SDRAM, Static Memory, NAND Flash and CompactFlash®
! LCD Controller
– Supports Passive or Active Displays
– Up to 16-bits per Pixel in STN Color Mode
– Up to 16M Colors in TFT Mode (24-bit per Pixel), Resolution up to 2048 x
2048
! USB
– USB 2.0 Full Speed (12 Mbits per second) Host Double Port
Dual On-chip Transceivers
Integrated FIFOs and Dedicated DMA Channels
– USB 2.0 Full Speed (12 Mbits per second) Device Port
On-chip Transceiver, 2-Kbyte Configurable Integrated FIFOs
! Bus Matrix
– Handles Five Masters and Five Slaves
– Boot Mode Select Option
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6198A–ATARM–15-Nov-05
Board Description
– Remap Command
! Fully Featured System Controller (SYSC) for Efficient System Management, including
– Reset Controller, Shutdown Controller, Four 32-bit Battery Backup Registers
for a Total of 16 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real-time Timer
– Three 32-bit PIO Controllers
! Reset Controller (RSTC)
– Based on Power-on Reset Cells, Reset Source Identification and Reset
Output Control
! Shutdown Controller (SHDWC)
– Programmable Shutdown Pin Control and Wake-up Circuitry
! Clock Generator (CKGR)
– 32.768 kHz Low-power Oscillator on Battery Backup Power Supply, Providing
a Permanent Slow Clock
– 3 to 20 MHz On-chip Oscillator and two PLLs
! Power Management Controller (PMC)
– Very Slow Clock Operating Mode, Software Programmable Power
Optimization Capabilities
– Four Programmable External Clock Signals
! Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Three External Interrupt Sources and One Fast Interrupt Source, Spurious
Interrupt Protected
! Debug Unit (DBGU)
– 2-wire USART and Support for Debug Communication Channel,
Programmable ICE Access Prevention
! Periodic Interval Timer (PIT)
– 20-bit Interval Timer plus 12-bit Interval Counter
! Watchdog Timer (WDT)
– Key Protected, Programmable Only Once, Windowed 12-bit Counter, Running
at Slow Clock
! Real-Time Timer (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock
! Three 32-bit Parallel Input/Output Controllers (PIO) PIOA, PIOB and PIOC
– 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous
Output
! Nineteen Peripheral DMA (PDC) Channels
3-2
AT91SAM9261-EK Evaluation Board User Guide
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Board Description
! Multimedia Card Interface (MCI)
– Compliant with Multimedia Cards and SDCards
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC,
MMC and SDCard Compliant
! Three Synchronous Serial Controllers (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and
Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
! Three Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation
– Support for ISO7816 T0/T1 Smart Card, Hardware and Software
Handshaking, RS485 Support
! Two Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
! One Three-channel 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
! Two-wire Interface (TWI)
– Master Mode Support, All Two-wire Atmel EEPROMs Supported
! IEEE 1149.1 JTAG Boundary Scan on All Digital Pins
! Required Power Supplies:
– 1.08V to 1.32V for VDDCORE and VDDBU
– 2.7V to 3.6V for VDDOSC and for VDDPLL
– 2.7V to 3.6V for VDDIOP (Peripheral I/Os) and for VDDIOM (Memory I/Os)
! Available in a 217-ball LFBGA RoHS-compliant Package
AT91SAM9261-EK Evaluation Board User Guide
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6198A–ATARM–15-Nov-05
Board Description
3.2
AT91SAM9261
Block Diagram
Figure 3-1. Block Diagram
JTAGSEL
ARM926EJ-S Core
TDI
TSYNC
JTAG
Boundary Scan
TDO
TMS
TCLK
ICE
ETM
Instruction Cache
16K bytes
Data Cache
16K bytes
MMU
TCK
TPS0-TPS2
NTRST
RTCK
TPK0-TPK15
TCM
Interface
BIU
System Controller
AIC
BMS
D0-D15
A0/NBS0
TST
FIQ
IRQ0-IRQ2
DRXD
DTXD
PCK0-PCK3
I
D
I
D
A1/NBS2/NWR2
A2-A15/A18-A21
A22/REG
ITCM
DTCM
DBGU
PDC
EBI
A16/BA0
Fast SRAM
160K bytes
CompactFlash
NAND Flash
A17/BA1
NCS0
NCS1/SDCS
NCS2
PLLA
PLLRCA
PLLRCB
NCS3/NANDCS
NRD/CFOE
NWR0/NWE/CFWE
NWR1/NBS1/CFIOR
NWR3/NBS3/CFIOW
SDCK
Fast ROM
32K bytes
PMC
PLLB
OSC
XIN
XOUT
5-layer
Matrix
SDCKE
SDRAM
Controller
RAS-CAS
SDWE
SDA10
WDT
PIT
NWAIT
A23-A24
Peripheral
Bridge
A25/CFRNW
Static
Memory
Controller
GPBREG
RTT
NCS4/CFCS0
NCS5/CFCS1
CFCE1
CFCE2
NCS6/NANDOE
NCS7/NANDWE
D16-D31
XIN32
XOUT32
OSC
Peripheral
DMA
Controller
SHDN
WKUP
SHDWC
HDMA
HDPA
VDDBU
GNDBU
POR
POR
DMA
FIFO
RSTC
USB Host
HDMB
HDPB
VDDCORE
NRST
FIFO
APB
DDM
DDP
PIOA
PIOB
PIOC
USB Device
DMA
FIFO
LCDD0-LCDD23
LCDVSYNC
LCDHSYNC
LCDDOTCK
LCDDEN
MCCK
MCCDA
MCDA0-MCDA3
MCI
LUT
LCD Controller
LCDCC
PDC
TF0
TK0
TD0
RD0
RK0
RF0
RXD0
TXD0
SCK0
RTS0
CTS0
SSC0
USART0
USART1
USART2
PDC
PDC
PDC
PDC
RXD1
TXD1
SCK1
RTS1
CTS1
TF1
TK1
TD1
RD1
RK1
RF1
SSC1
PDC
PDC
RXD2
TXD2
SCK2
RTS2
CTS2
TF2
TK2
TD2
RD2
RK2
RF2
SSC2
SPI0_NPCS0
SPI0_NPCS1
SPI0_NPCS2
SPI0_NPCS3
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
Timer Counter
SPI0
SPI1
TC0
TC1
TC2
PDC
PDC
SPI1_NPCS10
SPI1_NPCS1
SPI1_NPCS12
SPI1_NPCS3
SPI1_MISO
SPI1_MOSI
SPI1_SPCK
TWD
TWI
TWCK
3-4
AT91SAM9261-EK Evaluation Board User Guide
6198A–ATARM–15-Nov-05
Board Description
3.3
Memory
! 32 Kbytes of Internal ROM
! 160 Kbytes of Internal High-speed SRAM
! Atmel 32 Mbit serial DataFlash
! 64 Mbytes of SDRAM memory
! 256 Mbytes of NAND Flash memory
3.4
3.5
3.6
3.7
Clock Circuitry
Reset Circuitry
! 18.432 MHz standard crystal for the embedded oscillator
! 32.768 kHz standard crystal for the slow clock oscillator
! Internal reset controller with a bi-directional reset pin
! External reset push button
Shutdown
Controller
! Programmable shutdown and Wake-Up
! Wake-up push button
Power Supply
Circuitry
! For dynamic power consumption, the AT91SAM9261 consumes a maximum of 50 mA
on VDDCORE at maximum speed in typical conditions (1.2V, 25°C), processor
running full-performance algorithm
! On-board 1.2V high efficiency step-down charge pump regulator with shutdown
control
! On-board 3.3V linear regulator with shutdown control
3.8
Remote
Communication
! One Serial interface (DBGU COM Port) via RS-232 DB9 male socket
! USB V2.0 Full-speed Compliant, 12 Mbits per second (UDP)
! Two USB Host port V2.0 Full-speed Compliant, 12 Mbits per second (UHP)
! One Ethernet 100-base TX with three status LEDs
3.9
Audio Stereo
Interface
! One Atmel stereo audio DAC AT73C213
! One 32 Ohm/20 mW Stereo Headset output (J20) with Master Volume and Mute
Controls
3.10
User Interface
! Four user input pushbuttons
! Two user green LEDs
! One yellow power LED (can be also software controlled)
AT91SAM9261-EK Evaluation Board User Guide
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6198A–ATARM–15-Nov-05
Board Description
! One ¼ VGA display LCD with Touchscreen and white LED backlight
3.11
3.12
Debug Interface
! 20-pin JTAG/ICE interface connector
! DBGU COM Port
Expansion Slot
! One DataFlash, SD/MMC card slot
! All I/Os of the AT91SAM9261 are routed to peripheral extension footprint connectors
(J16 and J17). This allows the developer to check the integrity of the components and
to extend the features of the board by adding external hardware components or
boards.
3-6
AT91SAM9261-EK Evaluation Board User Guide
6198A–ATARM–15-Nov-05
Section 4
Configuration Straps
4.1
Configuration
Straps
Table 4-1 gives details on configuration straps on the AT91SAM9261-EK evaluation
board and their default settings.
Table 4-1. Configuration Jumpers and Straps
Default
Designation
Setting
Feature
J2
Closed
3.3V Jumper (1)
This jumper footprint is provided for 3.3V power consumption
measurement use. By default, it is closed. To use this feature,
the user has to open the strap by cutting it before soldering a
jumper.
J3
J4
Closed
Forces power on. To use the software shutdown control, J3
must be opened.
Opened
Closed
Closed
2-3
Enables Boot on the internal ROM
Enables Boot on the NCS0
VDDPLL Jumper (1)
J8
J9
VDDBU Jumper select (1)
1-2 : Lithium 3V Battery
2-3 : 1.2V from VDDCORE
J12
J21
Closed
1-2
VDDCORE Jumper (1)
NPCS0 select
1-2 : AT45DB321C (MN7)
2-3 : Dataflash card interface (J22).
Warning: In this case NPCS03 must be configured as
input.
S2
S3
S4
S5
S6
Opened
Closed
Closed
Opened
Opened
Disables the ICE NTRST input
Enables the ICE RTCK return. S6 must be opened
Enables the ICE NRST input
Selects ICE mode or JTAG mode (Closed)
Disables TCK <-> RTCK local loop. If S6 is closed, S3 must be
opened.
AT91SAM9261-EK Evaluation Board User Guide
4-1
6198A–ATARM–15-Nov-05
Configuration Straps
Table 4-1. Configuration Jumpers and Straps
Default
Designation
Setting
Closed
Opened
Closed
Opened
Closed
Closed
Closed
Opened
Feature
Enables the use of 18.432 MHz crystal. If external clock used,
S7-S8 must be opened and S9 closed.
S7-S8
S9
S10
S12
S13
S14
S15
S16
Enables the use of SDRAM (NCS1_SDCS)
Disables Serial DataFlash write protect.
Disables NAND FLASH write protect.
Enables the use of interrupt ETHERNET MAC (PC11_FIQ).
Enables the use of ETHERNET MAC (NCS2).
Disables the use of NWAIT ETHERNET MAC signal
(PC2_NWAIT)
S19
S20
S21
S22
S23
S24
S25
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Enables the use of the User LED DS7 (PA14)
Enables the use of the User LED DS8 (PA13)
Enables the use of the DBGU RXD signal (PA9)
Enables the use of the USB CNX detection (PB29)
Enables the use of AUDIO DAC INTERFACE (NPCS03)
Enables the use of TOUCH SCEEN CONTROLLER (NPCS02)
Enables the use of TOUCH SCEEN CONTROLLER BUSY
signal (PA11)
S26
Closed
Enables the use of TOUCH SCEEN CONTROLLER PENIRQ
(PC2_IRQ0)
TP1
TP2
N.A
N.A
N.A
N.A
N.A
N.A
N.A
N.A
3.3V Test point.
GND Test point.
TP3
1.2V Test point.
TP4
GND Test point.
TP63
TP64
TP65
TP66
0 to 3.3V analog user's input
0 to 3.3V analog user's input
AGND of TP63
AGND of TP64
Note:
1. These jumpers are provided for measuring power consumption. By default, they are
closed. To use this feature, the user has to open the strap and insert an anmeter.
4-2
AT91SAM9261-EK Evaluation Board User Guide
6198A–ATARM–15-Nov-05
Section 5
Schematics
5.1
Schematics
This section contains the following schematics:
! Power Supply and Audio
! AT91SAM9261
! SDRAM and NAND Flash
! Ethernet
! LCD and User Interface
! Serial and I/O Expansion
AT91SAM9261-EK Evaluation Board User Guide
5-1
6198A–ATARM–15-Nov-05
8
7
6
5
4
3
2
1
D
C
B
A
D
C
B
A
3V3
AUDIO DAC INTERFACE
10 SQUARE CM COPPER AREA FOR HEAT SINKING
WITH NO SOLDER MASK
R1
120R
3V3
LT1963AEQ-3.3
6
C2
MN1
REGULATED
5V ONLY
5V
3V3
POWER LED
R2
100K
10µF
10V
GND
VOUT
GND FB
J2
R67
100K
J1
1
2
2
4
PA[0..31]
TP1
3.3V
VIN
SD
1
DS1
YELLOW
MN15
PAINN
VBAT
CBP
HPP
AT73C213
+
15
12
14
13
DOUT
DIN
CLK
CS
C1
330µF
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
PA0
PA1
PA2
PA29
25
PA[0..31]
CR1
5V
26
27
28
C3
10µF
C4
10µF
3
5
3
2
Q1
IRLML2402
SPI0_NPCS3
TP2
GND
HPN
LPHN
11
10
S23
NRST
SMODE
RSTB
22
21
PA23
1
PAINP
16
30
29
M5V
MONOP
MONON
VDIG
24
2
3V3
C5
1µF
C6
1µF
AVDD
AVDDHS
VCM
VCC_DAC
LINER
LINEL
7
6
Q2
5
6
1
5
2
4
3
8
6
3
4
1V2
Si1563EDH
5V
C7
R3
C1M C1P C2M C2P
C107 10µF
C110
100NF
22µF 100K
9
1
5
1
7
J3
TP3
VIN
VOUT
AUXP
AUXN
31
32
1.2V
C111 10µF
C8
10PF
VREF
FORCE
POWER
ON
J20
C108 C109
100NF 100NF
GND_DAC
PCK2
TD1
TF1
PB[0..31]
TPS60500
R68
47R
C10
4.7µF
3.5 PHONEJACK STEREO
100µF
10
2
FB
C112
C113
6V3
HSR
HSL
MCLK
SDIN
LRFS
BCLK
C9
15PF
PB31
3
1
4
2
4
3
20
17
19
18
R5
10K
R6
10K
R4
200K
PA19
PA17
PA18
EN
PG
GND
9
TK1
MN2
100µF
6V3
TP4
INGND
8
GNDB
33
GNDD
23
PA[0..31]
SHDN
GND
ADHESIVE FEET
GND_DAC
Z3
Z4
VCC_DAC
3V3
L4
4.7µH
11.1
11.1
Z7
Z8
C114
10µF
10V
11.1
11.1
R69 0R
GND_DAC
Wednesday, September 14, 2005
C
B
A
JPG
JPG
JPG
DES.
14/09/05
04/20/05
02/23/05
DATE
INIT EDIT
XXX XX/XX/05
REV MODIF.
VER.
DATE
SHEET
1
SCALE1/1
REV.
AT91SAM9261-EK
POWER SUPPLY & AUDIO
C
6
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
PC[0..15]
PB[0..31]
D[0..31]
A[0..22]
BOOT MODE SELECT
PB3 BMS
R7 1K
J4
MN3
PA[0..31]
ETM
TRACE PORT
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
R11
T12
U13
P10
T13
U14
T14
R12
T15
U16
R13
T16
U15
R14
T17
P13
P14
R15
R17
P16
P17
N15
N14
N16
N17
M14
M15
L15
M16
M17
L14
L16
D
C
B
A
D
C
B
A
PA0/SPI0_MISO/MCDA0
PA1/SPI0_MOSI/MCCDA
PA2/SPI0_SPCK/MCCK
PA3/SPI0_NPCS0
PA4/SPI0_NPCS1/MCDA1
PA5/SPI0_NPCS2/MCDA2
PA6/SPI0_NPCS3/MCDA3
PA7/TWD/PCK0
PA8/TWCK/PCK1
PA9/DRXD/PCK2
PA10/DTXD/PCK3
PA11/TSYNK/SCK1
PA12/TCLK/RTS1
PA13/TPS0/CTS1
PA14/TPS1/SCK2
PA15/TPS2/RTS2
PA16/TPK0/CTS2
PA17/TPK1/TF1
PA18/TPK2/TK1
PA19/TPK3/TD1
PA20/TPK4/RD1
PA21/TPK5/RK1
PA22/TPK6/RF1
PA23/TPK7/RTS0
PA24/TPK8/SPI1_NPCS1
PA25/TPK9/SPI1_NPCS2
PA26/TPK10/SPI1_NPCS3
PA27/TPK11/SPI0_NPCS1
PA28/TPK12/SPI0_NPCS2
PA29/TPK13/SPI0_NPCS3
PA30/TPK14/A23
PA13
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
D0
D1
D2
D3
D4
D5
D6
D7
PIPESTAT[0]
PIPESTAT[1]
PIPESTAT[2]
TRACESYNC
TRACEPKT[0]
TRACEPKT[1]
TRACEPKT[2]
TRACEPKT[3]
TRACEPKT[4]
TRACEPKT[5]
TRACEPKT[6]
TRACEPKT[7]
VSUPPLY
TRACEPKT[8]
TRACEPKT[9]
TRACEPKT[10]
TRACEPKT[11]
TRACEPKT[12]
TRACEPKT[13]
TRACEPKT[14]
TRACEPKT[15]
ICE_NTRST
TDI
TMS
TCK
ICE_RTCK
TDO
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
G1
G2
H1
H2
J1
D0
D1
D2
D3
D4
D5
D6
D7
D8
PA14
PA15
PA11
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
J2
K1
K4
K2
L1
K3
L2
D8
D9
D9
D10
D11
D12
D13
D14
D15
D10
D11
D12
D13
D14
D15
L3
3V3
R8
10K
M1
N1
M2
EXTTRIG
ICE_NRST
DBGRQ
GND
7
5
3
1
TRACECLK
PA12
6
4
2
R9
0R
A0
A1
A2
A3
A4
A5
A6
A7
D8
B8
A8
A7
B7
D7
A6
B6
C6
A5
D6
B5
A4
B4
A3
B3
A2
C4
B2
A1
B1
C2
C1
NBS0/A0
NWR2/NBS2/A1
R10
10K
A2
A3
A4
A5
A6
A7
A8
A9
C11
100NF
J5
DNP
A8
A9
PA31/TPK15/A24
3V3
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A10
A11
A12
A13
A14
A15
BA0/A16
BA1/A17
A18
A19
A20
A21
A22
A12
B12
DDP
DDM
DDP
DDM
RR1
100K
C12
B14
HDPA
HDMA
HDPA
HDMA
AT91SAM9261
J6
ICE INTERFACE
ICE_NTRST
TDI
TMS
TCK
A13
A14
HDPB
HDMB
HDPB
HDMB
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19
S2
E17
C17
D17
U17
F16
B10
TDI
TMS
TCK
RTCK
TDO
JTAGSEL
ICE_RTCK
TDO
S3
ICE_NRST
S4
NRST
S5
F2
J4
3V3
RAS
CAS
RAS
CAS
S6
F17
NTRST
G3
E4
F1
H4
SDWE
SDA10
SDCKE
SDCK
SDWE
SDA10
SDCKE
SDCK
C12
4.7NF
R11
1,96K
1%
U9
PLLRCB
470pF
C13
R12
C14
4.7NF
1,5K
1%
F4
D2
D1
G4
E3
NCS0
SDCS_NCS1
NCS2
SMCS_NCS3
CFOE_NOE_NRD
NCS0
SDCS/NCS1
NCS2
NANDCS/NCS3
CFOE/NRD
U10
U12
PLLRCA
XOUT
470pF
Y1
C15
C16
10PF
S7
E2
E1
F3
CFWE_NWE_NWR0
CFIOR_NBS1_NWR1
CFIOW_NBS3_NWR3
18.4320MHz
CFWE/NWE/NWR0
CFIOR/NBS1/NWR1
CFIOW/NBS3/NWR3
J7
DNP
C17
10PF
S8
S9
U11
T10
XIN
1
3
5
2
4
VDDOSC
C18
F15
NRST
NRST
100NF
T11
3V3
GNDOSC
XOUT32
C19
SMB MALE
10PF
A10
A11
R13
1K
32.768 kHz
Y2
C20
10PF
C10
XIN32
TST
J8
R10
C21
100NF
A9
C14
D10
3V3
VDDPLL
NC
NC
NC
Z14
VDDOSC + VDDPLL
CURRENT MEASURE
P9
GNDPLL
R14
1K
BP1
CR1225
+
3V
MN10
R1100D121C
RESET
1V2
3V3
R16
1,50M
DNP
R17
100K
C43
10µF
10V
3
2
1
J9
J10
Wednesday, September 14, 2005
R15 1K
C28
10µF
10V
WAKE UP
C
B
A
JPG
JPG
JPG
DES.
14/09/05
04/20/05
02/23/05
DATE
C126
100NF
C22
100NF
C24 C26
100NF 100NF
C25
C29
C31
C33
C35
C36
C38
C40
C42
INIT EDIT
XXX XX/XX/05
100NF 100NF 100NF 100NF 100NF 100NF 100NF 100NF
C30 C32 C34 C37 C39 C41
100NF 100NF 100NF 100NF 100NF 100NF
REV MODIF.
VER.
DATE
SHEET
2
BP2
C23
10µF
10V
C27
J12
SCALE1/1
REV.
VDDBU
SHDN
WKUP
AT91SAM9261-EK
100NF 100NF
1V2
AT91SAM9261
C
VDDCORE CURRENT MEASURE
5
6
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
4
3
2
1
8
7
6
5
4
3
2
1
EBI SDRAM INTERFACE
A[0..22]
D[0..31]
RAS
CAS
SDWE
SDA10
SDCKE
SDCK
D
C
B
A
D
C
B
A
CFIOR_NBS1_NWR1
CFIOW_NBS3_NWR3
MN4
MN5
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
D0
D1
D2
D3
D4
D5
D6
D7
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
23
24
25
26
29
30
31
32
33
34
22
35
2
4
5
7
23
24
25
26
29
30
31
32
33
34
22
35
2
4
5
7
SDCS_NCS1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
MT48LC16M16A2
MT48LC16M16A2
8
8
10
11
13
42
44
45
47
48
50
51
53
10
11
13
42
44
45
47
48
50
51
53
D8
D9
DQ9
DQ9
SDA10
D10
D11
D12
D13
D14
D15
SDA10
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
A13
A13
A16
A17
A16
A17
BA0
BA1
BA0
BA1
20
21
20
21
BA0
BA1
BA0
BA1
A14
A14
36
40
36
40
3V3
3V3
A12
N.C
A12
N.C
1
1
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
14
27
3
9
43
49
14
27
3
9
43
49
SDCKE
SDCK
NBS0
SDCKE
SDCK
NBS2
37
38
37
38
CKE
CLK
CKE
CLK
A0
A1
15
39
15
39
DQML
DQMH
DQML
DQMH
CFIOR_NBS1_NWR1
CFIOW_NBS3_NWR3
28
41
54
6
12
46
52
28
41
54
6
12
46
52
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
3V3
CAS
RAS
CAS
RAS
17
18
17
18
CAS
RAS
CAS
RAS
C50
100NF 100NF
C44 C45
C51
C52
C53
C54
C55
C56
C57
100NF 100NF
C46
100NF 100NF
100NF 100NF
C49
R18
100K
SDWE
SDWE
C47
C48
16
19
16
19
WE
CS
WE
CS
100NF 100NF 100NF
100NF 100NF
100NF
256 Mbits
256 Mbits
S10
PA[0..31]
DUAL FOOTPRINT
D[0..31]
3V3
PC[0..15]
MN7
3V3
MN6A
MT29F2G16AABWP
MN6B
K9F1208U0A-Y
PA0
PA1
PA2
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
SPI0_NPCS0
8
1
2
4
6
SO
SI
SCK
CS
VCC
GND
WP
A21
A22
PC0
PC1
PC14
D0
D1
D2
D3
D4
D5
D6
D7
A21
A22
PC0
PC1
PC14
D0
D1
D2
D3
D4
D5
D6
D7
C58
100NF
16
17
8
18
26
28
30
32
40
42
44
46
27
29
31
33
41
43
45
47
16
17
8
18
9
29
30
31
32
41
42
43
44
CLE
ALE
RE
WE
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
CLE
ALE
RE
WE
CE
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
7
R19
100K
9
3V3
R20
CE
3
5
RESET
PC15
WP
PC15
WP
7
7
100K
R/B
R/B
WP
AT45DB321C-CNC
S12
D8
D9
19
19
WRITE PROTECT
NORMALLY OPEN
WP
48
47
46
45
40
39
38
35
34
33
28
27
NRST
I/O9
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
D10
D11
D12
D13
D14
D15
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
S13
1
2
3
4
5
6
10
11
14
15
20
21
22
23
24
34
1
2
3
4
5
1
2
3
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
PA3
3V3
SD CARD / MMC CARD
DATAFLASH CARD
INTERFACE
J21
R72
10K
6
39
38
36
10
11
14
15
20
21
22
23
24
25
26
N.C
PRE
N.C
J22
PA4
PA0
MCDA1
SPI0_MISO MCDA0
8
7
6
5
4
3
2
1
9
3V3
PA2
SPI0_SPCK MCCK
3V3
37
12
37
12
3V3
VCC
VCC
VCC
VCC
C60
100NF
PA1
PA6
PA5
SPI0_MOSI MCCDA
SPI0_NPCS3 MCDA3
MCDA2
48
25
13
VSS
VSS
VSS
36
13
VSS
VSS
35
N.C
C59
100NF
FPS009
C115
100NF
2 Gbits
512 Mbits
Wednesday, September 14, 2005
C
B
A
JPG
JPG
JPG
DES.
14/09/05
04/20/05
02/23/05
DATE
INIT EDIT
XXX XX/XX/05
REV MODIF.
VER.
DATE
REV.
SCALE1/1
S3HEET
6
AT91SAM9261-EK
SDRAM & NANDFLASH
C
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
3V3
R21 1K
DS2
GREEN LINK&ACT
D
C
B
A
D
C
B
A
FULL DUPLEX
YELLOW
DS3
DS4
R22 1K
R24 1K
3V3
R23
4,7K
GREEN SPEED 100
Note1: 8/16 bit DataBus
selection; Removed R27
when using 16-bit mode;
otherwise is 8-bit mode.
3V3
L1
742792093
VCCA
C61
100NF
3V3
MN8
R25
49R9
1%
R26
49R9
1%
R27
4,7K
DNP
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
DGND
NC
TXD0
TX_CLK
TEST5
RX_CLK
RX_ER
RX_DV
COL
J13
J0026D21
D[0..15]
A[0..22]
LINK_O
WAKEUP
PW_RST#
DGND
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
DVDD
IO16
CMD
SA4
SA5
TD+
CT
TX+
TX-
RX+
RX-
1
2
3
6
1
3
2
NRST
C62
100NF
D15
D14
D13
D12
D11
D10
D9
PC[0..15]
TD-
CRS
DGND
RXD3
RXD2
RXD1
RXD0
LINK_I
DVDD
AVDD
TXO-
TXO+
AGND
AGND
RXI-
RD+
CT
7
6
8
DM9000
3V3 VCCA
D8
3V3
RD-
A2
C63
100NF
75 75
75
75
R28
4,7K
SA6
SA7
SA8
SA9
DGND
INT
4
5
7
8
R29
49R9
1%
R30
49R9
1%
4
5
RXI+
AVDD
AVDD
BGRES
1nF
PC11 FIQ
S14
C64
100NF
R31
6,80K
1%
3V3
3V3
R32
100K
Y3
25MHz
2
1
CFOE_NOE_NRD
CFWE_NWE_NWR0
S15
C66
22PF
C67
22PF
NCS2
D0
D1
D2
D3
D4
D5
D6
D7
3V3
VCCA
L2
4.7µH
3V3
3V3
3V3
3V3
3V3
3V3
VCCA
VCCA
C68
C69
C70
C71
C72
C73
C74
C75
C76
10µF
10V
C77
100NF
C79
100NF
100NF 100NF 100NF 100NF 100NF 100NF
100NF 100NF
C78
10µF
10V
PC10 RST
3V3
R70 0R
R71 0R
R34
4,7K
S16
PC2 NWAIT
NOT USED
Wednesday, September 14, 2005
C
B
A
JPG
JPG
JPG
DES.
14/09/05
04/20/05
02/23/05
DATE
INIT EDIT
XXX XX/XX/05
REV MODIF.
VER.
DATE
REV.
SCALE1/1
S4HEET
6
AT91SAM9261-EK
C
ETHERNET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
3V3
PA[0..31]
PC[0..15]
3V3
R84
100K
PA12
TOUCH SCREEN CONTROLLER
54132-4097
R74 47R
MN16
X_RIGHT
Y_LOW
X_LEFT
Y_UP
X_LEFT
Y_UP
X_RIGHT
Y_LOW
R73
R76
R77
R78
0R
0R
0R
0R
PA2
PA1
PA0
PA28
SPI0_SPCK
SPI0_MOSI
SPI0_MISO
SPI0_NPCS2
2
3
4
5
16
14
12
15
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
XP
YP
XM
YM
DCLK
DIN
DOUT
CS
R75
10K
M5V
S24
D
C
B
A
D
C
B
A
Vctrl
VCTRL
MN11
PCI
B0
B1
B2
S25 PA11
S26 PC2
BUSY
IRQ0
1
2
3
4
8
7
6
5
13
11
RST
IN
N.C
GND
N.C
N.C
N.C
N.C
BUSY
PENIRQ
C116
10NF
C119
10NF
LCDD18
LCDD19
LCDD20
PB23
PB24
PB25
R79 0R
3V3
Z17 TX09D71VM1CCA
C87
4.7NF
9
1
10
R80
R81
VREF
VCC
VCC
100K
C117 C118
10NF 10NF
7
8
DNP
IN3
IN4
B3
B4
B5
LCDD21
LCDD22
LCDD23
PB26
PB27
PB28
MC34064D
3
2
L5 4.7µH
100K
TP63
C120
10µF
10V
TP64
G0
G1
G2
LCDD10
LCDD11
LCDD12
PB15
PB16
PB17
PA12 POWER CONTROL IN
1
6
GND
R82 0R
AGND
TP65
ADS7843E
C122
100NF
C121 C123
100NF 100NF
Q6
IRLML2402
G3
G4
G5
LCDD13
LCDD14
LCDD15
PB18
PB19
PB20
TP66
TWO USER'S ANALOG INPUTS
Full-Scale Input Span 0 to VREF
R0
R1
R2
LCDD2
LCDD3
LCDD4
PB7
PB8
PB9
R83 10K
PB4
VCTRL
LCDCC
R3
R4
R5
LCDD5
LCDD6
LCDD7
PB10
PB11
PB12
C84
100NF
DTMG LCDDEN
PB3
8
7
6
5
4
3
2
1
HSYNCLCDHSYNC PB1
DCLK LCDDDOTCK PB2
3V3
PB[0..31]
J23
C124
100NF
C125
10V
10µF
PA[0..31]
PA27
BP3
3V3
GREEN
S19
R50 220R
PA14
PA13
PA26
PA25
PA24
BP4
BP5
BP6
DS7
GREEN
DS8
S20
R51 220R
Wednesday, September 14, 2005
USER INTERFACE
C
B
A
JPG
JPG
JPG
DES.
14/09/05
04/20/05
02/23/05
DATE
INIT EDIT
REV MODIF.
XXX XX/XX/05
VER.
DATE
REV.
SCALE1/1
S5HEET
6
AT91SAM9261-EK
C
LCD & USER'S INTERFACE
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
3V3
MN13
1
16
C1+
VCC
C91
100NF
C92
100NF
15
2
GND
V+
3
4
C1-
C2+
C93
100NF
MALE RIGHT ANGLED
J15
C94
100NF
C95
100NF
1
6
2
7
3
8
4
9
5
5
6
C2-
V-
SERIAL DEBUG PORT
R52 0R
RXD
TXD
11
14
D
C
B
A
D
C
B
A
EXPANSION CONNECTORS
T
PA10
PA9
DBGU_TXD
10
12
9
7
T
S21
J16
J17
PA[0..31] PB[0..31] PC[0..15]
DBGU_RXD
13
8
R
R
R53 0R
1
3
5
7
9
2
4
6
8
1
3
5
7
9
2
4
6
8
PB0
PB2
PB4
PB6
PB1
PB3
PB5
PB7
A1
A4
A7
A2
A3
A6
A9
A12
A14
A16
A19
A5
PA0
PB0
PC0
A11
A13
A15
A18
A0
A10
A17
A21
A22
ADM3202ARN
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
PA1
PA2
PB1
PB2
PC1
PC2
PB8
PB9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
PB10
PB12
PB14
PB16
PB18
PB20
PB22
PB24
PB26
PB28
PB30
PB11
PB13
PB15
PB17
PB19
PB21
PB23
PB25
PB27
PB29
PB31
PA3
PB3
PC3
PA4
PA5
PB4
PB5
PC4
PC5
PA6
PA7
PB6
PB7
PC6
PC7
A8
A20
PA8
PB8
PC8
PA9
PB9
PC9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
PC10
PC11
PC12
PC13
PC14
PC15
SDCS_NCS1
CFIOR_NBS1_NWR1
CFOE_NOE_NRD
CFIOW_NBS3_NWR3
RAS
SDCKE
NCS2
CFWE_NWE_NWR0
SDA10
NCS0
5V
PA0
PA2
PA4
PA6
PA1
PA3
PA5
PA7
F1
500 mA
F2
500 mA
SDWE
CAS
J18
SDCK
CCUSBA-32002-30X
PA8
PA9
SMCS_NCS3
USB HOST INTERFACE
PA10
PA12
PA14
PA16
PA18
PA20
PA22
PA24
PA26
PA28
PA30
PA11
PA13
PA15
PA17
PA19
PA21
PA23
PA25
PA27
PA29
PA31
D2
D3
D1
D0
D5
D7
A1
B1
B2
B3
B4
39R
39R
R54
A
B
A2
A3
A4
HDMA
HDPA
D10
D8
D12
D11
D6
R55
D4
D15
D13
D14
C96
47pF
C97
47pF
1 2
3 4
R56
15K
R57
15K
D9
C98
100NF
C99
100NF
PC0
PC2
PC4
PC6
PC8
PC10
PC12
PC14
D16
D18
D20
D22
D24
D26
D28
D30
PC1
PC3
PC5
PC7
PC9
PC11
PC13
PC15
D17
D19
D21
D23
D25
D27
D29
D31
3V3
3V3
5V
3V3
3V3
5V
39R
39R
R58
R59
HDMB
HDPB
A[0..22]
D[0..31]
C101
47pF
R60
15K
R61
15K
C100
47pF
A0
D0
A1
A2
D1
D2
A3
D3
A4
A5
D4
D5
S22
R62 15K
A6
A7
D6
D7
PB29
USB_CNX
USER'S GRID AERA
A8
D8
A9
D9
R63
22K
NRST
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
NOT POPULATED
WKUP
SHDN
VDDBU
3V3
Q5
IRLML6302
MN14
GND
3V3
5V
3V3
5V
3V3
5V
5
4
VCC
PB30
NRST
1.27 PITCH
USB_DP_PUP
1
2
3
1
C102
100NF
SN74LVC1G00DBV
3V3
5V
R64
1,5K
2.54 PITCH
J19
USB DEVICE INTERFACE
C103
33PF
39R
39R
R65
R66
2
3
1
4
DDM
DDP
C104
100NF
C105
15PF
C106
15PF
5
6
Wednesday, September 14, 2005
C
B
JPG
JPG
14/09/05
04/20/05
INIT EDIT
REV MODIF.
A
JPG
DES.
02/23/05
DATE
XXX XX/XX/05
VER.
DATE
SHEET
6
SCALE1/1
REV.
AT91SAM9261-EK
C
SERIAL & I/O EXPANSION
6
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
Atmel Corporation
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