AT93C46-10PK-5.0C [ATMEL]
EEPROM, 64X16, Serial, CMOS, PDIP8, 0.300 INCH, PLASTIC, MS-001BA, DIP-8;
| 型号： | AT93C46-10PK-5.0C |
| 厂家： | 
ATMEL |
| 描述： | EEPROM, 64X16, Serial, CMOS, PDIP8, 0.300 INCH, PLASTIC, MS-001BA, DIP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总15页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Medium-voltage and Standard-voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
• User-selectable Internal Organization
– 1K: 128 x 8 or 64 x 16
– 2K: 256 x 8 or 128 x 16
– 4K: 512 x 8 or 256 x 16
• Three-wire Serial Interface
• 2 MHz Clock Rate (5V)
• Self-timed Write Cycle (10 ms max)
• High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• 8-lead PDIP and 8-lead JEDEC SOIC Packages
Three-wire
Serial
Automotive
EEPROMs
Description
The AT93C46/56/66 provides 1024/2048/4096 bits of serial electrically erasable pro-
grammable read only memory (EEPROM) organized as 64/128/256 words of 16 bits
each, when the ORG pin is connected to VCC and 128/256/512 words of 8 bits each
when it is tied to ground. The device is optimized for use in many automotive applica-
tions where low power and low voltage operations are essential. The AT93C46/56/66
is available in space-saving 8-lead PDIP and 8-lead JEDEC SOIC packages. The
AT93C46/56/66 is enabled through the Chip Select pin (CS), and accessed via a
3-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock
(SK). Upon receiving a Read instruction at DI, the address is decoded and the data is
clocked out serially on the data output pin DO. The WRITE cycle is completely self-
timed and no separate erase cycle is required before write. The Write cycle is only
enabled when it is in the Erase/Write Enable state. When CS is brought “high” follow-
ing the initiation of a write cycle, the DO pin outputs the Ready/Busy status.
1K (128 x 8 or 64 x 16)
2K (256 x 8 or 128 x 16)
4K (512 x 8 or 256 x 16)
AT93C46
AT93C56(1)
AT93C66(2)
The AT93C46/56/66 is available in 4.5V to 5.5V and 2.7V to 5.5V versions.
Note: 1. This device is not recom-
mended for new designs.
Table 1. Pin Configuration
8-lead PDIP
Pin Name
CS
Function
Please refer to AT93C56A.
Chip Select
2. This device is not recom-
mended for new designs.
Please refer to AT93C66A.
CS
SK
DI
1
2
3
4
8
7
6
5
VCC
DC
SK
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
ORG
GND
DI
DO
DO
GND
VCC
ORG
8-lead SOIC
Power Supply
Internal Organization
CS
1
8
7
6
5
VCC
SK
DI
2
3
4
DC
ORG
GND
DO
Rev. 3264E–SEEPR–10/04
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions beyond those indicated in the operational sec-
tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability
Operating Temperature......................................−55°C to +125°C
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 1. Block Diagram
Note:
When the ORG pin is connected to VCC, the “x 16” organization is selected. When it is connected to ground, the “x 8” organiza-
tion is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the
internal 1 Meg ohm pullup, then the “x 16” organization is selected.
For the AT93C46, if “x 16” organization is the mode of choice and Pin 6 (ORG) is left unconnected, Atmel recommends
using the AT93C46A device. For more details, see the AT93C46A datasheet.
2
AT93C46/56/66
3264E–SEEPR–10/04
AT93C46/56/66
Table 2. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Symbol
COUT
CIN
Test Conditions
Max
5
Units
pF
Conditions
VOUT = 0V
VIN = 0V
Output Capacitance (DO)
Input Capacitance (CS, SK, DI)
5
pF
Note:
1. This parameter is characterized and is not 100% tested.
Table 3. DC Characteristics
Applicable over recommended operating range from: TA = −40°C to +125°C, VCC = +2.7V to +5.5V (unless otherwise
noted).
Symbol
VCC1
Parameter
Test Condition
Min
2.7
4.5
Typ
Max
5.5
Unit
V
Supply Voltage
Supply Voltage
VCC2
5.5
V
READ at 1.0 MHz
WRITE at 1.0 MHz
CS = 0V
0.5
0.5
6.0
17
2.0
mA
mA
µA
µA
µA
µA
ICC
Supply Current
VCC = 5.0V
2.0
ISB1
ISB2
IIL
Standby Current
Standby Current
Input Leakage
VCC = 2.7V
10.0
30
VCC = 5.0V
CS = 0V
VIN = 0V to VCC
VIN = 0V to VCC
0.1
0.1
1.0
IOL
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
1.0
(1)
VIL1
−0.6
V
CC x 0.3
2.7V ≤ VCC ≤ 5.5V
(1)
VIH1
VCC x 0.7
VCC + 1
0.4
V
V
V
VOL1
VOH1
IOL = 2.1 mA
2.7V ≤ VCC ≤ 5.5V
IOH = −0.4 mA
2.4
Note:
1. VIL min and VIH max are reference only and are not tested.
3
3264E–SEEPR–10/04
Table 4. AC Characteristics
Applicable over recommended operating range from TA = −40°C to + 125°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
SK Clock
Frequency
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
0
0
2
1
fSK
MHz
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
tSKH
tSKL
tCS
SK High Time
SK Low Time
ns
ns
ns
ns
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
Minimum CS
Low Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
50
50
tCSS
CS Setup Time
Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
100
100
tDIS
tCSH
tDIH
DI Setup Time
CS Hold Time
DI Hold Time
Relative to SK
Relative to SK
Relative to SK
ns
ns
ns
0
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
100
100
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
500
tPD1
tPD0
tSV
Output Delay to ‘1’
Output Delay to ‘0’
CS to Status Valid
AC Test
AC Test
AC Test
ns
ns
ns
ns
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
500
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
CS to DO in High
Impedance
AC Test
CS = VIL
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
100
100
tDF
tWP
Write Cycle Time
5.0V, 25°C
2.7V ≤ VCC ≤ 5.5V
3
10
ms
Endurance(1)
1M
Write Cycles
Note:
1. This parameter is characterized and is not 100% tested.
4
AT93C46/56/66
3264E–SEEPR–10/04
AT93C46/56/66
Table 5. Instruction Set for the AT93C46
Address
Data
Op
Instruction
SB
Code
x 8
x 16
x 8
x 16
Comments
Reads data stored in memory, at
specified address
READ
1
10
A6 - A0
A5 - A0
Write enable must precede all
programming modes
EWEN
1
00
11XXXXX
11XXXX
ERASE
WRITE
1
1
11
01
A6 - A0
A6 - A0
A5 - A0
A5 - A0
Erase memory location An - A0
Writes memory location An - A0
D7 - D0
D7 - D0
D15 - D0
Erases all memory locations. Valid
only at VCC = 4.5V to 5.5V
ERAL
1
00
10XXXXX
10XXXX
Writes all memory locations. Valid
only at VCC = 4.5V to 5.5V
WRAL
EWDS
1
1
00
00
01XXXXX
00XXXXX
01XXXX
00XXXX
D15 - D0
Disables all programming instructions
Note:
The Xs in the address field represent don’t care values and must be clocked.
Table 6. Instruction Set for the AT93C56(1) and AT93C66(2)
Address
Op
Data
Instruction
SB
Code
x 8
x 16
x 8
x 16
Comments
Reads data stored in memory, at
specified address
READ
1
10
A8 - A0
A7 - A0
Write enable must precede all
programming modes
EWEN
1
00
11XXXXXXX
11XXXXXX
ERASE
WRITE
1
1
11
01
A8 - A0
A8 - A0
A7 - A0
A7 - A0
Erase memory location An - A0
Writes memory location An - A0
D7 - D0
D15 - D0
Erases all memory locations. Valid
only at VCC = 4.5V to 5.5V
ERAL
1
00
10XXXXXXX
10XXXXXX
Writes all memory locations. Valid
only at VCC = 5.0V 10% and Disable
Register cleared
WRAL
EWDS
1
1
00
00
01XXXXXXX
00XXXXXXX
01XXXXXX
00XXXXXX
D7 - D0
D15 - D0
Disables all programming instructions
Note:
1. This device is not recommended for new designs. Please refer to AT93C56A.
2. This device is not recommended for new designs. Please refer to AT93C66A.
3. The Xs in the address field represent don’t care values and must be clocked.
5
3264E–SEEPR–10/04
Functional
Description
The AT93C46/56/66 is accessed via a simple and versatile 3-wire serial communication
interface. Device operation is controlled by seven instructions issued by the host pro-
cessor. A valid instruction starts with a rising edge of CS and consists of a Start Bit (logic
“1”) followed by the appropriate Op Code and the desired memory Address location.
READ (READ): The Read (READ) instruction contains the address code for the mem-
ory location to be read. After the instruction and address are decoded, data from the
selected memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic “0”) precedes the 8- or 16-bit data output string.
ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable
(EWEN) instruction must be executed first before any programming instructions can be
carried out. Please note that once in the EWEN state, programming remains enabled
until an EWDS instruction is executed or VCC power is removed from the part.
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified
memory location to the logical “1” state. The self-timed erase cycle starts once the
ERASE instruction and address are decoded. The DO pin outputs the Ready/Busy sta-
tus of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A
logic “1” at pin DO indicates that the selected memory location has been erased, and the
part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be
written into the specified memory location. The self-timed programming cycle, tWP, starts
after the last bit of data is received at serial data input pin DI. The DO pin outputs the
Ready/Busy status of the part if CS is brought high after being kept low for a minimum of
250 ns (tCS). A logic “0” at DO indicates that programming is still in progress. A logic “1”
indicates that the memory location at the specified address has been written with the
data pattern contained in the instruction and the part is ready for further instructions. A
Ready/Busy status cannot be obtained if the CS is brought high after the end of the self-
timed programming cycle, tWP
.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the mem-
ory array to the logic “1” state and is primarily used for testing purposes. The DO pin
outputs the Ready/Busy status of the part if CS is brought high after being kept low for a
minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations
with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy
status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS).
The WRAL instruction is valid only at VCC = 5.0V 10%.
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be
executed after all programming operations. The operation of the Read instruction is
independent of both the EWEN and EWDS instructions and can be executed at any
time.
6
AT93C46/56/66
3264E–SEEPR–10/04
AT93C46/56/66
Timing Diagrams
Figure 2. Synchronous Data Timing
Note:
1. This is the minimum SK period.
Table 7. Organization Key for Timing Diagrams
AT93C46 (1K)
AT93C56 (2K)(1)
x 8 x 16
AT93C66 (4K)(2)
I/O
AN
DN
x 8
A6
x 16
A5
x 8
A8
x 16
A7
(3)
(4)
A8
D7
A7
D15
D7
D15
D7
D15
Notes: 1. This device is not recommended for new designs. Please refer to AT93C56A.
2. This device is not recommended for new designs. Please refer to AT93C66A.
3. A8 is a don’t care value, but the extra clock is required.
4. A7 is a don’t care value, but the extra clock is required.
Figure 3. READ Timing
tCS
High Impedance
7
3264E–SEEPR–10/04
Figure 4. EWEN Timing
tCS
CS
SK
DI
...
1
0
0
1
1
Figure 5. EWDS Timing
tCS
CS
SK
DI
...
0
0
0
1
0
Figure 6. WRITE Timing
tCS
CS
SK
DI
...
...
AN
DN
1
0
1
A0
D0
HIGH IMPEDANCE
BUSY
READY
DO
tWP
Figure 7. WRAL Timing(1)
tCS
CS
SK
DI
1
0
0
0
1
...
DN ... D0
BUSY
HIGH IMPEDANCE
DO
READY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
8
AT93C46/56/66
3264E–SEEPR–10/04
AT93C46/56/66
Figure 8. ERASE Timing
tCS
CS
STANDBY
CHECK
STATUS
SK
DI
A0
1
1
1
AN
...
AN-1 AN-2
tDF
tSV
HIGH IMPEDANCE
HIGH IMPEDANCE
BUSY
DO
READY
tWP
Figure 9. ERAL Timing(1)
tCS
CS
STANDBY
CHECK
STATUS
SK
DI
1
0
0
1
0
tDF
tSV
BUSY
HIGH IMPEDANCE
HIGH IMPEDANCE
DO
READY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
9
3264E–SEEPR–10/04
AT93C46 Ordering Information
Ordering Code
Package
Operation Range
AT93C46-10PA-5.0C
AT93C46-10SA-5.0C
8P3
8S1
Automotive
(−40°C to 125°C)
AT93C46-10PA-2.7C
AT93C46-10SA-2.7C
8P3
8S1
Automotive
(−40°C to 125°C)
Package Type
8P3
8S1
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
Options
−5.0
−2.7
Standard Operation (4.5V to 5.5V)
Low Voltage (2.7V to 5.5V)
10
AT93C46/56/66
3264E–SEEPR–10/04
AT93C46/56/66
AT93C56(1) Ordering Information
Ordering Code
Package
Operation Range
AT93C56-10PA-5.0C
AT93C56-10SA-5.0C
8P3
8S1
Automotive
(−40°C to 125°C)
AT93C56-10PA-2.7C
AT93C56-10SA-2.7C
8P3
8S1
Automotive
(−40°C to 125°C)
Note:
1. This device is not recommended for new designs. Please refer to AT93C56A.
Package Type
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
Options
8P3
8S1
−5.0
−2.7
Standard Operation (4.5V to 5.5V)
Low Voltage (2.7V to 5.5V)
11
3264E–SEEPR–10/04
AT93C66(1) Ordering Information
Ordering Code
Package
Operation Range
AT93C66-10PA-5.0C
AT93C66-10SA-5.0C
8P3
8S1
Automotive
(−40°C to 125°C)
AT93C66-10PA-2.7C
AT93C66-10SA-2.7C
8P3
8S1
Automotive
(−40°C to 125°C)
Note:
1. This device is not recommended for new designs. Please refer to AT93C66A.
Package Type
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
Options
8P3
8S1
−5.0
−2.7
Standard Operation (4.5V to 5.5V)
Low Voltage (2.7V to 5.5V)
12
AT93C46/56/66
3264E–SEEPR–10/04
AT93C46/56/66
Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
–
MAX
0.210
0.195
0.022
0.070
0.045
0.014
0.400
–
NOM
–
NOTE
SYMBOL
D1
A2 A
A
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
–
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.100 BSC
0.300 BSC
0.130
0.325
0.280
b
E1
e
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
13
3264E–SEEPR–10/04
8S1 – JEDEC SOIC
C
1
E
E1
L
N
∅
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
b
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.00
3.99
6.20
C
D
E1
E
–
–
D
–
–
Side View
e
1.27 BSC
L
0.40
0˚
–
–
1.27
8˚
∅
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
REV.
TITLE
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
B
R
Small Outline (JEDEC SOIC)
14
AT93C46/56/66
3264E–SEEPR–10/04
Atmel Corporation
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San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
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RF/Automotive
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74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
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Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
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Tel: 1(408) 441-0311
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