AT93C46-10TU-1.8 [ATMEL]
Three-wire Serial EEPROMs; 三线串行EEPROM
| 型号： | AT93C46-10TU-1.8 |
| 厂家： | 
ATMEL |
| 描述： | Three-wire Serial EEPROMs |
| 文件： | 总21页 (文件大小：372K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
• User-selectable Internal Organization
– 1K: 128 x 8 or 64 x 16
– 2K: 256 x 8 or 128 x 16
– 4K: 512 x 8 or 256 x 16
• Three-wire Serial Interface
• 2 MHz Clock Rate (5V)
• Self-timed Write Cycle (10 ms max)
• High Reliability
Three-wire
Serial
EEPROMs
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• Automotive Grade, Extended Temperature and Lead-Free/Halogen-Free
Devices Available
• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead MAP, 8-lead TSSOP,
and 8-ball dBGA2 Packages
1K (128 x 8 or 64 x 16)
2K (256 x 8 or 128 x 16)
4K (512 x 8 or 256 x 16)
Description
The AT93C46/56/66 provides 1024/2048/4096 bits of serial electrically erasable pro-
grammable read-only memory (EEPROM), organized as 64/128/256 words of 16 bits
each (when the ORG pin is connected to VCC), and 128/256/512 words of 8 bits each
(when the ORG pin is tied to ground). The device is optimized for use in many indus-
trial and commercial applications where low-power and low-voltage operations are
essential. The AT93C46/56/66 is available in space-saving 8-lead PDIP, 8-lead
JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead MAP, 8-lead TSSOP, and 8-lead dBGA2
packages.
AT93C46
AT93C56(1)
AT93C66(2)
The AT93C46/56/66 is enabled through the Chip Select pin (CS) and accessed via a
three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift
Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the
data is clocked out serially on the DO pin. The Write cycle is completely self-timed,
and no separate Erase cycle is required before Write. The Write cycle is only enabled
when the part is in the Erase/Write Enable state. When CS is brought high following
the initiation of a Write cycle, the DO pin outputs the Ready/Busy status of the part.
Note: 1. This device is not recom-
mended for new designs.
Please refer to AT93C56A.
2. This device is not recom-
mended for new designs.
Please refer to AT93C66A.
The AT93C46/56/66 is available in 2.7V to 5.5V and 1.8V to 5.5V versions.
Table 1. Pin Configurations
8-lead SOIC
8-lead dBGA2
Pin Name
CS
Function
8
7
6
5
1
2
3
4
VCC
DC
CS
SK
D1
D0
CS
SK
DI
1
8
7
6
5
VCC
DC
Chip Select
2
3
4
ORG
GND
ORG
GND
SK
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
DO
DI
8-lead SOIC
Rotated (R)
(1K JEDEC Only)
8-lead PDIP
DO
CS
1
2
3
4
8
7
6
5
VCC
DC
VCC
CS
1
2
3
4
8
7
6
5
ORG
GND
DO
SK
DI
DC
GND
VCC
ORG
DC
ORG
GND
DO
Power Supply
Internal Organization
Don’t Connect
SK
DI
8-lead MAP
8-lead TSSOP
CS
SK
DI
1
2
3
4
8
7
6
5
VCC
8
7
6
5
1
2
3
4
VCC
DC
CS
DC
SK
DI
ORG
GND
ORG
GND
DO
DO
0172Z–SEEPR–9/05
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only, and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Operating Temperature......................................−55°C to +125°C
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 1. Block Diagram
Note:
When the ORG pin is connected to VCC, the “x 16” organization is selected. When it is
connected to ground, the “x 8” organization is selected. If the ORG pin is left uncon-
nected and the application does not load the input beyond the capability of the internal 1
Meg ohm pullup, then the “x 16” organization is selected. The feature is not available on
the 1.8V devices.
For the AT93C46, if “x 16” organization is the mode of choice and Pin 6 (ORG) is left
unconnected, Atmel recommends using the AT93C46A device. For more details, see the
AT93C46A datasheet.
2
AT93C46/56/66
0172Z–SEEPR–9/05
AT93C46/56/66
Table 2. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol
COUT
CIN
Test Conditions
Max
5
Units
pF
Conditions
VOUT = 0V
VIN = 0V
Output Capacitance (DO)
Input Capacitance (CS, SK, DI)
5
pF
Note:
1. This parameter is characterized and is not 100% tested.
Table 3. DC Characteristics
Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = +1.8V to +5.5V,
AE = -40°C to +125°C, VCC = +1.8V to +5.5V (unless otherwise noted)
T
Symbol
VCC1
Parameter
Test Condition
Min
1.8
2.7
4.5
Typ
Max
5.5
Unit
V
Supply Voltage
Supply Voltage
Supply Voltage
VCC2
5.5
V
VCC3
5.5
V
READ at 1.0 MHz
WRITE at 1.0 MHz
CS = 0V
0.5
0.5
0
2.0
mA
mA
µA
µA
µA
µA
µA
ICC
Supply Current
VCC = 5.0V
2.0
ISB1
ISB2
ISB3
IIL
Standby Current
Standby Current
Standby Current
Input Leakage
VCC = 1.8V
0.1
VCC = 2.7V
CS = 0V
6.0
17
10.0
30
VCC = 5.0V
CS = 0V
VIN = 0V to VCC
VIN = 0V to VCC
0.1
0.1
1.0
IOL
Output Leakage
1.0
(1)
VIL1
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
−0.6
2.0
0.8
2.7V ≤ VCC ≤ 5.5V
V
V
(1)
VIH1
VCC + 1
VCC x 0.3
VCC + 1
0.4
(1)
VIL2
−0.6
1.8V ≤ VCC ≤ 2.7V
(1)
VIH2
VCC x 0.7
VOL1
VOH1
VOL2
VOH2
I
OL = 2.1 mA
V
V
V
V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 2.7V
IOH = −0.4 mA
2.4
I
OL = 0.15 mA
0.2
IOH = −100 µA
VCC – 0.2
Note:
1. VIL min and VIH max are reference only and are not tested.
3
0172Z–SEEPR–9/05
Table 4. AC Characteristics
Applicable over recommended operating range from TAI = −40°C to + 85°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
0
0
0
2
1
0.25
SK Clock
Frequency
fSK
MHz
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
tSKH
tSKL
tCS
SK High Time
SK Low Time
ns
ns
ns
ns
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
Minimum CS
Low Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
50
50
200
tCSS
CS Setup Time
Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
100
400
tDIS
tCSH
tDIH
DI Setup Time
CS Hold Time
DI Hold Time
Relative to SK
Relative to SK
Relative to SK
ns
ns
ns
0
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
100
400
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
Output Delay to
“1”
tPD1
tPD0
tSV
AC Test
AC Test
AC Test
ns
ns
ns
ns
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
Output Delay to
“0”
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
CS to Status
Valid
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
100
400
CS to DO in High
Impedance
AC Test
CS = VIL
tDF
10
ms
ms
tWP
Write Cycle Time
5.0V, 25°C
4.5V ≤ VCC ≤ 5.5V
0.1
1M
3
Endurance(1)
Write Cycles
Note:
1. This parameter is characterized and is not 100% tested.
4
AT93C46/56/66
0172Z–SEEPR–9/05
AT93C46/56/66
Table 5. Instruction Set for the AT93C46
Address
Data
Op
Instruction
SB
Code
x 8
x 16
x 8
x 16
Comments
Reads data stored in memory, at
specified address
READ
1
10
A6 – A0
A5 – A0
Write enable must precede all
programming modes
EWEN
1
00
11XXXXX
11XXXX
ERASE
WRITE
1
1
11
01
A6 – A0
A6 – A0
A5 – A0
A5 – A0
Erases memory location An – A0
Writes memory location An – A0
D7 – D0
D7 – D0
D15 – D0
Erases all memory locations. Valid
only at VCC = 4.5V to 5.5V
ERAL
1
00
10XXXXX
10XXXX
Writes all memory locations. Valid
only at VCC = 4.5V to 5.5V
WRAL
EWDS
1
1
00
00
01XXXXX
00XXXXX
01XXXX
00XXXX
D15 – D0
Disables all programming instructions
Note:
The Xs in the address field represent DON’T CARE values and must be clocked.
Table 6. Instruction Set for the AT93C56(1) and AT93C66(2)
Address
Op
Data
Instruction
SB
Code
x 8
x 16
x 8
x 16
Comments
Reads data stored in memory, at
specified address
READ
1
10
A8 – A0
A7 – A0
Write enable must precede all
programming modes
EWEN
1
00
11XXXXXXX
11XXXXXX
ERASE
WRITE
1
1
11
01
A8 – A0
A8 – A0
A7 – A0
A7 – A0
Erases memory location An – A0
Writes memory location An– A0
D7 – D0
D15 – D0
Erases all memory locations. Valid
only at VCC = 4.5V to 5.5V
ERAL
1
00
10XXXXXXX
10XXXXXX
Writes all memory locations. Valid
only at VCC = 5.0V ±10% and Disable
Register cleared
WRAL
EWDS
1
1
00
00
01XXXXXXX
00XXXXXXX
01XXXXXX
00XXXXXX
D7 – D0
D15 – D0
Disables all programming instructions
Notes: 1. This device is not recommended for new designs. Please refer to AT93C56A.
2. This device is not recommended for new designs. Please refer to AT93C66A.
5
0172Z–SEEPR–9/05
Functional
Description
The AT93C46/56/66 is accessed via a simple and versatile three-wire serial communi-
cation interface. Device operation is controlled by seven instructions issued by the host
processor. A valid instruction starts with a rising edge of CS and consists of a start bit
(logic “1”) followed by the appropriate op code and the desired memory address
location.
READ (READ): The Read (READ) instruction contains the address code for the mem-
ory location to be read. After the instruction and address are decoded, data from the
selected memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic “0”) precedes the 8- or 16-bit data output string.
ERASE/WRITE ENABLE (EWEN): To assure data integrity, the part automatically goes
into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write
Enable (EWEN) instruction must be executed first before any programming instructions
can be carried out. Please note that once in the EWEN state, programming remains
enabled until an EWDS instruction is executed or VCC power is removed from the part.
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified
memory location to the logical “1” state. The self-timed erase cycle starts once the
Erase instruction and address are decoded. The DO pin outputs the Ready/Busy status
of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A
logic “1” at pin DO indicates that the selected memory location has been erased and the
part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be
written into the specified memory location. The self-timed programming cycle tWP starts
after the last bit of data is received at serial data input pin DI. The DO pin outputs the
Read/Busy status of the part if CS is brought high after being kept low for a minimum of
250 ns (tCS). A logic “0” at DO indicates that programming is still in progress. A logic “1”
indicates that the memory location at the specified address has been written with the
data pattern contained in the instruction and the part is ready for further instructions. A
Ready/Busy status cannot be obtained if the CS is brought high after the end of the self-
timed programming cycle tWP.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the mem-
ory array to the logic “1” state and is primarily used for testing purposes. The DO pin
outputs the Ready/Busy status of the part if CS is brought high after being kept low for a
minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations
with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy
status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS).
The WRAL instruction is valid only at VCC = 5.0V ± 10%.
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be
executed after all programming operations. The operation of the Read instruction is
independent of both the EWEN and EWDS instructions and can be executed at any
time.
6
AT93C46/56/66
0172Z–SEEPR–9/05
AT93C46/56/66
Timing Diagrams
Figure 2. Synchronous Data Timing
µs
Note:
1. This is the minimum SK period.
Table 7. Organization Key for Timing Diagrams
AT93C46 (1K)
AT93C56 (2K)(1)
x 8 x 16
AT93C66 (4K)(2)
I/O
AN
DN
x 8
A6
x 16
A5
x 8
A8
x 16
A7
(3)
(4)
A8
D7
A7
D15
D7
D15
D7
D15
Notes: 1. This device is not recommended for new designs. Please refer to AT93C56A.
2. This device is not recommended for new designs. Please refer to AT93C66A.
3. A8 is a don’t care value, but the extra clock is required.
4. A7 is a don’t care value, but the extra clock is required.
7
0172Z–SEEPR–9/05
Figure 3. READ Timing
tCS
High Impedance
Figure 4. EWEN Timing
tCS
CS
SK
DI
...
1
0
0
1
1
Figure 5. EWDS Timing
tCS
CS
SK
DI
...
0
0
0
1
0
8
AT93C46/56/66
0172Z–SEEPR–9/05
AT93C46/56/66
Figure 6. WRITE Timing
tCS
CS
SK
DI
...
...
AN
DN
1
0
1
A0
D0
HIGH IMPEDANCE
BUSY
READY
DO
tWP
Figure 7. WRAL Timing(1)
tCS
CS
SK
DI
1
0
0
0
1
...
DN ... D0
BUSY
HIGH IMPEDANCE
DO
READY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
Figure 8. ERASE Timing
tCS
CS
STANDBY
CHECK
STATUS
SK
DI
A0
1
1
1
AN
...
AN-1 AN-2
tDF
tSV
HIGH IMPEDANCE
HIGH IMPEDANCE
BUSY
DO
READY
tWP
9
0172Z–SEEPR–9/05
Figure 9. ERAL Timing(1)
tCS
CS
STANDBY
CHECK
STATUS
SK
DI
1
0
0
1
0
tDF
tSV
BUSY
HIGH IMPEDANCE
HIGH IMPEDANCE
DO
READY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
10
AT93C46/56/66
0172Z–SEEPR–9/05
AT93C46/56/66
AT93C46 Ordering Information(1)
Ordering Code
Package
Operation Range
AT93C46-10PI-2.7
AT93C46-10SI-2.7
AT93C46R-10SI-2.7
AT93C46W-10SI-2.7
AT93C46-10TI-2.7
8P3
8S1
8S1
8S2
8A2
Industrial
(−40°C to 85°C)
AT93C46-10PI-1.8
AT93C46-10SI-1.8
AT93C46R-10SI-1.8
AT93C46W-10SI-1.8
AT93C46-10TI-1.8
8P3
8S1
8S1
8S2
8A2
Industrial
(−40°C to 85°C)
AT93C46-10PU-2.7
AT93C46-10PU-1.8
AT93C46-10SU-2.7
AT93C46-10SU-1.8
AT93C46W-10SU-2.7
AT93C46W-10SU-1.8
AT93C46-10TU-2.7
AT93C46-10TU-1.8
AT93C46Y1-10YU-2.7
8P3
8P3
8S1
8S1
8S2
8S2
8A2
8A2
8Y1
Lead-free/Halogen-free/
Industrial Temperature
(−40°C to 85°C)
AT93C46Y1-10YU-1.8
AT93C46Y5-10YU-2.7
AT93C46Y5-10YU-1.8
8Y1
8Y5
8Y5
AT93C46U3-10UU-2.7
AT93C46U3-10UU-1.8
8U3-1
8U3-1
AT93C46-W2.7-11(2)
AT93C46-W1.8-11(2)
Industrial
Die Sale
Die Sale
(−40°C to 85°C)
Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the Table 3 on page 3 and Table 4 on
page 4.
2. Available in waffle pack and wafer form, order as SL719 for wafer form. Bumped die available upon request.
Package Type
8P3
8S1
8S2
8A2
8U3-1
8Y1
8Y5
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8-ball, Die Ball Grid Array Package (dBGA2)
8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
8-lead, 2.00 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
Options
−2.7
−1.8
R
Low Voltage (2.7V to 5.5V)
Low Voltage (1.8V to 5.5V)
Rotated Pinout
11
0172Z–SEEPR–9/05
AT93C56(1) Ordering Information
Ordering Code(2)
Package
Operation Range
AT93C56-10PI-2.7
AT93C56-10SI-2.7
AT93C56W-10SI-2.7
AT93C56-10TI-2.7
AT93C56Y1-10YI-2.7
8P3
8S1
8S2
8A2
8Y1
Industrial
(−40°C to 85°C)
AT93C56-10PI-1.8
AT93C56-10SI-1.8
AT93C56W-10SI-1.8
AT93C56-10TI-1.8
AT93C56Y1-10YI-1.8
8P3
8S1
8S2
8A2
8Y1
Industrial
(−40°C to 85°C)
Notes: 1. This device is not recommended for new designs. Please refer to AT93C56A.
2. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in Table 3 on page 3 and Table 4 on
page 4.
Package Type
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
Options
8P3
8S1
8S2
8A2
8Y1
−2.7
Low Voltage (2.7V to 5.5V)
1.8
Low Voltage (1.8V to 5.5V)
12
AT93C46/56/66
0172Z–SEEPR–9/05
AT93C46/56/66
AT93C66(1) Ordering Information
Ordering Code(2)
Package
Operation Range
AT93C66-10PI-2.7
AT93C66-10SI-2.7
AT93C66W-10SI-2.7
AT93C66-10TI-2.7
AT93C66Y1-10YI-2.7
8P3
8S1
8S2
8A2
8Y1
Industrial
(−40°C to 85°C)
AT93C66-10PI-1.8
AT93C66-10SI-1.8
AT93C66W-10SI-1.8
AT93C66-10TI-1.8
AT93C66Y1-10YI-1.8
8P3
8S1
8S2
8A2
8Y1
Industrial
(−40°C to 85°C)
Notes: 1. This device is not recommended for new designs. Please refer to AT93C66A.
2. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in Table 3 on page 3 and Table 4 on
page 4.
Package Type
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
Options
8P3
8S1
8S2
8A2
8Y1
−2.7
−1.8
Low Voltage (2.7V to 5.5V)
Low Voltage (1.8V to 5.5V)
13
0172Z–SEEPR–9/05
Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
MAX
NOM
NOTE
SYMBOL
D1
A2 A
A
0.210
0.195
0.022
0.070
0.045
0.014
0.400
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.325
0.280
b
E1
e
0.100 BSC
0.300 BSC
0.130
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
14
AT93C46/56/66
0172Z–SEEPR–9/05
AT93C46/56/66
8S1 – JEDEC SOIC
C
1
E
E1
L
N
∅
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
b
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.00
3.99
6.20
C
D
E1
E
–
–
D
–
–
Side View
e
1.27 BSC
L
0.40
0˚
–
–
1.27
8˚
∅
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
REV.
TITLE
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
B
R
Small Outline (JEDEC SOIC)
15
0172Z–SEEPR–9/05
8S2 – EIAJ SOIC
C
1
E
E1
L
N
Top View
∅
End View
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.70
0.05
0.35
0.15
5.13
5.18
7.70
0.51
0˚
MAX
2.16
0.25
0.48
0.35
5.35
5.40
8.26
0.85
8˚
NOM
NOTE
SYMBOL
A1
A
A1
b
5
5
C
D
E1
E
D
2, 3
Side View
L
∅
e
1.27 BSC
4
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs are not included.
3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
4. Determines the true geometric position.
5. Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/−0.005 mm.
10/7/03
TITLE
REV.
DRAWING NO.
2325 Orchard Parkway
San Jose, CA 95131
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
8S2
C
R
16
AT93C46/56/66
0172Z–SEEPR–9/05
AT93C46/56/66
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
3.00
NOTE
SYMBOL
D
2.90
3.10
2, 5
A
b
E
6.40 BSC
4.40
E1
A
4.30
–
4.50
1.20
1.05
0.30
3, 5
4
–
A2
b
0.80
0.19
1.00
e
A2
–
D
e
0.65 BSC
0.60
L
0.45
0.75
Side View
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
DRAWING NO.
TITLE
REV.
2325 Orchard Parkway
San Jose, CA 95131
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
B
8A2
R
17
0172Z–SEEPR–9/05
8U3-1 – dBGA2
E
D
1.
b
A1
PIN 1 BALL PAD CORNER
A2
Top View
A
PIN 1 BALL PAD CORNER
Side View
1
2
3
4
(d1)
d
7
6
5
8
e
COMMON DIMENSIONS
(Unit of Measure = mm)
(e1)
MIN
0.71
0.10
0.40
0.20
MAX
0.91
0.20
0.50
0.30
NOM
0.81
NOTE
SYMBOL
Bottom View
8 SOLDER BALLS
A
A1
A2
b
0.15
0.45
0.25
D
1.50 BSC
2.00 BSC
0.50 BSC
0.25 REF
1.00 BSC
0.25 REF
1. Dimension “b” is measured at the maximum solder ball diameter.
This drawing is for general information only.
E
e
e1
d
d1
6/24/03
TITLE
REV.
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch,
Small Die Ball Grid Array Package (dBGA2)
PO8U3-1
A
R
18
AT93C46/56/66
0172Z–SEEPR–9/05
AT93C46/56/66
8Y1 – MAP
PIN 1 INDEX AREA
A
1
3
4
2
PIN 1 INDEX AREA
E1
D1
D
L
8
6
5
7
b
e
A1
E
Bottom View
End View
Top View
COMMON DIMENSIONS
(Unit of Measure = mm)
A
SYMBOL
MIN
–
MAX
0.90
0.05
5.10
3.20
1.15
1.15
0.35
NOM
–
NOTE
A
A1
D
0.00
4.70
2.80
0.85
0.85
0.25
–
4.90
3.00
1.00
1.00
0.30
0.65 TYP
0.60
Side View
E
D1
E1
b
e
L
0.50
0.70
2/28/03
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package
(MAP) Y1
8Y1
C
R
19
0172Z–SEEPR–9/05
8Y5 – MAP
b
D2
(8x)
Pin 1
Index
Area
Pin 1 ID
L (8x)
D
e (6x)
A3
1.50 REF.
Bottom View
Top View
A
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
2.00 BSC
3.00 BSC
1.50
NOTE
SYMBOL
D
E
D2
E2
A
1.40
1.75
–
1.60
1.95
0.90
0.05
0.85
1.85
–
A1
A2
A3
L
0.0
–
0.02
–
0.20 REF
0.30
0.20
0.20
0.40
0.30
e
0.50 BSC
0.25
A1
A2
b
2
Side View
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions,
tolerances, datums, etc.
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
11/12/03
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
8Y5, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Mini-Map, Dual
No Lead Package (DFN)
8Y5
A
R
20
AT93C46/56/66
0172Z–SEEPR–9/05
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
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Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
2325 Orchard Parkway
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Fax: 1(408) 436-4314
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0172Z–SEEPR–9/05
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