AT93C46C-10SC-2.5 [ATMEL]
3-Wire Serial EEPROM; 3线串行EEPROM
| 型号： | AT93C46C-10SC-2.5 |
| 厂家： | 
ATMEL |
| 描述： | 3-Wire Serial EEPROM |
| 文件： | 总11页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Low-Voltage and Standard-Voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 2.5 (VCC = 2.5V to 5.5V)
• 3-Wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• 2 MHz Clock Rate (5V) Compatibility
• Self-Timed Write Cycle (10 ms max)
• High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
– ESD Protection: > 4000V
3-Wire
Serial EEPROM
1K (64 x 16)
• Automotive Grade and Extended Temperature Devices Available
• 8-Pin PDIP and JEDEC SOIC Packages
Description
The AT93C46C provides 1024 bits of serial electrically-erasable programmable read
only memory (EEPROM) organized as 64 words of 16 bits each. The device is opti-
mized for use in many industrial and commercial applications where low-power and
low-voltage operation are essential. The AT93C46C is available in space saving 8-pin
PDIP and 8-pin JEDEC packages.
AT93C46C
The AT93C46C is enabled through the Chip Select pin (CS), and accessed via a 3-
wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock
(SK). Upon receiving a READ instruction at DI, the address is decoded and the data is
clocked out serially on the data output pin DO. The WRITE cycle is completely self-
timed and no separate ERASE cycle is required before WRITE. The WRITE cycle is
only enabled when the part is in the ERASE/WRITE ENABLE state. When CS is
brought “high” following the initiation of a WRITE cycle, the DO pin outputs the
READY/BUSY status of the part.
The AT93C46C is available in 4.5V to 5.5V, 2.7V to 5.5V, and 2.5V to 5.5V versions.
8-Pin PDIP
Pin Configurations
Pin Name Function
3-Wire, 1K
Serial E2PROM
CS
SK
DI
1
2
3
4
8
7
6
5
VCC
DC
CS
Chip Select
NC
SK
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
DO
GND
DI
DO
GND
VCC
NC
DC
8-Pin SOIC
Power Supply
No Connect
CS
1
8
7
6
5
VCC
SK
DI
2
3
4
DC
Don’t Connect
NC
DO
GND
Rev. 1122A–07/98
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Operating Temperature.................................. -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground.....................................-1.0V to +7.0V
Maximum Operating Voltage........................................... 6.25V
DC Output Current........................................................ 5.0 mA
Block Diagram
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Test Conditions
Max
5
Units
pF
Conditions
VOUT = 0V
VIN = 0V
COUT
Output Capacitance (DO)
CIN
Input Capacitance (CS, SK, DI)
5
pF
Note:
1. This parameter is characterized and is not 100% tested.
AT93C46C
2
AT93C46C
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +2.5V to +5.5V,
TAC = 0°C to +70°C, VCC = +2.5V to +5.5V (unless otherwise noted).
Symbol
VCC1
VCC2
VCC3
ICC
Parameter
Test Condition
Min
2.5
2.7
4.5
Typ
Max
5.5
Units
V
Supply Voltage
Supply Voltage
Supply Voltage
Supply Current
5.5
V
5.5
V
READ at 1.0 MHz
WRITE at 1.0 MHz
CS = 0V
0.5
0.5
2.0
mA
mA
µA
µA
µA
µA
µA
V
VCC = 5.0V
2.0
ISB1
ISB2
ISB3
IIL
Standby Current
Standby Current
Standby Current
Input Leakage
VCC = 2.5V
14.0
14.0
35.0
0.1
20.0
20.0
50.0
1.0
VCC = 2.7V
CS = 0V
VCC = 5.0V
CS = 0V
VIN = 0V to VCC
VIN = 0V to VCC
IOL
Output Leakage
0.1
1.0
(1)
VIL1
Input Low Voltage
Input High Voltage
-0.6
VCC x 0.3
2.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
(1)
VIH1
V
CC x 0.7
V
CC + 1
VOL1
VOH1
Output Low Voltage
Output High Voltage
I
I
OL = 2.1 mA
OH = -0.4 mA
0.4
V
V
V
V
2.4
VOL2
VOH2
Output Low Voltage
Output High Voltage
IOL = 0.15 mA
0.2
2.5V ≤ VCC ≤ 2.7V
IOH = -100 µA
VCC - 0.2
Note:
1. VIL min and VIH max are reference only and are not tested.
AC Characteristics
Applicable over recommended operating range from TA = -40°C to + 85°C, VCC = +2.5V to + 5.5V,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
fSK
SK Clock Frequency
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
0
0
0
2
1
0.5
MHz
tSKH
tSKL
tCS
SK High Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
250
250
500
ns
SK Low Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
250
250
500
ns
Minimum CS Low Time
CS Setup Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
250
250
500
ns
tCSS
Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
50
50
100
ns
3
AC Characteristics (Continued)
Applicable over recommended operating range from TA = -40°C to + 85°C, VCC = +2.5V to + 5.5V,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
tDIS
DI Setup Time
Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
100
100
200
ns
tCSH
tDIH
CS Hold Time
DI Hold Time
Relative to SK
Relative to SK
0
ns
ns
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
100
100
200
tPD1
tPD0
tSV
Output Delay to ‘1’
AC Test
AC Test
AC Test
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
250
250
500
ns
ns
ns
ns
Output Delay to ‘0’
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
250
250
500
CS to Status Valid
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
250
250
500
tDF
CS to DO in High Impedance
AC Test
CS = VIL
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
100
100
200
tWP
Write Cycle Time
0.1
10
ms
ms
4.5V ≤ VCC ≤ 5.5V
1
Endurance(1)
5.0V, 25°C, Page Mode
1 M
Write Cycle
Note:
1. This parameter is characterized and is not 100% tested.
Instruction Set for the AT93C46C
Address
Instruction
READ
SB
1
Op Code
x 16
Comments
10
00
11
01
00
00
00
A5 - A0
Reads data stored in memory, at specified address.
Write enable must precede all programming modes.
Erase memory location An - A0.
EWEN
ERASE
WRITE
ERAL
1
11XXXX
A5 - A0
1
1
A5 - A0
Writes memory location An - A0.
1
10XXXX
01XXXX
00XXXX
Erases all memory locations. Valid only at VCC = 4.5V to 5.5V.
Writes all memory locations. Valid only at VCC = 4.5V to 5.5V.
Disables all programming instructions.
WRAL
1
EWDS
1
AT93C46C
4
AT93C46C
Functional Description
The AT93C46C is accessed via a simple and versatile
three-wire serial communication interface. Device opera-
tion is controlled by seven instructions issued by the host
processor. A valid instruction starts with a rising edge
of CS and consists of a Start Bit (logic ‘1’) followed by the
appropriate Op Code and the desired memory Address
location.
WRITE (WRITE): The Write (WRITE) instruction contains
the 16 bits of data to be written into the specified memory
location. The self-timed programming cycle tWP starts after
the last bit of data is received at serial data input pin DI.
The DO pin outputs the READY/BUSY status of the part if
CS is brought high after being kept low for a minimum of
250 ns (tCS). A logic ‘0’ at DO indicates that programming is
still in progress. A logic ‘1’ indicates that the memory loca-
tion at the specified address has been written with the data
pattern contained in the instruction and the part is ready for
further instructions. A Ready/Busy Status cannot be
obtained if the CS is brought high after the end of the
READ (READ): The Read (READ) instruction contains
the Address code for the memory location to be read. After
the instruction and address are decoded, data from the
selected memory location is available at the serial output
pin DO. Output data changes are synchronized with the ris-
ing edges of serial clock SK. It should be noted that a
dummy bit (logic ‘0’) precedes the 16-bit data output string.
self-timed programming cycle, tWP
.
ERASE ALL (ERAL): The Erase All (ERAL) instruction
programs every bit in the memory array to the logic ‘1’ state
and is primarily used for testing purposes. The DO pin out-
puts the READY/BUSY status of the part if CS is brought
high after being kept low for a minimum of 250 ns (tCS). The
ERAL instruction is valid only at VCC = 5.0V ± 10%.
ERASE/WRITE (EWEN): To assure data integrity, the
part automatically goes into the Erase/Write Disable
(EWDS) state when power is first applied. An Erase/Write
Enable (EWEN) instruction must be executed first before
any programming instructions can be carried out. Please
note that once in the Erase/Write Enable state, program-
ming remains enabled until an Erase/Write Disable
(EWDS) instruction is executed or VCC power is removed
from the part.
WRITE ALL (WRAL): The Write All (WRAL) instruction
programs all memory locations with the data patterns spec-
ified in the instruction. The DO pin outputs the
READY/BUSY status of the part if CS is brought high after
being kept low for a minimum of 250 ns (tCS). The WRAL
instruction is valid only at VCC = 5.0V ± 10%.
ERASE (ERASE): The Erase (ERASE) instruction pro-
grams all bits in the specified memory location to the logical
‘1’ state. The self-timed erase cycle starts once the ERASE
instruction and address are decoded. The DO pin outputs
the READY/BUSY status of the part if CS is brought high
after being kept low for a minimum of 250 ns (tCS). A logic
‘1’ at pin DO indicates that the selected memory location
has been erased, and the part is ready for another instruc-
tion.
ERASE/WRITE DISABLE (EWDS): To protect against
accidental data disturb, the Erase/Write Disable (EWDS)
instruction disables all programming modes and should be
executed after all programming operations. The operation
of the READ instruction is independent of both the EWEN
and EWDS instructions and can be executed at any time.
5
Timing Diagrams
Synchronous Data Timing
Note:
1. This is the minimum SK period.
AT93C46C
6
AT93C46C
Organization Key for Timing Diagrams
AT93C46C
I/O
AN
DN
x 16
A5
D15
READ Timing
tCS
CS
SK
DI
...
AN
1
1
0
A0
0
DN ...
D0
DO
EWEN Timing(1)
Note:
1. Requires a minimum of nine clock cycles.
EWDS Timing(1)
Note:
1. Requires a minimum of nine clock cycles.
7
WRITE Timing
WRAL Timing(1)(2)
Notes: 1. Valid only at VCC = 4.5V to 5.5V.
2. Requires a minimum of nine clock cycles.
AT93C46C
8
AT93C46C
ERASE Timing
TERAL Timing(1)
Note:
1. Valid only at VCC = 4.5V to 5.5V.
9
Ordering Information
tWP (max)
ICC (max)
ISB (max)
fMAX
(ms)
(µA)
(µA)
(kHz)
Ordering Code
Package
Operation Range
10
10
10
10
10
10
2000
2000
800
50.0
50.0
20.0
20.0
20.0
20.0
2000
2000
1000
1000
500
AT93C46C-10PC
AT93C46C-10SC
8P3
8S1
Commercial
(0°C to 70°C)
AT93C46C-10PI
AT93C46C-10SI
8P3
8S1
Industrial
(-40°C to 85°C)
AT93C46C-10PC-2.7
AT93C46C-10SC-2.7
8P3
8S1
Commercial
(0°C to 70°C)
800
AT93C46C-10PI-2.7
AT93C46C-10SI-2.7
8P3
8S1
Industrial
(-40°C to 85°C)
600
AT93C46C-10PC-2.5
AT93C46C-10SC-2.5
8P3
8S1
Commercial
(0°C to 70°C)
600
500
AT93C46C-10PI-2.5
AT93C46C-10SI-2.5
8P3
8S1
Industrial
(-40°C to 85°C)
Package Type
8P3
8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-Lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
Options
8S1
Blank
-2.7
Standard Device (4.5V to 5.5V)
Low Voltage (2.7V to 5.5V)
-2.5
Low Voltage (2.5V to 5.5V)
AT93C46C
10
AT93C46C
Packaging Information
8P3, 8-Lead, 0.300" Wide, Plastic Dual Inline
Package (PDIP)
8S1, 8-Lead, 0.150" Wide, Plastic Gull Wing Small
Outline (JEDEC SOIC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-001 BA
Dimensions in Inches and (Millimeters)
.400 (10.16)
.355 (9.02)
.020 (.508)
.013 (.330)
PIN
1
.244 (6.20)
.228 (5.79)
.157 (3.99)
.150 (3.81)
.280 (7.11)
.240 (6.10)
PIN 1
.037 (.940)
.027 (.690)
.300 (7.62) REF
.210 (5.33) MAX
.050 (1.27) BSC
.100 (2.54) BSC
SEATING
PLANE
.196 (4.98)
.189 (4.80)
.068 (1.73)
.053 (1.35)
.015 (.380) MIN
.150 (3.81)
.115 (2.92)
.022 (.559)
.014 (.356)
.070 (1.78)
.045 (1.14)
.010 (.254)
.004 (.102)
.325 (8.26)
.300 (7.62)
0
8
0
REF
.010 (.254)
.007 (.203)
REF
15
.012 (.305)
.008 (.203)
.430 (10.9) MAX
.050 (1.27)
.016 (.406)
11
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