AT97SC3201-09MC [ATMEL]
Data Encryption Circuit, CMOS, PQCC40,;
| 型号： | AT97SC3201-09MC |
| 厂家： | 
ATMEL |
| 描述： | Data Encryption Circuit, CMOS, PQCC40, ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总7页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• TCG/TCPA V1.1b Compatible
• Single Chip Turnkey Solution
• Hardware Asymmetric Crypto Engine
• 2048 RSA Sign in 500 ms
• AVR 8-bit RISC Microprocessor
• Internal EEPROM Storage for RSA Keys
• 33 MHz LPC (Low Pin Count) Bus for Easy PC Interface
• Secure Hardware and Firmware Design
• True Random Number Generator (RNG)
• Secure Real-time Clock Option
• 3.3V 10% Supply Voltage
• 28-lead TSSOP Package or 40-lead QFN Package
• 0–70°C Temperature Range
Trusted
Platform
Module
Description
The AT97SC3201 is a fully integrated security module designed to be integrated into
personal computers and other embedded systems. It implements version 1.1b of the
Trusted Computing Platform Alliance (TCPA) specification for Trusted Platform
Modules (TPM). This specification has been adopted by the Trusted Computing Group
(TCG).
AT97SC3201
Summary
The TPM includes a crypto accelerator capable of computing a 2048-bit RSA
signature in 500 ms and a 1024-bit RSA signature in 100 ms. Communication to and
from the TPM occur through a 33-MHz LPC interface.
Figure 1. Pin Configurations
28 pin TSSOP
9.6 mm, 0.65 mm pitch
6.1 mm plastic width
Pin Name Description
1
2
28 LPCPD#
27 SERIRQ
26 LAD0
25 GND
NC
NC
Lreset#
Lframe#
Xtal1
System Reset, Active-low. Input
LPC Frame Indicator
3
NC
4
GND
5
24 3V
SB3V
6
23 LAD1
22 LFRAME#
21 LCLK
20 LAD2
19 3V
32.768 kHz Crystal
GPIO6
NC
7
8
TestI
Xtal2
32.768 kHz Crystal
9
TestBI/BADD
3V
10
11
12
13
14
LAD0–3
GND
LPC Command, Address and Data
Ground
18 GND
GND
17 LAD3
16 LRESET#
15 CLKRUN
VBAT
XtalI/32K in
XtalO
VBB
2.5–4.0V Battery Input
3.3V ( 10%) Supply Voltage
VCC
40 pin QFN
6.0 mm x 6.0 mm
0.50 mm pitch
CLKRUN# Clock Control
SIRQ
Lclk
Serial IRQ Line
33-MHz PCI Clock
Input/Output A
NC
GND
SB3V
GPIO6
NC
TestI
1
30 LAD0
29 GND
28 3V
27 LAD1
26 LFRAME#
25 LCLK
24 LAD2
23 3V
2
3
4
5
6
7
8
9
IOA
TestBI/BADD
3V
IOB
Input/Output B
GND
VBAT 10
22 GND
21 LAD3
IOC
Input/Output C
Xtamper
External Tamper Detect
Rev. 2015ES-TPM–05/05
Note: This is a summary document. A complete document is
available under NDA. For more information, please contact your
local Atmel sales office.
Figure 2. AT97SC3201 Block Diagram
ROM
Program
EEPROM
Program
AVR
8/16 Bit
CPU
33 MHz
LPC
Interface
SRAM
EEPROM
Data
IOA
IOB
GPIO
IOC
VBB
RNG
CRYPTO
Engine
RTC
32.768 kHz
Timer
Physical
Security
Circuitry
The chip includes a full hardware random number generator that is used for the TCG protocol
and is also available to the system for any random numbers it may need during normal
operation.
A real-time clock function is available using an external battery and crystal. The chip provides
tamper detection if the battery or crystal are removed or tampered with, and the current time
value can be signed by the appropriate internal keys to verify its accuracy. (Contact Atmel for
current status of this option.)
The battery detector can be used without the crystal for lower cost. In this mode, the TPM can
indicate to the system if it has been removed from the PC in any way and can also take
actions internally.
The chip uses a dynamic internal memory management scheme to store from 10 to 20 keys.
Other than the standard TCG commands (TPM_Evictkey, TPM_Loadkey), no system inter-
vention is required to manage this internal key cache.
The TPM is offered to OEM manufacturers as a turnkey solution, including the firmware inte-
grated on the chip. In addition, Atmel provides the necessary driver software for integration
into certain operating systems, along with BIOS drivers. A TCG Software Stack (TSS), also
supplied by Atmel and available under license, provides communication support to any appli-
cation using MSCAPI or PKCS #11 Cryptographic APIs. (Contact Atmel for a complete list of
operating systems supported.)
Full documentation for TCG primitives can be found on the TCG Web site,
www.trustedcomputinggroup.org. This specification includes only mechanical and electrical
information.
2
AT97SC3201
2015ES-TPM–05/05
AT97SC3201
Absolute Maximum Ratings
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only
and functional operation of the device at these or
any other conditions beyond those indicated in
the operational sections of this specification may
cause temporary or permanent failure. Exposure
to absolute maximum rating conditions for
extended periods may affect device reliability.
Operating Temperature..............................0°C to +70°C
Storage Temperature (without Bias)...........0°C to + 70°C
Voltage on I/O Pins..............................−0.1 to VCC +0.3V
Voltage on VCC with Respect to Ground.................6.0V
Maximum ESD Voltage..........................................2000V
Table 1. DC Parameters*
Symbol Parameter
Min
Nom
Max
3.6
50
Units
V
Notes
VCC
ICC
IST
Supply Voltage
3.0
3.3
25
5
Operating Current at fclk = 33 MHz
Static Current
mA
mA
10
VCC = 3.6V; fxtal = 0 Hz,
active inputs
ISL
Sleep Current, Chip Idle
Battery Current
40
2
100
µA
µA
µA
V
VCC = 3.6V; fxtal = 0 Hz
VCC = 0V; fxtal = 0 Hz
Vin = VCC or GND
IBB
4
ILIO
VIH
VIL
Input Leakage
0.1
3
Input High Threshold
Input Low Threshold
Output High Voltage
Output Low Voltage
Output Low Current, CLKRUN#
Input Pin Capacitance
0.5 * VCC
−0.5
VCC + 0.5
0.3 * VCC
V
VOH
VOL
IOLCR
CI
0.9 * VCC
0.98 * VCC
V
At IOUT = −500 uA
At IOUT = 1.5mA
At VOUT = .615 * VCC
Note 1
0.1 * VCC
V
7
mA
pF
6
* VCC = 3.0 to 3.6V; Temperature = 0 to 70°C
Note: 1. These parameters guaranteed by design.
3
2015ES-TPM–05/05
Table 2. AC Parameters*
Symbol Parameter
Min
Nom
Max
Units
Notes
TVAL
CLK to Signal Valid Delay – LAD0-3
2
5
11
ns
Measured at Vtrise = 0.285 * VCC and Vtfal =
0.615 * VCC. Measured from clk at Vtest = 0.4
* VCC; Load = 200Ω
TON
Float to Active Delay
2
4
ns
ns
ns
ns
ms
m
TOFF
Active to Float Delay
28
TSU
Input Setup Time to CLK
Input Hold Time from CLK
Reset Active Time after Power Stable
Reset Active after CLK Stable
Reset Active to Output Float Delay
CLK Period
7
0
2
TH
−500
TRST
1
Note 2
TRST-CLK
TRST-OFF
TCLKIN
TCLKLO
TCLKHI
100
Note 2
40
31
18
18
ns
ns
ns
ns
Note 2
29.5
13.4
13.4
30
Note 3
CLK Low Duration
Note 1, Note 3
Note 1, Note 3
CLK High Duration
* Cl = 10pf. VCC = 3.0 to 3.7V; Temperature = 0 to 70°C
Note:
1. All parameters measured with respect to signal crossing Vtest = 0.4 * VCC unless otherwise noted.
2. These parameters guaranteed by design.
3. The minimum parameter must never be violated under any circumstances unless Ireset# is asserted. If proper CLKRUN#
signaling is observed, the maximum specification can be violated.
Table 3. Ordering Information
Ordering Code(1)
Package
Operation Range
AT97SC3201-09AC
28A3 (TSSOP)
28A3 (TSSOP)
40ML1 (QFN)
40ML1 (QFN)
Commercial (0° to 70° C)
Commercial (0° to 70° C)
Commercial (0° to 70° C)
Commercial (0° to 70° C)
AT97SC3201-X9AC
AT97SC3201-09MC
AT97SC3201-X9MC
lead-free(2)
lead-free(2)
Note:
1. Current as of time of publication. Contact Atmel Marketing for possible updated options.
2. Also RoHS
4
AT97SC3201
2015ES-TPM–05/05
AT97SC3201
Package Drawing
28A3 – TSSOP
b
L
L1
E1
E
e
End View
Top View
COMMON DIMENSIONS
(Unit of Measure = mm)
D
MIN
MAX
NOM
9.70
NOTE
SYMBOL
A2
A
D
9.60
9.80
2, 5
E
8.10 BSC
6.10
E1
A
6.00
–
6.20
1.20
1.05
0.30
3, 5
4
Side View
–
A2
b
0.80
0.19
1.00
–
e
0.65 BSC
0.60
L
0.45
0.75
L1
1.00 REF
Notes: 1. This drawing is for general information only. Please refer to JEDEC Drawing MO-153, Variation DB for additional information.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in)
per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b
dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
1/8/02
DRAWING NO.
28A3
TITLE
REV.
2325 Orchard Parkway
San Jose, CA 95131
28A3, 28-lead, 6.1 x 9.7 mm Body, 0.65 pitch,
Thin Shrink Small Outline Package (TSSOP)
A
R
5
2015ES-TPM–05/05
40ML1 - QFN
A
A1
A3
D
N
A2
1
2
3
Pin 1 Indicator
E
Top View
L
0
Side View
COMMON DIMENSIONS
(Unit of Measure = mm)
D2
MIN
MAX
NOM
6.00 BSC
6.00 BSC
4.10
NOTE
SYMBOL
D
E2
E
D2
E2
A
3.95
3.95
-
4.25
4.25
0.90
0.05
0.70
1
4.10
2
0.85
b
3
A1
A2
A3
L
0.0
-
0.01
0.65
N
0.20 REF
0.40
e
0.30
0.18
0.50
0.30
e
0.50 BSC
0.23
PIN1 ID
b
2
Bottom View
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-220, Variation WJJD-2, for proper dimensions,
tolerances, datums, etc.
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
3/9/04
DRAWING NO. REV.
40ML1
TITLE
2325 Orchard Parkway
San Jose, CA 95131
40ML1, 40-lead 6.0 x 6.0 mm Body, 0.50 mm Pitch, Molded Quad
Flat No Lead Package (MLF2)
A
R
6
AT97SC3201
2015ES-TPM–05/05
Atmel Corporation
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Printed on recycled paper.
2015ES-TPM–05/05
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