AT97SC3203S-X11AC [ATMEL]
RISC Microcontroller, 8-Bit, EEPROM, 33MHz, CMOS, PDSO28, 9.70 X 6.10 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153DB, TSSOP-28;
| 型号： | AT97SC3203S-X11AC |
| 厂家： | 
ATMEL |
| 描述： | RISC Microcontroller, 8-Bit, EEPROM, 33MHz, CMOS, PDSO28, 9.70 X 6.10 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153DB, TSSOP-28 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 微控制器 光电二极管 |
| 文件： | 总11页 (文件大小：197K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Full TCG V1.2 Compatibility
• Single-chip Turnkey Solution
• Hardware Asymmetric Crypto Engine
• 2048 RSA Sign in 500 ms
• AVR® RISC Microprocessor
• Internal EEPROM Storage for RSA Keys
• 100 KHz System Management Bus (SMBus) Two-wire Interface
• Secure Hardware and Firmware Design and Chip Layout
• True Random Number Generator (RNG)
• Secure Real-time Clock Option
• 3.3V 10% Supply Voltage
• 28-lead TSSOP Package or 40-lead QFN Package
• 0–70°C Temperature Range
Trusted
Platform
Module
Description
The AT97SC3203S is a fully integrated security module designed to be integrated into
embedded systems. It implements version 1.2 of the Trusted Computing Group (TCG)
specification for Trusted Platform Modules (TPM).
AT97SC3203S
for
SMBus protocol
28-lead TSSOP
Figure 1. Pin Configurations
SMBDAT
SMBCLK
NC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
2
NC
Pin Name
XtalI/32K in
XtalO
Description
3
NC
GND
4
GND
3V
SB3V
GPIO6
NC
5
32.768 kHz Crystal Input
32.768 kHz Crystal Output
Ground
6
NC
7
NC
TestI
8
AVRCLK
NC
TestBI
3V
9
10
11
12
13
14
3V
GND
GND
GND
NC
VBAT
Xtall/32K in
XtalO
NC
Summary
VBAT
2.5–4.0V Battery Input
3.3V ( 10%) Supply Voltage
33-MHz AVR Clock Input
SMBus Data Input/Output
SMBus Clock Input
NC
VCC
40-lead QFN
AVR clk
SMBDAT
SMBCLK
GPIO6
NC
40 39 38 37 36 35 34 33 32 31
NC
GND
SB3V
GPIO6
NC
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
NC
GND
3V
General Purpose Input/Output
No Connect
NC
NC
TestI
AVRclk
NC
TestBI
3V
TestI
Test Input (disabled)
Test Input (disabled)
Standby 3V
3V
GND
VBAT
GND
NC
TestBI
SB3V
11 12 13 14 15 16 17 18 19 20
5132AS–TPM–8/05
Note: This is a summary document. A complete document
is available under NDA. For more information, please con-
tact your local Atmel sales office.
The TPM includes a crypto accelerator capable of computing a 2048-bit RSA signature in 500 ms and a 1024-bit RSA sig-
nature in 100 ms. Communication to and from the TPM occurs through a modified 100-KHz SMBus two-wire interface.
Figure 2. AT97SC3203S Block Diagram
ROM
Program
EEPROM
Program
AVR
8 Bit
CPU
33 MHz
AVR
Clock Input
SRAM
EEPROM
Data
SMBDAT
SMBCLK
GPIO6
SMBus Interface
or GPIO
RNG
CRYPTO
Engine
VBB
32.768 kHz
RTC
Timer
Physical
Security
Circuitry
The chip includes a hardware random number generator that is used for the TCG proto-
col and is also available to the system for generation of random numbers it may need
during normal operation.
The chip uses a dynamic internal memory management scheme to store RSA key pairs.
Other than the standard TCG commands (TPM_Evictkey, TPM_Loadkey), no system
intervention is required to manage this internal key cache.
Full documentation for TCG primitives can be found on the TCG Web site located at
www.trustedcomputinggroup.org. This specification includes only mechanical, electrical
and SMBus protocol information.
2
AT97SC3203S
5132AS–TPM–8/05
AT97SC3203S
Table 1. Pin Descriptions
Pin
Description
VCC
Power supply, 3.3V 10%. The chip should be bypassed with a suitable capacitor located close to the pin. A low power
state is automatically entered when the chip is idle. No further action is required by the system.
GND
VBAT
Ground
Battery input. This pin may optionally be connected to an external battery. VBAT serves two functions. If the primary
VCC power supply drops below the threshold voltage (approximately 3V), the internal power detection latch will switch
from VCC to VBAT. In addition, the TPM battery-detection security function can be enabled to detect removal of the TPM.
The chip includes an on-board latch powered by VBAT that can be read and written under the appropriate
circumstances and can be used to detect the removal of the chip from a system. For non-PC battery-powered
applications, it is recommended that VBAT be tied to ground.
SB3V
Standby 3.3V Supply. If no separate standby power supply is connected to this pin, the pin should be tied directly to
the 3V power supply pin.
AVRclk
33-MHz clock used to drive the internal AVR microprocessor.
This pin serves as the SMBus Data Input/Output for the TPM.
This pin serves as the SMBus Clock Input to the TPM.
SMBDAT
SMBCLK
GPIO6
General Purpose Input/Output. Internal pull-up resistor. This pin is mapped to NV Index TPM_NV_INDEX_GPIO_00
and serves as the GPIO-Express-00. Default TPM configuration: GPIO Input. GPIO6 also serves as the XOR chain
Output during I/O test mode.
XtalI/32K in
XtalO
32.768 kHz crystal connection. The chip includes an optional real-time clock that may be controlled with a crystal
connected across these pads. The crystal is powered by VBB or VCC, whichever is higher. No additional external
components are required. The chip includes an internal security detector that can detect loss of power or extreme
changes in the clock frequency. If the real-time clock function is not used, Xtal1 should be connected to ground, and
Xtal2 should be left floating.
NC
No connect pins should be connected through a resistor to VCC to reduce standby current. This is most easily
accomplished by shorting all NC pins together and connecting through a single resistor toVCC
.
TestBI
TestI
TestBI and TestI functions are disabled after completing Atmel production tests. These pins should be connected
through a resistor toVCC
.
3
5132AS–TPM–8/05
Design
Considerations
While the electrical design of a board containing the AT97SC3203S is straightforward, a
number of design decisions must be made.
VCC
The chip is powered from an external 3.3V supply that should be bypassed with a high-
quality bypass capacitor having a value of no less than 0.1µF and located in close prox-
imity to the pins. Care should be taken to prevent excessive noise on VCC and the
SMBus interface pins.
VBAT
There is a block of low current circuitry on the chip that includes a power detection latch,
external tamper latch and real-time clock. When VCC is above approximately 3.0V, this
block is powered by VCC; otherwise, it is powered by VBAT
.
The power detection latch can be used as a tamper-detection security function to deter-
mine if power (both VBAT and VDD) is removed from the chip. The system must initialize
the power detection latch. Subsequently, the latch may be queried in software to deter-
mine if power has been removed, which would indicate tampering with the TPM. If the
TPM_TakeOwnership command is executed when VCC = 3.3V and VBAT = 0V, then no
internal actions will occur until the next TPM_TakeOwnership command is executed.
This feature can be permanently disabled; see the Atmel-specific commands document
for more details.
RTC
When VCC is above 3.0V, negligible current is consumed from VBAT. The optional real-
time clock consumes current from the VBAT pin that is in addition to that specified
through the IBAT specification (see Table 2 on page 6).
AVRclk
A 33-MHz clock input on this pin is required for the internal AVR processor. The TPM
contains circuitry to detect attacks on the TPM security. This circuitry will disable the
TPM operation if the AVRclk input frequency exceeds approximately 33.9 MHz or drops
below 32.2 MHz.
SMBCLK
Processing of SMBus command inputs by the AVR occurs during SMBCLK clock low
period. For this reason the SMBCLK duty cycle must guarantee a low period of at least 5
µseconds. Reduction of the clock low period below 5 µseconds will result in failure of the
TPM.
4
AT97SC3203S
5132AS–TPM–8/05
AT97SC3203S
SMBus Operation
Summary
The AT97SC3203S implements a modified SMBus protocol as defined by the System
Management Bus Specification, Version 2.0 (http://www.smbus.org/specs). Basic
SMBus operation and exceptions to the published specification are outlined below.
SMBus is a two-wire communication protocol. The system clock must be provided by
the system master host processor to the TPM SMBCLK input pin. SMBDAT is a bidirec-
tional I/O port. Data will be driven alternately by the system host and by the TPM. A 33-
MHz clock must also be provided by the system to the AVR CLK pin to enable operation
of the internal AVR microprocessor.
Figure 3. SMBus Topology
AVR CLK
33 MHz
VCC = 3.3V
VCC = 3.3V
VBB
AT97SC3203S
SMBus Master
Rp
TPM
SMBCLK
SMBDAT
5
5132AS–TPM–8/05
Absolute Maximum Ratings
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only
and functional operation of the device at these or
any other conditions beyond those indicated in
the operational sections of this specification may
cause temporary or permanent failure. Exposure
to absolute maximum rating conditions for
extended periods may affect device reliability.
Operating Temperature..............................0°C to +70°C
Storage Temperature (without Bias)...........0°C to + 70°C
Voltage on I/O Pins..............................−0.1 to VCC +0.3V
Voltage on VCC with Respect to Ground.................6.0V
Maximum ESD Voltage..........................................2000V
Table 2. DC Parameters (VCC = 3.0 to 3.6V; Temperature = 0 to 70°C)
Symbol Parameter
Min
Nom
3.3
25
Max
3.6
50
Units
V
Notes
VCC
ICC
IST
Supply Voltage
3.0
Operating Current at fclk = 33 MHz
Static Current
mA
mA
5
10
VCC = 3.6V; fxtal = 0 Hz,
active inputs
ISL
IBB
Sleep Current, Chip Idle
Battery Current
40
2
100
µA
µA
µA
V
VCC = 3.6V; fxtal = 0 Hz
VCC = 0V; fxtal = 0 Hz.
Vin = VCC or GND
4
ILIO
VIH
Input Leakage
0.1
3
Input High Threshold
Input Low Threshold
Output High Voltage
Output Low Voltage
Input Pin Capacitance
0.5 * VCC
−0.5
VCC + 0.5
0.3 * VCC
VIL
V
VOH
VOL
CI
0.9 * VCC
0.98 * VCC
V
At IOUT = −500 uA
At IOUT = 1.5mA
Note 1
0.1 * VCC
V
6
pF
Note:
1. These parameters guaranteed but not tested.
6
AT97SC3203S
5132AS–TPM–8/05
AT97SC3203S
Table 3. SMBus AC Parameters (VCC = 3.0 to 3.6V; Temperature = 0 to 70°C)
Symbol
fSMB
Parameter
Min
0
Max
Units
KHz
µS
SMBus Operating Frequency, SMBCLK
Clock Pulse Width Low, SMBCLK
Clock Pulse Width High, SMBCLK
Data Out Hold Time
100
8.0
5.0
tLOW
5.0
2.0
100
1.0
1.0
1.0
500
100
tHIGH
tDH
µS
µS
tAA
Clock Low to Data Out Valid
Start Hold Time
µS
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
µS
Start Set-up Time
µS
Data Hold Time
µS
Data Set-up Time
nS
Inputs Rise Time1
1.0
µS
tF
Inputs Fall Time1
300
nS
tPOR
Time in which a device must be operational after Power-
on-Reset
500
ms
fAVR
AVRclk Frequency
32.3
33.9
MHz
Note:
1. These parameters guaranteed but not tested.
7
5132AS–TPM–8/05
Table 4. Ordering Information
Ordering Code
Package
28A3
Operation Range
AT97SC3203S-011AC
AT97SC3203S-X11AC
AT97SC3203S-011MC
AT97SC3203S-X11MC
Commercial (0° to 70° C)
Commercial (0° to 70° C)
Commercial (0° to 70° C)
Commercial (0° to 70° C)
28A3
lead-free
lead-free
40ML1
40ML1
Notes: 1. Correct as of publication date. Contact Atmel Marketing for updates.
2. Also RoHS
8
AT97SC3203S
5132AS–TPM–8/05
AT97SC3203S
Package Drawing
28A3 – TSSOP
b
L
L1
E1
E
e
End View
Top View
COMMON DIMENSIONS
(Unit of Measure = mm)
D
MIN
MAX
NOM
9.70
NOTE
SYMBOL
A2
A
D
9.60
9.80
2, 5
E
8.10 BSC
6.10
E1
A
6.00
–
6.20
1.20
1.05
0.30
3, 5
4
Side View
–
A2
b
0.80
0.19
1.00
–
e
0.65 BSC
0.60
L
0.45
0.75
L1
1.00 REF
Notes: 1. This drawing is for general information only. Please refer to JEDEC Drawing MO-153, Variation DB for additional information.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in)
per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b
dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
1/8/02
DRAWING NO.
28A3
TITLE
REV.
2325 Orchard Parkway
San Jose, CA 95131
28A3, 28-lead, 6.1 x 9.7 mm Body, 0.65 pitch,
Thin Shrink Small Outline Package (TSSOP)
A
R
9
5132AS–TPM–8/05
40ML1
A
A1
A3
D
N
A2
1
2
3
Pin 1 Indicator
E
Top View
L
0
Side View
COMMON DIMENSIONS
(Unit of Measure = mm)
D2
MIN
MAX
NOM
6.00 BSC
6.00 BSC
4.10
NOTE
SYMBOL
D
E2
E
D2
E2
A
3.95
3.95
-
4.25
4.25
0.90
0.05
0.70
1
4.10
2
0.85
b
3
A1
A2
A3
L
0.0
-
0.01
0.65
N
0.20 REF
0.40
e
0.30
0.18
0.50
0.30
e
0.50 BSC
0.23
PIN1 ID
b
2
Bottom View
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-220, Variation WJJD-2, for proper dimensions,
tolerances, datums, etc.
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
3/9/04
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
40ML1, 40-lead 6.0 x 6.0 mm Body, 0.50 mm Pitch, Molded Quad
Flat No Lead Package (MLF2)
40ML1
A
R
10
AT97SC3203S
5132AS–TPM–8/05
Atmel Corporation
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Printed on recycled paper.
5132AS–TPM–8/05
相关型号：
AT97SC3203S-X11MC
RISC Microcontroller, 8-Bit, EEPROM, 33MHz, CMOS, 6 X 6 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-220WJJD-2, MLF2-40
ATMEL
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