ATA3745P3-TGQY [ATMEL]
UHF ASK/FSK Receiver; 超高频ASK / FSK接收器
| 型号： | ATA3745P3-TGQY |
| 厂家： | 
ATMEL |
| 描述： | UHF ASK/FSK Receiver |
| 文件： | 总30页 (文件大小：534K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Supply Voltage 4.5V to 5.5V
• Operating Temperature Range –40°C to +85°C
• Minimal External Circuitry Requirements, No RF Components on the PC Board Except
Matching to the Receiver Antenna
• High Sensitivity, Especially at Low Data Rates
• Sensitivity Reduction Possible Even While Receiving
• Fully Integrated VCO
• Low Power Consumption Due to Configurable Self-polling with a Programmable Time
Frame Check
UHF ASK/FSK
Receiver
• Single-ended RF Input for Easy Matching to λ / 4 Antenna or Printed Antenna on PCB
• Low-cost Solution Due to High Integration Level
• ESD Protection According to MIL-STD 883 (4 KV HBM) Except Pin POUT (2 KV HBM)
• High Image Frequency Suppression Due to 1 MHz IF in Conjunction With a SAW
Front-end Filter. Up to 40 dB is Thereby Achievable With Newer SAWs
• Programmable Output Port for Sensitivity Selection or for Controlling External
Periphery
ATA3745
• Communication to the Microcontroller Possible via a Single, Bi-directional Data Line
• Power Management (Polling) is also Possible by Means of a Separate Pin via the
Microcontroller
1. Description
The ATA3745 is a multi-chip PLL receiver device supplied in an SO20 package. It has
been specially developed for the demands of RF low-cost data transmission systems
with low data rates from 1 kBaud to 10 kBaud in Manchester or Bi-phase code. The
receiver is well-suited to operate with Atmel’s PLL RF transmitter ATA2745. It can be
used in the frequency receiving range of f0 = 310 MHz to 440 MHz for ASK data trans-
mission. All the statements made below refer to 433.92 MHz and 315 MHz
applications.
The main applications of the ATA3745 are in the areas of outside temperature meter-
ing, socket control, garage door openers, consumption metering, light/fan or
air-conditioning control, jalousies, wireless keyboards, and various other consumer
market applications.
4901B–RKE–11/07
Figure 1-1. System Block Diagram
UHF ASK/FSK
UHF ASK/FSK
Remote control transmitter
Remote control receiver
1 Li cell
ATA2745
ATA3745
1 to 3 Micro-
controller
Data
Interf.
Demod
Encoder
ATARx9x
PLL
Keys
Antenna Antenna
XTO
VCO
PLL
XTO
Power
amp.
LNA
VCO
Figure 1-2. Block Diagram
VS
ASK
Dem_out
50 kΩ
Demodulator
and Data Filter
CDEM
DATA
AVCC
RSSI
Limiter out
ENABLE
Sensitivity
reduction
IF Amp
Polling circuit
and
control logic
TEST
POUT
MODE
AGND
DGND
4th Order
FE
CLK
DVCC
Standby
Logic
LPF
3 MHz
MIXVCC
LNAGND
LFGND
LFVCC
IF Amp
LPF
3 MHz
VCO
XTO
XTO
LF
f
LNA_IN
LNA
:64
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ATA3745
2. Pin Configuration
Figure 2-1. Pinning SO20
NC
ASK
1
20
19
18
17
16
15
14
13
12
11
DATA
2
ENABLE
TEST
POUT
MODE
DVCC
XTO
CDEM
AVCC
3
4
AGND
DGND
MIXVCC
LNAGND
LNA_IN
NC
5
6
7
8
LFGND
LF
9
10
LFVCC
Table 2-1.
Pin Description
Pin
1
Symbol
NC
Function
Not connected
ASK high
2
ASK
3
CDEM
AVCC
AGND
DGND
MIXVCC
LNAGND
LNA_IN
NC
Lower cut-off frequency data filter
Analog power supply
Analog ground
4
5
6
Digital ground
7
Power supply mixer
High-frequency ground LNA and mixer
RF input
8
9
10
11
12
13
14
15
16
17
18
19
20
Not connected
LFVCC
LF
Power supply VCO
Loop filter
LFGND
XTO
Ground VCO
Crystal oscillator
DVCC
MODE
POUT
TEST
Digital power supply
Selecting 433.92 MHz/315 MHz. Low: 4.90625 MHz (USA), High: 6.76438 MHz (Europe)
Programmable output port
Test pin, during operation at GND
ENABLE
DATA
Enables the polling mode. Low: polling mode off (sleep mode). High: polling mode on (active mode)
Data output/configuration input
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3. RF Front End
The RF front end of the receiver is a heterodyne configuration that converts the input signal
into a 1-MHz IF signal. As shown in the block diagram, the front end consists of an LNA (low
noise amplifier), LO (local oscillator), a mixer and an RF amplifier.
The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO (crystal
oscillator) generates the reference frequency fXTO. The VCO (voltage-controlled oscillator)
generates the drive voltage frequency fLO for the mixer. fLO is dependent on the voltage at pin
LF. fLO is divided by a factor of 64. The divided frequency is compared to fXTO by the phase fre-
quency detector. The current output of the phase frequency detector is connected to a passive
loop filter and thereby generates the control voltage VLF for the VCO. By means of that config-
uration, VLF is controlled such that fLO / 64 is equal to fXTO. If fLO is determined, fXTO can be
calculated using the following formula:
fLO
fXTO = -------
64
The XTO is a one-pin oscillator that operates at the series resonance of the quartz crystal. Fig-
ure 3-1shows the proper layout, with the crystal connected to GND via a capacitor CL. The
value of that capacitor is recommended by the crystal supplier. The value of CL should be opti-
mized for the individual board layout to achieve the exact value of fXTO and thereby of fLO
.
When designing the system in terms of receiving bandwidth, the accuracy of the crystal and
XTO must be considered.
Figure 3-1. PLL Peripherals
V
S
DVCC
XTO
C
L
LFGND
LF
R
820Ω
1
V
S
LFVCC
C
C
10
9
4.7 nF
1 nF
The passive loop filter connected to pin LF is designed for a loop bandwidth of
BLoop = 100 kHz. This value for BLoop exhibits the best possible noise performance of the LO.
Figure 3-1 shows the appropriate loop filter components to achieve the desired loop band-
width. If the filter components are changed for any reason, please note that the maximum
capacitive load at pin LF is limited. If the capacitive load is exceeded, a bit check may no
longer be possible since fLO cannot settle in time before the bit check starts to evaluate the
incoming data stream. Therefore, self polling also does not work in that case.
fLO is determined by the RF input frequency fRF and the IF frequency fIF using the following for-
mula: fLO = fRF – fIF
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ATA3745
To determine fLO, the construction of the IF filter must be considered at this point. The nominal
IF frequency is fIF = 1 MHz. To achieve a good accuracy of the filter’s corner frequencies, the
filter is tuned by the crystal frequency fXTO. This means that there is a fixed relation between fIF
and fLO that depends on the logic level at pin MODE. This is described by the following formu-
las:
fLO
MODE = 0 (USA) fIF = ---------
314
fLO
MODE = 1 (Europe) fIF = -----------------
432.92
The relation is designed to achieve the nominal IF frequency of fIF = 1 MHz for most applica-
tions. For applications where fRF = 315 MHz, the MODE must be set to “0”. In the case of
fRF = 433.92 MHz, the MODE must be set to “1”. For other RF frequencies, fIF is not equal to
1 MHz. fIF is then dependent on the logical level at pin MODE and on fRF. Table 3-1 summa-
rizes the different conditions.
The RF input either from an antenna or from a generator must be transformed to the RF input
pin LNA_IN. The input impedance of that pin is provided in the electrical parameters. The par-
asitic board inductances and capacitances also influence the input matching. The RF receiver
ATA3745 exhibits its highest sensitivity at the best signal-to-noise ratio (SNR) in the LNA.
Hence, noise matching is the best choice for designing the transformation network.
A good practice when designing the network is to start with power matching. From that starting
point, the values of the components can be varied to some extent to achieve the best
sensitivity.
If a SAW is implemented into the input network, a mirror frequency suppression of
∆PRef = 40 dB can be achieved. There are SAWs available that exhibit a notch at ∆f = 2 MHz.
These SAWs work best for an intermediate frequency of IF = 1 MHz. The selectivity of the
receiver is also improved by using a SAW. In typical automotive applications, a SAW is used.
Figure 3-2 on page 6 shows a typical input matching network for fRF = 315 MHz and
fRF = 433.92 MHz using a SAW. Figure 3-3 on page 6 illustrates an input matching to 50Ω
without a SAW. The input matching networks shown in Figure 3-3 on page 6 are the reference
networks for the parameters given in the section “Electrical Characteristics” on page 23.
Table 3-1.
Conditions
Calculation of LO and IF Frequency
Local Oscillator
Frequency
Intermediate Frequency
fIF = 1 MHz
fRF = 315 MHz, MODE = 0
fLO = 314 MHz
fRF = 433.92 MHz, MODE = 1
fLO = 432.92 MHz
fIF = 1 MHz
fRF
300 MHz < fRF < 365 MHz, MODE =
0
fLO = -------------------
fLO
fIF = ---------
314
1
1 + ---------
314
fRF
fLO = ---------------------------
365 MHz < fRF < 450 MHz, MODE =
1
fLO
fIF = -----------------
432.92
1
1 + -----------------
432.92
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Figure 3-2. Input Matching Network With SAW Filter
8
8
9
LNAGND
LNAGND
ATA3745
LNA_IN
ATA3745
9
C
L
C
L
3
3
LNA_IN
25 nH
25 nH
22 pF
47 pF
C
C
C
C
17
16
17
16
100 pF
8.2 pF
® LL2012
100 pF
22 pF
® LL2012
TOKO
fRF = 433.92 MHz
fRF = 315 MHz
L
L
3
3
TOKO
27 nH
47 nH
F27NJ
F47NJ
® LL2012
® LL2012
TOKO
TOKO
F82NJ
RF
RF
IN
F33NJ
IN
1
2
5
6
1
2
5
6
B3555
B3551
IN
OUT
IN
OUT
L
2
L
2
C
C
2
IN_GND
OUT_GND
IN_GND
OUT_GND
2
33 nH
82 nH
CASE_GND
3, 4 7, 8
CASE_GND
8.2 pF
10 pF
3, 4
7, 8
Figure 3-3. Input Matching Network Without SAW Filter
fRF = 433.92 MHz
8
fRF = 315 MHz
8
LNAGND
LNAGND
ATA3745
LNA_IN
ATA3745
9
9
LNA_IN
15 pF
25 nH
33 pF
25 nH
RF
RF
IN
IN
3.3 pF
22 nH
100 pF
3.3 pF
39 nH
100 pF
® LL2012
TOKO
F22NJ
® LL2012
TOKO
F39NJ
Please note that for all coupling conditions (see Figure 3-2 and Figure 3-3), the bond wire
inductivity of the LNA ground is compensated. C3 forms a series resonance circuit together
with the bond wire. L = 25 nH is a feed inductor to establish a DC path. Its value is not critical
but must be large enough not to detune the series resonance circuit. For cost reduction, this
inductor can be easily printed on the PCB. This configuration improves the sensitivity of the
receiver by about 1 dB to 2 dB.
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ATA3745
4. Analog Signal Processing
4.1
IF Amplifier
The signals coming from the RF front end are filtered by the fully integrated 4th-order IF filter.
The IF center frequency is fIF = 1 MHz for applications where fRF = 315 MHz or
f
RF = 433.92 MHz is used. For other RF input frequencies, refer to Table 3-1 on page 5 to
determine the center frequency.
The receiver ATA3745 employs an IF bandwidth of BIF = 600 kHz. This IC can be used
together with the ATA2745. SAW transmitters exhibit much higher transmit frequency toler-
ances compared to PLL transmitters. Generally, it is necessary to use BIF = 600 kHz together
with such transmitters.
4.2
RSSI Amplifier
The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed
into the demodulator. The dynamic range of this amplifier is ∆RRSSI = 60 dB. If the RSSI ampli-
fier is operated within its linear range, the best signal-to-noise ratio (SNR) is maintained in
ASK mode. If the dynamic range is exceeded by the transmitter signal, the SNR is defined by
the ratio of the maximum RSSI output voltage and the RSSI output voltage due to a disturber.
The dynamic range of the RSSI amplifier is exceeded if the RF input signal is about 60 dB
higher compared to the RF input signal at full sensitivity.
Since different RF input networks may exhibit slightly different values for the LNA gain, the
sensitivity values given in the electrical characteristics refer to a specific input matching. This
matching is illustrated in Figure 3-3 on page 6 and exhibits the best possible sensitivity.
4.3
Demodulator and Data Filter
The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK
demodulator.
In ASK mode, an automatic threshold control (ATC) circuit is employed to set the detection ref-
erence voltage to a value where a good SNR is achieved. This circuit also implies the effective
suppression of any kind of in-band noise signals or competing transmitters. If the SNR
exceeds 10 dB, the data signal can be detected properly.
The output signal of the demodulator is filtered by the data filter before it is fed into the digital
signal processing circuit. The data filter improves the SNR as its band-pass can be adapted to
the characteristics of the data signal. The data filter consists of a 1st-order high-pass and a
1st-order low-pass filter.
The high-pass filter cut-off frequency is defined by an external capacitor connected to pin
CDEM. The cut-off frequency of the high-pass filter is defined by the following formula:
1
fcu_DF = ------------------------------------------------------------
2 × π × 30 kΩ× CDEM
In self-polling mode, the data filter must settle very rapidly to achieve a low current consump-
tion. Therefore, CDEM cannot be increased to very high values if self polling is used. On the
other hand, CDEM must be large enough to meet the data filter requirements according to the
data signal. Recommended values for CDEM are given in the section “Electrical Characteris-
tics” on page 23.
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4901B–RKE–11/07
The cut-off frequency of the low-pass filter is defined by the selected baud rate range
(BR_Range). BR_Range is defined in the OPMODE register (refer to “Configuration of the
Receiver” on page 18). BR_Range must be set in accordance to the used baud rate.
The ATA3745 is designed to operate with data encoding where the DC level of the data signal
is 50%. This is valid for Manchester and Bi-phase encoding. If other modulation schemes are
used, the DC level should always remain within the range of VDC_min = 33% and
VDC_max = 66%. The sensitivity may be reduced by up to 1.5 dB in that condition.
Each BR_Range is also defined by a minimum and a maximum edge-to-edge time (tee_sig).
These limits are defined in the section “Electrical Characteristics” on page 23. They should not
be exceeded to maintain full sensitivity of the receiver.
4.4
Receiving Characteristics
The RF receiver ATA3745 can be operated with and without a SAW front end filter. The selec-
tivity with and without a SAW front-end filter is illustrated in Figure 4-1. This example relates to
ASK mode of the ATA3745. Note that the mirror frequency is reduced by 40 dB. The plots are
printed relative to the maximum sensitivity. If a SAW filter is used, an insertion loss of about
4 dB must be considered.
When designing the system in terms of receiving bandwidth, the LO deviation must be consid-
ered as it also determines the IF center frequency. The total LO deviation is calculated to be
the sum of the deviation of the crystal and the XTO deviation of the ATA3745. Low-cost crys-
tals are specified to be within ±100 ppm. The XTO deviation of the ATA3745 is an additional
deviation due to the XTO circuit. This deviation is specified to be ±50 ppm. If a crystal of
±100 ppm is used, the total deviation is ±150 ppm in that case. Note that the receiving band-
width and the IF-filter bandwidth are equivalent in ASK mode.
Figure 4-1. Receiving Frequency Response
0.0
-10.0
-20.0
without SAW
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
with SAW
-90.0
-100.0
-6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0
1.0 2.0 3.0 4.0 5.0 6.0
df (MHz)
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ATA3745
5. Polling Circuit and Control Logic
The receiver is designed to consume less than 1 mA while being sensitive to signals from a
corresponding transmitter. This is achieved via the polling circuit. This circuit enables the sig-
nal path periodically for a short time. During this time, the bit check logic verifies the presence
of a valid transmitter signal. Only if a valid signal is detected does the receiver remain active
and transfer the data to the connected microcontroller. If there is no valid signal present, the
receiver is in sleep mode most of the time, resulting in low current consumption. This condition
is called polling mode. A connected microcontroller is disabled during that time.
All relevant parameters of the polling logic can be configured by the connected microcontrol-
ler. This flexibility enables the user to meet the specifications in terms of current consumption,
system response time, data rate, etc.
Regarding the number of connection wires to the microcontroller, the receiver is very flexible.
It can be either operated by a single bi-directional line to save ports to the connected micro-
controller, or it can be operated by up to three uni-directional ports.
5.1
Basic Clock Cycle of the Digital Circuitry
The complete timing of the digital circuitry and the analog filtering is derived from one clock.
Figure 5-1 shows how this clock cycle TClk is derived from the crystal oscillator (XTO) in com-
bination with a divider. The division factor is controlled by the logical state at pin MODE. As
described in “RF Front End” on page 4, the frequency of the crystal oscillator (fXTO) is defined
by the RF input signal (fRFin) which also defines the operating frequency of the local oscillator
(fLO).
Figure 5-1. Generation of the Basic Clock Cycle
T
CLK
MODE
L: USA (:10)
H: Europe (:14)
Divider
:14/10
16
f
DVCC
XTO
15
XTO
14
XTO
Pin MODE can now be set in accordance with the desired clock cycle TClk. TClk controls the fol-
lowing application-relevant parameters:
• Timing of the polling circuit including bit check
• Timing of analog and digital signal processing
• Timing of register programming
• Frequency of the reset marker
• IF filter center frequency (fIF0
)
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4901B–RKE–11/07
Most applications are dominated by two transmission frequencies: fSend = 315 MHz is mainly
used in the USA, fSend = 433.92 MHz in Europe. In order to ease the usage of all TClk-depen-
dent parameters, the electrical characteristics display three conditions for each parameter.
• USA applications
(fXTO = 4.90625 MHz, MODE = L, TClk = 2.0383 µs)
• European applications
(fXTO = 6.76438 MHz, MODE = H, TClk = 2.0697 µs)
• Other applications
(TClk is dependent on fXTO and on the logical state of pin MODE. The electrical
characteristic is given as a function of TClk).
The clock cycle of some function blocks depends on the selected baud rate range
(BR_Range) which is defined in the OPMODE register. This clock cycle TXClk is defined by the
following formulas for further reference:
BR_Range =
BR_Range0:
BR_Range1:
BR_Range2:
BR_Range3:
TXClk = 8 × TClk
TXClk = 4 × TClk
TXClk = 2 × TClk
TXClk = 1 × TClk
5.2
Polling Mode
According to Figure 3-2 on page 6, the receiver stays in polling mode in a continuous cycle of
three different modes. In sleep mode, the signal processing circuitry is disabled for the time
period TSleep while consuming low current of IS = ISoff. During the start-up period, TStartup, all sig-
nal processing circuits are enabled and settled. In the following bit check mode, the incoming
data stream is analyzed bit by bit looking for a valid transmitter signal. If no valid signal is
present, the receiver is set back to sleep mode after the period TBitcheck. This period varies
check by check as it is a statistical process. An average value for TBitcheck is given in the sec-
tion “Electrical Characteristics” on page 23. During TStartup and TBitcheck the current
consumption is IS = ISon. The average current consumption in polling mode is dependent on
the duty cycle of the active mode and can be calculated as:
I
Soff × TSleep + ISon × (TStartup + TBitcheck
ISpoll = ------------------------------------------------------------------------------------------------------------
Sleep + TStartup + TBitcheck
)
T
During TSleep and TStartup, the receiver is not sensitive to a transmitter signal. To guarantee the
reception of a transmitted command, the transmitter must start the telegram with an adequate
preburst. The required length of the preburst is dependent on the polling parameters TSleep
,
T
Startup, TBitcheck and the startup time of a connected microcontroller (TStart_µC). TBitcheck thus
depends on the actual bit rate and the number of bits (NBitcheck) to be tested.
The following formula indicates how to calculate the preburst length.
TPreburst ≥ TSleep + TStartup + TBitcheck + TStart_µC
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5.2.1
Sleep Mode
The length of period TSleep is defined by the 5-bit word Sleep of the OPMODE register, the
extension factor XSleep described inTable 5-8 on page 20, and the basic clock cycle TClk. It is
calculated to be:
TSleep = Sleep × XSleep × 1024 × TClk
In US and European applications, the maximum value of TSleep is about 60 ms if XSleep is set
to 1. The time resolution is about 2 ms in that case. The sleep time can be extended to almost
half a second by setting XSleep to 8. XSleep can be set to 8 by bit XSleepStd or by bit XSleepTemp
resulting in a different mode of action as described below:
,
X
SleepStd = 1 implies the standard extension factor. The sleep time is always extended.
X
SleepTemp = 1 implies the temporary extension factor. The extended sleep time is used as long
as every bit check is OK. If the bit check fails once, this bit is set back to 0 automatically,
resulting in a regular sleep time. This functionality can be used to save current in presence of
a modulated disturber similar to an expected transmitter signal. The connected microcontroller
is rarely activated in that condition. If the disturber disappears, the receiver switches back to
regular polling and is again sensitive to appropriate transmitter signals.
Table 5-6 on page 19 shows how the highest register value of Sleep sets the receiver to a per-
manent sleep condition. The receiver remains in that condition until another value for Sleep is
programmed into the OPMODE register. This function is desirable where several devices
share a single data line.
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4901B–RKE–11/07
Figure 5-2. Polling Mode Flow Chart
Sleep Mode:
All circuits for signal processing are
disabled. Only XTO and Polling logic are
enabled.
Sleep:
5-bit word defined by Sleep0 to
Sleep4 in OPMODE register
IS = ISON
TSleep = Sleep
× XSleep × 1024 × TClk
XSleep
:
Extension factor defined by
XSleepTemp according to Table 5-7
TClk
:
Basic clock cycle defined by fXTO
and pin MODE
Start-up Mode:
The signal processing circuits are
enabled. After the start-up time (TStartup
all circuits are in stable
)
TStartup
:
Is defined by the selected baud-rate
range and TClk. The baud-rate range
is defined by Baud0 and Baud1 in
the OPMODE register.
condition and ready to receive.
IS = ISON
TStartup
Bit-check Mode:
The incoming data stream is
analyzed. If the timing indicates a valid
transmitter signal, the receiver is set to
receiving mode. Otherwise it is set to
Sleep mode.
XBit-check
:
Depends on the result of the bit check.
If the bit check is ok, TBit-check
depends on the number of bits to be
checked (NBit-check) and on the
utilized data rate.
IS = ISON
TBit-check
If the bit check fails, the average
time period for that check depends
on the selected baud-rate range and
on TClk. The baud-rate range is
defined by Baud0 and Baud1 in the
OPMODE register.
Bit Check
OK ?
NO
YES
Receiving Mode:
The receiver is turned on permanently
and passes the data stream to the
connected microcontroller.
It can be set to Sleep mode through an
OFF command via pin DATA or ENABLE
I
S = ISON
OFF Command
Figure 5-3. Timing Diagram for a Completely Successful Bit Check
Bit check ok
(Number of checked Bits: 3)
Enable IC
Bit check
1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit
Dem_out
Data
Polling mode
Receiving mode
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ATA3745
5.3
Bit Check Mode
In bit check mode, the incoming data stream is examined to distinguish between a valid signal
from a corresponding transmitter and signals due to noise. This is done by subsequent time
frame checks where the distances between 2 signal edges are continuously compared to a
programmable time window. The maximum count of this edge-to-edge test, before the
receiver switches to receiving mode, is also programmable.
5.3.1
Configuring the Bit Check
Assuming a modulation scheme that contains 2 edges per bit, two time frame checks verify
one bit. This is valid for Manchester, Bi-phase and most other modulation schemes. The max-
imum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable NBitcheck in the
OPMODE register. This implies 0, 6, 12 and 18 edge-to-edge checks respectively. If NBitcheck is
set to a higher value, the receiver is less likely to switch to the receiving mode due to noise. In
the presence of a valid transmitter signal, the bit check takes less time if NBitcheck is set to a
lower value. In polling mode, the bit check time is not dependent on NBitcheck. Figure 5-3 on
page 12 shows an example where 3 bits are tested successfully and the data signal is trans-
ferred to pin DATA.
Figure 5-4 shows that the time window for the bit check is defined by two separate time limits.
If the edge-to-edge time tee is in between the lower bit check limit TLim_min and the upper bit
check limit TLim_max, the check will be continued. If tee is smaller than TLim_min or tee exceeds
TLim_max, the bit check will be terminated and the receiver switches to sleep mode.
Figure 5-4. Valid Time Window for Bit Check
1/fSig
Tee
Dem_out
TLim_min
TLim_max
For best noise immunity it is recommended to use a low span between TLim_min and TLim_max
.
This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A
“11111...” or a “10101...” sequence in Manchester or Bi-phase is a good choice in this regard.
A good compromise between receiver sensitivity and susceptibility to noise is a time window of
±25% regarding the expected edge-to-edge time tee. Using preburst patterns that contain vari-
ous edge-to-edge time periods, the bit check limits must be programmed according to the
required span.
The bit check limits are determined by means of the formulas below:
TLim_min = Lim_min × TXClk
TLim_max = (Lim_max – 1) × TXClk
Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.
Using the above formulas, Lim_min and Lim_max can be determined according to the
required TLim_min, TLim_max and TXClk. The time resolution when defining TLim_min and TLim_max is
T
XClk. The minimum edge-to-edge time tee (tDATA_L_min, tDATA_H_min) is defined in Section
“Receiving Mode” on page 15. Due to this, the lower limit should be set to Lim_min ≥ 10. The
maximum value of the upper limit is Lim_max = 63.
13
4901B–RKE–11/07
Figure 5-5, Figure 5-6 and Figure 5-7 illustrate the bit check for the default bit check limits
Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits are
enabled during TStartup. The output of the demodulator (Dem_out) is undefined during that
period. When the bit check becomes active, the bit check counter is clocked with the cycle
TXClk
.
Figure 5-5 shows how the bit check proceeds if the bit-check counter value CV_Lim is within
the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In Figure 5-7,
the bit check fails as the value CV_lim is lower than the limit Lim_min. The bit check also fails
if CV_Lim reaches Lim_max. This is illustrated in Figure 5-8 on page 15.
Figure 5-5. Timing Diagram During Bit Check
Bit check ok
Bit check ok
(Lim_min = 14, Lim_max = 24)
Enable IC
TStartup
Bit check
1/2 Bit
1/2 Bit
1/2 Bit
Dem_out
Bit check
0
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 111213 141516 17 18 1 2 3 4 5 6 7 8 9 10 1112 13 1415 1 2 3 4
counter
TXCLK
Figure 5-6. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)
Bit check failed (CV_Lim_ < Lim_min)
(Lim_min = 14, Lim_max = 24)
Enable IC
Bit check
1/2 Bit
Dem_out
Bit check
0
1
2
3
4
5
6
1
2
3
4
5
6
7
8
9 10 1112
0
counter
Startup mode
Bit check mode
Sleep mode
Figure 5-7. Timing Diagram for Failed Bit Check (Condition: CV_Lim ≥ Lim_max)
(Lim_min = 14, Lim_max = 24)
Bit check failed (CV_Lim_ ≥ Lim_max)
Enable IC
Bit check
1/2 Bit
Dem_out
Bit check
0
counter
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
9 10 111213 1415 16 17 18 19 2021 222324
0
Start up mode
Bit check mode
Sleep mode
14
ATA3745
4901B–RKE–11/07
ATA3745
5.3.2
Duration of the Bit Check
If no transmitter signal is present during the bit check, the output of the demodulator delivers
random signals. The bit check is a statistical process and TBitcheck varies for each check.
Therefore, an average value for TBitcheck is given in the section “Electrical Characteristics” on
page 23. TBitcheck depends on the selected baud rate range and on TClk. A higher baud rate
range causes a lower value for TBitcheck resulting in lower current consumption in polling mode.
In the presence of a valid transmitter signal, TBitcheck is dependant on the frequency of that sig-
nal, fSig and the count of the checked bits, NBitcheck. A higher value for NBitcheck thereby results
in a longer period for TBitcheck requiring a higher value for the transmitter preburst TPreburst
.
5.4
Receiving Mode
If the bit check has been successful for all bits specified by NBitcheck, the receiver switches to
receiving mode. As seen in Figure 5-4 on page 13, the internal data signal is switched to pin
DATA in that case. A connected microcontroller can be woken up by the negative edge at pin
DATA. The receiver stays in that condition until it is switched back to polling mode explicitly.
5.4.1
Digital Signal Processing
The data from the demodulator (Dem_out) is digitally processed in different ways and as a
result converted into the output signal data. This processing depends on the selected baud
rate range (BR_Range). Figure 5-8 illustrates how Dem_out is synchronized by the extended
clock cycle TXClk. This clock is also used for the bit check counter. Data can change its state
only after TXClk elapsed. The edge-to-edge time period tee of the Data signal, as a result, is
always an integral multiple of TXClk
.
The minimum time period between two edges of the data signal is limited to tee ≥ TDATA_min
.
This implies an efficient suppression of spikes at the DATA output. At the same time, it limits
the maximum frequency of edges at DATA. This eases the interrupt handling of a connected
microcontroller. TDATA_min is to some extent affected by the preceding edge-to-edge time inter-
val tee as illustrated in Figure 5-9 on page 16. If tee is in between the specified bit check limits,
the following level is frozen for the time period TDATA_min = tmin1; if tee is outside the bit check
limits, TDATA_min = tmin2 is the relevant stable time period.
The maximum time period for DATA to be low is limited to TDATA_L_max. This function ensures a
finite response time during programming or switching off the receiver via pin DATA.
T
DATA_L_max is thereby longer than the maximum time period indicated by the transmitter data
stream. Figure 5-10 on page 16 gives an example where Dem_out remains low after the
receiver has switched to receiving mode.
Figure 5-8. Synchronization of the Demodulator Output
TXClk
Clock bit check
counter
Dem_out
DATA
tee
15
4901B–RKE–11/07
Figure 5-9. Debouncing of the Demodulator Output
Dem_out
DATA
tmin1
Lim_min ≤ CV_Lim < Lim_max
tee
tmin2
CV_Lim < Lim_min or CV_Lim ≥ Lim_max
tee
Figure 5-10. Steady L State Limited DATA Output Pattern after Transmission
Enable IC
Bit check
Dem_out
DATA
tDATA_L_max
tmin2
Sleep mode
Bit-check mode
Receiving mode
After the end of a data transmission, the receiver remains active and random noise pulses
appear at pin DATA. The edge-to-edge time period tee of the majority of these noise pulses is
equal to or slightly higher than TDATA_min
.
5.4.2
Switching the Receiver Back to Sleep Mode
The receiver can be set back to polling mode via pin DATA or via pin ENABLE.
When using pin DATA, this pin must be pulled to low for the period t1 by the connected micro-
controller. Figure 5-11 on page 17 illustrates the timing of the OFF command (see also Figure
5-15 on page 22). The minimum value of t1 depends on the BR_Range. The maximum value
for t1 is not limited, but it is recommended not to exceed the specified value to prevent erasing
the reset marker. This item is explained in more detail in “Configuration of the Receiver” on
page 18. Setting the receiver to sleep mode via DATA is achieved by programming bit 1 of the
OPMODE register to “1”. Only one synchronous pulse (t3) is issued.
The duration of the OFF command is determined by the sum of t1, t2 and t10. After the OFF
command, the sleep time TSleep elapses. Note that the capacitive load at pin DATA is limited.
The resulting time constant t together with an optional external pull-up resistor should not be
exceeded, to ensure proper operation.
If the receiver is set to polling mode via pin ENABLE, an "L" pulse (TDoze) must be issued at
that pin. Figure 5-12 on page 17 illustrates the timing of that command. After the positive edge
of this pulse, the sleep time TSleep elapses. The receiver remains in sleep mode as long as
ENABLE is held to "L". If the receiver is polled exclusively by a microcontroller, TSleep can be
programmed to “0” to enable an instantaneous response time. This command is the faster
option than via pin DATA, at the cost of an additional connection to the microcontroller.
16
ATA3745
4901B–RKE–11/07
ATA3745
Figure 5-11. Timing Diagram of the OFF Command Via Pin DATA
t1
t2
t3
t5
t4
t10
t7
Out1
(microcontroller)
X
X
X
X
DATA (ATA3745)
Serial bi-directional
data line
Bit 1
("1")
(Start Bit)
Receiving
mode
TSleep
Start-up mode
OFF command
Figure 5-12. Timing Diagram of the OFF Command Via Pin ENABLE
TDoze
TSleep
toff
ENABLE
X
X
X
DATA (ATA3745)
X
Serial bi-directional
data line
Receiving mode
Startup mode
17
4901B–RKE–11/07
5.5
Configuration of the Receiver
The ATA3745 receiver is configured via two 12-bit RAM registers called OPMODE and LIMIT.
The registers can be programmed by means of the bi-directional DATA port. If the register
contents have changed due to a voltage drop, this condition is indicated by a certain output
pattern called reset marker (RM). The receiver must be reprogrammed in that case. After a
power-on reset (POR), the registers are set to default mode. If the receiver is operated in
default mode, there is no need to program the registers.
Table 5-2 shows the structure of the registers. Table 5-1 shows the effect of bit 1 and bit 2 in
programming the registers: bit 1 defines if the receiver is set back to polling mode via the OFF
command (see “Receiving Mode” on page 15), or if it is programmed. Bit 2 represents the reg-
ister address. It selects the appropriate register to be programmed.
Table 5-1.
Effect of Bit 1 and Bit 2 in Programming the Registers
Bit 1
Bit 2
Action
1
0
0
x
1
0
The receiver is set back to polling mode (OFF command)
The OPMODE register is programmed
The LIMIT register is programmed
Table 5-3 on page 19 and the following illustrate the effect of the individual configuration
words. The default configuration is highlighted for each word.
BR_Range sets the appropriate baud rate range. At the same time it defines XLim. XLim is
used to define the bit check limits TLim_min and TLim_max as shown in Table 5-3 on page 19.
POUT can be used to control the sensitivity of the receiver. In that application, POUT is set to
“1” to reduce the sensitivity. This implies that the receiver operates with full sensitivity after a
POR.
Table 5-2.
Effect of the Configuration Words within the Registers
Bit1 Bit2
Bit2
Bit4
Bit5
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Bit12
Bit13
Bit14
OFF Command
1
OPMODE Register
0
0
1
1
BR_Range
NBitcheck
VPOUT
POUT
0
Sleep
Sleep2
0
XSleep
XSleep Std XSleep Temp
Baud1
0
Baud0
0
BitChk1
1
BitChk0
0
Sleep4
0
Sleep3
1
Sleep1
1
Sleep0
1
(Default)
0
0
LIMIT Register
0
0
0
0
Lim_min
Lim_max
Lim_min5 Lim_min4 Lim_min3 Lim_min2 Lim_min1 Lim_min0 Lim_max5 Lim_max4 Lim_max3 Lim_max2 Lim_max1 Lim_max0
(Default)
0
0
1
1
1
0
0
1
1
0
0
0
18
ATA3745
4901B–RKE–11/07
ATA3745
Table 5-3.
Effect of the Configuration Word BR_Range
BR_Range
Baud1
Baud0
Baud Rate Range/Extension Factor for Bit Check Limits (XLim)
BR_Range0 (application USA/Europe: BR_Range0 = 1.0 kBaud to 1.8 kBaud) (Default)
XLim = 8 (Default)
0
0
1
1
0
BR_Range1 (application USA/Europe: BR_Range1 = 1.8 kBaud to 3.2 kBaud)
XLim = 4
1
0
1
BR_Range2 (application USA/Europe: BR_Range2 = 3.2 kBaud to 5.6 kBaud)
XLim = 2
BR_Range3 (application USA/Europe: BR_Range3 = 5.6 kBaud to 10 kBaud)
XLim = 1
Table 5-4.
Effect of the Configuration Word NBitcheck
NBitcheck
BitChk1
BitChk0
Number of Bits to be Checked
0
0
1
1
0
1
0
1
0
3
6 (Default)
9
Table 5-5.
Effect of the Configuration Bit VPOUT
VPOUT
POUT
Level of the Multi-purpose Output Port POUT
0
1
0 (Default)
1
Table 5-6.
Effect of the Configuration Word Sleep
Sleep
Sleep4
Sleep3
Sleep2
Sleep1
Sleep0
Start Value for Sleep Counter (TSleep = Sleep × XSleep × 1024 × TClk)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0 (Receiver is continuously polling until a valid signal occurs)
1 (TSleep ≈ 2 ms for XSleep = 1 in US/European applications)
2
3
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
0
1
0
1
1
11 (USA: TSleep = 22.96 ms, Europe: TSleep = 23.31 ms) (Default)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
29
30
31 (Permanent sleep mode)
19
4901B–RKE–11/07
Table 5-7.
Effect of the Configuration Word XSleep
XSleep
XSleepStd
XSleepTemp
Extension Factor for Sleep Time (TSleep = Sleep × XSleep × 1024 × TClk)
0
0
1
1
0
1
0
1
1 (Default)
8 (XSleep is reset to 1 if bit check fails once)
8 (XSleep is set permanently)
8 (XSleep is set permanently)
Table 5-8.
Effect of the Configuration Word Lim_min
Lim_min
Lower Limit Value for Bit Check
Lim_min < 10 is not applicable
(TLim_min = Lim_min × XLim × TClk)
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
10
11
12
13
14 (Default)
0
0
1
1
1
0
(USA: TLim_min = 228 µs, Europe: TLim_min = 232 µs)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
61
62
63
Table 5-9.
Effect of the Configuration Word Lim_max
Lim_max
Upper Limit Value for Bit Check
Lim_max < 12 is not applicable
(TLim_max = (Lim_max – 1) × XLim × TClk)
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
0
1
0
12
13
14
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
24 (Default)
0
1
1
0
0
0
(USA: TLim_max = 375 µs, Europe: TLim_max = 381 µs)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
61
62
63
20
ATA3745
4901B–RKE–11/07
ATA3745
5.5.1
Conservation of the Register Information
The ATA3745 has integrated power-on reset and brown-out detection circuitry to provide a
mechanism to preserve the RAM register information.
According to Figure 5-13, a power-on reset (POR) is generated if the supply voltage VS drops
below the threshold voltage VThReset. The default parameters are programmed into the config-
uration registers in that condition. Once VS exceeds VThReset, the POR is canceled after the
minimum reset period tRst. A POR is also generated when the supply voltage of the receiver is
turned on.
To indicate that condition, the receiver displays a reset marker (RM) at pin DATA after a reset.
The RM is represented by the fixed frequency fRM at a 50% duty cycle. RM can be canceled
via an "L" pulse t1 at pin DATA. The RM implies the following characteristics:
• fRM is lower than the lowest feasible frequency of a data signal. By this means, RM cannot
be misinterpreted by the connected microcontroller.
• If the receiver is set back to polling mode via pin DATA, RM cannot be canceled by accident
if t1 is applied according to the proposal in “Programming the Configuration Register” on
page 22.
By means of that mechanism, the receiver cannot lose its register information without commu-
nicating that condition via the reset marker RM.
Figure 5-13. Generation of the Power-on Reset
VS
VThreset
POR
tRst
X
DATA (ATA3745)
1/fRM
Figure 5-14. Timing of the Register Programming
t1
t2
t3
t5
t9
t8
TSleep
t4
t6
t7
Out1
(microcontroller)
X
X
X
X
DATA (ATA3745)
Serial bi-directional
data line
Bit 1
("0")
Bit 2
("1")
Bit 13
("0")
Bit 14
("1")
(Start bit)
(Register
select)
(Poll 8)
(Poll 8R)
Receiving
mode
Start-up
mode
Programming frame
21
4901B–RKE–11/07
5.5.2
Programming the Configuration Register
The configuration registers are programmed serially via the bi-directional data line according
to Figure 5-14 on page 21 and Figure 5-15.
Figure 5-15. One-wire Connection to a Microcontroller
ATA3745
Microcontroller
Internal pull-up
resistor
Bi-directional
data line
DATA
I/O
DATA
Out1 (microcontroller)
(ATA3745)
To start programming, the serial data line DATA is pulled by the microcontroller to “L” for the
time period t1. When DATA has been released, the receiver becomes the master device.
When the programming delay period t2 has elapsed, it emits 14 subsequent synchronization
pulses with the pulse length t3. After each of these pulses, a programming window occurs.
The delay until the program window starts is determined by t4, the duration is defined by t5.
Within the programming window, the individual bits are set. If the microcontroller pulls down
pin DATA for the time period t7 during t5, the corresponding bit is set to “0”. If no programming
pulse t7 is issued, this bit is set to “1”. All 14 bits are subsequently programmed in this way.
The time frame to program a bit is defined by t6.
Bit 14 is followed by the equivalent time window t9. During this window, the equivalent
acknowledge pulse t8 (E_Ack) occurs if the mode word just programmed is equivalent to the
mode word that was already stored in that register. E_Ack should be used to verify that the
mode word was correctly transferred to the register. The register must be programmed twice
in that case.
Programming of a register is possible both during sleep and active mode of the receiver. Dur-
ing programming, the LNA, LO, low-pass filter, IF amplifier and the demodulator are disabled.
The programming start pulse t1 initiates the programming of the configuration registers. If bit 1
is set to “1”, it represents the OFF command, setting the receiver back to polling mode at the
same time. For the length of the programming start pulse t1, the following convention should
be considered:
• t1(min) < t1 < 1535 × TClk: [t1(min) is the minimum specified value for the relevant
BR_Range]
Programming (or the OFF command) is initiated if the receiver is not in reset mode. If the
receiver is in reset mode, programming (or the OFF command) is not initiated, and the reset
marker RM is still present at pin DATA. This period is generally used to switch the receiver to
polling mode. In a reset condition, RM is not canceled by accident.
• t1 > 5632 × TClk
Programming (or the OFF command) is initiated in any case. RM is cancelled if present. This
period is used if the connected microcontroller detected RM. If a configuration register is pro-
grammed, this time period for t1 can generally be used. Note that the capacitive load at pin
DATA is limited. The resulting time constant t together with an optional external pull-up resistor
may not be exceeded to ensure proper operation.
22
ATA3745
4901B–RKE–11/07
ATA3745
6. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
VS
Min.
Max.
6
Unit
V
Supply voltage
Power dissipation
Ptot
450
150
+125
+85
10
mW
°C
Junction temperature
Storage temperature
Ambient temperature
Maximum input level, input matched to 50Ω
Tj
Tstg
–55
–40
°C
Tamb
Pin_max
°C
dBm
7. Thermal Resistance
Parameters
Symbol
Value
Unit
Junction ambient
RthJA
100
K/W
8. Electrical Characteristics
All parameters refer to GND, VS = 5V, Tamb = 25°C, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. The possible operating
range refer to different circuit conditions: VS = 4.5V to 5.5V, Tamb = –40°C to +85°C
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Sleep mode
(XTO and polling logic active)
ISoff
190
350
µA
Current consumption
IC active
(startup, bit check, or receiving mode)
Pin DATA = H
ISon
7.0
8.6
mA
LNA Mixer
LNA/mixer/IF amplifier
input matched according to Figure 3-3
on page 6
Third-order intercept point
IIP3
–28
dBm
Input matched according to Figure 3-3
on page 6, required according to
I-ETS 300220
LO spurious emission at RFIn
ISLORF
–73
7
–57
dBm
dB
Input matching according to Figure
3-3 on page 6
Noise figure LNA and mixer (DSB)
LNA_IN input impedance
NF
at 433.92 MHz
at 315 MHz
1.0 || 1.56
1.3 || 1.0
kΩ || pF
kΩ || pF
ZiLNA_IN
IP1db
1 dB compression point (LNA, mixer, Input matched according to Figure 3-3
–40
dBm
dBm
IF amplifier)
on page 6, referred to RFin
Input matched according to Figure 3-3
Maximum input level
Pin_max
–23
on page 6, BER ≤ 10-3, ASK mode
23
4901B–RKE–11/07
8. Electrical Characteristics (Continued)
All parameters refer to GND, VS = 5V, Tamb = 25°C, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. The possible operating
range refer to different circuit conditions: VS = 4.5V to 5.5V, Tamb = –40°C to +85°C
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Local Oscillator
Operating frequency range VCO
fVCO
309
439
MHz
For best LO noise
(design parameter)
R1 = 820Ω
C9 = 4.7 nF
C10 = 1 nF
Loop bandwidth of the PLL
Capacitive load at pin LF
BLoop
100
kHz
nF
The capacitive load at pin LF is limited
if bit check is used. The limitation
therefore also applies to self polling.
CLF_tot
10
XTO crystal frequency,
appropriate load capacitance must be
connected to XTAL
XTO operating frequency
6.764375 MHz
fXTO
6.764375
–50 ppm
4.90625
–50 ppm
6.764375 MHz
+50 ppm
6.764375
4.90625
4.90625 MHz
4.90625
+50 ppm
MHz
Series resonance resistor of the
crystal
fXTO = 6.764 MHz
4.906 MHz
150
220
Ω
Ω
RS
Static capacitance at pin XT0
CXT0
6.5
pF
Analog Signal Processing
Input matched according to Figure 5-1
ASK (level of carrier)
BER ≤ 10-3, B = 600 kHz
fin = 433.92 MHz/315 MHz
T = 25°C, VS = 5V
PRef_ASK
fIF = 1 MHz
Input sensitivity ASK 600-kHz IF filter
BR_Range0
BR_Range1
BR_Range2
BR_Range3
–106
–104.5
–104
–110
–108.5
–108
–113.5
–112
dBm
dBm
dBm
dBm
–111.5
–109.5
–102
–106
600-kHz version
Sensitivity variation ASK for full
operating range including IF filter
compared to Tamb = 25°C, VS = 5V
fin = 433.92 MHz/315 MHz
fIF = 0.81 MHz to 1.19 MHz
∆PRef
+3
+5
dB
dB
f
IF = 0.75 MHz to 1.25 MHz
PASK = PRef_ASK + ∆PRef
SNR to suppress in-band noise
signals
ASK mode
SNRASK
11
60
dB
dB
Dynamic range RSSI ampl.
∆RRSSI
1
fcu_DF = -----------------------------------------------------------
Lower cut-off frequency of the data
filter
2 × π × 30kΩ× CDEM
fcu_DF
0.11
0.16
0.20
kHz
CDEM = 33 nF
24
ATA3745
4901B–RKE–11/07
ATA3745
8. Electrical Characteristics (Continued)
All parameters refer to GND, VS = 5V, Tamb = 25°C, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. The possible operating
range refer to different circuit conditions: VS = 4.5V to 5.5V, Tamb = –40°C to +85°C
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
ASK mode
BR_Range0 (Default)
BR_Range1
BR_Range2
39
22
12
8.2
nF
nF
nF
nF
Recommended CDEM for best
performance
CDEM
BR_Range3
BR_Range0 (Default)
1000
560
320
180
µs
µs
µs
µs
Maximum edge-to-edge time period of BR_Range1
the input data signal for full sensitivity BR_Range2
BR_Range3
tee_sig
BR_Range0 (Default)
270
156
89
µs
µs
µs
µs
Minimum edge-to-edge time period of BR_Range1
the input data signal for full sensitivity BR_Range2
BR_Range3
tee_sig
50
Threshold voltage for reset
VThRESET
1.95
39
2.8
3.75
V
Digital Ports
Data output
Iol = 1 mA
VOI
RPup
τ
CL
CL
0.08
50
0.3
61
2.5
41
V
- Saturation voltage LOW
- Internal pull-up resistor
- Maximum time constant
- Maximum capacitive load
kΩ
µs
pF
pF
τ = CL (Rpup//RExt
without external pull-up resistor
Rext = 5 kΩ
)
540
POUT output
- Saturation voltage LOW
- Saturation voltage HIGH
IPOUT = 1 mA
IPOUT = –1 mA
VOl
VOh
0.08
0.3
V
V
VS – 0.3V VS – 0.14V
ASK input
- High-level input voltage
ASK
VIh
0.8 × VS
V
ENABLE input
- Low-level input voltage
- High-level input voltage
Idle mode
Active mode
VIl
VIh
0.2 × VS
0.2 × VS
0.2 × VS
V
V
0.8 × VS
0.8 × VS
MODE input
- Low-level input voltage
- High-level input voltage
Division factor = 10
Division factor = 14
VIl
VIh
V
V
TEST input
- Low-level input voltage
Test input must always be set to LOW
VIl
V
25
4901B–RKE–11/07
9. Electrical Characteristics
All parameters refer to GND, VS = 5V, Tamb = 25°C, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. The possible operating
range refer to different circuit conditions: VS = 4.5V to 5.5V, Tamb = –40°C to +85°C
6.76438-Mhz Oscillator
(Mode 1)
4.90625-Mhz Oscillator
(Mode 0)
Variable Oscillator
Typ.
Parameter
Test Condition
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Max.
Unit
Basic Clock Cycle of the Digital Circuitry
Basic clock
cycle
MODE = 0 (USA)
MODE = 1 (Europe)
2.0383
1 / (fXTO / 10)
1 / (fXTO / 14)
µs
µs
TClk
2.0697
BR_Range0
BR_Range1
BR_Range2
BR_Range3
16.6
8.3
4.1
16.3
8.2
4.1
8 × TClk
4 × TClk
2 × TClk
1 × TClk
µs
µs
µs
µs
Extended
basic clock
cycle
TXClk
2.1
2.0
Polling Mode
Sleep ×
Sleep ×
Sleep ×
XSleep ×
1024 ×
TClk
Sleep and XSleep are
defined in the
OPMODE register
XSleep
×
XSleep
×
Sleep time
TSleep
ms
1024 ×
2.0697
1024 ×
2.0383
BR_Range0
BR_Range1
BR_Range2
BR_Range3
1855
1061
1061
663
1827
1045
1045
653
896.5
512.5
512.5
320.5
× TClk
µs
µs
µs
µs
Start-up time
TStartup
Average bit check
time while polling
BR_Range0
BR_Range1
BR_Range2
0.45
0.24
0.14
0.14
0.47
0.26
0.16
0.15
ms
ms
ms
ms
TBitcheck
BR_Range3
Time for Bit
check
Bit check time for a
valid input signal fSig
NBitcheck = 0
ms
ms
ms
ms
TBitcheck
TXClk
NBitcheck = 3
NBitcheck = 6
NBitcheck = 9
3 / fSig
6 / fSig
9 / fSig
3.5 / fSig 3 / fSig
6.5 / fSig 6 / fSig
9.5 / fSig 9 / fSig
3.5 / fSig
6.5 / fSig
9.5 / fSig
3.5 / fSig
6.5 / fSig
9.5 / fSig
Receiving Mode
Intermediate
frequency
MODE = 0 (USA)
MODE = 1 (Europe)
1.0
f
XTO × 64 / 314
MHz
MHz
fIF
1.0
fXTO × 64 / 432.92
BR_Range0
BR_Range1
BR_Range2
BR_Range3
1.0
1.8
3.2
5.6
1.8
3.2
5.6
1.0
1.8
3.2
5.6
1.8
3.2
5.6
BR_Range0 × 2 ms / TClk
BR_Range1 × 2 ms / TClk
BR_Range2 × 2 ms / TClk
BR_Range3 × 2 ms / TClk
kBaud
kBaud
kBaud
kBaud
Baud rate
range
BR_Range
10.0
10.0
TDATA_min
tmin1
tmin2
tmin1
tmin2
tmin1
tmin2
tmin1
tmin2
Minimum time
period
between
BR_Range0
BR_Range1
BR_Range2
BR_Range3
149
182
75
147
179
73
9 × TXClk
11 × TXCl
9 × TXClk
11 × TXClk
9 × TXClk
11 × TXClk
9 × TXClk
11 × TXClk
µs
µs
µs
µs
µs
µs
µs
µs
edges at
91
90
pin DATA
(Figure 5-9 on
page 16)
37.3
45.5
18.6
22.8
36.7
44.8
18.3
22.4
Maximum low
period at
DATA
(Figure 5-10
on page 16)
BR_Range0
BR_Range1
BR_Range2
BR_Range3
2169
1085
542
2136
1068
534
131 × TXClk
131 × TXClk
131 × TXClk
131 × TXClk
µs
µs
µs
µs
TDATA_L_max
271
267
26
ATA3745
4901B–RKE–11/07
ATA3745
9. Electrical Characteristics
All parameters refer to GND, VS = 5V, Tamb = 25°C, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. The possible operating
range refer to different circuit conditions: VS = 4.5V to 5.5V, Tamb = –40°C to +85°C
6.76438-Mhz Oscillator
(Mode 1)
4.90625-Mhz Oscillator
(Mode 0)
Variable Oscillator
Typ.
Parameter
Test Condition
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Max.
Unit
OFF
command at
pin ENABLE
(Figure 5-12
on page 17)
1.5 ×
TClk
tDoze
3.1
3.05
µs
Configuration of the Receiver
Frequency of
the reset
marker
(Figure 5-13
on page 21)
1
---------------------------------
fRM
117.9
119.8
Hz
4096 × TCLK
2188
1104
561
3176
3176
3176
3176
2155
1087
553
3128
3128
3128
3128
1057 ×
TClk
533 ×
TClk
271 ×
TClk
140 ×
TClk
1535 ×
TClk
1535 ×
TClk
1535 ×
TClk
1535 ×
TClk
BR_Range0
Programming
BR_Range1
start pulse
(Figure 5-11
BR_Range2
on page 17,
t1
µs
Figure 5-14 on
290
286
BR_Range3
page 21)
11656
11479
5632 ×
TClk
after POR
Programming
delay period
(Figure 5-11
on page 17,
Figure 5-14 on
page 21)
384.5 ×
TClk
385.5 ×
TClk
t2
t3
795
798
783
786
µs
µs
Synchron-
ization pulse
(Figure 5-11
on page 17,
Figure 5-14 on
page 21)
265
131
261
129
128 × TClk
Delay until the
program
window starts
(Figure 5-11
on page 17,
Figure 5-14 on
page 21)
t4
63.5 × TClk
µs
Programming
window
(Figure 5-11
on page 17,
Figure 5-14 on
page 21)
t5
t6
530
522
256 × TClk
µs
µs
Time frame
of a bit
(Figure 5-14
on page 21)
1060
1044
512 × TClk
27
4901B–RKE–11/07
9. Electrical Characteristics
All parameters refer to GND, VS = 5V, Tamb = 25°C, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. The possible operating
range refer to different circuit conditions: VS = 4.5V to 5.5V, Tamb = –40°C to +85°C
6.76438-Mhz Oscillator
(Mode 1)
4.90625-Mhz Oscillator
(Mode 0)
Variable Oscillator
Typ.
Parameter
Test Condition
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Max.
Unit
Programming
pulse (Figure
5-11 on page
17, Figure
5-14 on page
21)
256 ×
TClk
t7
133
529
131
521
64 × TClk
µs
Equivalent
acknowledge
pulse: E_Ack
(Figure 5-14
on page 21)
t8
t9
265
534
930
261
526
916
128 × TClk
258 × TClk
449.5 × TClk
µs
µs
µs
Equivalent
time window
(Figure 5-14
on page 21)
OFF bit
programming
window
t10
(Figure 5-11
on page 17)
28
ATA3745
4901B–RKE–11/07
ATA3745
10. Ordering Information
Extended Type Number
Package
Remarks
ATA3745P3-TGQY
SO20
Taped and reeled, Pb-free
11. Package Information
9.15
8.65
Package SO20
Dimensions in mm
12.95
12.70
7.5
7.3
2.35
0.25
0.25
0.10
0.4
10.50
10.20
1.27
11.43
20
11
technical drawings
according to DIN
specifications
1
10
12. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
4901B-RKE-11/07
• Put datasheet in the newest template
29
4901B–RKE–11/07
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4901B–RKE–11/07
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