ATA5275 [ATMEL]
125 kHz TRANSMITTER IC FOR TPM; 125千赫发射器IC，适用于TPM
| 型号： | ATA5275 |
| 厂家： | 
ATMEL |
| 描述： | 125 kHz TRANSMITTER IC FOR TPM |
| 文件： | 总16页 (文件大小：324K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Antenna Driver Stage with Adjustable Antenna Peak Current for up to 1.5 A
• Frequency Tuning Range from 100 kHz to 150 kHz
• Automatic Antenna Peak Current Regulation
• Self-tuning Oscillator for Antenna Resonant Frequency Adaption
• Capable of Driving a High-Q Antenna
• Integrated 5 V Regulator for External Load up to 10 mA
• Bi-directional Single Wire Interface for Microcontroller or ECU
• LF Baud Rates up to 4 kbaud and Amplitude Shift Keying (ASK) Modulation
• Low Power Standby Mode < 50 µA
• Antenna Driver Diagnosis: Peak Current, Antenna Frequency and Battery Voltage
Monitoring
125 kHz
Transmitter IC
for TPM
• Power Supply Range 8 V to 24 V Direct Battery Input
• Load Dump Protection up to 45 V for 12 V Boards
• Operation at Temperature -40°C to +105°C
• EMI and ESD According to Automotive Requirements
• Highly Integrated, Fewer External Components Required
• Driver Overcurrent Protection
ATA5275
• Overtemperature Protection
Preliminary
Applications
• Tire Pressure Measurement (TPM)
Benefits
• Self Tuning Capability to Antenna Resonance Frequency
• Adjustable Antenna Peak Current Value
• Highest Integration Level for Embedded Automotive Systems
Electrostatic sensitive device.
Observe precautions for handling.
Description
The ATA5275 is an integrated 1.5 A peak current BCDMOS antenna driver IC dedi-
cated as a 125 kHz wake-up channel transmitter for TPM applications.
It includes the full functionality to generate a magnetic LF field in conjunction with an
antenna coil to transmit data and power to a receiver. The transmission can be con-
trolled via a one wire I/O-interface by an external unit.
The smart power IC is delivered in a QFN20 power package with heat slug.
Rev. 4739C–AUTO–02/05
1. General Description
The ATA5275 is a 125-kHz transmitter IC. It is dedicated to driving 125 kHz LC antenna tanks,
specifically for the wake-up channel in Tire Pressure Measurement (TPM) applications.
It includes a control logic with VCO which generates the 125 kHz signal for the output driver
stage. A phase lock circuit regulates the driver output frequency on the antenna resonance fre-
quency, achieving a maximum field strength on the antenna. The driver duty cycle is regulated
and stabilizes the antenna current for a wide supply voltage range.
The IC can be controlled by a microcontroller or ECU via the one wire bi-directional interface. It
is used for the data transmission and to indicate errors. For the data transmission ASK modula-
tion is used. The antenna signal is modulated by the DIO interface line.
The IC has a build in diagnosis function and detects detuning and broken or short wire of the
antenna circuitry. If a failure is detected the IC indicates it by an error signal via the DIO line.
The integrated 5 V regulator can be used externally for a load up to 10 mA.
Figure 1-1. Block Diagram
20
DVCC3
19
BOOST
18
VCC
17
DIO
16
VDIO
1
5 V
REG
15
TM1
REF
BIAS
K-
Line
DVCC2
ATA5275
2
14
TM2
125-kHz Transmitter
DVCC1
13
3
TM3
DRV3
12
4
RCR
DRV2
VCO
11
5
REXT
DRV1
6
7
8
9
10
DVSS3
DVSS2
DVSS1
SENSE
VSS
2
ATA5275 [Preliminary]
4739C–AUTO–02/05
ATA5275 [Preliminary]
2. Pin Configuration
Figure 2-1. Pinning QFN20
20
DVCC3
19
BOOST
18
VCC
17
DIO
16
VDIO
1
15
TM1
DVCC2
2
14
TM2
DVCC1
3
13
TM3
ATA5275
DRV3
4
12
RCR
DRV2
5
11
REXT
DRV1
10
6
7
8
9
VSS
DVSS3 DVSS2 DVSS1 SENSE
Table 2-1.
Pin Description
Pin (1)
Symbol
DVCC2
DVCC1
DRV3
DRV2
DRV1
DVSS3
DVSS2
DVSS1
SENSE
VSS
Function
1
Battery supply input
Battery supply input
2
3
Antenna driver stage output
Antenna driver stage output
Antenna driver stage output
Power supply ground
4
5
6
7
Power supply ground
8
Power supply ground
9
Current zero crossing sense input
Analog and digital ground
External reference current input
External reference for antenna peak current
For test purposes only
10
11
12
13
14
15
16
17
18
19
20
REXT
RCR
TM3
TM2
For test purposes only
TM1
For test purposes only
VDIO
DIO line interface voltage selection
One-wire serial interface line
DIO
VCC
5 V supply output (for external storage capacitor only)
External bootstrap cap
BOOST
DVCC3
Battery supply input
Note:
1. Pin numbers valid for all revisions of the ATA5275
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4739C–AUTO–02/05
3. Functional Description
3.1
Operation Modes
There are two different operation modes for the ATA5275:
• Standby mode
• Transmission mode
3.2
Standby Mode and Wake-up
After power-on-reset, the ATA5275 is in standby mode. For minimum power consumption, only
the internal 5 V supply and the DIO line interface are active. The IC can be activated by the
external control unit via the serial interface. The DIO line is called logic high if it is pulled up to
the VDIO voltage level. The DIO line is called logic low if it is pulled down to the VSS voltage
level. A low signal at the DIO line wakes-up the IC.
The circuit enters the standby mode if either of these three conditions are fulfilled:
1. After power-on-reset and the DIO is high (see Figure 3-1)
2. After a time out of TOUTL(1) during which DIO is permanently low (see Figure 3-3 on
page 5)
3. After a time out of TOUTH(2) during which DIO is permanently high and an acknowledge
time TACK/TERR(1) (see Figure 3-2)
Notes: 1. Time does not depend on the antenna resonance frequency.
2. Time depends on the antenna resonance frequency.
Figure 3-1. STBY After POR
STBY
t
DIO
t
POR
t
Figure 3-2. STBY After DIO = H
STBY
t
TACK/TERR
TOUT_H
DIO
t
4
ATA5275 [Preliminary]
4739C–AUTO–02/05
ATA5275 [Preliminary]
Figure 3-3. STBY After DIO = L
TOUT_L
STBY
DIO
t
t
3.3
Transmission Mode
3.3.1
ASK Modulation
For the transmission of a wake-up signal or data to a receiver, the ATA5275 generates a
antenna resonance synchronized signal at the antenna driver output (DRV pin). A connected LC
antenna radiates a magnetic field. For the data transmission the field can be 100% amplitude
modulated by the DIO interface input. If a low level signal is applied at the DIO pin, the driver
generates a square wave signal DRV for the antenna. If a high level signal is applied at the DIO
pin the driver is stopped and switched to ground. In this way ASK modulated data can be trans-
mitted (see Figure 3-4).
Figure 3-4. Data Transmission
DIO
DRV
COIL
3.3.2
Anti-bouncing Filter in Transmission Mode
The DIO input signal is delayed for a anti-bouncing time.
The driver is switched on after a delay time of TDL (typically 64 µs) if the DIO is pulled to a low
level continuously. The driver is switched-off after a delay time of TDH if the DIO is pulled to high
level.
The TDH time depends on the antenna resonance frequency, suppressing short disturbance
pulses from the DIO Line.
Figure 3-5. Anti-bouncing
TD_L
TD_H
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4739C–AUTO–02/05
3.3.3
Time Out and Time Out Reset
The IC has a time out supervisor for the interface line to avoid unintended continuous transmis-
sion in case of line errors. The time out timer runs if the DIO pin is pulled to a low level. If the DIO
pin is permanently low for more than the time TOUTL the driver is switched off and the IC enters
the standby mode. This avoids the discharging of the supply battery if the DIO line has a failure
like a body contact or another permanent low level failure. The time TOUTL depends on the
antenna resonance frequency.
Figure 3-6. Time Out and Time Out Reset Protocol
Transmission
Delay
Time Out
Reset Periode
Timeout
Reset
Transmission
Delay
Time Out
Standby
Standby
TD_L TOUT_L
TOR
TORP
TD_H
DIO
DRV
For continuous transmission periods the internal time out timer must be reset within the time out
reset period TORP with a short high pulse of length TOR at DIO. Any transmission time periods
can be made by cyclical resetting of the time out timer (see Figure 3-6). The time TORP and TOR
depends on the antenna resonance frequency.
3.3.4
Transmission Acknowledge and Error Signal
If no failure is detected during a transmission sequence the IC acknowledges the transmission
by pulling the DIO line to low level for time TACK (typically 256 µs). The acknowledge signal is
generated at the end of a transmission sequence if the DIO line was high for the time TOUTH (typ-
ically 16 ms).
Their are two types of error detection (see section “Diagnosis and Protection”):
• Immediate switch-off of the driver stage
• The failure is indicated through the DIO line based on transmission acknowledge and Error
signal
At the end of transmission the IC indicates the failure by an error signal by pulling the DIO line to
a low level for time TERR (typically 128 µs) instead of TACK
.
With the acknowledge and the error signal a connected microcontroller is able to recognize fail-
ures of the IC or the antenna module as well as DIO line failures like a broken wire or a short
circuit.
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ATA5275 [Preliminary]
4739C–AUTO–02/05
ATA5275 [Preliminary]
Figure 3-7. Transmission Acknowledge and Error Signal
Time Out
TOUT_H
Time Out
TOUT_H
Error Signal
TERR
Acknowledge
TACK
Failure Detection
TDFx
DIO
DRV
COIL
Failure
The various failure types are monitored during transmission in time TFDx (see section “Diagno-
sis and Protection”). The time TFDx depends on the antenna resonance frequency.
3.4
Internal Voltage Regulator and POR
The IC contains a 5-V regulator. It is used for the supply voltage VCC of the logic circuits and the
low voltage analog circuits. Additionally, the VCC can be used externally for loads up to 10 mA.
The stabilized voltage is available at pin VCC and must be buffered with an external capacitor.
3.4.1
3.4.2
Reset
After power on or after a voltage breakdown the power-on-reset circuit of the IC generates a
reset pulse which sets the logic circuit to a defined initial state. A RESET is generated if the VCC
is below the reset threshold voltage VPOR and after power on.
DIO Interface
The interface can be operated either as a 5-V microcontroller interface or as automotive K-line
interface with the car battery voltage. In which mode it operates must be selected with the VDIO
pin. If it is connected to 5 V the DIO pin operates as microcontroller interface and if it is con-
nected with the battery voltage it operates as automotive interface according to the K-line
specification.
3.5
Oscillator and Carrier Frequency Generation
A Voltage Controlled Oscillator (VCO) is used to clock the interface logic and the gate driver
logic. The antenna driver output signal DRV is derived from this clock. The VCO operates in two
modes: the self-oscillation mode with clock CLKSO and the resonance tracking mode with clock
CLKRT.
3.5.1
Self-oscillating Mode
If the antenna half-bridge is not activated the VCO is in self-oscillating mode. It runs at a center
frequency CLKSO of typically 125 kHz with an accuracy of ±8%. For that purpose, an external
reference resistor has to be applied to pin REXT. The resistor at pin REXT determines the VCO
frequency proportionally. The recommended value is 100 kΩ achieving 125 kHz oscillator
frequency.
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4739C–AUTO–02/05
3.5.2
Resonance Tracking Mode
In case the antenna half-bridge is activated the VCO is tracked by the antenna current by means
of it zero crossing detection. The VCO runs at the antenna resonance frequency stationary. The
clock CLKRT deviates ±1.4% from the antenna resonance frequency, depending on the antenna
quality and resonance frequency (see section “Application Hints”). For that purpose, an antenna
current shunt resistor has to be applied to the SENSE pin. The shunt resistance is used inter-
nally for the zero crossing detection of the antenna current only.
By this feature the antenna operates with the maximum voltage, current and field strength. It is
recommended specially for systems with high antenna Q-factors and low LC tolerances.
3.6
Coil Driver Output and Antenna Peak Current Control
The driver circuit consists on a DMOS half-bridge designed for 1.5 A peak current with low on-
resistance RDSON. It is short-circuit and overtemperature protected (see section “Diagnosis and
Protection”). The half-bridge is switched on by a low level signal at DIO and generates a square
wave voltage for the antenna RLC circuitry.
A very useful function of the driver stage is the build-in antenna current control loop. The IC
senses the current through the antenna internally and controls the peak value IAPEAK by control-
ling the duty cycle DCDRV of the driver output.
So the antenna can be designed for maximum antenna current with the typical or even the mini-
mum supply voltage. For higher supply voltages the current is controlled by reducing the driver
duty cycle. The reference value for the antenna current IAPEAK can be adjusted externally with a
resistor RCR at the RCR pin.
50 kΩ
RCR
--------------
IAPEAK = 750 mA ×
Note:
Applying the formula above, the right driver current for the antenna has to be adjusted for the
worst supply voltage case. The IC operates from 14% up to 86% duty cycle for that case and
reduces the duty cycle for higher voltages (for the definition of the duty cycle DCDRV, see “Applica-
tion Hints” on page 13).
This feature allows the user to operate the IC in a wide field of operational voltage field and pro-
tects the driver stage and the antenna from antenna overcurrent.
The driver out square wave starts with a duty cycle of 50%. After tree or four cycles the duty
cycle can reach its maximum. As far as the peak current will stay smaller than IApeak this duty
cycle maximum is really 100%. If during the ramp up of the antenna current the envelope of the
peak current will be greater than IApeak + 20% a pulse skipping function will suppress the next
driver output pulse to minimize the antenna current overshoot.
3.7
Diagnosis and Protection
The IC supervises several parameters of IC operation for transmission diagnosis and circuit
protection.
In any case of circuit protection mode or error detection the IC indicates this states according to
the transmission protocol via the DIO line (see chapter “Transmission Acknowledge and Error
Signal” on page 6).
8
ATA5275 [Preliminary]
4739C–AUTO–02/05
ATA5275 [Preliminary]
3.7.1
Circuit Protection Cases
The circuit protection is activated in normal mode. It is switched off in standby mode. In case a
protection switch-off occurs the half-bridge is set in tri-state mode.
For all cases, there is a filter implemented to debounce half-bridge switch-off for a time of TDEB
(typically 20 µs). This debounce filter is activated in case the half-bridge is activated. Otherwise
it is RESET.
These are the following circuit protection cases:
1. Load dump protection: In case the voltage at DVCC exceeds a voltage VBATLD (typi-
cally 31 V).
2. Overcurrent protection: In case the current through the high side DMOS of the half-
bridge exceeds a value of IOCH or the current through the low side DMOS of the half-
bridge exceeds a value of IOCL (typically 2 A).
3. Overtemperature protection: In case the junction temperature exceeds a value of TSD
(typically 165°C).
3.7.2
Error Diagnosis
During the transmission the diagnosis function of the IC supervises the antenna current and fre-
quency and the half-driver bridge supply voltage. If any error is detected at the end of the
transmission cycle the error indication is set (as in circuit protection case).
There are the following diagnosis cases:
1. Under-voltage detection: Monitors if DVCC is below VBATUV (typically 6.5 V).
2. Antenna frequency error: Diagnosis if the oscillation frequency during transmission is
outside the typical tracking range 90 kHz to 160 kHz.
3. Antenna peak current error: Diagnosis if the peak current is greater than the adjusted
IAPEAK + 15% typically.
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4739C–AUTO–02/05
4. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
VSS
Min.
0
Max.
0
Unit
V
Ground
Power ground
DVSS1,2,3
DVCC1,2,3
DRV1,2,3
BOOST
VCC
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-2
+0.3
V
Reverse protected battery voltage
Half-bridge driver output
Bootstrap
+44
V
DVCC + 0.3
DVCC + 6(2)
+7
V
V
5-V regulator output
V
REXT
VCC + 0.3
VCC + 0.3
VCC + 0.3
DVCC + 0.3
DVCC + 0.3
DVCC + 0.3
250
V
Analog reference input
RCR
V
Digital test mode
TM1,2,3
VDIO
V
DIO interface supply
DIO interface
V
DIO
V
Zero crossing analog input
Electromagnetic Interference
SENSE
EMI
V
V/M
Minimum ESD protection
(100 pF through 1.5 kΩ)
2 (on PCB)
kV
Power dissipation
Ptot
ϑ j
2(1)
150
W
°C
°C
°C
°C
Junction temperature
Storage temperature
ϑ STORE
ϑ ambient
ϑ SOLDERING
-55
-40
+125
+105
220 + 5
Ambient temperature range under bias
Soldering temperature (10 s)
Notes: 1. May be limited by external thermal resistance.
2. If the low side driver is switched on, it is not allowed to connect a voltage source to pin BOOST.
5. Thermal Resistance
Parameters
Symbol
Value
Unit
Thermal resistance, junction ambient
RthJA
35
K/W
6. Operating Range
The operating conditions define the limits for functional operation and parametric characteristics of the device. Functionality outside these
limits is not implied if not otherwise stated explicitly.
Parameters
Symbol
VVBAT1
ϑ amb
Value
8 to 24
Unit
V
Operating supply voltage
Operating temperature range
-40 to +105
°C
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ATA5275 [Preliminary]
4739C–AUTO–02/05
ATA5275 [Preliminary]
7. Electrical Characteristics(1)
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
1
Power Supply
I(VCC) = 10 mA,
including load and line
regulation
1.1
Main supply voltage
VCC
VCC
4.7
5.0
5.3
V
A
1.2
1.3
Supply current
Standby current
without antenna load
DVCC
DVCC
ISUPP
ISTBY
2
10
35
20
60
mA
µA
A
B
Pin DVCC = 13.5 V,
20
Tamb = 90°C
Power-on-reset
threshold voltage
1.4
1.5
VCC
DVCC
DVCC
VPOR
3.5
29
4
4.5
35
V
V
A
A
Load dump protection
voltage
VBATLD
31
Under voltage
detection
1.6
1.7
1.8
2
VBATUV
TSD
6.0
150
5
6.5
165
15
7.0
180
25
V
A
B
Thermal shut down
oC
µs
Protection debounce
filter
TDEB
C, D
Half-bridge Driver Stage
Coil driver resistance
low side driver
DRV,
DVSS
2.1
RDSONL
RDSONH
IOCL
0.3
0.3
0.7
0.7
2.2
2.2
Ω
Ω
A
A
A
A
A
A
Coil driver resistance
high side driver
DVCC,
DRV
2.2
2.3
2.4
Overcurrent protection
threshold low side
DRV,
DVSS
1.5
1.5
1.9
Overcurrent protection
threshold high side
DVCC,
DRV
IOCH
1.75
10% to 90% slope
time,
0% = DVSS,
100% = DVCC
DVCC = 12 V
(smooth edges)
2.5
2.6
Driver output rise time
Driver output fall time
DRV
DRV
TDRV,RISE
50
50
100
100
150
150
ns
ns
D
D
10% to 90% slope
time,
0% = DVSS,
100% = DVCC
DVCC = 12 V
(smooth edges)
TDRV,FALL
3
Antenna Peak Current Control
Duty cycle control
range
(2)
3.1
DRV
RCR
DCDRV
15
1.15
1.0
85
1.28
1.8
%
V
B
A
B
Peak current control
reference
3.2
3.3
VRCR
1.215
1.3
Peak current control
accuracy
RCR = 25 kΩ
IApeak
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. 8 V < V(DVCC) < 24 V; -40° C < ϑ amb < 105°C, unless otherwise specified; all values refer to GND
2. Definition of DCDRV see “Application Hints” on page 13
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4739C–AUTO–02/05
7. Electrical Characteristics(1) (Continued)
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Antenna peak under
current threshold
0% NOM value = IAacc
RCR = 25 kΩ
3.4
IAUC
-30
-20
-10
%
A
Antenna peak
overcurrent threshold
0% NOM value = IAacc
RCR = 25 kΩ
3.5
IAOV
30
20
10
%
A
4
Oscillator and Phase Control
Self oscillating mode =
4.1
4.2
VCO initial frequency
half-bridge not
activated
CLKSO
CLKTR
115
80
125
135
200
kHz
kHz
A
B
Tracking frequency
mode = half-bridge
activated
VCO frequency
tracking range
Phase shift between
voltage at DRV and
zero crossing of
current through
SENSE
Antenna resonance
frequency range =
100 kHz to150 kHz,
antenna quality = 5 to
50
DRV,
SENSE
4.3
ϕA
-120
0
+120
ns
B
Phase control set-up
time
-240 ns ≤ ϕA ≤
+240 ns
DRV,
SENSE
4.4
4.5
Tsetup
fVCOH
fVCOL
160
200
105
µs
D
A
A
High frequency failure
threshold
DRV
DRV
150
80
160
90
kHz
kHz
Low frequency failure
threshold
4.6
5
DIO Interface
Pin VDIO = 13.5 V,
5.1
5.2
VDIO leakage current Pin DIO = 13.5 V
amb = 90°C
VDIO
DIO
IVDIO,STBY
2
4
4
5
µA
µA
A
A
T
Pin VDIO = 13.5 V,
Pin DIO = 13.5 V
Tamb = 90°C
DIO leakage current
IDIO,LEAK
2
200
5.3
5.4
DIO sink current
Output low level
DIO
DIO
IDIO,LIMIT
VDIOL
36
44
52
mA
V
A
A
IDIO = 20 mA
1.2
1.5
Input low level
threshold
%V
(VDIO)
5.5
5.6
100% = DVCC
DIO
DIO
VDIO,THL
VDIO,TLH
30
30
45
50
70
70
A
A
Input high level
threshold
%V
(VDIO)
100% = DVCC
6
Transmission Protocol
6.1
LF data baud rate
BdRF
TDL
1
4
kbit/s
µs
C, D
B
Anti-bouncing time for DIO = H → L,
activate half-bridge
6.2
6.3
6.4
64
for fVCO = 125 kHz
Anti-bouncing time for DIO = L → H,
de-activate half-bridge for fVCO = 125 kHz
TDH
64
µs
µs
B
B
Acknowledge pulse
width
TACK
256
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. 8 V < V(DVCC) < 24 V; -40° C < ϑ amb < 105°C, unless otherwise specified; all values refer to GND
2. Definition of DCDRV see “Application Hints” on page 13
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ATA5275 [Preliminary]
7. Electrical Characteristics(1) (Continued)
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Error signal pulse
width
6.5
TERR
128
µs
B
Transmission time out
de-activated half-
bridge
6.6
TOUTL
16
ms
B
Transmission time out
activated half-bridge
6.7
6.8
6.9
TOUTH
TOR
16
32
15
ms
µs
Time out reset pulse
width
Time out reset pulse
period
TORP
ms
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. 8 V < V(DVCC) < 24 V; -40° C < ϑ amb < 105°C, unless otherwise specified; all values refer to GND
2. Definition of DCDRV see “Application Hints” on page 13
8. External Components
The following external components have to be applied to the circuit for functional operation.
Component
Pin
REXT
RCR(4)
VCC
VCC(1)
BOOST
SENSE(2)
DIO
Min.
Typ.
Max.
Unit
Rext
RCR
C0
100
kΩ
kΩ
µF
nF
nF
Ω
25
200
22
100
1
CRF
CB
0.68
0.1(3)
0.6
2
1
6
RS
0.5
1
RDIO
kΩ
Notes: 1. For EMC reasons only.
2. Sensitivity at input SENSE is proportional to resistor Rs times antenna peak current.
3. For antenna peak value 1.5 A.
4. Recommended range: RCR = 25 to 100 kΩ.
9. Application Hints
A typical application of ATA5275 is shown in Figure 9-1 on page 14. The peak value of the
antenna current can be estimated by the formula:
VDVCC
-- -----------------
2
π
π
2
--
ÎA
=
×
× sin
× DCDRV × cosϕA
RA
Here RA denotes the equivalent series resistance of the driver load, i.e., the external coil series
resistance in series with the shunt resistance and the internal drain-source-on-resistance of the
NDMOS. The duty cycle DCDRV is the ratio of the driver high-side on-time with respect to the half
of the oscillation period.
The phase difference ϕA is measured as the time difference between the point of mass of VDRV
and the peak value of the antenna current.
13
4739C–AUTO–02/05
Figure 9-1. Application Circuit
State
Machine
Gate
Driver
Control
Half
Bridge
14
ATA5275 [Preliminary]
4739C–AUTO–02/05
ATA5275 [Preliminary]
10. Ordering Information
Extended Type Number
Package
Remarks
ATA5275-PGQ
QFN20, 5 mm x 5 mm
-
11. Package Information
15
4739C–AUTO–02/05
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