ATA5283P-6AQJ [ATMEL]
Interface IC for 125 kHz Wake-up Function; 接口IC，适用于125 kHz的唤醒功能
| 型号： | ATA5283P-6AQJ |
| 厂家： | 
ATMEL |
| 描述： | Interface IC for 125 kHz Wake-up Function |
| 文件： | 总14页 (文件大小：259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Wake-up Function for a Microcontroller with Preamble Detection
• 1 mVrms Sensitivity
• 1 µA Standby Current
• Power Supply: 2V to 3.8V
• Baud Rate: up to 4 kbps (ASK Modulation)
• Operation Temperature: up to 125°C
• Withstands +175°C
• Few External Components
Interface IC for
125 kHz
Application
• Tire Pressure Monitoring (TPM)
Wake-up
1. Description
Function
The ATA5283 is a 125 kHz ultra-low power receiver used for the wake-up function of
Tire Pressure Monitoring (TPM) application. The sensitive input stage of the IC ampli-
fies and demodulates the carrier signal from the antenna coil to a digital output signal
for a microcontroller. During the standby mode the preamble detection unit monitors
the incoming signal and activates the wake-up output and the data output, if the IC
receives a proper 125 kHz carrier signal.
ATA5283
By combining the IC with an antenna coil, a microcontroller, an RF transmitter/trans-
ceiver, a battery, temperature- and pressure sensor, it is possible to design a
complete Tire Pressure Monitoring system (TPM).
Figure 1-1. Block Diagram
Battery
VDD
ATA5283
Lx
Amplifier
with AGC
COIL
RESET
Vref
N_WAKEUP
N_DATA
Condi-
tioner
Preamble
check
TST1
TST2
GND
4598H–AUTO–03/07
2. Pin Configuration
Figure 2-1. Pinning TSSOP8L
COIL
TST1
TST2
VSS
1
2
3
4
8
7
6
5
VDD
N_WAKEUP
N_DATA
RESET
Figure 2-2. Pin Description
Pin
1
Symbol
COIL
Function
Antenna coil input
2
TST1
Test pin (reserved)
Test pin (reserved)
Signal ground
3
TST2
4
VSS
5
RESET
N_DATA
N_WAKEUP
VDD
External reset input
Data signal
6
7
Low active wake-up signal for microcontroller
Battery voltage
8
2
ATA5283
4598H–AUTO–03/07
ATA5283
3. Functional Description
The ATA5283 is an ultra-low power ASK receiver. Without a carrier signal it operates in the
standby listen mode. In this mode it monitors the coil input with a very low current consumption.
To activate the IC and the connected control unit, the transmitting stage must send the preamble
carrier burst. After a preamble is detected the IC is activated. It adapts the gain of the input stage
and enables the wake-up and the data output. The first gap at the end of the preamble gener-
ates a wake-up signal for the microcontroller. After that the receiver outputs the data signal at
N_DATA. To return the IC into the standby listen mode it must be reset via the RESET input.
3.1
3.2
AGC Amplifier
The input stage contains an Automatic Gain Control (AGC) amplifier to amplify the input signal
from the coil. The gain is adjusted by the automatic gain control circuit if a preamble signal is
detected. The high dynamic range of the AGC enables the IC to operate with input signals from
1 mVrms to 1.1Vrms. After the AGC settling time the amplifier output delivers a 125 kHz signal with
an amplitude adjusted for the following evaluation circuits’ preamble detection, signal condi-
tioner, wake-up.
Preamble Detection
Before data transmission the IC stays in standby listen mode. To prevent the circuit from unin-
tended operations in a noisy environment the preamble detection circuit checks the input signal.
A valid signal is detected by a counter after 192 carrier periods without interrupts. Short inter-
rupts which are suppressed by the signal conditioner are tolerated. When a valid carrier
(preamble) is found the circuit starts the automatic gain control. It requires up to 512 carrier peri-
ods to settling. The complete preamble should have 704 carrier periods minimum. The preamble
is terminated and the data transfer is started with the first gap (Start Gap) in the carrier (see Fig-
ure 3-1).
Figure 3-1. Communication Protocol
Preamble
Start
gap
Procedure
> 5.64 ms
Data
192 Periods
of LF
> 512 Periods
of LF
Signal
N_DATA
N_WAKEUP
RESET
Gain
control
No gain
control
AGC
adjustment
Gain control
active
No gain
control
Current
profile
2 µA
0.5 µA
1 µA
3
4598H–AUTO–03/07
3.3
Automatic Gain Control
For a correct demodulation the signal conditioner needs appropriate internal signal amplitude.
To control the input signal the ATA5283 has a build in digital AGC. The gain control circuit regu-
lates the internal signal amplitude to the reference value (Ref2, Figure 3-2). It decreases the
gain by one step if the internal signal exceeds the reference level for two periods and it
increases the gain by one step if eight periods do not achieve the reference level. In the standby
listen mode the gain is reset to the maximum value. If a valid preamble signal (192 valid carrier
clocks) is detected the automatic gain control is activated.
Note:
With the variation of the gain the coil input impedance changes from high impedance to minimal
143 kΩ because of the internal regulator circuit (see Figure 3-8 on page 8).
Figure 3-2. Automatic Gain Control
Transmitted
signal
Coil
input
Gain control
reference
Ref. 2
Gap detection Ref. 1
reference
100%
50%
Gain controlled
signal
Internal comparator
signal
N_DATA
4
ATA5283
4598H–AUTO–03/07
ATA5283
3.4
Signal Conditioner
The signal conditioner demodulates the amplifier output signal and converts it to a binary signal.
It compares the carrier signal with the 50% reference level (see Ref1 in Figure 3-3) and delivers
a logical 1, if the carrier signal stays below the reference and a logical 0, if it exceeds the refer-
ence level. A smoothing filter suppress the space between the half-waves as well as a few
missing periods in the carrier and glitches during the gaps.
The output signal of the signal conditioner is used as the internal data signal for the data output,
the wake-up logic and the preamble detection.
The timing of the demodulated data signal is delayed related to the signal at the transmitting
end. This delay is a function of the carrier frequency, the behavior of the smoothing filter and the
antenna Q-factor. The smoothing filter causes a delay of 3 to 6 periods (see tb and td in Figure
3-3). The rest of the delay is caused by the build-up time of the antenna signal and is condi-
tioned on the Q-factor (see ta and tc in Figure 3-3).
Figure 3-3. Output Timing
Ref.2
100%
50%
Ref.1
Coil
input
Comparator
output
N_DATA
t
t
c
b
t
t
a
d
t
t
OFF
ON
The following diagrams show the delay of the data signal as a function of the antenna Q-factor.
Figure 3-4. Turn On Delay Time (tON) versus Antenna Q-Factor
250
f
= 125 kHz
field
200
150
typ.
max.
min.
100
50
0
0
10
20
30
40
50
Q-factor
5
4598H–AUTO–03/07
Figure 3-5. Turn Off Delay Time (toff) versus Antenna Q-Factor
200
180
160
140
120
f
= 125 kHz
field
typ.
max.
100
80
60
min.
40
20
0
0
10
20
30
40
50
Q-factor
3.5
3.6
3.7
Data Output
The data output N_DATA outputs the demodulated and digitized LF signal according to the
envelope of the antenna input signal. In the standby mode the N_DATA output is disabled and
set to level 1. It is enabled by the wake-up signal and it outputs 1 level if the IC detects the car-
rier signal and a 0 level during the gaps (see Figure 3-1 on page 3).
As the circuit does not check the received data (except the preamble), it is up to the user to
choose the kind of encoding (pulse distance, Manchester, bi-phase...) wanted.
Wake-up Signal
The wake-up signal (N_WAKEUP) indicates that the ATA5283 has detected the end of a pream-
ble signal and has left the standby mode. It can be used as a wake-up or a chip select signal for
an external device (see Figure 3-1 on page 3).
After a preamble is detected the first valid gap (Start Gap) sets the N_WAKEUP output to low
and enables the data output N_DATA. The N_WAKEUP holds the low level until the IC is reset
to the standby mode by a reset signal.
Reset
The IC is reset either by the internal POR circuit during a power on sequence or by a high pulse
at the RESET pin. After the reset all internal counters are in the initial state and the IC is in the
standby listen mode.
The POR circuit generates a reset while the supply voltage VDD is below the power on reset
threshold VPOR and release the function of the IC if VDD exceeds this threshold.
A high signal at the RESET pin resets the complete circuit. If the IC is activated a reset signal is
necessary to activate the standby listen mode.
The RESET pin can also be used to hold the IC in a power down state. In this state the IC is out
of operation and the current consumption is below the standby current.
Note:
The RESET pin is high impedance CMOS input. To avoid floating effects like undefined input
states and malfunctions it should not be open.
6
ATA5283
4598H–AUTO–03/07
ATA5283
3.8
Standby Listen Mode
In the standby listen mode the IC monitors the coil input with a very low current consumption.
The automatic gain control is switched off and the gain is set to the maximum value. The
N_DATA and the N_WAKEUP output are set to a high level.
Before the controller enters its standby mode after the communication, it should activate the
standby listen mode of the ATA5283 with a reset signal. This measure ensures that the IC
enters the power saving standby mode and that the IC wakes the controller correctly with the
next preamble signal.
3.9
Applications
Figure 3-6 shows a typical TPM application of the ATA5283. Combined with the antenna reso-
nant circuit the ATA5283 is used as wake-up receiver for the microcontroller and the connected
temperature- and pressure-sensor.
Note:
To avoid supply voltage ripples to affect the microcontroller, an RC filter (R1 = 100Ω, C1 = 10 nF)
is recommended.
Figure 3-6. Application
R1
C1
125 kHz
8
ATA5283
Temp.
sensor
Amplifier
with
RESET
5
AGC
LA
CA
Central
board
Antenna
driver
1
Micro
controller
N_WAKEUP
N_DATA
7
6
controller
ATA5275
Pressure
sensor
Vref
2
3
4
UHF Rx
T5743
UHF Tx
433 kHz
ATAR862
7
4598H–AUTO–03/07
Figure 3-7. Pin Connection and Pin Protection
ATA5283
COIL_X
TST1
TST2
VSS
1
2
3
4
8
7
6
5
VDD
Divider impedance
143 kΩ to 5 MΩ
VDD
VDD
N_WAKEUP
N_DATA
RESET
2 kΩ
2 kΩ
1 kΩ
VDD
VDD
VDD
VDD
Figure 3-8. Coil Input Impedance
10000
max.
typ.
min.
1000
100
1
10
100
1000
10000
Coil Input Signal (mVpp
)
8
ATA5283
4598H–AUTO–03/07
ATA5283
4. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
VDD
VIN
Value
Unit
V
Power supply
–0.3 to +6.5
Input voltage (except coil inputs)
Input current coil
VSS – 0.3 < VIN < VDD + 0.3
V
ICI
±10
mA
V
Input voltage coil
VCI
VDD – 3.5 < VCI < VDD + 3.5
ESD protection (human body)
Operating temperature range
Withstanding 175°C
Storage temperature range
Soldering temperature
VESD
Tamb
tTEMP
Tstg
4
kV
°C
min.
°C
°C
–40 to +125
30
–40 to +150
260
Tsld
5. Thermal Resistance
Parameters
Symbol
Value
Unit
Thermal resistance junction ambient
RthJA
210
K/W
6. Operating Range
Parameters
Symbol
VDD
Value
2 to 3.8
Unit
V
Power supply range
Operating temperature range
TOP
–40 to +125
°C
9
4598H–AUTO–03/07
7. Electrical Characteristics
VSS = 0V, VDD = 2V to 3.8V, Tamb = –40°C to +105°C, characterized up to 125°C, unless other specified
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
1
Power Supply and Coil Limiter
1.1
Power supply
8
VDD
2
3.2
3.8
0.8
0.8
0.8
1.0
1.5
V
A
A
A
C
A
C
Reset supply current –40
Reset supply current +25
Reset supply current +85
Reset supply current +105
Reset supply current +125
µA
µA
µA
µA
µA
1, 2, 3,
8
1.2
IDDR
0.4
Supply current
(standby listen mode) –40
1.4
1.5
1.6
1.6
1.7
4.0
4.1
4.2
4.2
4.2
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
Vp
Vp
Vp
A
A
C
A
C
A
A
C
A
C
A
A
A
Supply current
(standby listen mode) +25
Supply current
(standby listen mode) +85
1, 2, 3,
8
1.3
IDDL
1.1
Supply current
(standby listen mode) +105
Supply current
(standby listen mode) +125
Supply current with carrier
(AGC active) –40
Supply current with carrier
(AGC active) +25
Supply current with carrier
(AGC active) +85
1,2, 3,
8
1.4
IDD
2
Supply current with carrier
(AGC active) +105
Supply current with carrier
(AGC active) +125
ICI = ± 1 mA
VDD = 2V
±1.4
±1.6
±1.8
Coil input voltage referred to
VDD (Input coil limiter for
channels X, Y, Z)
ICI = ± 1 mA
VDD = 3.2V
1.5
1-3
VC
ICI = ± 1 mA
VDD = 3.8V
2
Amplifiers
2.1
2.2
2.3
2.4
2.5
Wake-up sensitivity
Bandwidth
125 kHz input signal
Without coil
7
6
6
6
1
VSENS
BW
fu
1
2.2
mVrms
kHz
kHz
kHz
kΩ
A
C
C
C
A
150
180
30
Upper corner frequency
Lower corner frequency
Input impedance
Without coil
Without coil
fo
f = 125 kHz
RIN
143
VIN ≥ 1 mVrms at
125 kHz
2.6
Input capacitance
1
CIN
10
pF
C
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
10
ATA5283
4598H–AUTO–03/07
ATA5283
7. Electrical Characteristics (Continued)
VSS = 0V, VDD = 2V to 3.8V, Tamb = –40°C to +105°C, characterized up to 125°C, unless other specified
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
3
Automatic Gain Control
VIN ≥ 3 mVrms at
125 kHz
3.1
Preamble detection time
AGC adjustment time
tDAGC
192
Periods
B
f = 125 kHz
VIN = 1 mVrms
tAGC
tAGC
tAGC
tAGC
tAGC
0
48
220
292
450
3.2
VIN = 3 mVrms
VIN = 30 mVrms
VIN = 100 mVrms
VIN = 1Vrms
Periods
C
512
20
Signal change rate
(gap detection)
Coil input signal 100%
to 37% (τ )
3.3
3.4
1
1
1
tEOS
tCORR
tCORR
Periods
Periods
Periods
C
C
C
Coil input signal:
50 to 100% changing
52
AGC correction time
(no gap detection)
Coil input signal:
100 to 50% changing
208
3.5
3.6
3.7
4
Data rate (Q < 20)
125 kHz ASK
DR
tON
4
Kb/s
µs
A
A
A
Delay time RF signal to data 125 kHz ASK
Delay time RF signal to data 125 kHz ASK
Interface
40
40
tOFF
µs
0.8 ×
VDD
4.1
Reset input level high
5
5
5
VHRESET
tRESET
VDD
V
µs
V
A
A
C
4.1.1 Reset pulse width
VRESET = VDD
20
0.2 ×
VDD
4.2
4.3
4.4
Reset input level low
VLRESET
0
Reset input leakage current
low
V
RESET = VSS
RESET = VDD
5
5
IIL
-0.2
0
0
µA
µA
A
A
Reset input leakage current
high
V
IIH
0.2
0.8 ×
VDD
4.5
4.6
4.7
N_WAKEUP output level high INWAKEUP = –100 µA
N_WAKEUP output level low INWAKEUP = 100 µA
7
7
6
6
VHNWAKE
VLNWAKE
VHNDATA
VLNDATA
VDD
V
V
V
V
A
A
A
A
0
0.2 × VDD
VDD
0.8 ×
VDD
N_DATA output level high
IN_DATA = –100 µA
IN_DATA = 100 µA
4.8
5
N_DATA output level low
0
1
0.2 × VDD
Power Supply and Reset
5.1
V
DD power on reset threshold
VPOR
tPON
TSbydel
tRST
1.5
1.9
V
A
C
Switch on VDD to circuit
active
5.2
5.2.1
5.3
Power-up time
100
ms
Standby reactivation delay
after pulse reset
f = 125 kHz
800
200
µs
µs
C
C
RESET reactivation caused by
negative spikes on VDD
tBDN = 500 ns
7
10
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
11
4598H–AUTO–03/07
8. Ordering Information
Extended Type Number
Package
TSSOP8L
TSSOP8L
Remarks
ATA5283P-6AQJ
5000 pieces, taped and reeled, Pb-free
500 pieces, taped and reeled, Pb-free
ATA5283P-6APJ
9. Package Information
Package: TSSOP 8L
Dimensions in mm
3±0.1
3±0.1
+0.06
3.8±0.3
4.9±0.1
0.31-0.07
0.65 nom.
3 x 0.65 = 1.95 nom.
8
5
4
technical drawings
according to DIN
specifications
1
Drawing-No.: 6.543-5083.01-4
Issue: 2; 15.03.04
12
ATA5283
4598H–AUTO–03/07
ATA5283
10. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
4598H-AUTO-03/07
• Number 5.2.1 in section 7 “Electrical Characteristics” on page 11 added
• Put datasheet in a new template
• Pb-free logo on page 1 deleted
4598G-AUTO-01/07
4598F-AUTO-09/05
• Put datasheet in a new template
• Pb-free logo on page 1 added
• Heading Rows on Table “Absolute Maximum Ratings” on page 9 added
• Ordering Information on page 12 changed
13
4598H–AUTO–03/07
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4598H–AUTO–03/07
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