ATA5774-PXQW_技术文档

General Features

• Complete Key Fob IC Consisting of an AVR^®Microcontroller and RF Transmitter PLL in

a Single QFN24 5 mm × 5 mm Package (Pitch 0.65 mm)

– f₀= 310 MHz to 350 MHz (ATA5773)

– f₀= 429 MHz to 439 MHz (ATA5774)

– f₀= 868 MHz to 928 MHz (ATA5771)

• Automotive Qualified

• Temperature Range –40°C to +85°C

• ESD Protection: HBM 2500V, MM 100V, CDM 1000V

• Supply voltage 2.0V to 4.0V for Single Li-cell Power Supply

• Low Power Consumption

– Active Mode: Typical 9.8 mA at 3.0V and 4 MHz Microcontroller-clock

– Power-down Mode: Typical 200 nA at 3.0V

• Modulation Scheme ASK/FSK

Microcontroller

with

UHF ASK/FSK

Transmitter

• Integrated PLL Loop Filter

• High Output Power (8 dBm at 315 MHz/7.5 dBm at 433 MHz/ 5.5 dBm at 868 MHz)

• High Performance, Low Power AVR 8-bit Microcontroller

• Advanced RISC Architecture

ATA5771

ATA5773

ATA5774

• Non-volatile Program and Data Memories

– 4 KByte of In-system Programmable Program Memory Flash

– 256 Bytes In-system Programmable EEPROM

– 256 Bytes Internal SRAM

• Peripheral Features

– Two Timer/Counter, 8- and 16-bit Counters with Two PWM Channels on Both

– 10-bit ADC

– Programmable Watchdog Timer with Separate On-chip Oscillator

– Universal Serial Interface (USI)

• Special Microcontroller Features

– debugWIRE On-chip Debug System

– In-system Programmable via SPI Port

– External and Internal Interrupt Sources

– Pin Change Interrupt on 12 Pins

– Enhanced Power-on Reset Circuit

– Programmable Brown-out Detection Circuit

– Internal Calibrated Oscillator

– On-chip Temperature Sensor

• 12 Programmable I/O Lines

1. General Description

The ATA5771/ATA5773/ATA5774 is a single key fob IC containing the AVR microcon-

troller ATtiny44V and the UHF PLL transmitters T5750/53/54 build-up using a stacked

die technique supplied in a QFN24 5 mm × 5 mm package. These devices have been

specially developed for the demands of RF low-cost data transmission systems with

data rates of up to 32 kBit/s. Its main applications are in the areas of Remote Key-

less-Entry (RKE), Passive Entry Go (PEG), and Remote Start. It can be used in the

frequency range of f₀= 310 MHz to 350 MHz, f₀= 429 MHz to 439 MHz or

f₀= 868 MHz to 928 MHz for ASK or FSK data transmission.

9137B–RKE–02/09

Figure 1-1. ASK System Block Diagram

UHF ASK/FSK

Remote Control Transmitter

ATA5771/73/74

S1

PXY

ATtiny44V

VDD

GND

PXY

VS

S1

T5750

T5753

T5754

Power

up/down

ENABLE

GND_RF

UHF ASK/FSK

Remote Control Receiver

ATA5760

ATA5761

ATA5723

ATA5724

ATA5728

ATA5745

ATA5746

f/4

PLL

1 to 6

Micro-

controller

CLK

Demod

Control

VCC_RF

VS

XTO

VCO

Antenna

PA_ENABLE

ANT2

PLL

XTO

Loop

Antenna

PA

ANT1

LNA

VCO

VS

2

ATA5771/ATA5773/ATA5774

9137B–RKE–02/09

ATA5771/ATA5773/ATA5774

Figure 1-2. FSK System Block Diagram

UHF ASK/FSK

Remote Control Transmitter

ATA5771/73/74

S1

PXY

ATtiny44V

VDD

GND

PXY

VS

S1

T5750

T5753

T5754

Power

up/down

ENABLE

GND_RF

UHF ASK/FSK

Remote Control Receiver

ATA5760

f/4

PLL

ATA5761

ATA5723

ATA5724

ATA5728

ATA5745

ATA5746

1 to 6

Micro-

controller

CLK

Demod

Control

VCC_RF

VS

XTO

VCO

Antenna

PA_ENABLE

ANT2

PLL

XTO

Loop

Antenna

PA

ANT1

LNA

VCO

VS

3

9137B–RKE–02/09

2. Pin Configuration

Figure 2-1. Pinning QFN24 5 mm x 5 mm

24 23 22 21 20 19

18

VCC

PB0

PB1

1

2

3

4

5

6

PA0

17

16

15

14

13

PA1

PA2

PB3/RESET

PB2

PA3/T0

PA4/USCK

PA5/MISO

PA7

7

8

9

10 11 12

Table 2-1.

Pin Description

1

Symbol

VCC

Function

Microcontroller supply voltage

2

PB0

Port B is a 4-bit bi-directional I/O port with internal pull-up resistor

3

PB1

4

PB3/RESET Port B is a 4-bit bi-directional I/O port with internal pull-up resistor/reset input

5

PB2

PA7

Port B is a 4-bit bi-directional I/O port with internal pull-up resistor

Port A is a 4-bit bi-directional I/O port with internal pull-up resistor

6

7

PA6 / MOSI Port A is a 4-bit bi-directional I/O port with internal pull-up resistor

CLK Clock output signal for microcontroller. The clock output frequency is set by the crystal to f_XTAL/4

PA_ENABLE Switches on power amplifier, used for ASK modulation

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

ANT2

ANT1

Emitter of antenna output stage

Open collector antenna output

GND

Ground

PA5/MISO

PA4/SCK

PA3/T0

PA2

Port A is a 4-bit bi-directional I/O port with internal pull-up resistor

Microcontroller ground

PA1

PA0

GND

XTAL

Connection for crystal

VS_RF

GND_RF

ENABLE

GND

Transmitter supply voltage

Transmitter ground

Enable input

Ground

GND

Ground/backplane (exposed die pad)

4

ATA5771/ATA5773/ATA5774

9137B–RKE–02/09

ATA5771/ATA5773/ATA5774

3. Functional Description

For a typical key fob application 3-4 interconnections between the microcontroller and the trans-

mitter are required (see Figure 1-1 on page 2 and Figure 1-2 on page 3). The CLK line is used to

allow the microcontroller to generate an XTAL-based transmitter signal. The ENABLE line is

used to start the XTO, PLL, and clock output of the transmitter. The PA_ENABLE line is used to

enable the power amplifier in ASK and FSK mode. In FSK mode a 4^thline is necessary to modu-

late the load capacity of the XTAL. To wake-up the system from standby mode at least one key

input is required. After pressing the key, the microcontroller starts up with the internal RC oscilla-

tor. For TX operation user software must control ENABLE, PA_ENABLE and XTAL load

capacity as described in the following section.

If ENABLE = L and PA_ENABLE = L the transmitter and the microcontroller (MCU) are in

standby mode, reducing the power consumption so that a lithium cell can be used as power sup-

ply for several years.

If ENABLE = H and PA_ENABLE = L, the XTO, PLL and the CLK driver from the transmitter are

activated. The crystal oscillator together with the PLL from the RF transmitter typically requires

< 1 ms (ATA5773 < 3 ms) until the PLL is locked and the clock output (Pin 8) is stable.

If ENABLE = H and PA_ENABLE = H, the XTO, PLL, CLK driver and the Power Amplifier (PA)

are switched on. The ASK modulation is done by switching on/off the power amplifier via

PA_ENABLE. The FSK modulation is done by switching on/off an additional capacitor between

the XTAL load capacitor and GND, thus changing the reference frequency of the PLL. This is

done using a MOS switch controlled by a microcontroller output. The power amplifier is switched

on via PA_ENABLE = H.

The MCU has to wait at least > 1 ms ATA5774 (> 3 ms ATA5773, > 4 ms ATA5771) after setting

ENABLE = H, before the external clock can be used. The external clock is connected via the

timer0 input pin that clocks the USI from the MCU to achieve an accurate data transfer. The fre-

quency of the internal RC oscillator is affected by ambient temperature and operating voltage.

The USI provides 2 two serial synchronous data transfer modes, with different physical I/O ports

for the data output. The two wire mode is used for ASK and the three wire mode is used for FSK.

Table 3-1.

Type

Typical Current Consumption in Active Mode at 3.0V and 25°C

Microcontroller (4 MHz

Transmitter

8.5 mA

Internal RC Oscillator)

Total

ATA5771

ATA5773

ATA5774

0.8 mA

9.3 mA

9.8 mA

9.0 mA

0.8 mA

9.0 mA

0.8 mA

Table 3-2.

Current Consumption in Power-down Mode at 3.0V and –40°C to +85°C

Microcontroller

(Watchdog Timer

Type

Transmitter

Disabled)

Total

ATA5771

ATA5773

ATA5774

Typ. < 10 nA

Max. 350 nA

Typ. 200 nA

Typ. < 210 nA

Max. 24 µA⁽¹⁾

Max. 24.35 µA⁽¹⁾

Note:

1. Maximum value measured in final test at 125°C. Value at 85°C: See Appendix 4, page 196,

Figure 23-12 “Power Down Supply Current versus V_CC

”

5

9137B–RKE–02/09

4. UHF ASK/FSK Transmitter Block

• Integrated PLL Loop Filter

• Maximum Output Power (ATA5771: 5.5 dBm, ATA5773: 8.0 dBm, ATA5774: 7.5 dBm) with Low

Supply Current

• Modulation Scheme ASK/FSK

– FSK Modulation is Achieved by Switching on/off an Additional Capacitor Between the XTAL

Load Capacitor and GND. This is Done Using a MOS Switch Controlled by a Microcontroller

Output.

• Easy to Design-in Due to Excellent Isolation of the PLL from the PA and Power Supply

• Supply Voltage 2.0V to 4.0V in the Temperature Range of –40°C to +85°C

• Single-ended Antenna Output with High Efficient Power Amplifier

• External CLK Output for Clocking the Microcontroller

More detailed information about the UHF ASK/FSK Transmitter Block can be found in Appendix

1, 2 and 3.

ATA5771

ATA5773

ATA5774

see Appendix 1:

see Appendix 2:

see Appendix 3:

Data sheet T5750 (868 MHz band)

Data sheet T5753 (315 MHz band)

Data sheet T5754 (433 MHz band)

Table 4-1.

Transmitter Pin Cross Reference List

Pin Name Pin Number T5750/53/54

CLK

Pin Number ATA5771/73/74

1

8

PA_ENABLE

ANT2

2

3

4

5

6

7

8

9

10

11

20

21

22

23

ANT1

XTAL

VS

GND

ENABLE

Note:

For the ATA5771/ATA5773/ATA5774 following points differs in the data sheets:

- The temperature range is limited to –40°C to +85°C

- ESD protection: HBM 2500V, MM 100V, CDM 1000V

- Figure 4-1 on page 7: Two output power measurement

- For FSK modulation an additional MOS switch is required

6

ATA5771/ATA5773/ATA5774

9137B–RKE–02/09

ATA5771/ATA5773/ATA5774

Figure 4-1. Output Power Measurement ATA5771/ATA5773/ATA5774

V_S

C₁= 1 nF

L₁

Power

meter

ANT1

ANT2

Z = 50Ω

C₂

Z_Lopt

R_in

50Ω

Table 4-2.

Output Power Measurement ATA5771/ATA5773/ATA5774

Device

L₁

C₂

ATA5771

ATA5773

ATA5774

10 nH

47 nH

33 nH

0.5 pF

3.3 pF

2.4 pF

7

9137B–RKE–02/09

5. Microcontroller Block

• High-performance Low-power AVR 8-bit Microcontroller

• Advanced Risc Architecture

• Non-volatile Program and Data Memory

– 4KByte of In-system Programmable Program Flash

– Endurance: 10.000 Write/Erase Cycles

– 256 Bytes In-system Programmable EEPROM

– Endurance: 100.000 Write/Erase Cycles

– 256 Bytes Internal SRAM

• Programming Lock for Self-programming Flash Program and EEPROM Data Security

• Peripheral Features

– Two Timer/Counter, 8- and 16-bit Counters with Two PWM Channels on Both

• Programmable Watchdog Timer with Separate On-chip Oscillator

• On-chip Analog Comparator

– Universal Serial Interface

• Special Microcontroller Features

– Debug Wire On-chip Debug System

– In-system Programmable via SPI Port

– External and Internal Interrupt Sources

– Pin Change Interrupt on 12 Pins

– Low Power Idle, ADC Noise Reduction, Standby and Power-down Modes

– Enhanced Power-on Reset Circuit

– Programmable Brown-out Detection Circuit

– Internal Calibrated Oscillator

– On-chip Temperature Sensor

• 12 Programmable I/O Lines

• Operating Voltage

– 1.8V to 5.5V

• Speed Grade

– 0 to 4 MHz at 2.0V to 4.0V

• Temperature Range

– –40°C to +85°C

• Low Power Consumption

– Active Mode: 4 MHz, 3V, 0.8 mA

– Power-down Mode: 3V, 0.2 µA

More detailed information about the Microcontroller Block can be found in Appendix 4 and 5.

ATA5771, ATA5773, ATA5774

see Appendix 4: Datasheet ATtiny44

and Appendix 5: Appendix B - ATtiny44V

8

ATA5771/ATA5773/ATA5774

9137B–RKE–02/09

ATA5771/ATA5773/ATA5774

Table 5-1.

Microcontroller Cross Reference List

Pin Number

Pin Name

ATtiny44V

ATA5771/ATA5773/ATA5774

VCC

1

2

1

2

PB0

PB1

3

PB3/NRESET

PB2

4

5

PA7

6

PA6/MOSI

PA5/MISO

PA4/USCK

PA3/T0

PA2

7

8

13

14

15

16

17

18

19

9

10

11

12

13

14

PA1

PA0

GND

Note:

For the ATA5771/ATA5773/ATA5774 following points differs in the data sheet ATtiny44V:

- The temperature range is limited to –40°C to +85°C

- The supply voltage range is limited from 2.0V to 4.0V

9

9137B–RKE–02/09

6. Application

Figure 6-1. Typical ASK Application ATA5771/ATA5773/ATA5774

VCC

68 nF

VCC

24

23

22

21

20

19

SW1

SW2

SW3

1

2

3

4

5

6

18

17

16

15

14

13

VCC

PB0

PB1

PA0

PA1

PA2

ATA577x

PB3/RESET

PB2

PA3/T0

PA4/SCK

PA5/MISO

PA7

7

8

9

10

11

12

VCC

RF Choke

10

ATA5771/ATA5773/ATA5774

9137B–RKE–02/09

ATA5771/ATA5773/ATA5774

Figure 6-2. Typical FSK Application ATA5771/ATA5773/ATA5774

VCC

68 nF

VCC

24

23

22

21

20

19

SW1

1

2

3

4

5

6

18

VCC

PB0

PB1

PA0

SW2

17

PA1

16

SW3

PA2

ATA577x

15

PB3/RESET

PB2

PA3/T0

14

PA4/SCK

13

PA7

PA5/MISO

7

8

9

10

11

12

VCC

RF Choke

11

9137B–RKE–02/09

7. Ordering Information

Extended Type Number

Package

Remarks

ATA5771-PXQW

QFN24 5 mm x 5 mm

Microcontroller with UHF Tx for 868 MHz to 928 MHz

Microcontroller with UHF Tx for 310 MHz to 350 MHz

Microcontroller with UHF Tx for 429 MHZ to 439 MHz

ATA5773-PXQW

ATA5774-PXQW

8. Package Information

Package: QFN 24 - 5 x 5

Exposed pad 3.6 x 3.6

(acc. JEDEC OUTLINE No. MO-220)

Dimensions in mm

Not indicated tolerances ±0.05

5

0.9±0.1

+0

0.05-0.05

3.6

24

1

19

24

18

13

1

6

technical drawings

according to DIN

specifications

6

12

0.65 nom.

7

Drawing-No.: 6.543-5122.01-4

Issue: 1; 15.11.05

3.25

12

ATA5771/ATA5773/ATA5774

9137B–RKE–02/09

ATA5771/ATA5773/ATA5774

9. Revision History

Please note that the following page numbers referred to in this section refer to the specific revision

mentioned, not to this document.

Revision No.

History

• Features on page 1 changed

• Figure 1-1 “ASK System Block Diagram” on page 2 changed

• Figure 1-2 “FSK System Block Diagram” on page 3 changed

• Section 3 “Functional Description” on page 5 changed

• Table 4-1 “Transmitter Pin Cross Reference List” on page 6 changed

• Section 5 “Microcontroller Block” on page 8 changed

9137B-RKE-02/09

13

9137B–RKE–02/09

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9137B–RKE–02/09

Features

• Integrated PLL Loop Filter

• ESD Protection also at ANT1/ANT2

(4 kV HBM/200V MM; Except Pin 2: 4 kV HBM/100V MM)

• High Output Power (5.5 dBm) with Low Supply Current (8.5 mA)

• Modulation Scheme ASK/FSK

– FSK Modulation is Achieved by Connecting an Additional Capacitor Between the

XTAL Load Capacitor and the Open Drain Output of the Modulating Microcontroller

• Easy to Design-in Due to Excellent Isolation of the PLL from the PA and Power Supply

• Single Li-cell for Power Supply

• Supply Voltage 2.0V to 4.0V in the Temperature Range of –40°C to +85°C/+125°C

• Package TSSOP8L

UHF ASK/FSK

Transmitter

• Single-ended Antenna Output with High Efficient Power Amplifier

• CLK Output for Clocking the Microcontroller

• One-chip Solution with Minimum External Circuitry

• 125°C Operation for Tire Pressure Systems

T5750

1. Description

The T5750 is a PLL transmitter IC which has been developed for the demands of RF

low-cost transmission systems at data rates up to 32 kBaud. The transmitting

frequency range is 868 MHz to 928 MHz. It can be used in both FSK and ASK

systems.

Figure 1-1. System Block Diagram

UHF ASK/FSK

Remote control transmitter

Remote control receiver

1 Li cell

T5750

T5760/

T5761

1 to 3 Micro-

controller

Demod

Control

Encoder

ATARx9x

PLL

Keys

Antenna Antenna

XTO

VCO

LNA

PLL

XTO

LNA

VCO

4546F–RKE–12/08

2. Pin Configuration

Figure 2-1. Pinning TSSOP8L

CLK

PA_ENABLE

ANT2

1

2

3

4

8

7

6

5

ENABLE

GND

VS

ANT1

XTAL

Table 2-1.

Pin Description

Symbol

Function

Configuration

VS

Clock output signal for micro con roller

The clock output frequency is set by the

crystal to f_XTAL/4

100Ω

CLK

1

CLK

50 kΩ

PA_ENABLE

U_REF= 1.1V

Switches on power amplifier, used for

ASK modulation

2

PA_ENABLE

20 µA

ANT1

ANT2

3

4

ANT2

ANT1

Emitter of antenna output stage

Open collector antenna output

2

T5750

4546F–RKE–12/08

T5750

Table 2-1.

Pin Description (Continued)

Symbol

Function

Configuration

VS

1.5 kΩ

1.2 kΩ

5

XTAL

Connection for crystal

XTAL

182 µA

6

7

VS

Supply voltage

Ground

See ESD protection circuitry (see Figure 4-5 on page 9)

GND

200 kΩ

ENABLE

8

ENABLE

Enable input

Figure 2-2. Block Diagram

T5750

Power up/down

f

CLK

PA_ENABLE

ANT2

ENABLE

4

1

8

7

f

64

GND

2

PDF

CP

VS

3

4

6

5

LF

ANT1

PA

VCO

XTO

XTAL

PLL

3

4546F–RKE–12/08

3. General Description

This fully integrated PLL transmitter allows particularly simple, low-cost RF miniature transmit-

ters to be assembled. The VCO is locked to 64 × f_XTALhence a 13.5672 MHz crystal is needed

for a 868.3 MHz transmitter and a 14.2969 MHz crystal for a 915 MHz transmitter. All other PLL

and VCO peripheral elements are integrated.

The XTO is a series resonance oscillator so that only one capacitor together with a crystal con-

nected in series to GND are needed as external elements.

The crystal oscillator together with the PLL needs typically < 1 ms until the PLL is locked and the

CLK output is stable. There is a wait time of ≥ 4 ms must be used until the CLK is used for the

microcontroller and the PA is switched on.

The power amplifier is an open-collector output delivering a current pulse which is nearly inde-

pendent from the load impedance. The delivered output power is hence controllable via the

connected load impedance.

This output configuration enables a simple matching to any kind of antenna or to 50Ω. A high

power efficiency of η= P_out/(I_S,PA× V_S) of 24% for the power amplifier at 868.3 MHz results when

an optimized load impedance of Z_Load= (166 + j226)Ω is used at 3V supply voltage.

4. Functional Description

If ENABLE = L and the PA_ENABLE = L, the circuit is in standby mode consuming only a very

small amount of current, so that a lithium cell used as power supply can work for several years.

With ENABLE = H the XTO, PLL and the CLK driver are switched on. If PA_ENABLE remains L

only the PLL and the XTO is running and the CLK signal is delivered to the microcontroller. The

VCO locks to 64 times the XTO frequency.

With ENABLE = H and PA_ENABLE = H the PLL, XTO, CLK driver and the power amplifier are

on. With PA_ENABLE the power amplifier can be switched on and off, which is used to perform

the ASK modulation.

4.1

4.2

ASK Transmission

The T5750 is activated by ENABLE = H. PA_ENABLE must remain L for t ≥ 4 ms, then the CLK

signal can be taken to clock the microcontroller and the output power can be modulated by

means of pin PA_ENABLE. After transmission PA_ENABLE is switched to L and the microcon-

troller switches back to internal clocking. The T5750 is switched back to standby mode with

ENABLE = L.

FSK Transmission

The T5750 is activated by ENABLE = H. PA_ENABLE must remain L for t ≥ 4 ms, then the CLK

signal can be taken to clock the microcontroller and the power amplifier is switched on with

PA_ENABLE = H. The chip is then ready for FSK modulation. The microcontroller starts to

switch on and off the capacitor between the XTAL load capacitor and GND with an open-drain

output port, thus changing the reference frequency of the PLL. If the switch is closed, the output

frequency is lower than if the switch is open. After transmission PA_ENABLE is switched to L

and the microcontroller switches back to internal clocking. The T5750 is switched back to

standby mode with ENABLE = L.

The accuracy of the frequency deviation with XTAL pulling method is about ±25% when the fol-

lowing tolerances are considered.

4

T5750

4546F–RKE–12/08

T5750

Figure 4-1. Tolerances of Frequency Modulation

V_S

C_Stray1

C_Stray2

L_M

C₄

XTAL

C_M

R_S

C₀

C₅

C_Switch

Using C₄= 9.2 pF ±2%, C₅= 6.8 pF ±5%, a switch port with C_Switch= 3 pF ±10%, stray capaci-

tances on each side of the crystal of C_Stray1= C_Stray2= 1 pF ±10%, a parallel capacitance of the

crystal of C₀= 3.2 pF ±10% and a crystal with C_M= 13 fF ±10%, an FSK deviation of ±21.5 kHz

typical with worst case tolerances of ±16.8 kHz to ±28.0 kHz results.

4.3

CLK Output

An output CLK signal is provided for a connected microcontroller, the delivered signal is CMOS

compatible if the load capacitance is lower than 10 pF.

4.3.1

Clock Pulse Take-over

The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel^®’s

ATARx9x has the special feature of starting with an integrated RC-oscillator to switch on the

T5750 with ENABLE = H, and after 4 ms to assume the clock signal of the transmission IC, so

that the message can be sent with crystal accuracy.

4.3.2

Output Matching and Power Setting

The output power is set by the load impedance of the antenna. The maximum output power is

achieved with a load impedance of Z_Load,opt= (166 + j226)Ω at 868.3 MHz. There must be a low

resistive path to V_Sto deliver the DC current.

The delivered current pulse of the power amplifier is 7.7 mA and the maximum output power is

delivered to a resistive load of 475Ω if the 0.53 pF output capacitance of the power amplifier is

compensated by the load impedance.

An optimum load impedance of:

Z

_Load= 475Ω || j/(2 × p × f × 0.53 pF) = (166 + j226)Ω thus results for the maximum output

power of 5.5 dBm.

The load impedance is defined as the impedance seen from the T5750’s ANT1, ANT2 into the

matching network. Do not confuse this large signal load impedance with a small signal input

impedance delivered as input characteristic of RF amplifiers and measured from the application

into the IC instead of from the IC into the application for a power amplifier.

Less output power is achieved by lowering the real parallel part of 475Ωwhere the parallel imag-

inary part should be kept constant.

Output power measurement can be done with the circuit of Figure 4-2 on page 6. Note that the

component values must be changed to compensate the individual board parasitics until the

T5750 has the right load impedance Z_Load,opt= (166 + j226)Ω at 868.3 MHz. Also the damping of

the cable used to measure the output power must be calibrated out.

5

4546F–RKE–12/08

Figure 4-2. Output Power Measurement

V_S

C₁

1 nF

L₁10 nH

Power

meter

Z = 50Ω

C₂

ANT1

1.5 pF

C₃

Z_Lopt

R_in

50Ω

2.7 pF

ANT2

4.4

Application Circuit

For the supply-voltage blocking capacitor C₃a value of 68 nF/X7R is recommended (see Figure

4-3 on page 7 and Figure 4-4 on page 8). C₁and C₂are used to match the loop antenna to the

power amplifier where C₁typically is 3.9 pF/NP0 and C₂is 1 pF/NP0; for C₂two capacitors in

series should be used to achieve a better tolerance value and to have the possibility to realize

the Z_Load,optby using standard valued capacitors.

C₁forms together with the pins of T5750 and the PCB board wires a series resonance loop that

suppresses the 1^stharmonic, hence the position of C₁on the PCB is important. Normally the

best suppression is achieved when C₁is placed as close as possible to the pins ANT1 and

ANT2.

The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the loop

antenna is too high.

L₁(≈ 50 nH to 100 nH) can be printed on PCB. C₄should be selected so that the XTO runs on

the load resonance frequency of the crystal. Normally, a value of 12 pF results for a 15 pF

load-capacitance crystal.

6

T5750

4546F–RKE–12/08

T5750

Figure 4-3. ASK Application Circuit

S1

VDD

VSS

BPXY

OSC1

ATARx9x

VS

1

S2

20

BPXY

7

T5750

Power up/down

CLK

ENABLE

f

4

1

2

8

7

f

64

PA_ENABLE

GND

PDF

CP

C3

C2

ANT2

VS

3

4

6

5

VS

Loop

Antenna

LF

C1

ANT1

XTAL

PA

VCO

XTO

PLL

L1

C4

VS

7

4546F–RKE–12/08

Figure 4-4. FSK Application Circuit

S1

VDD

BPXY

OSC1

ATARx9x

VS

1

20

18

S2

VSS

BP42/T2O

BPXY

7

T5750

Power up/down

CLK

ENABLE

f

4

1

2

8

7

f

64

PA_ENABLE

GND

PDF

CP

C3

C2

ANT2

VS

3

4

6

5

Loop

Antenna

LF

VS

C1

C5

XTAL

ANT1

XTAL

PA

VCO

XTO

PLL

L1

C4

VS

8

T5750

4546F–RKE–12/08

T5750

Figure 4-5. ESD Protection Circuit

VS

ANT1

ANT2

CLK

PA_ENABLE

XTAL

ENABLE

GND

5. Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Parameters

Symbol

Minimum

Maximum

Unit

V

Supply voltage

V_S

5

100

Power dissipation

Junction temperature

Storage temperature

Ambient temperature

Input voltage

P_tot

mW

°C

V

T_j

T_stg

150

–55

–0.3

125

T_amb

125

(V_S+ 0.3)⁽¹⁾

V_{maxPA_ENABLE}

Note:

1. If V_S+ 0.3 is higher than 3.7V, the maximum voltage will be reduced to 3.7V.

6. Thermal Resistance

Parameters

Symbol

Value

Unit

Junction ambient

R_thJA

170

K/W

7. Electrical Characteristics

V_S= 2.0V to 4.0V, T_amb= –40°C to 125°C unless otherwise specified.

Typical values are given at V_S= 3.0V and T_amb= 25°C. All parameters are referred to GND (pin 7).

Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Power down,

V

_ENABLE< 0.25V, –40°C to 85°C

350

7

nA

µA

nA

Supply current

V_{PA_ENABLE}< 0.25V, –85°C to +125°C

V_{PA_ENABLE}< 0.25V, 25°C

I_{S_Off}

<10

(100% correlation tested)

Power up, PA off, V_S= 3V,

V_ENABLE> 1.7V, V_{PA_ENABLE}< 0.25V

I_S

3.6

8.5

5.5

4.6

11

8

mA

Supply current

Output power

Power up, V_S= 3.0,

V_ENABLE> 1.7V, V_{PA_ENABLE}> 1.7V

I_{S_Transmit}

P_Ref

V_S= 3.0V, T_amb= 25°C,

f = 868.3 MHz, Z_Load= (166 + j226)Ω

3.5

dBm

Note:

1. If V_Sis higher than 3.6V, the maximum voltage will be reduced to 3.6V.

9

4546F–RKE–12/08

7. Electrical Characteristics (Continued)

V_S= 2.0V to 4.0V, T_amb= –40°C to 125°C unless otherwise specified.

Typical values are given at V_S= 3.0V and T_amb= 25°C. All parameters are referred to GND (pin 7).

Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

T_amb= –40°C to +85°C,

V_S= 3.0V

V_S= 2.0V

Output power variation for the full

temperature range

ΔP_Ref

–1.5

–4.0

dB

T_amb= –40°C to +125°C,

Output power variation for the full V_S= 3.0V

ΔP_Ref

–2.0

–4.5

dB

temperature range

V_S= 2.0V,

P_Out= P_Ref+ ΔP_Ref

Achievable output-power range

Selectable by load impedance

P_{Out_typ}

–3

+5.5

dBm

f_CLK= f₀/128

Load capacitance at pin CLK = 10 pF

f_O±1 × f_CLK

f_O±4 × f_CLK

Spurious emission

–52

dBc

other spurious are lower

f

_XTO= f₀/64

f_XTAL= resonant frequency of the XTAL,

_M≤ 10 fF, load capacitance selected

Oscillator frequency XTO

(= phase comparator frequency)

C

f_XTO

accordingly

T_amb= –40°C to +85°C,

T_amb= –40°C to +125°C

–30

–40

f_XTAL

+30

+40

ppm

PLL loop bandwidth

250

–116

–80

kHz

Referred to f_PC= f_XT0,

25 kHz distance to carrier

Phase noise of phase comparator

In loop phase noise PLL

Phase noise VCO

–110

–74

dBc/Hz

25 kHz distance to carrier

dBc/Hz

at 1 MHz

at 36 MHz

–89

–120

–86

–117

dBc/Hz

Frequency range of VCO

f_VCO

868

928

MHz

Clock output frequency (CMOS

microcontroller compatible)

f₀/256

MHz

V_0h

V_0l

V_S× 0.8

V

Voltage swing at pin CLK

C_Load≤ 10 pF

V_S× 0.2

110

7

Series resonance R of the crystal

Capacitive load at pin XT0

Rs

Ω

pF

FSK modulation frequency rate

ASK modulation frequency rate

Duty cycle of the modulation signal = 50%

0

32

kHz

32

Low level input voltage

High level input voltage

Input current high

V_Il

V_Ih

I_In

0.25

V

µA

ENABLE input

1.7

20

Low level input voltage

High level input voltage

Input current high

V_Il

V_Ih

I_In

0.25

V

µA

(1)

PA_ENABLE input

V_S

5

Note:

1. If V_Sis higher than 3.6V, the maximum voltage will be reduced to 3.6V.

10

T5750

4546F–RKE–12/08

T5750

8. Ordering Information

Extended Type Number

Package

Remarks

T5750-6AQJ

TSSOP8L

Taped and reeled, Marking: T570, Pb-free

9. Package Information

Package: TSSOP 8L

Dimensions in mm

3±0.1

+0.06

3.8±0.3

4.9±0.1

0.31-0.07

0.65 nom.

3 x 0.65 = 1.95 nom.

8

5

4

technical drawings

according to DIN

specifications

1

Drawing-No.: 6.543-5083.01-4

Issue: 2; 15.03.04

11

4546F–RKE–12/08

10. Revision History

Please note that the following page numbers referred to in this section refer to the specific revision

mentioned, not to this document.

Revision No.

History

• Put datasheet in the newest template

4546F-RKE-12/08

• Section 7 “Electrical Characteristics” on page 10 changed

• Put datasheet in the newest template

• Pb-free logo on page 1 deleted

4546E-RKE-02/07

4546D-RKE-09/05

• Pb-free logo on page 1 added

• Ordering Information on page 11 changed

• Put datasheet in the newest template

4546C-RKE-05/05

• Rename M4xCx9x in ATARx9x

• Table “Absolute Maximum Ratings” on page 9: New heading rows added

• Table “Absolute Maximum Ratings” on page 9: row “Input voltage” added

• Table “Absolute Maximum Ratings” on page 9: table note 1 added

• Table “Electrical Characteristics” on pages 9 to 10: row “PA_ENABLE input”

changed

4546B-RKE-07/04

• Table “Electrical Characteristics” on pages 9 to 10: table note 1 added

• Table “Ordering Informations” on page 11: Remarks changed

12

T5750

4546F–RKE–12/08

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