ATA6620-TAQY [ATMEL]
LIN ABUS TRANSCEIVER WITH INTEGRATED VOLTAGE REGULATOR; 具有集成稳压器,LIN收发器安博型号: | ATA6620-TAQY |
厂家: | ATMEL |
描述: | LIN ABUS TRANSCEIVER WITH INTEGRATED VOLTAGE REGULATOR |
文件: | 总19页 (文件大小:235K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Features
•
•
•
•
•
Supply Voltage up to 40V
Operating Voltage VS = 5V to 18V
Typically 10 µA Supply Current During Sleep Mode
Typically 40 µA Supply Current in Silent Mode
Linear Low-drop Voltage Regulator:
– Normal Mode: VCC = 5V ±2%/50 mA
LIN Bus
– Silent Mode: VCC = 5V ±7%/50 mA
– Sleep Mode: VCC is Switched Off
Transceiver
with Integrated
Voltage
•
•
•
•
•
•
•
•
•
•
•
•
VCC Undervoltage Detection with Reset Output NRES (10 ms Reset Time)
Voltage Regulator is Short-circuit and Over-temperature Protected
LIN Physical Layer According to LIN Specification Revision 2.0
Wake-up Capability via LIN Bus (90 µs Dominant)
TXD Time-out Timer (9 ms)
60V Load-dump Protection at LIN Pin
Regulator
Bus Pin is Overtemperature and Short-circuit Protected versus GND and Battery
High EMC Level
5V CMOS-Compatible I/O Pins to MCU
ATA6620
ESD HBM 6kV at Pins LIN and VS
Interference and Damage Protection According to ISO/CD7637
Package: SO8
Preliminary
1. Description
ATA6620 is a fully integrated LIN transceiver, designed according to the LIN specifica-
tion 2.0, with a low-drop voltage regulator (5V/50 mA). The combination of voltage
regulator and bus transceiver makes it possible to develop simple, but powerful, slave
nodes in LIN Bus systems. ATA6620 is designed to handle the low-speed data com-
munication in vehicles (for example, in convenience electronics). Improved slope
control at the LIN driver ensures secure data communication up to 20 kBaud with an
RC oscillator for the protocol handling. The bus output is designed to withstand high
voltage. Sleep mode (voltage regulator switched off) and Silent mode (communication
off; VCC voltage on) guarantee minimized current consumption.
Rev. 4850A–AUTO–02/05
Figure 1-1. Block Diagram
1
VS
VCC
ATA6620
Normal and
Pre-normal
Mode
RXD
5
Receiver
LIN
4
Filter
VCC
Wake-up Bus Timer
Slew Rate Control
Short Circuit and
Overtemperature
Protection
TXD
6
TXD
Time-out
Timer
VCC
8
Normal Mode
Voltage Regulator
5V/50 mA/2%
Sleep
Mode
VCC
Switched
EN
2
NRES
Control
Unit
7
Undervoltage Reset
Silent Mode
Voltage Regulator
5V/50 mA/7%
GND
3
Off
2. Pin Configuration
Figure 2-1. Pinning SO8
VS
EN
1
2
3
4
8
7
6
5
VCC
NRES
TXD
GND
LIN
RXD
Table 2-1.
Pin Description
Pin
1
Symbol
VS
Function
Battery supply
2
EN
Enables Normal mode if the input is high
Ground
3
GND
LIN
4
LIN bus line input/output
Receive data output
5
RXD
TXD
NRES
VCC
6
Transmit data input
7
Output undervoltage reset, low at reset
Output voltage regulator 5V/50 mA
8
2
ATA6620 [Preliminary]
4850A–AUTO–02/05
ATA6620 [Preliminary]
3. Functional Description
3.1
Supply Pin (VS)
LIN operating voltage is VS = 5V to 18V. An undervoltage detection is implemented to disable
transmission if VS falls below 5V, in order to avoid false bus messages. After switching on VS,
the IC starts with the Pre-normal mode and the voltage regulator is switched on (that is,
5V/50 mA output capability).
The supply current in Sleep mode is typically 10 µA and 40 µA in Silent mode.
3.2
3.3
Ground Pin (GND)
The IC is neutral on the LIN pin in case of GND disconnection. It is able to handle a ground shift
up to 3V for supply voltage above 9V at the VS pin.
Voltage Regulator Output Pin (VCC)
The internal 5V voltage regulator is capable of driving loads with up to 50 mA, supplying the
microcontroller and other ICs on the PCB. It is protected against overload by means of current
limitation and overtemperature shut-down. Furthermore, the output voltage is monitored and will
cause a reset signal at the NRES output pin if it drops below a defined threshold Vthun
.
3.4
3.5
Undervoltage Reset Output (NRES)
This push-pull output is supplied from the VCC voltage. If the VCC voltage falls below the under-
voltage detection threshold of Vthun, NRES switches to low after tres_f (Figure 4-6 on page 9).
Even if VCC = 0V the NRES stays low, because it is internally driven from the VS voltage. If VS
voltage ramps down, NRES stays low until VS < 1.5V and then becomes highly resistant.
The implemented undervoltage delay keeps NRES low for tReset = 10 ms after VCC reaches its
nominal value.
Bus Pin (LIN)
A low-side driver with internal current limitation and thermal shutdown, as well as an internal
pull-up resistor according to LIN specification 2.0 is implemented. The voltage range is from
–27V to +60V. This pin exhibits no reverse current from the LIN bus to VS, even in the case of a
GND shift or VBatt disconnection. The LIN receiver thresholds are compatible with the LIN proto-
col specification.
The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are
slope controlled. The output has a short-circuit limitation. This is a self-adapting current limita-
tion; that is, during current limitation, as the chip temperature increases, the current decreases.
3.6
Input Pin (TXD)
This pin is the microcontroller interface to control the state of the LIN output. TXD must be pulled
to ground in order to drive the LIN bus low. If TXD is high or unconnected (internal pull-up resis-
tor), the LIN output transistor is turned off and the bus is in the recessive state.
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4850A–AUTO–02/05
3.7
3.8
Dominant Time-out Function (TXD)
The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being
driven permanently in the dominant state. If TXD is forced to low longer than TDOM > 4 ms, the
LIN bus driver is switched to the recessive state. To reset this dominant time-out mode, TXD
must be switched to high (>10 µs) before normal data transmission can be started.
Output Pin (RXD)
This pin reports the state of the LIN bus to the microcontroller. LIN high (recessive state) is
reported by a high level at RXD; LIN low (dominant state) is reported by a low level at RXD. The
output has an internal pull-up structure with typically 5 kΩ to VCC. The AC characteristics are
measured with an external load capacitor of 20 pF.
The output is short-circuit protected. In unpowered mode (that is, VS = 0V), RXD is switched off.
3.9
Enable Input Pin (EN)
This pin controls the operation mode of the interface. After power up of VS (battery), the IC
switches to Pre-normal mode, even if EN is low or unconnected (internal pull-down resistor). If
EN is high, the interface is in Normal mode.
A falling edge at EN while TXD is still high forces the device to Silent mode. A falling edge at EN
while TXD is low forces the device to Sleep mode.
4. Mode of Operation
Figure 4-1. Mode of Operation
a: VS > 5V
b: VS < 4V
c: Bus wake-up event
Unpowered Mode
VBatt = 0V
a
b
Pre-normal Mode
VCC: 5V/2%/50 mA with undervoltage reset
Communication: OFF
b
b
c
EN = 1
c
b
Go to silent command
EN = 0
TXD = 1
Silent Mode
VCC: 5V/7%/50 mA
with undervoltage reset
Local wake-up event
Normal Mode
Communication:
OFF
EN = 1
VCC: 5V/2%/50 mA
with undervoltage reset
Go to sleep command
EN = 0
TXD = 0
Communication:
ON
Sleep Mode
VCC: switched off
Communication: OFF
Local wake-up event
EN = 1
4
ATA6620 [Preliminary]
4850A–AUTO–02/05
ATA6620 [Preliminary]
Table 4-1.
Mode of
Mode of Operation
Communication
Operation
Pre-normal
Normal
VCC
5V
5V
5V
0V
RXD
5V
LIN
OFF
ON
Recessive
Recessive
Recessive
Recessive
5V
Silent
OFF
OFF
5V
Sleep
0V
4.1
4.2
Normal Mode
Silent Mode
This is the normal transmitting and receiving mode of the LIN Interface, in accordance with LIN
specification 2.0. The VCC voltage regulator operates with a 5V output voltage, with a low toler-
ance of ±2% and a maximum output current of 50 mA.
If an undervoltage condition occurs, NRES is switched to low and the ATA6620 changes state to
Pre-normal mode. All features are available.
A falling edge at EN while TXD is high switches the IC into Silent mode. The TXD Signal has to
be logic high during the Mode Select window (Figure 4-2 on page 6). For EN and TXD either two
independent outputs can be used, or two outputs from the same microcontroller port; in the sec-
ond case, the mode change is only one command.
In Silent mode the transmission path is disabled. Supply current from VBatt is typically
I
VSsi = 40 µA with no load at the VCC regulator.
The overall supply current from VBatt is the result of 40 µA plus the VCC regulator output current
IVCCs
.
The 5V regulator is in low tolerance mode (4.65V to 5.35V) and can source up to 50 mA. In
Silent mode the internal slave termination between pin LIN and pin VS is disabled to minimize
the power dissipation in case pin LIN is short-circuited to GND. Only a weak pull-up current (typ-
ically 10 µA) between pin LIN and pin VS is present.
The Silent mode voltage is sufficient to run an external microcontroller on the ECU, for example
in Power Down mode. The undervoltage reset is VCCthS < 4.4V. If an undervoltage condition
occurs, NRES is switched to low and the ATA6620 changes state to Pre-normal mode.
A falling edge at pin LIN followed by a dominant bus level maintained for a certain time period
(Tbus) results in a remote wake-up request. The device switches from Silent mode to Pre-normal
mode, then the internal LIN slave termination resistor is switched on. The remote wake-up
request is indicated by a low level at pin RXD to interrupt the microcontroller. (Figure 4-5 on
page 8)
With EN high, ATA6620 switches directly from Silent to Normal mode.
5
4850A–AUTO–02/05
Figure 4-2. Switch to Silent Mode
Silent Mode
Normal Mode
EN
Mode select window
TXD
Td = 3.2 µs
NRES
VCC
Delay time silent mode
Td_sleep = maximum 20 µs
LIN
LIN switches directly to recessive mode
Figure 4-3. LIN Wake-up Waveform Diagram from Silent Mode
Normal Mode
Pre-normal Mode
LIN Bus
RXD
Low or floating
Low
Bus wake-up filtering
time T
bus
VCC
Silent mode
Pre-normal mode
Normal mode
EN High
Regulator Wake-up Time
Node ln silent mode
EN
NRES
If undervoltage switch to pre-normal mode
Undervoltage detection active
6
ATA6620 [Preliminary]
4850A–AUTO–02/05
ATA6620 [Preliminary]
4.3
Sleep Mode
A falling edge at EN while TXD is low switches the IC into Sleep mode. The TXD Signal has to
be logic low during the Mode Select window (Figure 4-4 on page 8). We recommend using the
same microcontroller port for EN as for TXD; in this case the mode change is only one
command.
In Sleep mode the transmission path is disabled. Supply current from VBatt is typically
IVSsleep = 10 µA. The VCC regulator is switched off; NRES and RXD are low. The internal slave
termination between pin LIN and pin VS is disabled to minimize the power dissipation in case pin
LIN is short-circuited to GND. Only a weak pull-up current (typically 10 µA) between pin LIN and
pin VS is present.
A falling edge at pin LIN followed by a dominant bus level maintained for a certain time period
(Tbus) results in a remote wake-up request. The device switches from Sleep mode to Pre-normal
mode. The VCC regulator is activated and the internal LIN slave termination resistor is switched
on. The remote wake-up request is indicated by a low level at pin RXD to interrupt the microcon-
troller. (Figure 4-5 on page 8)
With EN high you can switch directly from Silent to Normal mode. In the application where the
ATA6620 supplies the microcontroller, the wake-up from Sleep mode is only possible via pin
LIN.
4.4
4.5
Pre-normal Mode
At system power-up the device automatically switches to Pre-normal mode. The voltage regula-
tor is switched on (VCC = 5V/50 mA) (see Figure 4-4 on page 8) after typically tVCC = 1 ms. The
NRES output switches to low for tres = 10 ms and sends a reset to the microcontroller. LIN com-
munication is switched off, and the undervoltage detection is active.
A power-down of VBatt (VS < 4V) during Silent or Sleep mode switches into Pre-normal mode
after powering up the IC.
Unpowered Mode
If battery voltage is connected to the application circuit (Figure 4-6 on page 9), the voltage at the
VS pin increases due to the block capacitor. When VS is higher than the VS undervoltage thresh-
old, VSth, the IC-mode changes from Unpowered to Pre-normal mode. The VCC output voltage
reaches nominal value after tVCC. This time depends on the VCC capacitor and the load.
NRES is low for the reset time delay tReset; no mode change is possible during this time.
7
4850A–AUTO–02/05
Figure 4-4. Switch to Sleep Mode
Sleep Mode
Normal Mode
EN
Mode select window
TXD
Td = 3.2 µs
NRES
VCC
Delay time sleep mode
T
d_sleep = maximum 20 µs
LIN
LIN switches directly to recessive mode
Figure 4-5. LIN Wake-up Diagram from Sleep Mode
Normal Mode
Pre-normal Mode
LIN Bus
RXD
Low or floating
Low
Bus wake-up filtering time
Tbus
On state
Off state
Regulator wake-up time
EN High
EN
Node in sleep mode
Low or floating
Reset
time
NRES
Microcontroller start-up
time delay
8
ATA6620 [Preliminary]
4850A–AUTO–02/05
ATA6620 [Preliminary]
Figure 4-6. VCC Voltage Regulator: Ramp Up and Undervoltage
VS
12V
5.5V
3V
VCC
5V
Vthun
NRES
Tes_f
TVCC
Tres
5V
5. Fail Safe Features
• During a short circuit at LIN, the output limits the output current to IBUS_LIM. Due to the power
dissipation, the chip temperature exceeds TLINoff and the LIN output is switched off. The chip
cools down and after a hysteresis of Thys, switches the output on again. During LIN
overtemperature switch-off, the VCC regulator works independently.
• There are now reverse currents < 3 µA at pin LIN during loss of VBatt or GND. This is optimal
behavior for bus systems where some slave nodes are supplied from battery or ignition.
• During a short circuit at VCC, the output limits the output current to IVCCn. Because of
undervoltage, NRES switches to low and sends a reset to the microcontroller. The IC
switches into Pre–normal mode. If the chip temperature exceeds the value TVCCoff, the VCC
output switches off. The chip cools down and after a hysteresis of Thys, switches the output on
again. Because of Pre-normal mode, the VCC voltage will switch on again although EN is
switched off from the microcontroller.The microcontroller can then start with normal
operation.
• Pin EN provides a pull-down resistor to force the transceiver into recessive mode if EN is
disconnected.
• Pin RXD is set floating if VBatt is disconnected.
• Pin TXD provides a pull-up resistor to force the transceiver into recessive mode if TXD is
disconnected.
9
4850A–AUTO–02/05
6. Voltage Regulator
The voltage regulator needs an external capacitor for compensation and to smooth the distur-
bances from the microcontroller. It is recommend to use an electrolytic capacitor with C > 1.8 µF
and a tantalum capacitor with C = 100 nF. The values of these capacitors can be varied by the
customer, depending on the application.
During mode change from Silent to Normal mode, the voltage regulator ramps up to 6V for only
a few microseconds before it drops back to 5V. This behavior depends on the value of the load
capacitor. With 4.7 µF, the overshoot voltage has its greatest value. This voltage decreases with
higher or lower load capacitors.
With this special SO8 package (fused lead frame to pin3) an Rthja of 100 K/W is achieved.
Therefore it is recommended to connect pin 3 with a wide GND plate on the printed board to get
a good heat sink.
The main power dissipation of the IC is created from the VCC output current IVCC, which is
needed for the application.
Figure 6-1 shows the safe operating area of the ATA6620.
Figure 6-1. Save Operating Area versus VCC Output Current and Supply Voltage VS at Differ-
ent Ambient Temperatures
60.00
IOUT, Tamb = 85°C
50.00
40.00
IOUT, Tamb = 105°C
30.00
20.00
IOUT, Tamb = 95°C
10.00
0.00
5
6
7
8
9
10
11
12 13 14
15 16
17 18
VS /V
10
ATA6620 [Preliminary]
4850A–AUTO–02/05
ATA6620 [Preliminary]
7. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Min.
Typ.
Max.
Unit
VS
- Continuous supply voltage
–0.3
–0.3
+40
V
V
Logic pins (RxD, TxD, EN, NRES)
+6.5
LIN
- DC voltage
- Transient voltage
–40
–150
+60
+100
V
V
VCC
- DC voltage
–0.3
–6
+6.5
+6
V
ESD (DIN EN 6100–4–2)
Pin LIN, VS versus GND according to LIN
specification EMC Evaluation V 1.3
kV
kV
HBM ESD S5.1 – all pins
–2
+2
CDM ESD STM 5.3.1–1999
- All pins
–500
–40
–55
–40
+500
+150
+150
+125
V
Junction temperature
Tj
Ts
Ta
°C
°C
°C
Storage temperature
Operating ambient temperature
Thermal resistance junction to ambient
(free air)
Rthja
145
K/W
Special heat sink at GND (pin 3) on PCB
Thermal shutdown of VCC regulator
Thermal shutdown of LIN output
Thermal shutdown hysteresis
Rthja
TVCCoff
TLINoff
Thys
100
175
175
K/W
°C
155
155
165
165
7
°C
°C
11
4850A–AUTO–02/05
8. Electrical Characteristics
5V < VS < 18V, Tamb = –40°C to 125°C
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
1
VS Pin
Nominal DC voltage
range
1.1
VS
VS
5
13.5
18
V
A
Sleep mode
Supply current in Sleep
mode
V
V
lin > VBatt – 0.5V
Batt < 14V
1.2
1.3
VS
VS
IVSsleep
10
40
20
50
µA
µA
A
A
(25°C to 125°C)
Bus recessive;
VBatt < 14V
(25°C to 125°C)
Supply current in Silent
mode
IVSsi
Without load at VCC
Supply current in
Normal mode
Bus recessive
Without load at VCC
1.4
1.5
1.6
1.7
1.8
VS
VS
VS
VS
VS
VS
IVSrec
IVSdom
PORth
PORhys
VSth
4
mA
mA
V
A
A
D
D
A
A
Supply current in
Normal mode
Bus dominant
55
3.3
V
CC load current 50 mA
Power On Reset
threshold
3
Power On Reset
threshold hysteresis
0.1
4.5
0.2
V
VS undervoltage
threshold
4.0
5
V
VS undervoltage
threshold hysteresis
1.9
VSth_hys
V
2
RXD Output Pin
Normal mode;
2.1
Low level input current VLIN = 0V
VRXD = 0.4V
RXD
IRXD
2
5
5
8
mA
A
2.2
2.3
2.4
3
Low level output voltage IRXD = 1 mA
High level output voltage IRXD = –1 mA
Internal resistor to VCC
RXD
RXD
RXD
VRXDL
VRXDH
RRXD
0.4
V
V
A
A
A
4.2
3
7
kΩ
TXD Input Pin
3.1
Low level voltage input
TXD
TXD
TXD
TXD
VTXDL
VTXDH
RTXD
ITXD
–0.3
3.5
+1.5
V
V
A
A
A
A
VCC
+
3.2
3.3
3.4
High level voltage input
0.3V
Pull-up resistor
VTXD = 0V
TXD = 5V
125
–3
250
600
kΩ
µA
High level leakage
current
V
+3
4
EN Input Pin
4.1
Low level voltage input
EN
EN
VENL
VENH
–0.3
3.5
+1.5
V
V
A
A
VCC
+
4.2
High level voltage input
0.3V
4.3
4.4
Pull-down resistor
VEN = 5V
EN
EN
REN
IEN
125
–3
250
600
+3
kΩ
A
A
Low level input current VEN = 0V
µA
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
12
ATA6620 [Preliminary]
4850A–AUTO–02/05
ATA6620 [Preliminary]
8. Electrical Characteristics (Continued)
5V < VS < 18V, Tamb = –40°C to 125°C
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
5
NRES Output Pin
VS ≥ 5.5V;
INRES = –1 mA
5.1
High level output voltage
Low level output voltage
Low level output low
NRES
NRES
NRES
NRES
NRES
VNRESH
VNRESL
VNRESLL
tReset
4.2
V
V
A
A
A
A
A
VS ≥ 5.5V;
5.2
5.3
5.4
0.4
0.2
13
5
INRES = –1 mA
10 kΩ to VCC;
VCC = 0.8V
V
V
VS ≥ 5.5V
Undervoltage reset time
7
ms
µs
CNRES = 20 pF
Reset debounce time for VVS ≥ 5.5V
falling edge NRES = 20 pF
5.5
6
tres_f
C
Voltage Regulator VCC Pin in Normal and Pre-normal Mode
5.5V < VS < 18V
(0 mA – 50 mA)
6.1
Output voltage VCC
VCC
VCC
VCCnor
VCClow
4.9
5.1
5.1
V
V
A
A
Output voltage VCC at
low VS
3.3V < VS < 5.5V
(0 mA – 50 mA)
VVS
– VD
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Regulator drop voltage VS > 4.0V, IVCC = 20 mA
Regulator drop voltage VS > 4.0V, IVCC = 50 mA
Regulator drop voltage VS > 3.3V, IVCC = 15 mA
VCC
VCC
VCC
VCC
VCC
VCC
VD
VD
250
500
200
mV
mV
mV
mA
mA
µF
A
A
A
A
A
A
VD
Output current
VS > 3V
IVCC
IVCCs
Cload
–50
–200
1.8
Output current limitation VS > 0V
–130
2.2
Load capacity
ESR < 5Ω
VCC undervoltage
threshold
Referred to VCC
VS > 5.5V
6.9
VCC
VCC
VCC
VthunN
Vhysthun
tVCC
4.4
40
4.8
V
A
A
A
Hysteresis of
undervoltage threshold VS > 5.5V
Referred to VCC
6.10
mV
ms
Ramp up time VS > 5.5V CVCC = 2.2 µF
to VCC > 4.9V
6.11
7
1
2
Rload at VCC: 100Ω
Voltage Regulator VCC Pin in Silent Mode
5.5V < VS < 18V
Output voltage VCC
7.1
VCC
VCCnor
4.65
5.35
V
A
(0 mA – 50 mA)
Output voltage VCC at
low VS
3.3V < VS < 5.5V
(0 mA – 50 mA)
VVS
– VD
7.2
7.3
VCC
VCC
VCClow
VD
5.1
V
A
A
Regulator drop voltage VS > 3.3V, IVCC = 15 mA
200
mV
At VCC undervoltage
threshold the state
switches back to
Pre-normal mode
Referred to VCC
VS > 5.5
7.4
VCC
VthunS
3.9
4.4
V
A
Hysteresis of
undervoltage
threshold
Referred to VCC
VS > 5.5V
7.5
7.6
VCC
VCC
Vhysthun
IVCCs
40
mV
mA
D
A
Output current limitation VS > 0V
–200
–130
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
13
4850A–AUTO–02/05
8. Electrical Characteristics (Continued)
5V < VS < 18V, Tamb = –40°C to 125°C
No. Parameters
LIN Bus Driver: Bus Load Conditions:
Load 1 (Small): 1 nF, 1 kΩ; Load 2 (Large): 10 nF, 500Ω; RRXD = 5 kΩ; CRXD = 20 pF
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
8
10.5, 10.6 and 10.7 Specifies the Timing Parameters for Proper Operation at 20 Kbps
Driver recessive output VTXD = 0V;
8.1
8.2
8.3
8.4
8.5
8.6
LIN
LIN
LIN
LIN
LIN
LIN
VBUSrec
V_LoSUP
V_HiSUP
V_LoSUP_1k
V_HiSUP_1k
RLIN
0.9 × VS
VS
1.2
2
V
V
A
A
A
A
A
A
voltage
ILIN = 0 mA
V
VS = 7.3V
Driver dominant voltage
Rload = 500 Ω
VVS = 18V
Driver dominant voltage
Driver dominant voltage
Driver dominant voltage
Pull–up resistor to VS
V
Rload = 500 Ω
VVS = 7.3V
Rload = 1000 Ω
0.6
0.8
20
V
VVS = 18V
V
Rload = 1000 Ω
The serial diode is
mandatory
30
60
kΩ
Self-adapting current
limitation
VBUS = VBatt_max
Tj = 125°C
Tj = 27°C
Tj = –40°C
52
100
150
110
170
230
mA
mA
mA
8.7
8.8
LIN
LIN
IBUS_LIM
A
A
Input leakage current at Input Leakage current
the receiver including
pull–up resistor as
specified
Driver off
VBUS = 0V
VBatt = 12V
IBUS_PAS_dom
–1
mA
µA
Driver off
8V < VBatt < 18V
8V < VBUS < 18V
Leakage current LIN
recessive
8.9
LIN
LIN
IBUS_PAS_rec
15
20
A
A
VBUS ≥ VBatt
Leakage current when
control unit
disconnected from
ground.
Loss of local ground
must not affect
communication in the
residual network
GNDDevice = VS
VBatt = 12V
0V < VBUS < 18V
8.10
IBUS_NO_gnd
–10
+0.5
+10
µA
µA
Node has to sustain the
current that can flow
under this condition.
Bus must remain
operational under this
condition
VBatt disconnected
VSUP_Device = GND
0V < VBUS < 18V
8.11
LIN
IBUS
0.5
3
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
14
ATA6620 [Preliminary]
4850A–AUTO–02/05
ATA6620 [Preliminary]
8. Electrical Characteristics (Continued)
5V < VS < 18V, Tamb = –40°C to 125°C
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
9
LIN Bus Receiver
Center of receiver
threshold
VBUS_CNT
(Vth_dom + Vth_rec)/2
=
0.475 ×
0.5 ×
VS
0.525 ×
9.1
LIN
VBUS_CNT
V
A
VS
VS
9.2
9.3
Receiver dominant state VEN = 5V
Receiver recessive state VEN = 5V
Receiver input
LIN
LIN
VBUSdom
VBUSrec
–27
0.4 × VS
V
V
A
A
0.6 × VS
40
0.028 ×
0.175 ×
9.4
9.5
9.6
V
hys = Vth_rec – Vth_dom
LIN
LIN
VBUShys
VLINH
VLINL
ILIN
0.1 x VS
V
V
A
A
hysteresis
VS
VS
Wake detection LIN
High level input voltage
VS – 1V
VS + 0.3V
VS – 3V
Wake detection LIN
Low level input voltage
ILIN = typically –3 mA
VS < 27V
LIN
LIN
–27
–30
V
A
A
9.7
LIN pull-up current
–10
90
µA
10
Internal Timers
Dominant time for
wake–up via LIN bus
10.1
10.2
VLIN = 0V
VEN = 5V
tbus
30
1
150
10
µs
µs
A
A
Time delay for mode
change from Pre-normal
into Normal mode via
pin EN
tnorm
5
Time delay for mode
change from Normal
mode to Sleep mode via
pin EN
10.3
10.4
VEN = 0V
tsleep
2
5
7
12
20
µs
A
A
TXD dominant time out
timer
VTXD = 0V
tdom
10
ms
THRec(max) = 0.744 × VS;
THDom(max) = 0.581 × VS;
VS = 7.0V to 18V;
tBit = 50 ms
D1 = tbus_rec(min)/(2 × tBit)
10.5 Duty cycle 1
10.6 Duty cycle 2
D1
D2
0.396
A
THRec(min) = 0.422 × VS;
THDom(min) = 0.284 × VS;
VS = 7.0V to 18V;
0.581
22.5
A
A
tBit = 50ms
D2 = tbus_rec(max)/(2 × tBit)
Slope time falling and
rising edge at LIN
tSLOPE_fall
tSLOPE_rise
10.7
11
3.5
µs
Receiver Electrical AC Parameters of the LIN Physical Layer
LIN Receiver, RXD Load Conditions (CRXD): 20 pF; Rpull-up = 2.4 kΩ
Propagation delay of
receiver Figure 4-4
trec_pd
max(trx_pdr, trx_pdf
=
11.1
trx_pd
6
µs
µs
A
A
)
Symmetry of receiver
11.2 propagation delay rising trx_sym = trx_pdr – trx_pdf
edge minus falling edge
trx_sym
–2
+2
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
15
4850A–AUTO–02/05
Figure 8-1. Definition of Bus Timing Characteristics
tBit
tBit
tBit
TXD
(Input to transmitting Node)
tBus_rec(min)
tBus_dom(max)
Thresholds of
THRec(max)
receiving node 1
THDom(max)
VS
(Transceiver supply
of transmitting node)
LIN Bus Signal
Thresholds of
THRec(min)
THDom(min)
receiving node 2
tBus_dom(min)
tBus_rec(max)
RXD
(Output of receiving Node1)
trx_pdf(1)
trx_pdr(1)
RXD
(Output of receiving Node2)
trx_pdr(2)
trx_pdf(2)
16
ATA6620 [Preliminary]
4850A–AUTO–02/05
ATA6620 [Preliminary]
Figure 8-2. Application Circuit
VBAT
1
VCC
ATA6620
Normal
VS
22 µF
RXD
5
and
Pre-normal
Mode
100 nF
Receiver
LIN
4
LIN-BUS
Filter
220 pF
VCC
Wake Up Bus Timer
Slew Rate Control
Short-circuit and
Overtemperature
Protection
TXD
6
TXD
Time-out
Timer
VCC
8
Normal Mode
Voltage Regulator
5V/50 mA
Sleep
Mode
VCC
Control
Unit
EN
2
NRES
7
Undervoltage Reset
Switched
Off
Silent Mode
Voltage Regulator
5V/10%
GND
3
22 µF
100 nF
17
4850A–AUTO–02/05
9. Ordering Information
Extended Type Number
Package
Remarks
ATA6620-TAQY
SO8
LIN System Basis Chip
10. Package Information
Package SO8
Dimensions in mm
5.2
4.8
5.00
3.7
4.85
1.4
0.25
0.2
0.4
3.8
0.10
1.27
6.15
5.85
3.81
8
5
technical drawings
according to DIN
specifications
1
4
18
ATA6620 [Preliminary]
4850A–AUTO–02/05
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