ATDH40D240 [ATMEL]
Programmable System Level Integration Prototyping System;型号: | ATDH40D240 |
厂家: | ATMEL |
描述: | Programmable System Level Integration Prototyping System |
文件: | 总13页 (文件大小:507K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Features
• Hardware
– Supports Programming for Atmel AT40K/AT40KAL and AT94KALSeries of
SRAM-based Programmable System Level Integration (PSLI) Devices
– Supports ISP (In-System Programming) for Atmel AT17 Series Configuration
EEPROMs
– Built-in Clock Source with GCLK/FCLK Jumper Settings
– Supports Modular Docking Platform for the ATDH40D FPGA Daughter Boards
– Runs Off Portable 9V DC Power Supply or External Power
– Supports 5.0V or 3.3V Supply
– Designed to Work with Atmel IDS 5.0 or Above
– Downloading for AT40K/AT17 Devices Direct from PC Parallel Port
– Can be Used to Support FPSLIC
Programmable
System Level
Integration
Prototyping
System
• System Contents
– ATDH2081
25-pin Parallel to 10-pin Header Adapter
– ATDH40Dxxx
Package-specific Daughterboard (Variable)
– ATDH40M
Programming Motherboard
– Standard Parallel Cable (PC Parallel Port DB25), 10-pin Header Cable,
9V DC/200 mA, 2.1 mm Center Positive Power Supply
ATDH40M
Description
ATDH40DXXX
The Atmel ATDH40M prototyping system allows designers to quickly and economi-
cally evaluate Atmel’s family of AT40K/AT40KAL FPGA and AT94K Field
Programmable System Level Integrated Circuit (FPSLIC™) devices and Atmel’s AT17
FPGA configuration memory devices. The ATDH40M board connects to any x86 PC
via parallel port through a 10-pin header cable to program the AT40K/AT40KAL
FPGA/AT94K FPSLIC, or through a parallel port cable to program the AT17 FPGA
Configuration EEPROMs. The motherboard interfaces with various daughter boards
in order to program different package footprints (see Table 1).
Table 1. Daughter Board Support List
Part Number
ATDH40D84
Description
84-pin Plastic Lead Chip Carrier
100-pin Very Thin Quad Flat Pack
100-pin Rectangular Quad Flat Pack
144-pin Thin Quad Flat Pack
160-pin Plastic Quad Flat Pack
208-pin Plastic Quad Flat Pack
240-pin Plastic Quad Flat Pack
ATDH40D100
ATDH40D100R
ATDH40D144
ATDH40D160
ATDH40D208
ATDH40D240
Rev. 1402B–06/01
The AT40K/AT40KAL FPGA devices are pin-compatible in
a given package footprint across the family. See Table 2 for
compatibility listings. The 208PQFP, for example, will sup-
port all AT40K family members.
FPSLIC is pin-compatible with AT40K/AT40KAL device
families and is supported by the ATDH40M Prototyping
System.
Table 2. Part and Package Availability Showing User I/O Counts
AT40K05/
AT40K05AL/
AT94K05AL
AT40K10
AT40K10AL
AT94K10AL
AT40K40/
AT40K40AL
AT94K40AL
AT40K20/
AT40K20AL
Package
PC84
Ordering Code
AJ
AQ
RQ
BQ
CQ
DQ
AG
EQ
FQ
BG
CG
62
78
78
114
128
128
-
62
78
78
114
130
161
192
192
-
62
-
62
-
VQ100
RQ100
TQ144
77
-
114
130
161
192
193
256
256
-
114
-
PQ160
PQ208
161
192
193
256
289
352
BG225(1)
PQ240
-
PQ304(1)
BG352(1)
BG432(1)
-
-
-
-
-
Note:
1. Daughtercard not available for ATDH40M.
2. Not all devices are available in all package options. Please check appropriate datasheet for a list of valid part/package
combinations.
Programming Setup
Figure 1 on page 3 is the board layout of the ATDH40M motherboard. Figure 2 shows the typical daughter board. To con-
nect the two boards together, the daughter board fits on top of the motherboard by aligning the two arrows together. The
two boards will only fit one way.
ATDH40M/D
2
ATDH40M/D
Figure 1. Motherboard Layout – ATDH40M
3
Figure 2. Daughter Board Layout Example – ATDH40D84
Power Configuration
Program/Boot Settings
Power for the motherboard can come from two sources. It
can be supplied by either the jack inputs J1 and J2, or by a
9V power input P1. The source that will drive the mother-
board is determined by switch SW3. Power supplied by the
jacks uses the external setting. Power supplied by the
9V source uses the internal setting. Voltage on the
motherboard for the latter setting is regulated by switch
SW2. LV parts use the 3.3V setting while the rest use the
5.0V setting. The LED L1 will light up only when power is
correctly supplied to VCC. Table 3 lists the possible
configurations. AT40KAL and AT94KAL devices must use
3.5V power setting.
Switches SW4 and SW5 determine the program and boot
settings for the ATDH40M. They are located on the bottom
left corner. Table 4 lists the switch combinations and their
effects. SW4 controls the SEREN signal line of the mother-
board to the 2:1 multiplexer (device U3) and the AT17
(device U1). SW% connects signal D0 from the PSLI
device to either the AT17 configuration memory device only
(down) or to the PC interface (up).
Table 4. Programming Modes
SW4
Up
SW5
Up
Effect
Program in Slave Serial from PC
Program AT17 Configuration Memory
Table 3. Motherboard Power Distribution
Down
Up
Up
SW1
Off
SW2
X
SW3
X
Voltage
Down Program in Master Serial from AT17
0.0V (no power)
Variable
On
X
External
Internal
On
3.3V
3.3V for
AT40KAL/AT94KAL
On
5.0V
Internal
5.0V for AT40K
ATDH40M/D
4
ATDH40M/D
Programming the AT40K FPGA Device
Troubleshooting
When SW4 and SW5 are set to up, the PSLI device can be
programmed by the PC parallel interface. The ATDH40M
interfaces with the PC through the 10-pin header socket H1
located on the bottom right corner. Programming the FPGA
is not possible by using the parallel port interface on the
motherboard. Located below the header H1 are the mode-
select dip-switches DIP-SW1. These control the mode set-
tings for the PSLI device (switches M0, (M1), M2). The
modes directly supported by the motherboard are only
Slave Serial and Master Serial. Programming the AT40K
FPGA from the PC can be achieved from the IDS desktop
or by using the software downld40.exe. Both tools accept
ASCII bitstream files generated by the IDS software (.BST).
1. Check that the motherboard is connected to the PC
either through the parallel port or through the 10-pin
header.
2. Check that the motherboard has power (SW1) and
the power configuration switches SW2 and SW3
are correct.
3. Make sure programming configuration switches
SW4 and SW5 are correct.
4. Verify that the daughter card is inserted correctly
and that it receives power.
5. Verify that the PSLI device and/or the PSLI.
Configurator are placed in their sockets correctly.
6. Set the mode switches before downloading to
the PSLI Device.
Programming the AT17 Configuration
Memory Device
7. Set the GCLK/FCLK jumpers before verifying
PSLI logic.
When SW4 is set to down and SW5 is set to up, the AT17
FPGA configuration memory can be programmed by the
parallel port interface located on the top left corner.
Programming the AT17 FPGA Configuration EEPROM is
not possible by using the 10-pin header H1. Programming
the AT17 FPGA Configuration EEPROM from the PC can
be achieved from the IDS desktop or by using the Configu-
rator Programming System (CPS) software supplied by the
IDS software.This software accepts the ASCII bitstream
files (.BST) generated by IDS.
Technical Support
• Check each of the items listed in the troubleshooting
section.
• Contact your local Atmel Representative or Distributor
who provided the PSLI board for technical support.
• Contact your local Atmel FAE (available at most sales
offices).
• Contact the Atmel PSLI technical support hotline at (408)
436-4119. Hours are Monday-Friday 9:00 a.m. – 6:00
p.m. PST.
Programming the PSLI Device Using
the AT17 Configuration Memory
When SW4 is set to up and SW5 is set to down, the AT17
Configurator can program the FPGA in Master Serial. To
ensure reliable system power-up, set jumper JMP1
(located below the Configurator socket). The Configurator
must be programmed prior to this setup.
• E-mail Atmel PSLI technical support at
fpga@atmel.com.
• Fax inquiries to “FPGA Tech Support” at (408) 487-2637
5
U2
Install either R4 or R1
LM317T
IN
OUT
R2
2.4K
ADJ
C1
C2
.01uF
1uF
R4
3.3K
R1
1.0K
Master Power
On/Off
U1
7805T
DC Power Pack
P1
D1
VI
VO
SW1
1N4001
GND
DC PWR
5.0V DC
500mA
5.0V
SW2 - SPDT
VCC
J1
3.3V
User Supplied
Power
VCC
J2
GND
Internal
L1
R3
220 Ohms
D2
SW3 - SPDT
External
LED
1N4001
VCC
SW6
Push Button Reset
R13
4.7K
C1
.01uF
ATMEL CORPORATION
Title:
AT40K Motherboard (Power Supply)
Document Number:
CHW 5310 (ATDH40M)
May 26, 1998
Sheet:
Size:
A
Date:
Rev: 2
Motherboard /RESET
Note: The voltage regulators LM317T & 7805T allow to switch between 3.3V and 5V.
1 OF 3
H1
DI
CI
DO
GND
NC
CON
CO
ERR
VCC
CHECK
1
3
5
7
9
2
4
6
8
10
Q1
4.00 MHz
VCC
1
7
8
NC
GND
14
VCC
OUT
H2
GCK1
GCK2
GCK3
GCK4
GCK5
GCK6
GCK7
GCK8
FCK1
FCK2
FCK3
FCK4
1
3
5
7
9
2
4
6
8
10
VCC
11 12
13 14
15 16
17 18
19 20
21 22
23 24
R11
I/O (CS0)
I(M2)
4.7K
R10
4.7K
R9
O(M1)
I(M0)
4.7K
R8
4.7K
PULL-UP
GND
S1
SW DIP-4
1
2
3
4
8
7
6
5
ATMEL CORPORATION
Title:
AT40K Motherboard (Mode and Clock Switches)
Document Number:
Size:
A
Rev: 2
2 OF 3
CHW 5310 (ATDH40M)
Date:
May 26, 1998
Sheet:
Note: The 12-pin header (H2) is used to connect the clocks with the jumpers. The DIP switch (S1) is used to set the different modes.
VCC
VCC
VCC
U1
DATA
CLK
RESET/OE*
CE*
R5
1
3
5
7
2
4
6
4.7K
WP1
WP2
8
GND
R12
4.7K
R6
4.7K
9
10
12
14
16
18
20
U2
11
13
15
17
19
D7
SELECT IN*
INIT*
2
4
6
3
5
7
9
CLK
RESET/OE*
CE*
CEO*
VCC
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
READY
SER_EN*
10
ACK*
20-PIN PLCC
AT17CXXX
12
14
11
R7
4.7K
2A1
2A2
2Y1
2Y2
13 DATA
1
1G
2G
D0 15
U3
GND
DATA_IN
SCLK
CCLK
RESET/OE 11
INIT 10
2
3
5
6
4
7
9
D0
1A
1B
2A
2B
3A
3B
4A
4B
1Y
2Y
3Y
4Y
74LS367
CLK
RESET/OE
CE 14
CON 13
12 CE
C3
P1
SEREN
1
15
16 VCC
.01uf
A*/B
G
8
GND
1
STROBE*
14 AUTO FEED*
D0
15 ERROR*
D1
16 INIT*
D2
17 SELECT IN*
D3
18 GND
D4
19 GND
D5
20 GND
D6
21 GND
UP - FPGA
SW4 - SPDT
DOWN - PROGRAM
2
74HCT157
DIP 16
3
4
5
CCLK
6
INIT
CON
D0
7
AT40K
8
UP
9
D7
MOTHERBOARD D0
22 GND
10 ACK*
23 GND
11 BUSY
24 GND
12 PE
SW5 - SPDT
DOWN
RESET
ATMEL CORPORATION
25 GND
13 SELECT
J1
Title:
AT40K Motherboard (Configuration and Multiplexing)
Document Number:
JUMPER
Size:
A
Date:
Rev: 2
3 OF 3
DB25
CHW 5310 (ATDH40M)
May 26, 1998
Sheet:
ATDH40M/D
ATDH40M Layout Schematics
Configurator/Multiplexing/Buses
C T 1 7 5 4 7 H
6 7
7 4 L S 3
9
Buses
ATDH40M/D
10
ATDH40M/D
Power Supply
G N D
A D J
1
11
PWR
1
14
15
16
17
18
19
20
21
22
23
24
25
AUTO FEED*
D0
2
10K
3
INIT*
4
SELECT IN*
5
VDD
6
DI
CI
DO
GND
NC
CON
CO
ERR
VCC
NC
1
3
5
7
9
2
4
6
8
10
7
8
GND
74C14
9
D7
10K
10
11
12
13
ACK*
PWR
0.1uF
ATMEL CORPORATION
Title:
Download Cable - 25 to 10 Way Adapter
Document Number:
Size:
A
Rev: 1
1 of 1
ATDH2081
Date:
Sep 1, 1998
Sheet:
Atmel Headquarters
Atmel Operations
Corporate Headquarters
2325 Orchard Parkway
San Jose, CA 95131
TEL (408) 441-0311
FAX (408) 487-2600
Atmel Colorado Springs
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL (719) 576-3300
FAX (719) 540-1759
Europe
Atmel Rousset
Zone Industrielle
13106 Rousset Cedex
France
Atmel U.K., Ltd.
Coliseum Business Centre
Riverside Way
Camberley, Surrey GU15 3YL
England
TEL (33) 4-4253-6000
FAX (33) 4-4253-6001
TEL (44) 1276-686-677
FAX (44) 1276-686-697
Asia
Atmel Asia, Ltd.
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimhatsui
East Kowloon
Hong Kong
TEL (852) 2721-9778
FAX (852) 2722-1369
Japan
Atmel Japan K.K.
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
Atmel FPGA Hotline
1-(408) 436-4119
Fax-on-Demand
North America:
1-(800) 292-8635
Atmel FPGA e-mail
fpga@atmel.com
International:
1-(408) 441-0732
FAQ
e-mail
literature@atmel.com
Available on web site
Web Site
http://www.atmel.com
BBS
1-(408) 436-4309
© Atmel Corporation 2001.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-
ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-
erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are
not authorized for use as critical components in life support devices or systems.
FPSLIC is the trademark of Atmel.
Printed on recycled paper.
Other terms and product names may be trademarks of others.
1402B–06/01/xM
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