ATF1500ASV-15AC100 [ATMEL]
Low-voltage, Complex Programmable Logic Device; 低电压，复杂可编程逻辑器件
| 型号： | ATF1500ASV-15AC100 |
| 厂家： | 
ATMEL |
| 描述： | Low-voltage, Complex Programmable Logic Device |
| 文件： | 总29页 (文件大小：312K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High-density, High-performance, Electrically-erasable Complex
Programmable Logic Device
– 3.0 to 3.6V Operating Range
– 64 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 44, 68, 84, 100 Pins
– 15 ns Maximum Pin-to-pin Delay
– Registered Operation up to 77 MHz
– Enhanced Routing Resources
• In-System Programmability (ISP) via JTAG
• Flexible Logic Macrocell
Low-voltage,
Complex
Programmable
Logic Device
– D/T/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open-collector Option
– Maximum Logic Utilization by Burying a Register with a COM Output
• Advanced Power Management Features
– Automatic 5 µA Standby for “L” Version
– Pin-controlled 100 µA Standby Mode (Typical)
– Programmable Pin-keeper Circuits on Inputs and I/Os
– Reduced-power Feature per Macrocell
• Available in Commercial and Industrial Temperature Ranges
• Available in 44-, 68-, and 84-lead PLCC; 44- and 100-lead TQFP; and 100-lead PQFP
• Advanced EE Technology
ATF1504ASV
ATF1504ASVL
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
• JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
• PCI-compliant
• Security Fuse Feature
Enhanced Features
• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
• Output Enable Product Terms
• Transparent-latch Mode
• Combinatorial Output with Registered Feedback within Any Macrocell
• Three Global Clock Pins
• ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
• Fast Registered Input from Product Term
• Programmable “Pin-keeper” Option
• VCC Power-up Reset Option
• Pull-up Option on JTAG Pins TMS and TDI
• Advanced Power Management Features
– Edge-controlled Power-down “L”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O
Rev. 1409I–PLD–2/03
44-lead PLCC
Top View
44-lead TQFP
Top View
TDI/I/O
I/O
7
8
9
39 I/O
38 I/O/TDO
37 I/O
I/O/TDI
I/O
1
2
3
4
5
6
7
8
9
33 I/O
I/O
32 I/O/TDO
31 I/O
GND 10
PD1/I/O 11
I/O 12
36 I/O
I/O
35 VCC
34 I/O
GND
PD1/I/O
I/O
30 I/O
29 VCC
28 I/O
I/O/TMS 13
I/O 14
33 I/O
32 I/O/TCK
31 I/O
TMS/I/O
I/O
27 I/O
VCC 15
I/O 16
26 I/O/TCK
25 I/O
30 GND
29 I/O
VCC
I/O 17
I/O 10
I/O 11
24 GND
23 I/O
68-lead PLCC
Top View
84-lead PLCC
Top View
I/O 12
VCCIO 13
I/O/TDI 14
I/O 15
74 I/O
I/O 10
60 I/O
73 I/O
VCCIO 11
I/O/TD1 12
I/O 13
59 I/O
72 GND
71 I/O/TDO
70 I/O
58 GND
57 I/O/TDO
56 I/O
I/O 16
I/O 14
I/O 17
69 I/O
I/O 15
55 I/O
I/O 18
68 I/O
GND 16
I/O/PD1 17
I/O 18
54 I/O
GND 19
I/O/PD1 20
I/O 21
67 I/O
53 VCCIO
52 I/O
66 VCCIO
65 I/O
I/O/TMS 19
I/O 20
51 I/O
I/O 22
64 I/O
50 I/O/TCK
49 I/O
VCCIO 21
I/O 22
I/O/TMS 23
I/O 24
63 I/O
48 GND
47 I/O
62 I/O/TCK
61 I/O
I/O 23
I/O 25
I/O 24
46 I/O
VCCIO 26
I/O 27
60 I/O
I/O 25
45 I/O
59 GND
58 I/O
GND 26
44 I/O
I/O 28
I/O 29
57 I/O
I/O 30
56 I/O
I/O 31
55 I/O
GND 32
54 I/O
2
ATF1504ASV(L)
1409I–PLD–2/03
ATF1504ASV(L)
100-lead TQFP
Top View
100-lead PQFP
Top View
NC
NC
1
2
3
4
5
6
7
8
9
75 I/O
NC
NC
1
2
3
4
5
6
7
8
9
80 NC
79 NC
78 I/O
77 I/O
76 GND
75 I/O/TDO
74 NC
73 I/O
72 NC
71 I/O
70 I/O
69 I/O
68 VCCIO
67 I/O
66 I/O
65 I/O
64 I/O/TCK
63 I/O
62 I/O
61 GND
60 I/O
59 I/O
58 I/O
57 NC
56 I/O
55 NC
54 I/O
53 VCCIO
52 NC
51 NC
74 GND
73 I/O/TDO
72 NC
71 I/O
VCCIO
I/O/TDI
NC
I/O
I/O
VCCIO
I/O/TDI
NC
I/O
70 NC
69 I/O
NC
I/O
68 I/O
I/O
I/O
67 I/O
NC
I/O 10
GND 11
I/O/PD1 12
I/O 13
66 VCCIO
65 I/O
I/O 10
I/O 11
64 I/O
I/O 12
63 I/O
GND 13
I/O/PD1 14
I/O 15
I/O 14
62 I/O/TCK
61 I/O
I/O/TMS 15
I/O 16
60 I/O
I/O 16
I/O 17
59 GND
58 I/O
I/O/TMS 17
I/O 18
VCCIO 18
I/O 19
57 I/O
I/O 19
I/O 20
56 I/O
VCCIO 20
I/O 21
I/O 21
55 NC
54 I/O
NC 22
I/O 22
I/O 23
53 NC
52 I/O
I/O 23
NC 24
NC 24
I/O 25
51 VCCIO
I/O 25
NC 26
I/O 27
GND 28
NC 29
NC 30
3
1409I–PLD–2/03
Description
The ATF1504ASV(L) is a high-performance, high-density complex programmable logic
device (CPLD) that utilizes Atmel’s proven electrically-erasable memory technology.
With 64 logic macrocells and up to 68 inputs, it easily integrates logic from several TTL,
SSI, MSI, LSI and classic PLDs. The ATF1504ASV(L)’s enhanced routing switch matri-
ces increase usable gate count and the odds of successful pin-locked design
modifications.
The ATF1504ASV(L) has up to 68 bi-directional I/O pins and four dedicated input pins,
depending on the type of device package selected. Each dedicated pin can also serve
as a global control signal, register clock, register reset or output enable. Each of these
control signals can be selected for use individually within each macrocell.
Each of the 64 macrocells generates a buried feedback that goes to the global bus.
Each input and I/O pin also feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus. Each macrocell also gener-
ates a foldback logic term that goes to a regional bus. Cascade logic between
macrocells in the ATF1504ASV(L) allows fast, efficient generation of complex logic func-
tions. The ATF1504ASV(L) contains four such logic chains, each capable of creating
sum term logic with a fan-in of up to 40 product terms.
The ATF1504ASV(L) macrocell, shown in Figure 1, is flexible enough to support highly-
complex logic functions operating at high speed. The macrocell consists of five sections:
product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop,
output select and enable, and logic array inputs.
4
ATF1504ASV(L)
1409I–PLD–2/03
ATF1504ASV(L)
Block Diagram
Unused product terms are automatically disabled by the compiler to decrease power
consumption. A security fuse, when programmed, protects the contents of the
ATF1504ASV(L). Two bytes (16 bits) of User Signature are accessible to the user for
purposes such as storing project name, part number, revision or date. The User Signa-
ture is accessible regardless of the state of the security fuse.
The ATF1504ASV(L) device is an in-system programmable (ISP) device. It uses the
industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully-compliant with
JTAG’s Boundary-scan Description Language (BSDL). ISP allows the device to be pro-
grammed without removing it from the printed circuit board. In addition to simplifying the
manufacturing flow, ISP also allows design modifications to be made in the field via
software.
Product Terms and Select
Mux
Each ATF1504ASV(L) macrocell has five product terms. Each product term receives as
its inputs all signals from both the global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the five product terms as
needed to the macrocell logic gates and control signals. The PTMUX programming is
determined by the design compiler, which selects the optimum macrocell configuration.
5
1409I–PLD–2/03
OR/XOR/CASCADE Logic
The ATF1504ASV(L)’s logic structure is designed to efficiently support all types of logic.
Within a single macrocell, all the product terms can be routed to the OR gate, creating a
5-input AND/OR sum term. With the addition of the CASIN from neighboring macrocells,
this can be expanded to as many as 40 product terms with little additional delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic
functions. One input to the XOR comes from the OR sum term. The other XOR input can
be a product term or a fixed high- or low-level. For combinatorial outputs, the fixed level
input allows polarity selection. For registered functions, the fixed levels allow DeMorgan
minimization of product terms. The XOR gate is also used to emulate T- and JK-type
flip-flops.
Flip-flop
The ATF1504ASV(L)’s flip-flop has very flexible data and control functions. The data
input can come from either the XOR gate, from a separate product term or directly from
the I/O pin. Selecting the separate product term allows creation of a buried registered
feedback within a combinatorial output macrocell. (This feature is automatically imple-
mented by the fitter software). In addition to D, T, JK and SR operation, the flip-flop can
also be configured as a flow-through latch. In this mode, data passes through when the
clock is high and is latched when the clock is low.
The clock itself can either be one of the Global CLK Signal (GCK[0 : 2]) or an individual
product term. The flip-flop changes state on the clock’s rising edge. When the GCK sig-
nal is used as the clock, one of the macrocell product terms can be selected as a clock
enable. When the clock enable function is active and the enable signal (product term) is
low, all clock edges are ignored. The flip-flop’s asynchronous reset signal (AR) can be
either the Global Clear (GCLEAR), a product term, or always off. AR can also be a logic
OR of GCLEAR with a product term. The asynchronous preset (AP) can be a product
term or always off.
Extra Feedback
I/O Control
The ATF1504ASV(L) macrocell output can be selected as registered or combinatorial.
The extra buried feedback signal can be either combinatorial or a registered signal
regardless of whether the output is combinatorial or registered. (This enhancement
function is automatically implemented by the fitter software.) Feedback of a buried com-
binatorial output allows the creation of a second latch within a macrocell.
The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be
individually configured as an input, output or for bi-directional operation. The output
enable for each macrocell can be selected from the true or compliment of the two output
enable pins, a subset of the I/O pins, or a subset of the I/O macrocells. This selection is
automatically done by the fitter software when the I/O is configured as an input, all mac-
rocell resources are still available, including the buried feedback, expander and cascade
logic.
Global Bus/Switch Matrix
Foldback Bus
The global bus contains all input and I/O pin signals as well as the buried feedback sig-
nal from all 64 macrocells. The switch matrix in each logic block receives as its inputs all
signals from the global bus. Under software control, up to 40 of these signals can be
selected as inputs to the logic block.
Each macrocell also generates a foldback product term. This signal goes to the regional
bus and is available to four macrocells. The foldback is an inverse polarity of one of the
macrocell’s product terms. The four foldback terms in each region allow generation of
high fan-in sum terms (up to nine product terms) with little additional delay.
6
ATF1504ASV(L)
1409I–PLD–2/03
ATF1504ASV(L)
Figure 1. ATF1504ASV(L) Macrocell
Programmable Pin-keeper Option for Inputs and I/Os
The ATF1504ASV(L) offers the option of programming all input and I/O pins so that pin keeper circuits can be utilized.
When any pin is driven high or low and then subsequently left floating, it will stay at that previous high- or low-level. This cir-
cuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which causes unnecessary power
consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate their DC
power consumption.
7
1409I–PLD–2/03
Input Diagram
I/O Diagram
Speed/Power
Management
The ATF1504ASV(L) has several built-in speed and power management features. The
ATF1504ASV(L) contains circuitry that automatically puts the device into a low power
standby mode when no logic transitions are occurring. This not only reduces power con-
sumption during inactive periods, but also provides proportional power savings for most
applications running at system speeds below 5 MHz. This feature may be selected as a
device option.
To further reduce power, each ATF1504ASV(L) macrocell has a reduced-power bit fea-
ture. This feature allows individual macrocells to be configured for maximum power
savings. This feature may be selected as a design option.
All ATF1504ASV(L) also have an optional power-down mode. In this mode, current
drops to below 5 mA. When the power-down option is selected, either PD1 or PD2 pins
(or both) can be used to power down the part. The power-down option is selected in the
design source file. When enabled, the device goes into power down when either PD1 or
PD2 is high. In the power-down mode, all internal logic signals are latched and held, as
are any enabled outputs.
All pin transitions are ignored until the PD pin is brought low. When the power-down fea-
ture is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However,
the pin’s macrocell may still be used to generate buried foldback and cascade logic
signals.
8
ATF1504ASV(L)
1409I–PLD–2/03
ATF1504ASV(L)
All power-down AC characteristic parameters are computed from external input or I/O
pins, with reduced-power bit turned on. For macrocells in reduced-power mode
(reduced-power bit turned on), the reduced-power adder, tRPA, must be added to the AC
parameters, which include the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP
.
The ATF1504ASV(L) macrocell also has an option whereby the power can be reduced
on a per macrocell basis. By enabling this power-down option, macrocells that are not
used in an application can be turned down, thereby reducing the overall power con-
sumption of the device.
Each output also has individual slew rate control. This may be used to reduce system
noise by slowing down outputs that do not need to operate at maximum speed. Outputs
default to slow switching, and may be specified as fast switching in the design file.
Design Software
Support
ATF1504ASV(L) designs are supported by several industry standard third party tools.
Automated fitters allow logic synthesis using a variety of high-level description lan-
guages and formats.
Power-up Reset
The ATF1504ASV is designed with a power-up reset, a feature critical for state machine
initialization. At a point delayed slightly from VCC crossing VRST, all registers will be ini-
tialized, and the state of each output will depend on the polarity of its buffer. However,
due to the asynchronous nature of reset and uncertainty of how VCC actually rises in the
system, the following conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup times must be met before driving
the clock pin high, and,
3. The clock must remain stable during TD.
The ATF1504ASV has two options for the hysteresis about the reset level, VRST, Small
and Large. To ensure a robust operating environment in applications where the device
is operated near 3.0V, Atmel recommends that during the fitting process users configure
the device with the Power-up Reset hysteresis set to Large. For conversions, Atmel
POF2JED users should include the flag “-power_reset” on the command line after “file-
name.POF”. To allow the registers to be properly reinitialized with the Large hysteresis
option selected, the following condition is added:
4. If VCC falls below 2.0V, it must shut off completely before the device is turned on
again.
When the Large hysteresis option is active, ICC is reduced by several hundred micro-
amps as well.
Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF1504ASV(L) fuse
patterns. Once programmed, fuse verify is inhibited. However, the 16-bit User Signature
remains accessible.
9
1409I–PLD–2/03
Programming
ATF1504ASV(L) devices are in-system programmable (ISP) devices utilizing the 4-pin
JTAG protocol. This capability eliminates package handling normally required for pro-
gramming and facilitates rapid design iterations and field changes.
Atmel provides ISP hardware and software to allow programming of the
ATF1504ASV(L) via the PC. ISP is performed by using either a download cable, a com-
parable board tester or a simple microprocessor interface.
To facilitate ISP programming by the Automated Test Equipment (ATE) vendors. Serial
Vector Format (SVF) files can be created by Atmel provided software utilities.
ATF1504ASV(L) devices can also be programmed using standard third-party program-
mers. With third-party programmer the JTAG ISP port can be disabled thereby allowing
four additional I/O pins to be used for logic.
Contact your local Atmel representatives or Atmel PLD applications for details.
ISP Programming
Protection
The ATF1504ASV(L) has a special feature that locks the device and prevents the inputs
and I/O from driving if the programming process is interrupted for any reason. The
inputs and I/O default to high-Z state during such a condition. In addition the pin keeper
option preserves the former state during device programming, if this circuit were previ-
ously programmed on the device. This prevents disturbing the operation of other circuits
in the system while the ATF1504ASV(L) is being programmed via ISP.
All ATF1504ASV(L) devices are initially shipped in the erased state thereby making
them ready to use for ISP.
Note:
For more information refer to the “Designing for In-System Programmability with Atmel
CPLDs” application note.
10
ATF1504ASV(L)
1409I–PLD–2/03
ATF1504ASV(L)
DC and AC Operating Conditions
Commercial
0°C - 70°C
3.0V - 3.6V
Industrial
-40°C - 85°C
3.0V - 3.6V
Operating Temperature (Ambient))
VCC (3.3V) Power Supply
DC Characteristics
Symbol
Parameter
Condition
IN = VCC
Min
Typ
Max
Units
Input or I/O Low
Leakage Current
IIL
V
-2
2
-10
µA
Input or I/O High
Leakage Current
IIH
10
40
Tri-State Output
Off-State Current
IOZ
VO = VCC or GND
-40
µA
Com.
Ind.
60
75
5
mA
mA
µA
Std Mode
Power Supply Current,
Standby
VCC = Max
IN = 0, VCC
ICC1
V
Com.
Ind.
“L” Mode
5
µA
Power Supply Current,
Power-down Mode
VCC = Max
IN = 0, VCC
ICC2
“PD” Mode
Std Power
0.1
5
mA
ma
V
Com
Ind
40
55
Reduced-power Mode
Supply Current, Standby
VCC = Max
(2)
ICC3
VIN = 0, VCC
VIL
VIH
Input Low Voltage
Input High Voltage
-0.3
1.7
0.8
VCCIO + 0.3
0.45
V
V
V
Com.
Ind.
V
IN = VIH or VIL
Output Low Voltage (TTL)
VCCIO = Min, IOL = 8 mA
0.45
VOL
Com.
Ind.
0.2
V
V
VIN = VIH or VIL
Output Low Voltage (CMOS)
VCC = Min, IOL = 0.1 mA
0.2
Output High Voltage
- 3.3V (TTL)
VIN = VIH or VIL
VCCIO = Min, IOH = -2.0 mA
2.4
V
V
VOH
Output High Voltage
- 3.3V (CMOS)
VIN = VIH or VIL
VCCIO - 0.2
VCCIO = Min, IOH = -0.1 mA
Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
2. When microcell reduced-power feature is enabled.
Pin Capacitance
Typ
Max
8
Units
pF
Conditions
CIN
VIN = 0V; f = 1.0 MHz
VOUT = 0V; f = 1.0 MHz
CI/O
8
pF
Note:
Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
The OGI pin (high-voltage pin during programming) has a maximum capacitance of 12 pF.
11
1409I–PLD–2/03
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Temperature Under Bias.................................. -40°C to +85°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Note:
1. Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns. Max-
imum output pin voltage is VCC + 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
Timing Model
Internal Output
Enable Delay
t
IOE
Global Control
Delay
Input
Delay
t
GLOB
Register
Delay
Cascade Logic
t
Delay
IN
Output
Delay
Logic Array
Delay
t
t
SU
PEXP
Switch
Matrix
t
H
t
OD1
t
t
t
t
LAD
PRE
t
t
OD2
t
UIM
CLR
OD3
Register Control
Delay
RD
t
XZ
t
COMB
t
t
t
ZX1
t
t
LAC
FSU
ZX2
t
t
IC
Fast Input
Delay
FH
ZX3
t
EN
t
FIN
Foldback Term
Delay
I/O
Delay
t
SEXP
t
IO
12
ATF1504ASV(L)
1409I–PLD–2/03
ATF1504ASV(L)
AC Characteristics
-15
-20
Symbol
tPD1
tPD2
tSU
Parameter
Min
3
Max
15
Min
Max
20
Units
ns
Input or Feedback to Non-Registered Output
I/O Input or Feedback to Non-Registered Feedback
Global Clock Setup Time
3
12
16
ns
11
0
13.5
ns
tH
Global Clock Hold Time
0
3
2
ns
tFSU
tFH
tCOP
tCH
Global Clock Setup Time of Fast Input
Global Clock Hold Time of Fast Input
Global Clock to Output Delay
Global Clock High Time
3
ns
1.0
MHz
ns
9
12
5
5
5
4
6
6
7
4
ns
tCL
Global Clock Low Time
ns
tASU
tAH
Array Clock Setup Time
ns
Array Clock Hold Time
ns
tACOP
tACH
tACL
tCNT
fCNT
tACNT
fACNT
fMAX
tIN
Array Clock Output Delay
Array Clock High Time
15
18.5
ns
6
6
8
8
ns
Array Clock Low Time
ns
Minimum Clock Global Period
Maximum Internal Global Clock Frequency
Minimum Array Clock Period
Maximum Internal Array Clock Frequency
Maximum Clock Frequency
Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Fast Input Delay
13
13
17
17
ns
76.9
66
MHz
ns
76.9
100
58.8
83.3
MHz
MHz
ns
2
2
2.5
2.5
2
tIO
ns
tFIN
2
ns
tSEXP
tPEXP
tLAD
tLAC
tIOE
Foldback Term Delay
8
10
1
ns
Cascade Logic Delay
1
ns
Logic Array Delay
6
8
ns
Logic Control Delay
3.5
3
4.5
3
ns
Internal Output Enable Delay
ns
Output Buffer and Pad Delay
(Slow slew rate = OFF; VCCIO = 5V; CL = 35 pF)
tOD1
tOD2
tOD3
tZX1
3
3
5
7
4
4
6
9
ns
ns
ns
ns
Output Buffer and Pad Delay
(Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF)
Output Buffer and Pad Delay
(Slow slew rate = ON; VCCIO = 5V or 3.3V; CL = 35 pF)
Output Buffer Enable Delay
(Slow slew rate = OFF; VCCIO = 5.0V; CL = 35 pF)
13
1409I–PLD–2/03
AC Characteristics (Continued)
-15
-20
Symbol
Parameter
Min
Max
Min
Max
Units
Output Buffer Enable Delay
(Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF)
tZX2
7
9
ns
Output Buffer Enable Delay
(Slow slew rate = ON; VCCIO = 5.0V/3.3V; CL = 35 pF)
tZX3
10
6
11
7
ns
tXZ
Output Buffer Disable Delay (CL = 5 pF)
Register Setup Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSU
5
4
2
2
6
5
2
2
tH
Register Hold Time
tFSU
tFH
Register Setup Time of Fast Input
Register Hold Time of Fast Input
Register Delay
tRD
2
2
2.5
3
tCOMB
tIC
Combinatorial Delay
Array Clock Delay
6
7
tEN
Register Enable Time
Global Control Delay
6
7
tGLOB
tPRE
tCLR
tUIM
tRPA
2
3
Register Preset Time
Register Clear Time
4
5
4
5
Switch Matrix Delay
2
2.5
13
Reduced-power Adder(2)
10
Notes: 1. See ordering information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC,tTIC, tACL, and tSEXP parameters for macrocells running in the reduced-
power mode.
3. See ordering information for valid part numbers.
Input Test Waveforms and Measurement Levels
tR, tF = 1.5 ns typical
Output AC Test Loads
3.0V
R1 = 703Ω
OUTPUT
PIN
R2 = 8060Ω
CL = 35 pF
14
ATF1504ASV(L)
1409I–PLD–2/03
ATF1504ASV(L)
Power-down Mode
The ATF1504ASV(L) includes an optional pin-controlled power-down feature. When this
mode is enabled, the PD pin acts as the power-down pin. When the PD pin is high, the
device supply current is reduced to less than 3 mA. During power down, all output data
and internal logic states are latched internally and held. Therefore, all registered and
combinatorial output data remain valid. Any outputs that were in a High-Z state at the
onset will remain at High-Z. During power down, all input signals except the power-down
pin are blocked. Input and I/O hold latches remain active to ensure that pins do not float
to indeterminate levels, further reducing system power. The power-down mode feature
is enabled in the logic design file or as a fitted or translated s/w option. Designs using
the power-down pin may not use the PD pin as a logic array input. However, all other PD
pin macrocell resources may still be used, including the buried feedback and foldback
product term array inputs.
Power Down AC Characteristics(1)(2)
-15
-20
Symbol Parameter
Min
15
Max
Min
20
Max
Units
ns
tIVDH
tGVDH
tCVDH
tDHIX
tDHGX
tDHCX
tDLIV
Valid I, I/O before PD High
Valid OE(2) before PD High
Valid Clock(2) before PD High
I, I/O Don’t Care after PD High
OE(2) Don’t Care after PD High
Clock(2) Don’t Care after PD High
PD Low to Valid I, I/O
15
20
ns
15
20
ns
25
25
25
1
30
30
30
1
ns
ns
ns
µs
tDLGV
tDLCV
tDLOV
PD Low to Valid OE (Pin or Term)
PD Low to Valid Clock (Pin or Term)
PD Low to Valid Output
1
1
µs
1
1
µs
1
1
µs
Notes: 1. For slow slew outputs, add tSSO
.
2. Pin or product term.
3. Includes tRPA for reduced-power bit enabled.
15
1409I–PLD–2/03
JTAG-BST/ISP
Overview
The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller
in the ATF1504ASV(L). The boundary-scan technique involves the inclusion of a shift-
register stage (contained in a boundary-scan cell) adjacent to each component so that
signals at component boundaries can be controlled and observed using scan testing
principles. Each input pin and I/O pin has its own boundary-scan cell (BSC) in order to
support boundary-scan testing. The ATF1504ASV(L) does not currently include a Test
Reset (TRST) input pin because the TAP controller is automatically reset at power-up.
The five JTAG modes supported include: SAMPLE/PRELOAD, EXTEST, BYPASS,
IDCODE and HIGHZ. The ATF1504ASV(L)’s ISP can be fully described using JTAG’s
BSDL as described in IEEE Standard 1149.1b. This allows ATF1504ASV(L) program-
ming to be described and implemented using any one of the third-party development
tools supporting this standard.
The ATF1504ASV(L) has the option of using four JTAG-standard I/O pins for boundary-
scan testing (BST) and in-system programming (ISP) purposes. The ATF1504ASV(L) is
programmable through the four JTAG pins using the IEEE standard JTAG programming
protocol established by IEEE Standard 1149.1 using 5V TTL-level programming signals
from the ISP interface for in-system programming. The JTAG feature is a programmable
option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are avail-
able as I/O pins.
JTAG Boundary-scan The ATF1504ASV(L) contains up to 68 I/O pins and four input pins, depending on the
device type and package type selected. Each input pin and I/O pin has its own bound-
Cell (BSC) Testing
ary-scan cell (BSC) in order to support boundary-scan testing as described in detail by
IEEE Standard 1149.1. A typical BSC consists of three capture registers or scan regis-
ters and up to two update registers. There are two types of BSCs, one for input or I/O
pin, and one for the macrocells. The BSCs in the device are chained together through
the capture registers. Input to the capture register chain is fed in from the TDI pin while
the output is directed to the TDO pin. Capture registers are used to capture active
device data signals, to shift data in and out of the device and to load data into the update
registers. Control signals are generated internally by the JTAG TAP controller. The BSC
configuration for the input and I/O pins and macrocells are shown below.
BSC Configuration
for Input and I/O Pins
(Except JTAG TAP
Pins)
Note:
The ATF1504ASV(L) has pull-up option on TMS and TDI pins. This feature is selected as
a design option.
16
ATF1504ASV(L)
1409I–PLD–2/03
ATF1504ASV(L)
BSC Configuration for Macrocell
Pin BSC
TDO
0
DQ
Pin
1
Capture
DR
Clock
TDI
Shift
TDO
OEJ
0
1
0
1
D Q
D Q
OUTJ
0
1
Pin
0
1
D Q
D Q
Capture
DR
Update
DR
Mode
TDI
Clock
Shift
Macrocell BSC
17
1409I–PLD–2/03
ATF1504ASV Dedicated Pinouts
44-lead
TQFP
44-lead
68-lead
J-lead
84-lead
J-lead
100-lead
PQFP
100-lead
TQFP
Dedicated Pin
INPUT/OE2/GCLK2
INPUT/GCLR
J-lead
40
39
38
37
35
5, 19
1
2
2
1
2
1
92
91
90
89
1
INPUT/OE1
44
68
84
90
88
INPUT/GCLK1
I/O /GCLK3
43
67
83
89
87
41
65
81
87
85
I/O / PD (1,2)
11, 25
7
17, 37
12
20, 46
14
14, 44
6
12, 42
4
I/O / TDI (JTAG)
I/O / TMS (JTAG)
I/O / TCK (JTAG)
I/O / TDO (JTAG)
7
13
19
23
17
15
26
32
32
50
62
64
62
38
57
71
75
73
6, 16, 26, 34,
38, 48, 58, 66
7, 19, 32, 42,
47, 59, 72, 82
13, 28, 40, 45,
61, 76, 88, 97
11, 26, 38, 43,
59, 74, 86, 95
GND
VCC
4, 16, 24, 36
9, 17, 29, 41
10, 22, 30, 42
3, 15, 23, 35
3, 11, 21, 31,
35, 43, 53, 63
3,13, 26, 38,
43, 53, 66, 78
5, 20, 36, 41,
53, 68, 84, 93
3, 18, 34, 39,
51, 66, 82, 91
1, 2, 7, 9,
1, 2, 5, 7, 22,
24, 27, 28, 49,
50, 53, 55, 70,
72, 77, 78
24, 26, 29, 30,
51, 52, 55, 57,
72, 74, 79, 80
N/C
–
–
–
–
# of Signal Pins
36
32
36
32
52
48
68
64
68
64
68
64
# User I/O Pins
OE (1, 2)
Global OE pins
GCLR
Global Clear pin
Global Clock pins
Power-down pins
GCLK (1, 2, 3)
PD (1, 2)
TDI, TMS, TCK, TDO
GND
JTAG pins used for boundary-scan testing or in-system programming
Ground pins
VCC
VCC pins for the device
18
ATF1504ASV(L)
1409I–PLD–2/03
ATF1504ASV(L)
ATF1504ASV I/O Pinouts
100-
lead
100-
lead
100-
lead
100-
lead
44-lead 44-lead 68-lead 84-lead
44-lead 44-lead 68-lead 84-lead
MC
1
PLC
A
PLCC
TQFP
PLCC
PLCC
PQFP
TQFP
MC
33
PLC
C
PLCC
TQFP
PLCC
PLCC
PQFP
TQFP
12
-
6
-
18
-
22
16
15
14
13
24
-
18
-
36
-
44
42
43
40
41
2
A
21
34
C
45
A/
PD1
C/
PD2
3
11
5
17
20
14
12
35
25
19
37
46
44
42
4
5
6
7
A
A
A
A
9
8
-
3
2
-
15
14
13
-
18
17
16
15
12
11
10
8
10
9
36
37
38
39
C
C
C
C
26
27
-
20
21
-
39
40
41
-
48
49
50
51
46
47
48
49
44
45
46
47
8
-
-
6
-
-
8/
TDI
A
7
1
12
14
6
4
40
C
28
22
42
52
50
48
9
A
A
A
A
A
A
A
-
-
-
-
10
-
12
11
10
9
4
3
100
99
98
97
96
94
93
41
42
43
44
45
46
47
C
C
C
C
C
C
C
29
-
23
-
44
-
54
55
56
57
58
60
61
54
56
58
59
60
62
63
52
54
56
57
58
60
61
10
11
12
13
14
15
6
-
44
-
9
8
7
5
-
100
99
98
96
95
-
-
45
46
47
49
-
-
-
-
-
8
-
-
5
-
43
-
6
31
-
25
-
5
48/
TCK
16
A
4
42
4
4
94
92
C
32
26
50
62
64
62
17
18
19
20
21
22
23
B
B
B
B
B
B
B
21
-
15
-
33
-
41
40
39
37
36
35
34
39
38
37
35
34
33
32
37
36
35
33
32
31
30
49
50
51
52
53
54
55
D
D
D
D
D
D
D
33
-
27
-
51
-
63
64
65
67
68
69
70
65
66
67
69
70
71
73
63
64
65
67
68
69
71
20
19
18
-
14
13
12
-
32
30
29
28
-
34
36
37
-
28
30
31
-
52
54
55
56
-
-
-
-
-
56/
TDO
24
B
17
11
27
33
31
29
D
38
32
57
71
75
73
25
26
27
28
29
30
31
B
B
B
B
B
B
B
16
-
10
-
25
-
31
30
29
28
27
25
24
27
25
23
22
21
19
18
25
23
21
20
19
17
16
57
58
59
60
61
62
63
D
D
D
D
D
D
D
39
-
33
-
59
-
73
74
75
76
77
79
80
77
78
81
82
83
85
86
75
76
79
80
81
83
84
-
-
24
23
22
20
-
-
-
60
61
62
64
-
-
-
-
-
-
-
-
-
14
-
8
-
40
-
34
-
32/
TMS
D/
GCLK3
B
13
7
19
23
17
15
64
41
35
65
81
87
85
19
1409I–PLD–2/03
SUPPLY CURRENT VS. FREQUENCY
LOW-POWER ("L") VERSION
(TA = 25°C)
SUPPLY CURRENT VS. SUPPLY VOLTAGE
(TA = 25°C, F = 0)
100
75
50
25
0
100.0
80.0
60.0
40.0
20.0
0.0
STANDARD POWER
STANDARD POWER
REDUCED POWER
REDUCED POWER MODE
2.50
2.75
3.00
3.25
3.50
3.75
4.00
0.00
5.00
10.00
15.00
20.00
SUPPLY VOLTAGE (V)
FREQUENCY (MHz)
OUTPUT SOURCE CURRENT
VS. SUPPLY VOLTAGE
(VOH = 2.4V, TA = 25°C)
SUPPLY CURRENT VS. SUPPLY VOLTAGE
PIN-CONTROLLED POWER-DOWN MODE
(TA = 25°C, F = 0)
800
700
600
500
400
0
-2
-4
STANDARD & REDUCED POWER MODE
-6
-8
-10
-12
-14
-16
2.75
3.00
3.25
3.50
3.75
4.00
2.50
2.75
3.00
3.25
3.50
3.75
4.00
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
OUTPUT SOURCE CURRENT
VS. OUTPUT VOLTAGE
(VCC = 3.3V, TA = 25°C)
SUPPLY CURRENT VS. FREQUENCY
STANDARD POWER (TA = 25°C)
150.0
125.0
100.0
75.0
50.0
25.0
0.0
10
0
-10
-20
-30
-40
-50
-60
-70
STANDARD POWER
REDUCED POWER MODE
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT VOLTAGE (V)
0.00
20.00
40.00
60.00
80.00
100.00
FREQUENCY (MHz)
OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE
SUPPLY CURRENT VS. SUPPLY VOLTAGE
LOW-POWER ("L") VERSION
(TA = 25°C, F = 0)
(VOL = 0.5V, TA = 25°C)
40
25
20
15
10
5
35
30
25
20
2.75
3.00
3.25
3.50
3.75
4.00
0
SUPPLY VOLTAGE (V)
2.50
2.75
3.00
3.25
3.50
3.75
4.00
SUPPLY VOLTAGE (V)
20
ATF1504ASV(L)
1409I–PLD–2/03
ATF1504ASV(L)
OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE
INPUT CURRENT VS. INPUT VOLTAGE
(VCC = 3.3V, TA = 25°C)
(VCC = 3.3V, TA = 25°C)
100
80
60
40
20
0
15
10
5
0
-5
-10
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
2.5
3
3.5
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT CLAMP CURRENT VS. INPUT VOLTAGE
(VCC = 3.3V, TA = 25°C)
0
-20
-40
-60
-80
-100
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
INPUT VOLTAGE (V)
21
1409I–PLD–2/03
ATF1504ASV(L) Ordering Information
tPD
tCO1
fMAX
(ns)
(ns)
(MHz)
Ordering Code
Package
Operation Range
15
15
20
20
8
100
ATF1504ASV-15 AC44
ATF1504ASV-15 JC44
ATF1504ASV-15 JC68
ATF1504ASV-15 JC84
ATF1504ASV-15 QC100
ATF1500ASV-15 AC100
44A
Commercial
44J
(0°C to 70°C)
68J
84J
100Q1
100A
8
100
ATF1504ASV-15 AI44
ATF1504ASV-15 JI44
ATF1504ASV-15 JI68
ATF1504ASV-15 JI84
ATF1504ASV-15 QI100
ATF1504ASV-15 AI100
44A
Industrial
44J
(-40°C to +85°C)
68J
84J
100Q1
100A
12
12
83.3
83.3
ATF1504ASVL-20 AC44
ATF1504ASVL-20 JC44
ATF1504ASVL-20 JC68
ATF1504ASVL-20 JC84
ATF1504ASVL-20 QC100
ATF1504ASVL-20 AC100
44A
Commercial
44J
(0°C to 70°C)
68J
84J
100Q1
100A
ATF1504ASVL-20 AI44
ATF1504ASVL-20 JI44
ATF1504ASVL-20 JI68
ATF1504ASVL-20 JI84
ATF1504ASVL-20 QI100
ATF1504ASVL-20 AI100
44A
Industrial
44J
(-40°C to +85°C)
68J
84J
100Q1
100A
Using “C” Product for Industrial
There is very little risk in using “C” devices for industrial applications because the VCC conditions for 3.3V products are the
same for commercial and industrial (there is only 15°C difference at the high end of the temperature range). To use com-
mercial product for industrial temperature ranges, de-rate ICC by 15%.
22
ATF1504ASV(L)
1409I–PLD–2/03
ATF1504ASV(L)
Packaging Information
44A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0˚~7˚
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
11.75
9.90
11.75
9.90
0.30
0.09
0.45
0.15
1.00
12.00
10.00
12.00
10.00
–
1.05
12.25
D1
E
10.10 Note 2
12.25
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
E1
B
10.10 Note 2
0.45
C
–
0.20
3. Lead coplanarity is 0.10 mm maximum.
L
–
0.75
e
0.80 TYP
10/5/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
44A
B
R
23
1409I–PLD–2/03
44J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
D2/E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
–
A1
A2
D
2.286
–
0.508
–
17.399
16.510
17.399
16.510
–
17.653
D1
E
–
16.662 Note 2
17.653
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
–
16.662 Note 2
16.002
D2/E2 14.986
–
B
0.660
0.330
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
44J
B
R
24
ATF1504ASV(L)
1409I–PLD–2/03
ATF1504ASV(L)
68J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
D2/E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
–
A1
A2
D
2.286
–
0.508
–
25.019
24.130
25.019
24.130
–
25.273
D1
E
–
24.333 Note 2
25.273
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
–
24.333 Note 2
23.622
D2/E2 22.606
–
B
0.660
0.330
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
68J
TITLE
2325 Orchard Parkway
San Jose, CA 95131
68J, 68-lead, Plastic J-leaded Chip Carrier (PLCC)
B
R
25
1409I–PLD–2/03
84J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
D2/E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
–
A1
A2
D
2.286
–
0.508
–
30.099
29.210
30.099
29.210
–
30.353
D1
E
–
29.413 Note 2
30.353
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AF.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
–
29.413 Note 2
28.702
D2/E2 27.686
–
B
0.660
0.330
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
84J, 84-lead, Plastic J-leaded Chip Carrier (PLCC)
84J
B
R
26
ATF1504ASV(L)
1409I–PLD–2/03
ATF1504ASV(L)
100Q1 – PQFP
Dimensions in Millimeters and (Inches)*
*Controlling dimensions: millimeters
JEDEC STANDARD MS-022, GC-1
17.45 (0.687)
16.95 (0.667)
PIN 1 ID
PIN 1
20.10 (0.791)
19.90 (0.783)
0.65 (0.0256) BSC
0.40 (0.016)
0.22 (0.009)
23.45 (0.923)
22.95 (0.904)
14.12 (0.556)
13.90 (0.547)
3.40 (0.134) MAX
0.23 (0.009)
0.11 (0.004)
0º~7º
1.03 (0.041)
0.73 (0.029)
0.50 (0.020)
0.25 (0.010)
04/11/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
100Q1, 100-lead, 14 x 20 mm Body, 3.2 mm Footprint, 0.65 mm Pitch,
Plastic Quad Flat Package (PQFP)
100Q1
A
R
27
1409I–PLD–2/03
100A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0˚~7˚
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
15.75
13.90
15.75
13.90
0.17
0.09
0.45
0.15
1.00
16.00
14.00
16.00
14.00
–
1.05
16.25
D1
E
14.10 Note 2
16.25
Notes:
1. This package conforms to JEDEC reference MS-026, Variation AED.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
E1
B
14.10 Note 2
0.27
C
–
0.20
3. Lead coplanarity is 0.08 mm maximum.
L
–
0.75
e
0.50 TYP
10/5/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
100A
C
R
28
ATF1504ASV(L)
1409I–PLD–2/03
Atmel Headquarters
Atmel Operations
Corporate Headquarters
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
TEL (49) 71-31-67-0
FAX (49) 71-31-67-2340
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
FAX 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
TEL (41) 26-426-5555
FAX (41) 26-426-5500
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
TEL (33) 2-40-18-18-18
FAX (33) 2-40-18-19-60
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
BP 123
38521 Saint-Egreve Cedex, France
TEL (33) 4-76-58-30-00
FAX (33) 4-76-58-34-80
ASIC/ASSP/Smart Cards
Zone Industrielle
Hong Kong
TEL (852) 2721-9778
FAX (852) 2722-1369
13106 Rousset Cedex, France
TEL (33) 4-42-53-60-00
FAX (33) 4-42-53-60-01
Japan
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
FAX 1(719) 540-1759
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
TEL (44) 1355-803-000
FAX (44) 1355-242-743
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
© Atmel Corporation 2003.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
Atmel® is the registered trademark of Atmel.
Other terms and product names may be the trademarks of others.
Printed on recycled paper.
1409I–PLD–2/03
xM
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明