ATF1504AS-7JC44 [ATMEL]
High- Performance EE CPLD; 高性能EE CPLD
| 型号： | ATF1504AS-7JC44 |
| 厂家： | 
ATMEL |
| 描述： | High- Performance EE CPLD |
| 文件： | 总21页 (文件大小：465K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High Density, High Performance Electrically Erasable Complex Programmable Logic
Device
– 64 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 44, 68, 84, 100 pins
– 7 ns Maximum Pin-to-Pin Delay
– Registered Operation Up To 100 MHz
– Enhanced Routing Resources
• In-System Programmability (ISP) via JTAG
• Flexible Logic Macrocell
High-
Performance
EE CPLD
– D/T/Latch Configurable Flip Flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic utilization by burying a register within a COM output
• Advanced Power Management Features
– Automatic 100 µA Stand-By for “Z” Version
– Pin-Controlled 4 mA Stand-By Mode (Typical)
– Programmable Pin-Keeper Inputs and I/Os
– Reduced-Power Feature Per Macrocell
• Available in Commercial and Industrial Temperature Ranges
• Available in 44-, 68-, and 84-pin PLCC; 44- and 100-pin TQFP; and 100-pin PQFP
• Advanced EE Technology
ATF1504AS
ATF1504ASZ
– 100% Tested
– Completely Reprogrammable
– 100 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-Up Immunity
• JTAG Boundary-Scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
• PCI-compliant
• 3.3 or 5.0V I/O pins
• Security Fuse Feature
Enhanced Features
• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
• Output Enable Product Terms
• D - Latch Mode
• Combinatorial Output with Registered Feedback within any Macrocell
• Three Global Clock Pins
• ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
• Fast Registered Input from Product Term
• Programmable “Pin-Keeper” Option
• VCC Power-Up Reset Option
• Pull-Up Option on JTAG Pins TMS and TDI
• Advanced Power Management Features
– Edge Controlled Power Down “L”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O
Description
The ATF1504AS is a high performance, high density Complex Programmable Logic
Device (CPLD) which utilizes Atmel’s proven electrically erasable memory technology.
With 64 logic macrocells and up to 68 inputs, it easily integrates logic from several
Rev. 0950D–07/98
(continued)
44-Lead TQFP
Top View
44-Lead PLCC
Top View
TDI/I/O
I/O
7
8
9
39 I/O
38 I/O/TDO
37 I/O
I/O/TDI
I/O
1
2
3
4
5
6
7
8
9
33 I/O
I/O
32 I/O/TDO
31 I/O
GND 10
PD1/I/O 11
I/O 12
36 I/O
I/O
35 VCC
34 I/O
GND
PD1/I/O
I/O
30 I/O
29 VCC
28 I/O
I/O/TMS 13
I/O 14
33 I/O
32 I/O/TCK
31 I/O
TMS/I/O
I/O
27 I/O
VCC 15
I/O 16
26 I/O/TCK
25 I/O
30 GND
29 I/O
VCC
I/O 17
I/O 10
I/O 11
24 GND
23 I/O
68-Lead PLCC
Top View
84-Lead PLCC
Top View
I/O 12
VCC 13
I/O/TDI 14
I/O 15
74 I/O
73 I/O
72 GND
71 I/O/TDO
70 I/O
69 I/O
68 I/O
67 I/O
66 VCC
65 I/O
64 I/O
63 I/O
62 I/O/TCK
61 I/O
60 I/O
59 GND
58 I/O
57 I/O
56 I/O
55 I/O
54 I/O
I/O 10
60 I/O
VCC 11
I/O/TD1 12
I/O 13
59 I/O
58 GND
57 I/O/TDO
56 I/O
I/O 16
I/O 14
I/O 17
I/O 15
55 I/O
I/O 18
GND 16
I/O/PD1 17
I/O 18
54 I/O
GND 19
I/O/PD1 20
I/O 21
53 VCC
52 I/O
I/O/TMS 19
I/O 20
51 I/O
I/O 22
50 I/O/TCK
49 I/O
I/O/TMS 23
I/O 24
VCC 21
I/O 22
48 GND
47 I/O
I/O 25
I/O 23
VCC 26
I/O 27
I/O 24
46 I/O
I/O 25
45 I/O
I/O 28
GND 26
44 I/O
I/O 29
I/O 30
I/O 31
GND 32
ATF1504AS(Z)
2
ATF1504AS(Z)
100-Lead PQFP
Top View
100-Lead TQFP
Top View
NC
NC
1
2
3
4
5
6
7
8
9
75 I/O
NC
NC
1
2
3
4
5
6
7
8
9
80 NC
79 NC
78 I/O
77 I/O
76 GND
75 I/O/TDO
74 NC
73 I/O
72 NC
71 I/O
70 I/O
69 I/O
68 VCCIO
67 I/O
66 I/O
65 I/O
64 I/O/TCK
63 I/O
62 I/O
61 GND
60 I/O
59 I/O
58 I/O
57 NC
56 I/O
55 NC
54 I/O
53 VCCIO
52 NC
51 NC
74 GND
73 I/O/TDO
72 NC
71 I/O
VCCIO
I/O/TDI
NC
I/O
I/O
VCCIO
I/O/TDI
NC
I/O
70 NC
69 I/O
NC
I/O
68 I/O
I/O
I/O
67 I/O
NC
I/O 10
GND 11
I/O/PD1 12
I/O 13
66 VCCIO
65 I/O
I/O 10
I/O 11
64 I/O
I/O 12
63 I/O
GND 13
I/O/PD1 14
I/O 15
I/O 14
62 I/O/TCK
61 I/O
I/O/TMS 15
I/O 16
60 I/O
I/O 16
I/O 17
59 GND
58 I/O
I/O/TMS 17
I/O 18
VCCIO 18
I/O 19
57 I/O
I/O 19
I/O 20
56 I/O
VCCIO 20
I/O 21
I/O 21
55 NC
54 I/O
NC 22
I/O 22
I/O 23
53 NC
52 I/O
I/O 23
NC 24
NC 24
I/O 25
51 VCCIO
I/O 25
NC 26
I/O 27
GND 28
NC 29
NC 30
3
TTL, SSI, MSI, LSI and classic PLDs. The ATF1504AS’s
enhanced routing switch matrices increase usable gate
count, and the odds of successful pin-locked design modifi-
cations.
block then selects 40 individual signals from the global bus.
Each macrocell also generates a foldback logic term, which
goes to a regional bus. Cascade logic between macrocells
in the ATF1504AS allows fast, efficient generation of com-
plex logic functions. The ATF1504AS contains four such
logic chains, each capable of creating sum term logic with a
fan in of up to 40 product terms.
The ATF1504AS has up to 68 bi-directional I/O pins and 4
dedicated input pins, depending on the type of device pack-
age selected. Each dedicated pin can also serve as a glo-
bal control signal; register clock, register reset or output
enable. Each of these control signals can be selected for
use individually within each macrocell.
The ATF1504AS macrocell shown in Figure 1, is flexible
enough to support highly complex logic functions operating
at high speed. The macrocell consists of five sections:
product terms and product term select multiplexer;
OR/XOR/CASCADE logic; a flip-flop; output select and
enable; and logic array inputs.
Each of the 64 macrocells generates a buried feedback,
which goes to the global bus. Each input and I/O pin also
feeds into the global bus. The switch matrix in each logic
Block Diagram
Unused product terms are automatically disabled by the
compiler to decrease power consumption. A Security Fuse,
when programmed, protects the contents of the
ATF1504AS. Two bytes (16-bits) of User Signature are
accessible to the user for purposes such as storing project
name, part number, revision or date. The User Signature is
accessible regardless of the state of the Security Fuse.
The ATF1504AS device is an In-System Programmable
(ISP) device. It uses the industry standard 4-pin JTAG
interface (IEEE Std. 1149.1), and is fully compliant with
JTAG’s Boundary Scan Description Language (BSDL). ISP
allows the device to be programmed without removing it
from the printed circuit board. In addition to simplifying the
manufacturing flow, ISP also allows design modifications to
be made in the field via software.
ATF1504ASZ
4
ATF1504ASZ
Product Terms and Select MUX
changes state on the clock’s rising edge. When the GCK
signal is used as the clock, one of the macrocell product
terms can be selected as a clock enable. When the clock
enable function is active and the enable signal (product
term) is low, all clock edges are ignored. The flip flop’s
asynchronous reset signal (AR) can be either the Global
Clear (GCLEAR), a product term, or always off. AR can
also be a logic OR of GCLEAR with a product term. The
asynchronous preset (AP) can be a product term or always
off.
Each ATF1504AS macrocell has five product terms. Each
product term receives as its inputs all signals from both the
global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the
five product terms as needed to the macrocell logic gates
and control signals. The PTMUX programming is deter-
mined by the design compiler, which selects the optimum
macrocell configuration.
OR/XOR/CASCADE Logic
Output Select and Enable
The ATF1504AS’s logic structure is designed to efficiently
support all types of logic. Within a single macrocell, all the
product terms can be routed to the OR gate, creating a 5-
input AND/OR sum term. With the addition of the CASIN
from neighboring macrocells, this can be expanded to as
many as 40 product terms with a very small additional
delay.
The ATF1504AS macrocell output can be selected as reg-
istered or combinatorial. The buried feedback signal can be
either combinatorial or registered signal regardless of
whether the output is combinatorial or registered.
The output enable multiplexer (MOE) controls the output
enable signals. Any buffer can be permanently enabled for
simple output operation. Buffers can also be permanently
disabled to allow use of the pin as an input. In this configu-
ration all the macrocell resources are still available, includ-
ing the buried feedback, expander and CASCADE logic.
The output enable for each macrocell can be selected as
either of the two dedicated OE input pins as an I/O pin con-
figured as an input, or as an individual product term.
The macrocell’s XOR gate allows efficient implementation
of compare and arithmetic functions. One input to the XOR
comes from the OR sum term. The other XOR input can be
a product term or a fixed high or low level. For combinato-
rial outputs, the fixed level input allows polarity selection.
For registered functions, the fixed levels allow DeMorgan
minimization of product terms. The XOR gate is also used
to emulate T- and JK-type flip-flops.
Global Bus/Switch Matrix
The global bus contains all input and I/O pin signals as well
as the buried feedback signal from all 64 macrocells. The
Switch Matrix in each Logic Block receives as its inputs all
signals from the global bus. Under software control, up to
40 of these signals can be selected as inputs to the Logic
Block.
Flip Flop
The ATF1504AS’s flip flop has very flexible data and con-
trol functions. The data input can come from either the XOR
gate, from a separate product term or directly from the I/O
pin. Selecting the separate product term allows creation of
a buried registered feedback within a combinatorial output
macrocell. (This feature is automatically implemented by
the fitter software). In addition to D, T, JK and SR opera-
tion, the flip flop can also be configured as a flow-through
latch. In this mode, data passes through when the clock is
high and is latched when the clock is low.
Foldback Bus
Each macrocell also generates a foldback product term.
This signal goes to the regional bus and is available to 4
macrocells. The foldback is an inverse polarity of one of the
macrocell’s product terms. The 4 foldback terms in each
region allows generation of high fan-in sum terms (up to 9
product terms) with a small additional delay.
The clock itself can either be one of the Global CLK Signal
GCK[0 : 2] or an individual product term. The flip flop
5
Figure 1. ATF1504AS Macrocell
by mode when no logic transitions are occurring. This not
only reduces power consumption during inactive periods,
but also provides a proportional power savings for most
applications running at system speeds below 50 MHz. This
feature may be selected as a design option.
Programmable Pin-Keeper Option for
Inputs and I/Os
The ATF1504AS offers the option of programming all input
and I/O pins so that pin keeper circuits can be utilized.
When any pin is driven high or low and then subsequently
left floating, it will stay at that previous high or low level.
This circuitry prevents unused input and I/O lines from
floating to intermediate voltage levels, which cause unnec-
essary power consumption and system noise. The keeper
circuits eliminate the need for external pull-up resistors and
eliminate their DC power consumption.
I/O Diagram
Input Diagram
To further reduce power, each ATF1504AS macrocell has
a Reduced Power bit feature. This feature allows individual
macrocells to be configured for maximum power savings.
This feature may be selected as a design option.
All ATF1504ASs also have an optional power down mode.
In this mode, current drops to below 10 mA. When the
power down option is selected, either PD1 or PD2 pins (or
both) can be used to power down the part. The power down
option is selected in the design source file. When enabled,
Speed/Power Management
The ATF1504AS has several built-in speed and power
management features. The ATF1504AS contains circuitry
that automatically puts the device into a low power stand-
ATF1504ASZ
6
ATF1504ASZ
the device goes into power down when either PD1 or PD2
is high. In the power down mode, all internal logic signals
are latched and held, as are any enabled outputs.
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup
times must be met before driving the clock pin-
high, and,
All pin transitions are ignored until the PD pin is brought
low. When the power down feature is enabled, the PD1 or
PD2 pin cannot be used as a logic input or output. How-
ever, the pin’s macrocell may still be used to generate bur-
ied foldback and cascade logic signals.
3. The clock must remain stable during TD.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF1504AS fuse patterns. Once programmed, fuse
verify is inhibited. However, the 16-bit User Signature
remains accessible.
All Power-Down AC Characteristic parameters are com-
puted from external input or I/O pins, with Reduced Power
Bit turned on. For macrocells in reduced-power mode
(Reduced power bit turned on), the reduced power adder,
tRPA, must be added to the AC parameters, which include
the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP
.
Programming
The ATF1504AS macrocell also has an option whereby the
power can be reduced on a per macrocell basis. By
enabling this power down option, macrocells that are not
used in an application can be turned down thereby reduc-
ing the overall power consumption of the device.
ATF1504AS devices are In-System Programmable (ISP)
devices utilizing the 4-pin JTAG protocol. This capability
eliminates package handling normally required for program
and facilitates rapid design iterations and field changes.
Atmel provides ISP hardware and software to allow pro-
gramming of the ATF1504AS via the PC. ISP is performed
by using either a download cable, or a comparable board
tester or a simple microprocessor interface.
Each output also has individual slew rate control. This may
be used to reduce system noise by slowing down outputs
that do not need to operate at maximum speed. Outputs
default to slow switching, and may be specified as fast
switching in the design file.
To facilitate ISP programming by the Automated Test
Equipment (ATE) vendors. Serial Vector Format (SVF) files
can be created by Atmel provided Software utilities.
Design Software Support
ATF1504AS designs are supported by several third party
tools. Automated fitters allow logic synthesis using a variety
of high level description languages and formats.
ATF1504AS devices can also be programmed using stan-
dard 3rd party programmers. With 3rd party programmer
the JTAG ISP port can be disabled thereby allowing 4 addi-
tional I/O pins to be used for logic.
Contact your local Atmel representatives or Atmel PLD
applications for details.
Power Up Reset
The ATF1504AS has a power-up reset option at two differ-
ent voltage trip levels when the device is being powered
down. Within the fitter, or during a conversion, if the
“power-reset” option is turned “on” (which is the default
option), the trip levels during power up or power down is at
2.8V. The user can change this default option from “on” to
“off” (within the fitter or specify it as a switch during conver-
sion). When this is done, the voltage trip level during
power-down changes from 2.8V to 0.7V. This is to ensure a
robust operating environment.
ISP Programming Protection
The ATF1504AS has a special feature which locks the
device and prevents the inputs and I/O from driving if the
programming process is interrupted due to any reason. The
inputs and I/O default to high-Z state during such a condi-
tion. In addition the pin keeper option preserves the former
state during device programming.
All ATF1504AS devices are initially shipped in the erased
state thereby making them ready to use for ISP.
The registers in the ATF1504AS are designed to reset dur-
ing power up. At a point delayed slightly from VCC crossing
Vrst, all registers will be reset to the low state. The output
state will depend on the polarity of the buffer.
Note:
For more information refer to the “Designing for In-Sys-
tem Programmability with Atmel CPLDs” application
note.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the fol-
lowing conditions are required:
7
DC and AC Operating Conditions
Commercial
0°C - 70°C
5V ± 5%
Industrial
-40°C - 85°C
5V ± 10%
Operating Temperature (Case)
V
CCINT or VCCIO (5V) Power Supply
CCIO (3.3V) Power Supply
V
3.0V - 3.6V
3.0V - 3.6V
DC Characteristics
Symbol Parameter
Condition
Min
Typ
Max
Units
Input or I/O Low
Leakage Current
IIL
VIN = VCC
-2
-10
µA
Input or I/O High
Leakage Current
IIH
2
10
40
Tri-State Output
IOZ
VO = VCC or GND
-40
µA
Off-State Current
Com.
Ind.
120
150
mA
mA
µA
µA
Std Mode
Power Supply Current,
Stand-by
VCC = Max
VIN = 0, VCC
ICC1
Com.
Ind.
100
100
“Z” Mode
Power Supply Current,
ICC2
VCC = Max
VIN = 0, VCC
“PD” Mode
4
10
mA
mA
Power Down Mode
Output Short Circuit
IOS
VOUT = 0.5V
-150
Current
Com.
Ind.
4.75
4.5
5.25
5.5
V
V
V
V
VCCIO
Supply Voltage
5.0V Device Output
3.3V Device Output
VCCIO
VIL
Supply Voltage
3.0
3.6
Input Low Voltage
-0.3
0.8
VCCINT
0.3
+
VIH
Input High Voltage
Output Low Voltage
Output High Voltage
2.0
V
V
Com.
Ind.
0.45
VIN = VIH or VIL
VCCIO = MIN, IOL = 12 mA
VOL
VIN = VIH or VIL
VCCIO = MIN, IOH = -4.0 mA
VOH
Note:
2.4
V
Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
Pin Capacitance
Typ
8
Max
10
Units
pF
Conditions
CIN
VIN = 0V; f = 1.0 MHz
CI/O
8
10
pF
VOUT = 0V; f = 1.0 MHz
Note:
Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
The OGI pin (high-voltage pin during programming) has a maximum capacitance of 12 pf.
ATF1504ASZ
8
ATF1504AS(Z)
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias.................................. -40°C to +85°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Note:
1. Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns. Max-
imum output pin voltage is VCC + 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
AC Characteristics
-7
-10
-15
-20
-25
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Units
Input or Feedback to
Non-Registered Output
tPD1
7.5
10
3
15
20
25
ns
I/O Input or Feedback to
Non-Registered Feedback
tPD2
7
9
3
12
16
25
ns
tSU
tH
Global Clock Setup Time
Global Clock Hold Time
6
0
7
0
11
0
16
0
20
0
ns
ns
Global Clock Setup Time of
Fast Input
tFSU
tFH
3
3
3
3
5
2
ns
Global Clock Hold Time of
Fast Input
0.5
0.5
1.0
1.5
MHz
tCOP
tCH
Global Clock to Output Delay
Global Clock High Time
Global Clock Low Time
Array Clock Setup Time
Array Clock Hold Time
Array Clock Output Delay
Array Clock High Time
Array Clock Low Time
4.5
7.5
5
8
10
20
13
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
3
3
2
4
4
3
3
5
5
4
4
6
6
4
5
7
7
5
6
tCL
tASU
tAH
tACOP
tACH
tACL
tCNT
10
15
3
3
4
4
6
6
8
8
10
10
Minimum Clock Global Period
8
8
10
10
13
13
17
17
22
22
Maximum Internal Global
Clock Frequency
fCNT
125
125
100
100
76.9
76.9
66
66
50
50
MHz
ns
tACNT
fACNT
Minimum Array Clock Period
Maximum Internal Array
Clock Frequency
MHz
(continued)
= Preliminary Information
9
AC Characteristics (Continued)
-7
-10
-15
-20
-25
Symbol
FMAX
tIN
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Units
MHz
ns
Maximum Clock Frequency
Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Fast Input Delay
166.7
125
100
83.3
60
0.5
0.5
1
0.5
0.5
1
2
2
2
8
1
6
6
3
2
2
2
2
tIO
ns
tFIN
2
2
ns
tSEXP
tPEXP
tLAD
Foldback Term Delay
Cascade Logic Delay
Logic Array Delay
4
5
10
1
12
1.2
8
ns
0.8
3
0.8
5
ns
7
ns
tLAC
Logic Control Delay
3
5
7
8
ns
tIOE
Internal Output Enable Delay
2
2
3
4
ns
Output Buffer and Pad Delay
(Slow slew rate = OFF;
VCCIO = 5V; CL = 35 pF)
tOD1
tOD2
tOD3
2
2.5
5
1.5
2.0
5.5
4
5
8
5
6
6
7
ns
ns
ns
Output Buffer and Pad Delay
(Slow slew rate = OFF;
VCCIO = 3.3V; CL = 35 pF)
Output Buffer and Pad Delay
(Slow slew rate = ON;
10
10
VCCIO = 5V or 3.3V; CL = 35 pF)
(continued)
Note:
See ordering information for valid part numbers.
= Preliminary Information
Timing Model
ATF1504ASZ
10
ATF1504ASZ
AC Characteristics (Continued)
-7
-10
-15
-20
-25
Max
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Min
Units
Output Buffer Enable Delay
(Slow slew rate = OFF;
VCCIO = 5.0V; CL = 35 pF)
tZX1
4.0
5.0
7
9
10
10
ns
Output Buffer Enable Delay
(Slow slew rate = OFF;
tZX2
4.5
5.5
7
9
ns
VCCIO = 3.3V; CL = 35 pF)
Output Buffer Enable Delay
(Slow slew rate = ON;
VCCIO = 5.0V/3.3V; CL = 35 pF)
tZX3
9
4
9
5
10
6
11
7
12
8
ns
ns
Output Buffer Disable Delay
(CL = 5 pF)
tXZ
tSU
Register Setup Time
Register Hold Time
3
2
3
3
4
4
2
2
5
5
2
2
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tH
tFSU
tFH
Register Setup Time of Fast Input
Register Hold Time of Fast Input
Register Delay
3
3
3
0.5
0.5
2.5
tRD
1
1
2
2
1
1
2
2
2
2
tCOMB
tIC
Combinatorial Delay
Array Clock Delay
3
5
6
7
8
tEN
Register Enable Time
Global Control Delay
Register Preset Time
Register Clear Time
Switch Matrix Delay
3
5
6
7
8
tGLOB
tPRE
tCLR
tUIM
tRPA
1
1
1
1
1
2
3
4
5
6
2
3
4
5
6
1
1
2
2
2
Reduced-Power Adder(2)
10
11
13
14
15
Notes: 1. See ordering information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC,tTIC, tACL, and tSEXP parameters for macrocells running in the reduced-
power mode.
= Preliminary Information
Input Test Waveforms and
Measurement Levels
Output AC Test Loads
(3.0V)*
(703 )*
tR, tF = 1.5 ns typical
(8060 )*
Note:
*Numbers in parenthesis refer to 3.0V operating condi-
tions (preliminary).
11
signals except the power down pin are blocked. Input and
I/O hold latches remain active to insure that pins do not
float to indeterminate levels, further reducing system
power. The power down pin feature is enabled in the logic
design file. Designs using the power down pin may not use
the PD pin logic array input. However, all other PD pin mac-
rocell resources may still be used, including the buried
feedback and foldback product term array inputs.
Power Down Mode
The ATF1504AS includes an optional pin controlled power
down feature.When this mode is enabled, the PD pin acts
as the power down pin. When the PD pin is high, the device
supply current is reduced to less than 3 mA. During power
down, all output data and internal logic states are latched
and held. Therefore, all registered and combinatorial output
data remain valid. Any outputs which were in a Hi-Z state at
the onset will remain at Hi-Z. During power down, all input
Power Down AC Characteristics(1)(2)
-7
-10
-15
-20
-25
Symbol Parameter
Min
7
Max
Min Max Min Max Min Max Min Max Units
tIVDH
tGVDH
tCVDH
tDHIX
tDHGX
tDHCX
tDLIV
Valid I, I/O Before PD High
10
10
10
15
15
15
20
20
20
25
25
25
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
Valid OE(2) Before PD High
Valid Clock(2) Before PD High
I, I/O Don’t Care After PD High
OE(2) Don’t Care After PD High
Clock(2) Don’t Care After PD High
PD Low to Valid I, I/O
7
7
12
12
12
1
15
15
15
1
25
25
25
1
30
30
30
1
35
35
35
1
tDLGV
tDLCV
tDLOV
PD Low to Valid OE (Pin or Term)
PD Low to Valid Clock (Pin or Term)
PD Low to Valid Output
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Notes: 1. For slow slew outputs, add tSSO
.
= Preliminary Information
2. Pin or Product Term.
standard JTAG programming protocol established by IEEE
Standard 1149.1 using 5V TTL-level programming signals
from the ISP interface for in-system programming. The
JTAG feature is a programmable option. If JTAG (BST or
ISP) is not needed, then the four JTAG control pins are
available as I/O pins.
JTAG-BST/ISP Overview
The JTAG boundary-scan testing is controlled by the Test
Access Port (TAP) controller in the ATF1504AS. The
boundary-scan technique involves the inclusion of a shift-
register stage (contained in a boundary-scan cell) adjacent
to each component so that signals at component bound-
aries can be controlled and observed using scan testing
principles. Each input pin and I/O pin has its own boundary
scan cell (BSC) in order to support boundary scan testing.
The ATF1504AS does not currently include a Test Reset
(TRST) input pin because the TAP controller is automati-
cally reset at power up. The five JTAG modes supported
include: SAMPLE/PRELOAD, EXTEST, BYPASS,
IDCODE and HIGHZ. The ATF1504AS’s ISP can be fully
described using JTAG’s BSDL as described in IEEE Stan-
dard 1149.1b. This allows ATF1504AS programming to be
described and implemented using any one of the 3rd party
development tools supporting this standard.
JTAG Boundary Scan Cell (BSC)
Testing
The ATF1504AS contains up to 68 I/O pins and 4 input
pins, depending on the device type and package type
selected. Each input pin and I/O pin has its own boundary
scan cell (BSC) in order to support boundary scan testing
as described in detail by IEEE Standard 1149.1. Typical
BSC consists of three capture registers or scan registers
and up to two update registers. There are two types of
BSCs, one for input or I/O pin, and one for the macrocells.
The BSCs in the device are chained together through the
capture registers. Input to the capture register chain is fed
in from the TDI pin while the output is directed to the TDO
pin. Capture registers are used to capture active device
data signals, to shift data in and out of the device and to
The ATF1504AS has the option of using four JTAG-stan-
dard I/O pins for boundary scan testing (BST) and in-sys-
tem programming (ISP) purposes. The ATF1504AS is
programmable through the four JTAG pins using the IEEE
ATF1504ASZ
12
ATF1504ASZ
load data into the update registers. Control signals are gen-
erated internally by the JTAG TAP controller. The BSC
configuration for the input and I/O pins and macrocells are
shown below.
BSC Configuration for Macrocell
Pin BSC
TDO
BSC Configuration for Input and I/O
Pins (except JTAG TAP Pins)
0
DQ
Pin
1
Capture
DR
Clock
Shift
TDI
TDO
OEJ
Note:
The ATF1504AS has pull-up option on TMS and TDI
pins. This feature is selected as a design option.
0
1
0
1
D Q
D Q
OUTJ
0
1
Pin
0
1
D Q
D Q
Capture
DR
Update
DR
Mode
TDI
Clock
Shift
Macrocell BSC
13
PCI Compliance
PCI Voltage-to-Current Curves for +5V
Signaling in Pull-Down Mode
The ATF1504AS also supports the growing need in the
industry to support the new Peripheral Component Inter-
connect (PCI) interface standard in PCI-based designs and
specifications. The PCI interface calls for high current driv-
ers which are much larger than the traditional TTL drivers.
In general, PLDs and FPGAs parallel outputs to support the
high current load required by the PCI interface. The
ATF1504AS allows this without contributing to system
noise while delivering low output to output skew. Having a
programmable high drive option is also possible without
increasing output delay or pin capacitance. The PCI electri-
cal characteristics appear on the next page.
Pull Down
VCC
AC drive
point
2.2
DC
drive point
0.55
Test Point
PCI Voltage-to-Current Curves for +5V
Signaling in Pull-Up Mode
Current (mA)
95
3.6
380
Pull Up
VCC
Test Point
2.4
DC
drive point
1.4
AC drive
point
Current (mA)
-44
-2
-178
ATF1504ASZ
14
ATF1504AS(Z)
PCI DC Characteristics (Preliminary)
Symbol
VCC
VIH
Parameter
Conditions
Min
4.75
2.0
Max
5.25
Units
V
Supply Voltage
Input High Voltage
Input Low Voltage
VCC + 0.5
0.8
V
VIL
-0.5
V
IIH
Input High Leakage Current
Input Low Leakage Current
Output High Voltage
Output Low Voltage
Input Pin Capacitance
CLK Pin Capacitance
IDSEL Pin Capacitance
Pin Inductance
VIN = 2.7V
70
µA
µA
V
IIL
VIN = 0.5V
-70
VOH
VOL
IOUT = -2 mA
IOUT = 3 mA, 6 mA
2.4
0.55
10
12
8
V
CIN
pF
pF
pF
nH
CCLK
CIDSEL
LPIN
20
Note:
Leakage Current is with Pin-Keeper off.
PCI AC Characteristics (Preliminary)
Symbol
Parameter
Conditions
Min
Max
Units
mA
mA
mA
µA
IOH(AC)
Switching
0 < VOUT ≤ 1.4
1.4 < VOUT < 2.4
3.1 < VOUT < VCC
VOUT = 3.1V
-44
Current High
-44+(VOUT - 1.4)/0.024
Equation A
-142
(Test High)
Switching
IOL(AC)
VOUT > 2.2V
95
mA
mA
mA
mA
mA
V/ns
V/ns
Current Low
2.2 > VOUT > 0
0.1 > VOUT > 0
VOUT = 0.71
VOUT/0.023
Equation B
206
(Test Point)
ICL
Low Clamp Current
Output Rise Slew Rate
Output Fall Slew Rate
-5 < VIN ≤ -1
-25+(VIN + 1)/0.015
SLEWR
SLEWF
0.4V to 2.4V load
2.4V to 0.4V load
0.5
0.5
3
3
Notes: 1. Equation A: IOH = 11.9 (VOUT - 5.25) * (VOUT + 2.45) for VCC > VOUT > 3.1V.
2. Equation B: IOL = 78.5 * VOUT * (4.4 - VOUT) for 0V < VOUT < 0.71V.
15
ATF1504AS Dedicated Pinouts
44-Pin
TQFP
44-Pin
68-Pin
J-Lead
84-Pin
J-Lead
100-Pin
PQFP
100-Pin
TQFP
Dedicated Pin
INPUT/OE2/GCLK2
INPUT/GCLR
J-Lead
40
39
38
37
35
5, 19
1
2
2
1
2
1
92
91
90
89
1
INPUT/OE1
44
68
84
90
88
INPUT/GCLK1
I/O /GCLK3
43
67
83
89
87
41
65
81
87
85
I/O / PD (1,2)
11, 25
7
17, 37
12
20, 46
14
14, 44
6
12, 42
4
I/O / TDI (JTAG)
I/O / TMS (JTAG)
I/O / TCK (JTAG)
I/O / TDO (JTAG)
7
13
19
23
17
15
26
32
32
50
62
64
62
38
57
71
75
73
6, 16, 26, 34,
38, 48, 58, 66
7, 19, 32, 42,
47, 59, 72, 82
13, 28, 40, 45,
61, 76, 88, 97
11, 26, 38, 43,
59, 74, 86, 95
GND
4, 16, 24, 36
9, 17, 29, 41
-
10, 22, 30, 42
VCCINT
VCCIO
3, 15, 23, 35
-
3, 35
3, 43
41, 93
39, 91
11, 21, 31, 43,
53, 63
13, 26, 38, 53,
66, 78
5, 20, 36, 53,
68, 84
3, 18, 34, 51,
66, 82
1, 2, 7, 9,
1, 2, 5, 7, 22,
24, 27, 28, 49,
50, 53, 55, 70,
72, 77, 78
24, 26, 29, 30,
51, 52, 55, 57,
72, 74, 79, 80
N/C
-
-
-
-
# of Signal Pins
36
32
36
32
52
48
68
64
68
64
68
64
# User I/O Pins
OE (1, 2)
Global OE Pins
GCLR
Global Clear Pin
Global Clock Pins
Power down pins
GCLK (1, 2, 3)
PD (1, 2)
TDI, TMS, TCK, TDO
GND
JTAG pins used for Boundary Scan Testing or In-System Programming
Ground Pins
VCCINT
VCC pins for the device (+5V - Internal)
VCCIO
VCC pins for output drivers (for I/O pins) (+5V or 3.3V - I/Os)
ATF1504AS(Z)
16
ATF1504AS(Z)
ATF1504AS I/O Pinouts
44-Pin
PLCC
44-Pin
TQFP
68-Pin
PLCC
84-Pin
PLCC
100-Pin
PQFP
100-Pin
TQFP
44-Pin
PLCC
44-Pin
TQFP
68-Pin
PLCC
84-Pin
PLCC
100-Pin
PQFP
100-Pin
TQFP
MC
1
PLC
A
MC
33
PLC
C
12
-
6
-
18
-
22
21
16
15
14
13
24
-
18
-
36
-
44
45
42
43
40
41
2
A
34
C
A/
PD1
C/
PD2
3
11
5
17
20
14
12
35
25
19
37
46
44
42
4
5
6
7
A
A
A
A
9
8
-
3
2
-
15
14
13
-
18
17
16
15
12
11
10
8
10
9
36
37
38
39
C
C
C
C
26
27
-
20
21
-
39
40
41
-
48
49
50
51
46
47
48
49
44
45
46
47
8
-
-
6
-
-
8/
TDI
A
7
1
12
14
6
4
40
C
28
22
42
52
50
48
9
A
A
A
A
A
A
A
-
-
-
-
10
-
12
11
10
9
4
3
2
41
42
43
44
45
46
47
C
C
C
C
C
C
C
29
-
23
-
44
-
54
55
56
57
58
60
61
54
56
58
59
60
62
63
52
54
56
57
58
60
61
10
11
12
13
14
15
1
6
-
44
-
9
8
7
5
-
100
99
98
96
95
98
97
96
94
93
-
-
45
46
47
49
-
-
-
-
-
8
-
-
5
-
43
-
6
31
-
25
-
5
48/
TCK
16
A
4
42
4
4
94
92
C
32
26
50
62
64
62
17
18
19
20
21
22
23
B
B
B
B
B
B
B
21
-
15
-
33
-
41
40
39
37
36
35
34
39
38
37
35
34
33
32
37
36
35
33
32
31
30
49
50
51
52
53
54
55
D
D
D
D
D
D
D
33
-
27
-
51
-
63
64
65
67
68
69
70
65
66
67
69
70
71
73
63
64
65
67
68
69
71
20
19
18
-
14
13
12
-
32
30
29
28
-
34
36
37
-
28
30
31
-
52
54
55
56
-
-
-
-
-
56/
TDO
24
B
17
11
27
33
31
29
D
38
32
57
71
75
73
25
26
27
28
29
30
31
B
B
B
B
B
B
B
16
-
10
-
25
-
31
30
29
28
27
25
24
27
25
23
22
21
19
18
25
22
21
20
19
17
16
57
58
59
60
61
62
63
D
D
D
D
D
D
D
39
-
33
-
59
-
73
74
75
76
77
79
80
77
78
81
82
83
85
86
75
76
79
80
81
83
84
-
-
24
23
22
20
-
-
-
60
61
62
64
-
-
-
-
-
-
-
-
-
14
-
8
-
40
-
34
-
32/
TMS
D/
GCLK3
B
13
7
19
23
17
15
64
41
35
65
81
87
85
17
Ordering Information
tPD
tCO1
fMAX
(ns)
(ns)
(MHz)
Ordering Code
Package
Operation Range
7.5
10
10
15
15
4.5
166.7
125
125
100
100
ATF1504AS-7 AC44
ATF1504AS-7 JC44
ATF1504AS-7 JC68
ATF1504AS-7 JC84
ATF1504AS-7 QC100
ATF1504AS-7 AC100
44A
44J
68J
84J
100Q1
100A
Commercial
(0°C to 70°C)
5
ATF1504AS-10 AC44
ATF1504AS-10 JC44
ATF1504AS-10 JC68
ATF1504AS-10 JC84
ATF1504AS-10 QC100
ATF1504AS-10 AC100
44A
44J
68J
84J
100Q1
100A
Commercial
(0°C to 70°C)
5
ATF1504AS-10 AI44
ATF1504AS-10 JI44
ATF1504AS-10 JI68
ATF1504AS-10 JI84
ATF1504AS-10 QI100
ATF1504AS-10 AI100
44A
44J
68J
84J
100Q1
100A
Industrial
(-40°C to +85°C)
8
ATF1504AS-15 AC44
ATF1504AS-15 JC44
ATF1504AS-15 JC68
ATF1504AS-15 JC84
ATF1504AS-15 QC100
ATF1500AS-15 AC100
44A
44J
68J
84J
100Q1
100A
Commercial
(0°C to 70°C)
8
ATF1504AS-15 AI44
ATF1504AS-15 JI44
ATF1504AS-15 JI68
ATF1504AS-15 JI84
ATF1504AS-15 QI100
ATF1504AS-15 AI100
44A
44J
68J
84J
100Q1
100A
Industrial
(-40°C to +85°C)
Package Type
44A
44-Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44-Lead, Plastic J-Leaded Chip Carrier OTP (PLCC)
68-Lead, Plastic J-Leaded Chip Carrier (PLCC)
84-Lead, Plastic J-Leaded Chip Carrier (PLCC)
100-Lead, Plastic Quad Flat Pack (PQFP)
44J
68J
84J
100Q1
100A
100-Lead, Thin Quad Flat Pack (TQFP)
ATF1504AS(Z)
18
ATF1504AS(Z)
Ordering Information (Continued)
tPD
tCO1
fMAX
(ns)
(ns)
(MHz)
Ordering Code
Package
Operation Range
20
25
25
12
15
15
83.3
ATF1504ASZ-20 AC44
ATF1504ASZ-20 JC44
ATF1504ASZ-20 JC68
ATF1504ASZ-20 JC84
ATF1504ASZ-20 QC100
ATF1504ASZ-20 AC100
44A
44J
68J
84J
100Q1
100A
Commercial
(0°C to 70°C)
70
ATF1504ASZ-25 AC44
ATF1504ASZ-25 JC84
ATF1504ASZ-25 JC68
ATF1504ASZ-25 JC84
ATF1504ASZ-25 QC100
ATF1504ASZ-25 AC100
44A
44J
68J
84J
100Q1
100A
Commercial
(0°C to 70°C)
70
ATF1504ASZ-25 AI44
ATF1504ASZ-25 JI84
ATF1504ASZ-25 JI68
ATF1504ASZ-25 JI84
ATF1504ASZ-25 QI100
ATF1504ASZ-25 AI100
44A
44J
68J
84J
100Q1
100A
Industrial
(-40°C to +85°C)
Package Type
44A
44-Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44-Lead, Plastic J-Leaded Chip Carrier OTP (PLCC)
68-Lead, Plastic J-Leaded Chip Carrier (PLCC)
84-Lead, Plastic J-Leaded Chip Carrier (PLCC)
100-Lead, Plastic Quad Flat Pack (PQFP)
44J
68J
84J
100Q1
100A
100-Lead, Thin Quad Flat Pack (TQFP)
19
Packaging Information
44A, 44-Lead, Thin (1.0 mm) Plastic Gull Wing
Quad Flat Package (TQFP)
Dimensions in Millimeters and (Inches)*
44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AC
.045(1.14) X 30° - 45°
.045(1.14) X 45°
PIN NO. 1
IDENTIFY
.012(.305)
.008(.203)
.630(16.0)
.590(15.0)
.656(16.7)
.650(16.5)
SQ
.032(.813)
.026(.660)
.021(.533)
.013(.330)
.695(17.7)
.685(17.4)
SQ
.043(1.09)
.020(.508)
.120(3.05)
.050(1.27) TYP
.500(12.7) REF SQ
.090(2.29)
.180(4.57)
.165(4.19)
.022(.559) X 45° MAX (3X)
* Controlling dimension: millimeters
68J, 68-Lead, Plastic J-Leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AE
84J, 84-Lead, Plastic J-Leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AF
ATF1504AS(Z)
20
ATF1504AS(Z)
Packaging Information
100A, 100-Lead, Thin (1.0 mm) Plastic Gull Wing
Quad Flat Package (TQFP)
100Q1, 100-Lead, Plastic Gull Wing Quad Flat
Package (PQFP)
Dimensions in Millimeters and (Inches)*
Dimensions in Millimeters and (Inches)
16.25(0.640)
15.75(0.620)
.687(17.44)
PIN 1 ID
.667(16.95)
PIN 1 ID
0.17(0.007)
0.27(0.011)
.792(20.12)
0.026(.65) BSC
.782(19.87)
0.56(0.022)
0.44(0.018)
.016(0.41)
.923(23.45)
.009(0.22)
.904(22.95)
.556(14.12)
.546(13.87)
14.10(0.555)
.134(3.40) MAX
7
0
0.95(0.037)
1.27(0.05)
13.90(0.547)
.010(0.25)
.004(0.10)
0.20(0.008)
0.10(0.004)
0-7
.041(1.03)
.028(0.73)
0.05(0.002)
0.15(0.006)
.004(0.10) MIN
0.45(0.018)
0.75(0.030)
*Controlling dimension: millimeters
21
相关型号：
SI9130DB
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