ATF1508AS-10QC160 [ATMEL]
High Performance E2 PLD; 高性能可编程逻辑器件E2
| 型号： | ATF1508AS-10QC160 |
| 厂家： | 
ATMEL |
| 描述： | High Performance E2 PLD |
| 文件： | 总22页 (文件大小：396K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High Density, High Performance Electrically Erasable Complex
Programmable Logic Device
– 128 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 68, 84, 100, 160-pins
– 7.5 ns Maximum Pin-to-Pin Delay
– Registered Operation Up To 125 MHz
– Enhanced Routing Resources
• Flexible Logic Macrocell
– D/T/Latch Configurable Flip Flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
High
Performance
E2 PLD
– Programmable Output Open Collector Option
– Maximum Logic utilization by burying a register within a COM output
• Advanced Power Management Features
– Automatic 100 µA Stand-By for “Z” Version (Max.)
– Pin-Controlled 100 µA Stand-By Mode (Typical)
– Programmable Pin-Keeper Inputs and I/Os
– Reduced-Power Feature Per Macrocell
• Available in Commercial and Industrial Temperature Ranges
• Available in 84-pin PLCC and 100-pin PQFP and TQFP and
160-pin PQFP Packages
ATF1508AS/Z
• Advanced Flash Technology
– 100% Tested
– Completely Reprogrammable
– 100 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-Up Immunity
• JTAG Boundary-Scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
• Fast In-System Programmability (ISP) via JTAG
• PCI-compliant
• 3.3 or 5.0V I/O pins
• Security Fuse Feature
Enhanced Features
• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
• Output Enable Product Terms
• D - Latch Mode
• Combinatorial Output with Registered Feedback within any Macrocell
• Three Global Clock Pins
• ITD ( Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
• Fast Registered Input from Product Term
• Programmable “Pin-Keeper” Option
• VCC Power-Up Reset Option
• Pull-Up Option on JTAG Pins TMS and TDI
• Advanced Power Management Features
– Edge Controlled Power Down “Z”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O for “Z” Parts
Rev. 0784C–4/98
84-Lead PLCC
Top View
100-Lead TQFP
Top View
I/O/PD1 12
VCCIO 13
I/O/TDI 14
I/O 15
74 I/O
I/O/PD1
I/O
1
2
3
4
5
6
7
8
9
75 I/O
73 I/O
74 GND
73 I/O/TDO
72 I/O
72 GND
71 I/O/TDO
70 I/O
VCCIO
I/O/TDI
I/O
I/O 16
71 I/O
I/O 17
69 I/O
I/O
70 I/O
I/O 18
68 I/O
I/O
69 I/O
GND 19
I/O 20
67 I/O
I/O
68 I/O
66 VCCIO
65 I/O
I/O
67 I/O
I/O 21
I/O 10
GND 11
I/O 12
66 VCCIO
65 I/O
I/O 22
64 I/O
64 I/O
I/O/TMS 23
I/O 24
63 I/O
I/O 13
63 I/O
62 I/O/TCK
61 I/O
I/O 14
62 I/O/TCK
61 I/O
I/O 25
I/O/TMS 15
I/O 16
VCCIO 26
I/O 27
60 I/O
60 I/O
59 GND
58 I/O
I/O 17
59 GND
58 I/O
I/O 28
VCCIO 18
I/O 19
I/O 29
57 I/O
57 I/O
I/O 30
56 I/O
I/O 20
56 I/O
I/O 31
55 I/O
I/O 21
55 I/O
GND 32
54 I/O
I/O 22
54 I/O
I/O 23
53 I/O
I/O 24
52 I/O
I/O 25
51 VCCIO
100-Lead PQFP
Top View
160-Lead PQFP
Top View
N/C
N/C
1
2
3
4
5
6
7
8
9
120 N/C
I/O
1
2
3
4
5
6
7
8
9
80 I/O
119 N/C
118 N/C
117 N/C
116 N/C
115 N/C
114 N/C
113 GND
112 I/O/TDO
111 I/O
110 I/O
109 I/O
108 I/O
107 I/O
106 I/O
105 I/O
104 VCCIO
103 I/O
102 I/O
101 I/O
100 I/O
99 I/O/TCK
98 I/O
I/O
I/O/PD1
I/O
79 I/O
78 I/O
77 I/O
76 GND
75 I/O/TDO
74 I/O
73 I/O
72 I/O
71 I/O
70 I/O
69 I/O
68 VCCIO
67 I/O
66 I/O
65 I/O
64 I/O/TCK
63 I/O
62 I/O
61 GND
60 I/O
59 I/O
58 I/O
57 I/O
56 I/O
55 I/O
54 I/O
53 VCCIO
52 I/O
51 I/O
N/C
N/C
N/C
VCCIO
I/O/TDI
I/O
N/C
N/C
VCCIO
I/O/TDI
I/O
I/O
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
GND 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O/TMS 22
I/O 23
I/O 24
I/O 25
VCCIO 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
N/C 34
N/C 35
N/C 36
N/C 37
N/C 38
N/C 39
N/C 40
I/O 10
I/O 11
I/O 12
GND 13
I/O 14
I/O 15
I/O 16
I/O/TMS 17
I/O 18
I/O 19
VCCIO 20
I/O 21
I/O 22
97 I/O
I/O 23
96 I/O
I/O 24
95 GND
94 I/O
I/O 25
I/O 26
93 I/O
I/O 27
92 I/O
GND 28
I/O 29
91 I/O
90 I/O
I/O 30
89 I/O
88 I/O
87 N/C
86 N/C
85 N/C
84 N/C
83 N/C
82 N/C
81 N/C
ATF1508AS/Z
2
ATF1508AS/Z
Block Diagram
6 to 12
3
Description
The ATF1508AS is a high performance, high density Com-
plex Programmable Logic Device (CPLD) which utilizes
Atmel’s proven electrically erasable Flash memory technol-
ogy. With 128 logic macrocells and up to 100 inputs, it eas-
ily integrates logic from several TTL, SSI, MSI, LSI and
classic PLDs. The ATF1508AS’s enhanced routing switch
matrices increase usable gate count, and increase odds of
successful pin-locked design modifications.
and control signals. The PTMUX programming is deter-
mined by the design compiler, which selects the optimum
macrocell configuration.
OR/XOR/CASCADE Logic
The ATF1508AS’s logic structure is designed to efficiently
support all types of logic. Within a single macrocell, all the
product terms can be routed to the OR gate, creating a 5-
input AND/OR sum term. With the addition of the CASIN
from neighboring macrocells, this can be expanded to as
many as 40 product terms with a very small additional
delay.
The ATF1508AS has up to 96 bi-directional I/O pins and 4
dedicated input pins, depending on the type of device pack-
age selected. Each dedicated pin can also serve as a glo-
bal control signal; register clock, register reset or output
enable. Each of these control signals can be selected for
use individually within each macrocell.
The macrocell’s XOR gate allows efficient implementation
of compare and arithmetic functions. One input to the XOR
comes from the OR sum term. The other XOR input can be
a product term or a fixed high or low level. For combinato-
rial outputs, the fixed level input allows polarity selection.
For registered functions, the fixed levels allow DeMorgan
minimization of product terms. The XOR gate is also used
to emulate T- and JK-type flip-flops.
Each of the 128 macrocells generates a buried feedback,
which goes to the global bus. Each input and I/O pin also
feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus.
Each macrocell also generates a foldback logic term, which
goes to a regional bus. Cascade logic between macrocells
in the ATF1508AS allows fast, efficient generation of com-
plex logic functions. The ATF1508AS contains eight such
logic chains, each capable of creating sum term logic with a
fan in of up to 40 product terms
Flip Flop
The ATF1508AS’s flip flop has very flexible data and con-
trol functions. The data input can come from either the
XOR gate, from a separate product term or directly from
the I/O pin. Selecting the separate product term allows cre-
ation of a buried registered feedback within a combinatorial
output macrocell. (This feature is automatically imple-
mented by the fitter software). In addition to D, T, JK and
SR operation, the flip flop can also be configured as a flow-
through latch. In this mode, data passes through when the
clock is high and is latched when the clock is low.
The ATF1508AS macrocell, shown in Figure 1, is flexible
enough to support highly complex logic functions operating
at high speed. The macrocell consists of five sections:
product terms and product term select multiplexer;
OR/XOR/CASCADE logic; a flip-flop; output select and
enable; and logic array inputs.
Unused Macrocells are automatically disabled by the com-
piler to decrease power consumption. A Security Fuse,
when programmed, protects the contents of the
ATF1508AS. Two bytes (16 bits) of User Signature are
accessible to the user for purposes such as storing project
name, part number, revision or date. The User Signature is
accessible regardless of the state of the Security Fuse.
The clock itself can either be the Global CLK Signal (GCK)
or an individual product term. The flip flop changes state on
the clock's rising edge. When the GCK signal is used as
the clock, one of the macrocell product terms can be
selected as a clock enable. When the clock enable function
is active and the enable signal (product term) is low, all
clock edges are ignored. The flip flop’s asynchronous reset
signal (AR) can be either the Global Clear (GCLEAR), a
product term, or always off. AR can also be a logic OR of
GCLEAR with a product term. The asynchronous preset
(AP) can be a product term or always off.
The ATF1508AS device is an In-System Programmable
(ISP) device. It uses the industry standard 4-pin JTAG
interface (IEEE Std. 1149.1), and is fully compliant with
JTAG’s Boundary Scan Description Language (BSDL). ISP
allows the device to be programmed without removing it
from the printed circuit board. In addition to simplifying the
manufacturing flow, ISP also allows design modifications to
be made in the field via software.
Output Select and Enable
The ATF1508AS macrocell output can be selected as reg-
istered or combinatorial. The buried feedback signal can be
either combinatorial or registered signal regardless of
whether the output is combinatorial or registered.
Product Terms and Select MUX
Each ATF1508AS macrocell has five product terms. Each
product term receives as its inputs all signals from both the
global bus and regional bus.
The output enable multiplexer (MOE) controls the output
enable signals. Any buffer can be permanently enabled for
simple output operation. Buffers can also be permanently
disabled to allow use of the pin as an input. In this configu-
ration all the macrocell resources are still available, includ-
The product term select multiplexer (PTMUX) allocates the
five product terms as needed to the macrocell logic gates
ATF1508AS/Z
4
ATF1508AS/Z
ing the buried feedback, expander and CASCADE logic.
The output enable for each macrocell can be selected as
one of the global OUTPUT enable signals. The device has
six global OE signals.
macrocell’s product terms. The 16 foldback terms in each
region allows generation of high fan-in sum terms (up to 21
product terms) with a small additional delay.
3.3V or 5.0V I/O Operation
Global Bus/Switch Matrix
The ATF1508AS device has two sets of VCC pins viz,
VCCINT and VCCIO. VCCINT pins must always be connected to
a 5.0V power supply. VCCINT pins are for input buffers and
are “compatible” with both 3.3V and 5.0V inputs. VCCIO pins
are for I/O output drives and can be connected for 3.3/5.0V
power supply.
The global bus contains all input and I/O pin signals as well
as the buried feedback signal from all 128 macrocells.
The Switch Matrix in each Logic Block receives as its inputs
all signals from the global bus. Under software control, up
to 40 of these signals can be selected as inputs to the
Logic Block.
Open-Collector Output Option
Foldback Bus
This option enables the device output to provide control
signals such as an interrupt that can be asserted by any of
the several devices.
Each macrocell also generates a foldback product term.
This signal goes to the regional bus and is available to 16
macrocells. The foldback is an inverse polarity of one of the
5
Figure 1. ATF1508AS Macrocell
Programmable Pin-Keeper Option
for Inputs and I/Os
Speed/Power Management
The ATF1508AS has several built-in speed and power
management features. The ATF1508AS contains circuitry
that automatically puts the device into a low power stand-
by mode when no logic transitions are occurring. This not
only reduces power consumption during inactive periods,
but also provides a proportional power savings for most
applications running at system speeds below 5 - 10 MHz.
The ATF1508AS offers the option of programming all input
and I/O pins so that “pin keeper” circuits can be utilized.
When any pin is driven high or low and then subsequently
left floating, it will stay at that previous high or low level.
This circuitry prevents unused input and I/O lines from
floating to intermediate voltage levels, which cause unnec-
essary power consumption and system noise. The keeper
circuits eliminate the need for external pull-up resistors and
eliminate their DC power consumption.
To further reduce power, each ATF1508AS macrocell has
a Reduced Power bit feature. This feature allows individual
macrocells to be configured for maximum power savings.
This feature may be selected as a design option.
I/O Diagram
Input Diagram
ATF1508AS/Z
6
ATF1508AS/Z
All ATF1508s also have an optional power down mode. In
this mode, current drops to below 10 mA. When the power
down option is selected, either PD1 or PD2 pins (or both)
can be used to power down the part. The power down
option is selected in the design source file. When enabled,
the device goes into power down when either PD1 or PD2
is high. In the power down mode, all internal logic signals
are latched and held, as are any enabled outputs.
uncertainty of how VCC actually rises in the system, the fol-
lowing conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup times
must be met before driving the clock pin high, and,
3. The clock must remain stable during TPR
.
Security Fuse Usage
All pin transitions are ignored until the PD pin is brought
low. When the power down feature is enabled, the PD1 or
PD2 pin cannot be used as a logic input or output. How-
ever, the pin’s macrocell may still be used to generate bur-
ied foldback and cascade logic signals.
A single fuse is provided to prevent unauthorized copying
of the ATF1508AS fuse patterns. Once programmed, fuse
verify is inhibited. However, User Signature and device ID
remains accessible.
All Power-Down AC Characteristic parameters are com-
puted from external input or I/O pins, with Reduced Power
Bit turned on. For macrocells in reduced-power mode
(Reduced power bit turned on), the reduced power adder,
tRPA, must be added to the AC parameters, which include
Programming
ATF1508AS devices are In-System Programmable (ISP)
devices utilizing the 4-pin JTAG protocol. This capability
eliminates package handling normally required for program
and facilitates rapid design iterations and field changes.
the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP
.
Each output also has individual slew rate control. This may
be used to reduce system noise by slowing down outputs
that do not need to operate at maximum speed. Outputs
default to slow switching, and may be specified as fast
switching in the design file.
Atmel provides ISP hardware and software to allow pro-
gramming of the ATF1508AS via the PC. ISP is perfomed
by using either a download cable, or a comparable board
tester or a simple microprocessor interface.
To facilitate ISP programming by the Automated Test
Equipment (ATE) vendors, Serial Vector Format (SVF)
files can be created by Atmel provided Software utilities.
Design Software Support
ATF1508AS designs are supported by several third party
tools. Automated fitters allow logic synthesis using a variety
of high level description languages and formats.
ATF1508AS devices can also be programmed using stan-
dard 3rd party programmers. With 3rd party programmer
the JTAG ISP port can be disabled thereby allowing 4 addi-
tional I/O pins to be used for logic.
Power Up Reset
Contact your local Atmel representatives or Atmel PLD
applications for details.
The ATF1508AS has a power-up reset option at two differ-
ent voltage trip levels when the device is being powered
down. Within the fitter, or during a conversion, if the
“power-reset” option is turned “on” ( which is the default
option), the trip levels during power up or power down is at
2.8V. The user can change this default option from “on” to
“off” (within the fitter or specify it as a switch during conver-
sion). When this is done, the voltage trip level during
power-down changes from 2.8V to 0.7V. This is to ensure a
robust operating environment.
ISP Programming Protection
The ATF1508AS has a special feature which locks the
device and prevents the inputs and I/O from driving if the
programming process is interrupted due to any reason. The
inputs and I/O default to high-Z state during such a condi-
tion. In addition the pin keeper option preserves the former
state during device programming.
All ATF1508AS devices are initially shipped in the erased
state thereby making them ready to use for ISP.
The registers in the ATF1508AS are designed to reset dur-
ing power up. At a point delayed slightly from VCC crossing
VRST, all registers will be reset to the low state. The output
state will depend on the polarity of the buffer.
Note:
For more information refer to the “Desigining for In-Sys-
tem Programmability with Atmel CPLDs” application
note.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
7
DC and AC Operating Conditions
Commercial
0°C - 70°C
5V ± 5%
Industrial
-40°C - 85°C
5V ± 10%
Operating Temperature (Case)
V
CCINT or VCCIO (5V) Power Supply
CCIO (3.3V) Power Supply
V
2.7V - 3.6V
2.7V - 3.6V
DC Characteristics
Symbol Parameter
Condition
Min Typ
Max
Units
µA
Input or I/O Low
IIL
VIN = VCC
-2
2
-10
Leakage Current
µA
Input or I/O High
IIH
10
40
Leakage Current
Tri-State Output
IOZ
VO = VCC or GND
-40
µA
Off-State Current
Com.
Ind.
160
180
mA
mA
µA
Std Mode
Power Supply
ICC1
VCC = Max
VIN = 0, VCC
Current, Stand-by
Com.
Ind.
100
140
“Z” Mode
µA
Power Supply Current,
ICC2
VCC = Max
VIN = 0, VCC
“PD” Mode
100
µA
Power Down Mode
Output Short
IOS
VOUT = 0.5V
-150
mA
Circuit Current
Com. 4.75
5.25
5.5
V
V
V
V
V
V
V
VCCIO
Supply Voltage
5.0V Device Output
3.3V Device Output
Ind.
4.5
2.7
-0.3
2.0
VCCIO
VIL
Supply Voltage
3.6
Input Low Voltage
Input High Voltage
0.8
VIH
VCCINT + 0.3
Com.
Ind.
0.45
0.45
VIN = VIH or VIL
VOL
Output Low Voltage
VCCIO = MIN, IOL = 12 mA
V
IN = VIH or VIL
VOH
Note:
Output High Voltage
2.4
V
VCCIO = MIN, IOH = -4.0 mA
Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
Pin Capacitance
Typ
8
Max
10
Units
pF
Conditions
CIN
VIN = 0V; f = 1.0 MHz
VOUT = 0V; f = 1.0 MHz
CI/O
8
10
pF
Note:
Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
The OGI pin ( high -voltage pin during programming) has a maximum capacitance of 12pf.
ATF1508AS/Z
8
ATF1508AS/Z
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias.................................. -40°C to +85°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Note:
1. Minimum voltage is -0.6V dc, which may under-
shoot to -2.0V for pulses of less than 20 ns. Max-
imum output pin voltage is VCC + 0.75V dc, which
may overshoot to 7.0V for pulses of less than 20
ns.
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
AC Characteristics
-7
-10
-15
-20
-25
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Units
Input or Feedback to
Non-Registered Output
tPD1
7.5
10
3
15
20
25
ns
I/O Input or Feedback to
Non-Registered Feedback
tPD2
7
9
3
12
16
20
ns
tSU
tH
Global Clock Setup Time
Global Clock Hold Time
7
0
7
0
11
0
16
0
20
0
ns
ns
Global Clock Setup Time of
Fast Input
tFSU
tFH
3
3
3
3
3
2
ns
Global Clock Hold Time of
Fast Input
0.5
0.5
1.0
1.5
MHz
tCOP
tCH
Global Clock to Output Delay
Global Clock High Time
Global Clock Low Time
Array Clock Setup Time
Array Clock Hold Time
Array Clock Output Delay
Array Clock High Time
Array Clock Low Time
4.5
7.5
5
8
10
20
13
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
3
4
4
3
3
5
5
4
4
6
6
4
5
7
7
5
6
tCL
tASU
tAH
3
2.5
tACOP
tACH
tACL
tCNT
10
15
3
3
4
4
6
6
8
8
10
10
Minimum Clock Global Period
8
8
10
10
13
13
17
17
22
22
Maximum Internal Global
Clock Frequency
fCNT
125
125
100
100
76.9
76.9
66
66
50
50
MHz
ns
tACNT
fACNT
Minimum Array Clock Period
Maximum Internal Array
Clock Frequency
MHz
(continued)
9
AC Characteristics
-7
-10
-15
-20
-25
Symbol
FMAX
tIN
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Units
MHz
ns
Maximum Clock Frequency
Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Fast Input Delay
166.7
125
100
41.7
33.3
0.5
0.5
1
0.5
0.5
1
2
2
2
8
1
6
6
3
2
2
2
2
tIO
ns
tFIN
2
2
ns
tSEXP
tPEXP
tLAD
Foldback Term Delay
Cascade Logic Delay
Logic Array Delay
4
5
10
1
12
1.2
8
ns
0.8
3
0.8
5
ns
7
ns
tLAC
Logic Control Delay
3
5
7
8
ns
tIOE
Internal Output Enable Delay
2
2
3
4
ns
Output Buffer and Pad Delay
(Slow slew rate = OFF;
VCCIO = 5V; CL = 35 pF)
tOD1
tOD2
tOD3
2
2.5
5
1.5
2.0
5.5
4
5
8
5
6
6
7
ns
ns
ns
Output Buffer and Pad Delay
(Slow slew rate = OFF;
VCCIO = 3.3V; CL = 35 pF)
Output Buffer and Pad Delay
(Slow slew rate = ON;
VCCIO = 5V or 3.3V; CL = 35 pF)
10
12
Note:
See ordering information for valid part numbers.
(continued)
Timing Model
U
ATF1508AS/Z
10
ATF1508AS/Z
AC Characteristics
-7
-10
-15
-20
-25
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Units
Output Buffer Enable Delay
(Slow slew rate = OFF;
VCCIO = 5.0V; CL = 35 pF)
tZX1
4.0
5.0
7
9
10
ns
Output Buffer Enable Delay
(Slow slew rate = OFF;
VCCIO = 3.3V; CL = 35 pF)
tZX2
4.5
5.5
7
9
10
ns
Output Buffer Enable Delay
(Slow slew rate = ON;
tZX3
9
4
9
5
10
6
11
7
12
8
ns
ns
VCCIO = 5.0V/3.3V; CL = 35 pF)
Output Buffer Disable Delay
(CL = 5 pF)
tXZ
tSU
Register Setup Time
Register Hold Time
3
2
2
3
4
4
2
2
5
5
2
2
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tH
tFSU
tFH
Register Setup Time of Fast Input
Register Hold Time of Fast Input
Register Delay
3
3
3
0.5
0.5
2.5
tRD
1
1
2
2
1
1
2
2
2
2
tCOMB
tIC
Combinatorial Delay
Array Clock Delay
3
5
6
7
8
tEN
Register Enable Time
Global Control Delay
Register Preset Time
Register Clear Time
Switch Matrix Delay
3
5
6
7
8
tGLOB
tPRE
tCLR
tUIM
tRPA
1
1
1
1
1
2
3
4
5
6
2
3
4
5
6
1
1
2
2
2
Reduced-Power Adder(2)
10
11
13
14
15
Notes: 1. See ordering information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC,tTIC, tACL, and tSEXP parameters for macrocells running in the reduced-
power mode.
Input Test Waveforms and
Measurement Levels
Output AC Test Loads:
(3.0V)*
(703 )*
(8060 )*
Note:
*Numbers in parenthesis refer to 3.0V operating condi-
tions (preliminary).
rR, tF = 1.5 ns typical
11
Power Down Mode
The ATF1508AS includes two pins for optional pin con-
trolled power down feature. When this mode is enabled, the
PD pin acts as the power down pin. When the PD1 and
PD2 pin is high, the device supply current is reduced to
less than 3 mA. During power down, all output data and
internal logic states are latched and held. Therefore, all
registered and combinatorial output data remain valid. Any
outputs which were in a Hi-Z state at the onset will remain
at Hi-Z. During power down, all input signals except the
power down pin are blocked. Input and I/O hold latches
remain active to insure that pins do not float to indetermi-
nate levels, further reducing system power. The power
down pin feature is enabled in the logic design file. Designs
using either power down pin may not use the PD pin logic
array input. However, all other PD pin as macrocell
resources may still be used, including the buried feedback
and foldback product term array inputs.
Power Down AC Characteristics(1)(2)
-7
-10
-15
-20
-25
Symbol Parameter
Min Max Min Max Min Max Min Max Min Max Units
tIVDH
tGVDH
tCVDH
tDHIX
tDHGX
tDHCX
tDLIV
Valid I, I/O Before PD High
7
7
7
10
10
10
15
15
15
20
20
20
25
25
25
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
Valid OE(2) Before PD High
Valid Clock(2) Before PD High
I, I/O Don’t Care After PD High
OE(2) Don’t Care After PD High
Clock(2) Don’t Care After PD High
PD Low to Valid I, I/O
12
12
12
1
15
15
15
1
25
25
25
1
30
30
30
1
35
35
35
1
tDLGV
tDLCV
tDLOV
PD Low to Valid OE (Pin or Term)
PD Low to Valid Clock (Pin or Term)
PD Low to Valid Output
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Notes: 1. For slow slew outputs, add tSSO
.
2. Pin or Product Term.
ATF1508AS/Z
12
ATF1508AS/Z
JTAG-BST Overview
The JTAG boundary-scan testing is controlled by the Test
Access Port (TAP) controller in the ATF1508AS. The
boundary-scan technique involves the inclusion of a shift-
register stage (contained in a boundary-scan cell) adjacent
to each component so that signals at component bound-
aries can be controlled and observed using scan testing
principles. Each input pin and I/O pin has its own boundary
scan cell (BSC) in order to support boundary scan testing.
The ATF1508AS does not currently include a Test Reset
(TRST) input pin because the TAP controller is automati-
cally reset at power up. The six JTAG BST modes sup-
ported include: SAMPLE/PRELOAD, EXTEST, BYPASS,
IDCODE. BST on the ATF1508AS is implemented using
the Boundary Scan Definition Language (BSDL) described
in the JTAG specification (IEEE Standard 1149.1). Any
third party tool that supports the BSDL format can be used
to perform BST on the ATF1508AS.
scan cell (BSC) in order to support boundary scan testing
as described in detail by IEEE Standard 1149.1. Typical
BSC consists of three capture registers or scan registers
and up to two update registers. There are two types of
BSCs, one for input or I/O pin, and one for the macrocells.
The BSCs in the device are chained together through the
capture registers. Input to the capture register chain is fed
in from the TDI pin while the output is directed to the TDO
pin. Capture registers are used to capture active device
data signals, to shift data in and out of the device and to
load data into the update registers. Control signals are gen-
erated internally by the JTAG TAP controller. The BSC
configuration for the input and I/O pins and macrocells are
shown below.
BSC Configuration Pins and
Macrocells (except JTAG TAP Pins)
The ATF1508AS also has the option of using four JTAG-
standard I/O pins for in-system programming (ISP). The
ATF1508AS is programmable through the four JTAG pins
using programming compatible with the IEEE JTAG Stan-
dard 1149.1. Programming is performed by using 5V TTL-
level programming signals from the JTAG ISP interface.
The JTAG feature is a programmable option. If JTAG (BST
or ISP) is not needed, then the four JTAG control pins are
available as I/O pins.
JTAG Boundary Scan Cell (BSC)
Testing
The ATF1508AS contains up to 96 I/O pins and 4 input
pins, depending on the device type and package type
selected. Each input pin and I/O pin has its own boundary
Note:
The ATF1508AS has pull-up option on TMS and TDI
pins. This feature is selected as a design option.
13
BSC Configuration for Macrocell
Pin BSC
TDO
0
DQ
Pin
1
Capture
DR
Clock
TDI
Shift
TDO
OEJ
0
1
0
D Q
D Q
1
OUTJ
0
1
Pin
0
1
D Q
D Q
Capture
DR
Update
DR
Mode
TDI
Clock
Shift
Macrocell BSC
ATF1508AS/Z
14
ATF1508AS/Z
PCI Compliance
The ATF1508AS also supports the growing need in the
industry to support the new Peripheral Component Inter-
connect (PCI) interface standard in PCI-based designs and
specifications. The PCI interface calls for high current driv-
ers which are much larger than the traditional TTL drivers.
PCI Voltage-to-Current Curves for +5V
Signaling in Pull-Up Mode
PCI Voltage-to-Current Curves for +5V
Signaling in Pull-Down Mode
Pull Down
Pull Up
VCC
VCC
AC drive
point
Test Point
2.4
2.2
DC
drive point
DC
drive point
1.4
0.55
AC drive
point
Test Point
Current (mA)
95
3.6
380
Current (mA)
-44
-2
-178
PCI DC Characteristics
Symbol
VCC
VIH
Parameter
Conditions
Min
4.75
2.0
Max
5.25
Units
V
Supply Voltage
Input High Voltage
Input Low Voltage
VCC + 0.5
0.8
V
VIL
-0.5
V
IIH
Input High Leakage Current
Input Low Leakage Current
Output High Voltage
Output Low Voltage
Input Pin Capacitance
CLK Pin Capacitance
IDSEL Pin Capacitance
Pin Inductance
VIN = 2.7V
VIN = 0.5V
70
µA
µA
V
IIL
-70
VOH
VOL
IOUT = -2 mA
2.4
IOUT = 3 mA, 6 mA
0.55
10
12
8
V
CIN
pF
pF
pF
nH
CCLK
CIDSEL
LPIN
20
Note:
Leakage Current is without Pin-Keeper off.
= Preliminary
15
PCI AC Characteristics
Symbol
Parameter
Conditions
0 < VOUT ≤ 1.4
1.4 < VOUT < 2.4
3.1 < VOUT < VCC
VOUT = 3.1V
Min
-44
Max
Units
mA
mA
mA
µA
IOH(AC)
Switching
Current High
-44+(VOUT-1.4)/0.024
Equation A
-142
(Test High)
Switching
IOL(AC)
VOUT > 2.2V
95
mA
mA
mA
mA
mA
V/ns
V/ns
Current Low
2.2 > VOUT > 0
0.1 > VOUT > 0
VOUT = 0.71
VOUT/0.023
Equation B
206
(Test Point)
ICL
Low Clamp Current
Output Rise Slew Rate
Output Fall Slew Rate
-5 < VIN ≤ -1
-25+(VIN+1)/0.015
SLEWR
SLEWF
0.4V to 2.4V load
2.4V to 0.4V load
0.5
0.5
3.0
3.0
Notes: 1. Equation A: IOH = 11.9(VOUT - 5.25) * (VOUT + 2.45) for VCC > VOUT > 3.1V.
2. Equation B: IOL = 78.5 * VOUT * (4.4 - VOUT) for 0V < VOUT < 0.71V.
= Preliminary
ATF1508AS/Z
16
ATF1508AS/Z
ATF1508AS Dedicated Pinouts
84-Pin
Dedicated Pin
INPUT/OE2/GCLK2
INPUT/GCLR
J-Lead
100-Pin PQFP
100-Pin TQFP
160-Pin PQFP
2
92
91
90
89
87
3,43
6
90
89
88
87
85
1,41
4
142
141
140
139
137
63,159
9
1
INPUT/OE1
84
INPUT/GCLK1
I/O /GCLK3
83
81
I/O / PD (1, 2)
I/O / TDI(JTAG)
I/O / TMS(JTAG)
I/O / TCK(JTAG)
I/O / TDO(JTAG)
12,45
14
23
17
64
75
15
62
73
22
62
99
71
112
7,19,32,42,
47,59,72,82
13,28,40,45,
61,76,88,97
11,26,38,43,
59,74,86,95
17,42,60,66,95,
113,138,148
GND
VCCINT
VCCIO
3,43
41,93
39,91
61,143
13,26,38,
53,66,78
5,20,36,53,68,84
3,18,34,51,66,82
8,26,55,79,104,133
1,2,3,4,5,6,7,34,35,36,
37,38,39,40,44,45,46,
47,74,75,76,77,81,82,
83,84,85,86,87,114,
115,116,117,118,119,
120,124,125,126,127,
154,155,156,157
N/C
-
-
-
# of SIGNAL PINS
# USER I/O PINS
68
64
84
80
84
80
100
96
OE (1, 2)
Global OE Pins
Global Clear Pin
Global Clock Pins
Power down pins
GCLR
GCLK (1, 2, 3)
PD (1, 2)
TDI, TMS, TCK, TDO
GND
JTAG pins used for Boundary Scan Testing or In-System Programming
Ground Pins
VCCINT
VCC pins for the device (+5V - Internal)
VCCIO
VCC pins for output drivers (for I/O pins) (+5V or 3.3V - I/Os)
17
ATF1508AS I/O Pinouts
84-Pin
J-Lead
100-Pin
PQFP
100-Pin
TQFP
160-Pin
PQFP
84-Pin
J-Lead
100-Pin
PQFP
100-Pin
TQFP
160-Pin
PQFP
MC
1
PLB
A
MC
33
PLB
C
-
-
4
-
2
-
160
-
-
-
27
-
25
-
41
-
2
A
34
C
A/
PD1
3
12
3
1
159
35
C
31
26
24
33
4
5
A
A
A
A
A
A
A
A
A
A
A
A
-
11
10
-
-
2
-
100
99
-
158
153
152
-
36
37
38
39
40
41
42
43
44
45
46
47
C
C
C
C
C
C
C
C
C
C
C
C
-
30
29
-
-
-
32
31
30
-
25
24
-
23
22
-
6
1
7
-
8
9
-
100
99
-
98
97
-
151
150
-
28
-
23
22
-
21
20
-
29
28
-
9
10
11
12
13
14
15
-
-
8
-
98
-
96
-
149
147
146
145
-
27
-
21
-
19
-
27
25
24
23
-
6
5
-
96
95
-
94
93
-
25
24
-
19
18
-
17
16
-
C/
TMS
16
A
4
94
92
144
48
23
17
15
22
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
22
-
16
-
14
-
21
-
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
41
-
39
-
37
-
59
-
21
-
15
-
13
-
20
19
18
16
-
40
-
38
-
36
-
58
57
56
54
-
20
-
14
12
-
12
10
-
39
-
37
35
-
35
33
-
-
-
18
17
-
11
10
-
9
15
14
-
37
36
-
34
33
-
32
31
-
53
52
-
8
-
16
-
9
7
13
12
11
10
-
35
-
32
-
30
-
51
50
49
48
-
-
-
15
-
8
6
34
-
31
30
-
29
28
-
7
5
-
-
-
-
B/
TDI
32
14
6
4
9
64
D
33
29
27
43
ATF1508AS/Z
18
ATF1508AS/Z
ATF1508AS I/O Pinouts (Continued)
84-Pin
J-Lead
100-Pin
PQFP
100-Pin
TQFP
160-Pin
PQFP
84-Pin
J-Lead
100-Pin
PQFP
100-Pin
TQFP
160-Pin
PQFP
MC
65
PLB
E
MC
97
PLB
G
44
-
42
-
40
-
62
-
63
-
65
-
63
-
100
-
66
E
98
G
E/
PD2
67
45
43
41
63
99
G
64
66
64
101
68
69
70
71
72
73
74
75
76
77
78
79
E
E
E
E
E
E
E
E
E
E
E
E
-
46
-
-
-
64
65
67
-
100
101
102
103
104
105
106
107
108
109
110
111
G
G
G
G
G
G
G
G
G
G
G
G
-
65
-
-
-
102
103
105
-
44
46
-
42
44
-
67
69
-
65
67
-
-
-
48
49
-
47
48
-
45
46
-
68
69
-
67
68
-
70
71
-
68
69
-
106
107
-
50
-
49
-
47
-
70
71
72
73
-
69
-
72
-
70
-
108
109
110
111
-
51
-
50
51
-
48
49
-
70
-
73
74
-
71
72
-
-
-
G/
TDO
80
E
52
52
50
78
112
71
75
73
112
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
-
-
54
-
52
-
80
-
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
-
-
77
-
75
-
121
-
54
-
55
-
53
-
88
89
90
91
-
73
-
78
-
76
-
122
123
128
129
-
55
56
-
56
57
-
54
55
-
74
75
-
79
80
-
77
78
-
57
-
58
59
-
56
57
-
92
93
-
76
-
81
82
-
79
80
-
130
131
-
-
-
58
-
60
-
58
-
94
96
97
98
-
77
-
83
-
81
-
132
134
135
136
-
60
61
-
62
63
-
60
61
-
79
80
-
85
86
-
83
84
-
F/
TCK
H/
GCLK3
96
62
64
62
99
128
81
87
85
137
19
SUPPLY CURRENT vs. SUPPLY VOLTAGE (TA = 25C)
SUPPLY CURRENT vs. SUPPLY VOLTAGE (TA = 25C)
STANDARD POWER, MC POWER CONTROL BIT TO NORMAL
LOW POWER, MC POWER CONTROL BIT TO LOW POWER
200
175
150
125
100
1.5
1.25
1
0.75
0.5
4.5
4.75
5
5.25
5.5
4.5
4.75
5
5.25
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. SUPPLY VOLTAGE (TA = 25C)
STANDARD POWER, MC POWER CONTROL BIT TO LOW POWER
SUPPLY CURRENT vs. FREQUENCY
LOW POWER, MC POWER BIT TO NORMAL
(VCC = 5.0V, TA = 25C)
200
175
150
125
100
250
200
150
100
50
0
4.5
4.75
5
5.25
5.5
0
5
10
20
50
SUPPLY VOLTAGE (V)
FREQUENCY (MHz)
SUPPLY CURRENT vs. SUPPLY VOLTAGE (TA = 25C)
LOW POWER, MC POWER CONTROL BIT TO NORMAL
SUPPLY CURRENT vs. FREQUENCY
LOW POWER, MC POWER BIT TO LOW POWER
(VCC = 5.0V, TA = 25C)
1.5
1.25
1
200
150
100
50
0.75
0.5
0
4.5
4.75
5
5.25
5.5
0
5
10
20
50
SUPPLY VOLTAGE (V)
FREQUENCY (MHz)
ATF1508AS/Z
20
ATF1508AS/Z
Ordering Information
tPD
(ns)
tCO1
(ns)
fMAX
(MHz)
Ordering Code
Package
Operation Range
7.5
10
15
15
20
25
25
4.5
166.7
125
100
100
83.3
70
ATF1508AS-7 JC84
ATF1508AS-7 QC100
ATF1508AS-7 AC100
ATF1508AS-7 QC160
84J
Commercial
100Q1
100A
160Q
(0°C to 70°C)
5
ATF1508AS-10 JC84
ATF1508AS-10 QC100
ATF1508AS-10 AC100
ATF1508AS-10 QC160
84J
Commercial
100Q1
100A
160Q
(0°C to 70°C)
8
ATF1508AS-15 JC84
ATF1508AS-15 QC100
ATF1508AS-15 AC100
ATF1508AS-15 QC160
84J
Commercial
100Q1
100A
160Q
(0°C to 70°C)
8
ATF1508AS-15 JI84
ATF1508AS-15 QI100
ATF1508AS-15 AI100
ATF1508AS-15 QI160
84J
Industrial
100Q1
100A
160Q
(-40°C to +85°C)
12
15
15
ATF1508ASZ-20 JC84
ATF1508ASZ-20 QC100
ATF1508ASZ-20 AC100
ATF1508ASZ-20 QC160
84J
Commercial
100Q1
100A
160Q
(0°C to 70°C)
ATF1508ASZ-25 JC84
ATF1508ASZ-25 QC100
ATF1508ASZ-25 AC100
ATF1508ASZ-25 QC160
84J
Commercial
100Q1
100A
160Q
(0°C to 70°C)
70
ATF1508ASZ-25 JI84
ATF1508ASZ-25 QI100
ATF1508ASZ-25 AI100
ATF1508ASZ-25 QI160
84J
Industrial
100Q1
100A
160Q
(-40°C to +85°C)
Package Type
84J
84-Lead, Plastic J-Leaded Chip Carrier (PLCC)
100-Lead, Plastic Quad Pin Flat Package (PQFP)
100Q1
100A
160Q
100-Lead, Very Thin Plastic Gull Wing Quad Flat Package (TQFP)
160-Lead, Plastic Quad Pin Flat Package (PQFP)
21
ATF1508AS/Z
Packaging Information
84J, 84 Lead, Plastic J-Leaded Chip Carrier (PLCC)
100Q1
, 100 Lead, Plastic Gull Wing Quad Flat
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AF
Package (PQFP)
Dimensions in Millimeters and (Inches)
.687(17.44)
PIN 1 ID
.667(16.95)
.792(20.12)
.782(19.87)
0.026(.65) BSC
.016(0.41)
.009(0.22)
.923(23.45)
.904(22.95)
.556(14.12)
.546(13.87)
.134(3.40) MAX
7
0
.010(0.25)
.004(0.10)
.041(1.03)
.028(0.73)
.004(0.10) MIN
*Controlling dimension: Millimeters
100A, 100 Lead, Very Thin (1.0mm) Plastic Gull
Wing Quad Flat Package (TQFP)
160Q, 160 Lead, Plastic Gull Wing Quad Flat
Package (PQFP)
Dimensions in Millimeters and (Inches)*
Dimensions in Millimeters and (Inches)
16.25(0.640)
15.75(0.620)
1.238(31.45)
SQ
1.218(30.95)
PIN 1 ID
PIN 1 ID
0.17(0.007)
0.27(0.011)
.016(0.40)
.008(0.20)
.0256(0.65) BSC
0.56(0.022)
0.44(0.018)
1.106(28.10)
1.098(27.90)
14.10(0.555)
SQ
.157(3.97)
.127(3.22)
0.95(0.037)
13.90(0.547)
7
0
0.20(0.008)
0.10(0.004)
1.27(0.05)
.009(0.23)
.004(0.10)
0-7
.037(0.95)
.025(0.65)
0.05(0.002)
0.15(0.006)
.020(0.50)
.002(0.05)
0.45(0.018)
0.75(0.030)
*Controlling dimension: Millimeters
*Controlling dimension: Millimeters
22
相关型号：
ATF1508AS-10QI100
EE PLD, 10ns, 128-Cell, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
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EE PLD, 15ns, PQFP100, 14 X 14 MM, 1 MM THICKNESS, 0.50 MM PITCH, PLASTIC, TQFP-100
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