ATF16V8B-15SI [ATMEL]
High Performance Flash PLD; 高性能闪存PLD
| 型号： | ATF16V8B-15SI |
| 厂家： | 
ATMEL |
| 描述： | High Performance Flash PLD |
| 文件： | 总16页 (文件大小：658K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ATF16V8B
Features
Industry Standard Architecture
•
Emulates Many 20-Pin PALs®
Low Cost Easy-to-Use Software Tools
High Speed Electrically Erasable Programmable Logic Devices
•
7.5 ns Maximum Pin-to-Pin Delay
Several Power Saving Options
•
Device
I
, Stand-By
50 mA
I
, Active
CC
CC
ATF16V8B
ATF16V8BQ
ATF16V8BQL
55 mA
40 mA
20 mA
High
Performance
Flash PLD
35 mA
5 mA
CMOS and TTL Compatible Inputs and Outputs
Input and I/O Pull-Up Resistors
Advanced Flash Technology
Reprogrammable
•
•
100% Tested
High Reliability CMOS Process
20 Year Data Retention
•
100 Erase/Write Cycles
2,000V ESD Protection
200 mA Latchup Immunity
Commercial, and Industrial Temperature Ranges
Dual-in-Line and Surface Mount Packages in Standard Pinouts
•
•
ATF16V8B
Block Diagram
Description
The ATF16V8B is a high performance CMOS (Electrically Erasable) Programmable
Logic Device (PLD) which utilizes Atmel’s proven electrically erasable Flash memory
technology. Speeds down to 7.5 ns are offered. All speed ranges are specified over
the full 5V ± 10% range for industrial temperature ranges, and 5V ± 5% for commercial
temperature ranges.
(continued)
DIP/SOIC
PLCC
Pin Configurations
Pin Name Function
CLK
I
Clock
Logic Inputs
Bidirectional Buffers
Output Enable
+5V Supply
I/O
OE
VCC
Top view
0364C
1-7
The ATF16V8Bs incorporate a superset of the generic ar-
chitectures, which allows direct replacement of the 16R8
family and most 20-pin combinatorial PLDs. Eight outputs
are each allocated eight product terms. Three different
modes of operation, configured automatically with soft-
ware, allow highly complex logic functions to be realized.
Description (Continued)
Several low power options allow selection of the best so-
lution for various types of power-limited applications. Each
of these options significantly reduces total system power
and enhances system reliability.
Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Temperature Under Bias................. -55°C to +125°C
Storage Temperature...................... -65°C to +150°C
Voltage on Any Pin with
(1)
Respect to Ground.........................-2.0V to +7.0V
Voltage on Input Pins
with Respect to Ground
During Programming.................... -2.0V to +14.0V
Note:
(1)
1. Minimum voltage is -0.6V dc, which may undershoot to -2.0V
for pulses of less than 20 ns. Maximum output pin voltage is
VCC + 0.75V dc, which may overshoot to 7.0V for pulses of
less than 20 ns.
Programming Voltage with
Respect to Ground.......................-2.0V to +14.0V
(1)
DC and AC Operating Conditions
Commercial
0°C - 70°C
5V ± 5%
Industrial
-40°C - 85°C
5V ± 10%
Operating Temperature (Case)
V
Power Supply
CC
1-8
ATF16V8B
ATF16V8B
DC Characteristics
Symbol Parameter
Condition
0 ≤ V
V (MAX)
IL
Min Typ
Max
Units
Input or I/O Low
≤
IN
I
IL
-35
-100
µA
Leakage Current
Input or I/O High
Leakage Current
I
3.5 ≤ V ≤ V
CC
10
µA
IH
IN
Com.
Ind.
55
55
50
50
35
5
85
95
75
80
55
10
15
mA
mA
B-7, -10
Com.
Ind.
mA
V
V
= MAX,
= MAX,
CC
Power Supply Current,
Standby
B-15, -25
BQ-10
I
CC
IN
mA
Outputs Open
Com.
Com.
Ind.
mA
mA
BQL-15, -25
5
mA
(2)
(2)
Com.
Ind.
1
mA/MHz
mA/MHz
mA
Clocked Power Supply V = MAX,
CC
I
I
BQL-15, -25
B-7, -10
CC2
Current
Outputs Open
1
Com.
Ind.
60
60
55
55
40
20
20
90
100
85
mA
V
= MAX,
CC
Clocked Power Supply
Current
Outputs Open,
f = 15 MHz
Com.
Ind.
mA
B-15, -25
BQ-10
CC3
95
mA
Com.
Com.
Ind.
55
mA
35
mA
BQL-15, -25
40
mA
Output Short Circuit
Current
(1)
OS
I
V
= 0.5V
-130
0.8
mA
OUT
V
V
Input Low Voltage
Input High Voltage
-0.5
2.0
V
V
IL
V
+ 0.75
IH
CC
V
V
= V or V ,
I
= -24 mA
IN
IH
IL
OL
V
V
Output High Voltage
Output High Voltage
0.5
V
V
OL
= MIN
Com., Ind.
CC
V
V
= V or V ,
IN
IH
IL
I
= -4.0 mA
2.4
OH
OH
= MIN
CC
Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
2. Low frequency only. See Supply Current versus Input Frequency curves.
1-9
AC Waveforms (1)
Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics (1)
-7 (2)
Min Max
-10
Max
-15
Max
-25
Symbol Parameter
Min
Min
Min
Max
Units
8 outputs
switching
3
7.5
7
3
10
3
15
3
25
ns
Input or Feedback to
Non-Registered Output
t
PD
1 output
switching
ns
t
t
t
t
t
t
Clock to Feedback
Clock to Output
Input or Feedback Setup Time
Hold Time
3
5
6
7
8
10
12
ns
ns
ns
ns
ns
ns
CF
CO
S
2
5
0
8
4
2
7.5
0
2
12
0
10
2
15
0
H
Clock Period
12
6
16
8
24
12
P
Clock Width
W
External Feedback 1/(t +t
)
100
125
125
68
74
83
45
50
62
37 MHz
40 MHz
41 MHz
S
CO
F
MAX
Internal Feedback 1/(t + t
)
S
CF
No Feedback 1/(t )
P
Input to Output Enable —
Product Term
t
t
3
2
9
9
3
2
10
10
3
2
15
15
3
2
20
20
ns
ns
EA
Input to Output Disable —
Product Term
ER
t
t
OE pin to Output Enable
OE pin to Output Disable
2
6
6
2
10
10
2
15
15
2
20
20
ns
ns
PZX
1.5
1.5
1.5
1.5
PXZ
Notes: 1. See ordering information for valid part numbers and speed grades.
2. Recommend ATF16V8C-7.
1-10
ATF16V8B
ATF16V8B
Input Test Waveforms and
Measurement Levels:
Output Test Loads:
Commercial
t , t < 5 ns (10% to 90%)
R
F
Pin Capacitance (f = 1 MHz, T = 25°C) (1)
Typ
Max
8
Units
pF
Conditions
C
C
5
6
V
V
= 0V
IN
IN
8
pF
= 0V
OUT
OUT
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power Up Reset
The registers in the ATF16V8Bs are designed to reset dur-
ing power up. At a point delayed slightly from V cross-
CC
ing V
, all registers will be reset to the low state. As a
RST
result, the registered output state will always be high on
power-up.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the un-
certainty of how V actually rises in the system, the fol-
CC
lowing conditions are required:
1) The V rise must be monotonic,
CC
Parameter Description
Typ
Max
Units
2) After reset occurs, all input and feedback setup times
must be met before driving the clock pin high, and
Power-Up
Reset Time
t
600
1,000
4.5
ns
PR
3) The clock must remain stable during t
.
PR
Power-Up
Reset
V
RST
3.8
V
Voltage
Preload of Registered Outputs
The ATF16V8B’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC
file preload sequence will be done automatically by most
of the approved programmers after the programming.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF16V8B fuse patterns. Once programmed, fuse
verify and preload are inhibited. However, the 64-bit User
Signature remains accessible.
The security fuse should be programmed last, as its effect
is immediate.
1-11
Electronic Signature Word
Input and I/O Pull-Ups
There are 64 bits of programmable memory that are al-
ways available to the user, even if the device is secured.
These bits can be used for user-specific data.
All ATF16V8B family members have internal input and I/O
pull-up resistors. Therefore, whenever inputs or I/Os are
not being driven externally, they will float to V . This en-
CC
sures that all logic array inputs are at known states.
These are relatively weak active pull-ups that can easily
be overdriven by TTL-compatible drivers (see input and
I/O diagrams below).
Programming/Erasing
Programming/erasing is performed using standard PLD
programmers. See CMOS PLD Programming Hardware &
Software Support for information on software/program-
ming.
Input Diagram
I/O Diagram
Functional Logic Diagram Description
The Logic Option and Functional Diagrams describe the
ATF16V8B architecture. Eight configurable macrocells
can be configured as a registered output, combinatorial
I/O, combinatorial output, or dedicated input.
architectural subsets can be found in each of the configu-
ration modes described in the following pages. The user
can download the listed subset device JEDEC program-
ming file to the PLD programmer, and the ATF16V8B can
be configured to act like the chosen device. Check with
your programmer manufacturer for this capability.
The ATF16V8B can be configured in one of three different
modes. Each mode makes the ATF16V8B look like a dif-
ferent device. Most PLD compilers can choose the right
mode automatically. The user can also force the selection
by supplying the compiler with a mode selection. The de-
termining factors would be the usage of register versus
combinatorial outputs and dedicated outputs versus out-
puts with output enable control.
Unused product terms are automatically disabled by the
compiler to decrease power consumption. A Security
Fuse, when programmed, protects the content of the
ATF16V8B. Eight bytes (64 fuses) of User Signature are
accessible to the user for purposes such as storing project
name, part number, revision, or date. The User Signature
is accessible regardless of the state of the Security Fuse.
The ATF16V8B universal architecture can be pro-
grammed to emulate many 20-pin PAL devices. These
Compiler Mode Selection
Registered
P16V8R
Complex
Simple
Auto Select
P16V8
P16V8C
P16V8AS
G16V8AS
GAL16V8_C8
“Simple”
ABEL, Atmel-ABEL
CUPL
G16V8MS
GAL16V8_R
“Registered”
P16V8R
G16V8MA
GAL16V8_C7
“Complex”
P16V8C
G16V8A
GAL16V8
GAL16V8A
P16V8A
(1)
(1)
(1)
LOG/iC
OrCAD-PLD
PLDesigner
Tango-PLD
P16V8C
G16V8R
G16V8C
G16V8AS
G16V8
Note: 1. Only applicable for version 3.4 or lower.
1-12
ATF16V8B
ATF16V8B
Macrocell Configuration
Software compilers support the three different OMC
modes as different device types. Most compilers have the
ability to automatically select the device type, generally
based on the register usage and output enable (OE) us-
age. Register usage on the device forces the software to
choose the registered mode. All combinatorial outputs
with OE controlled by the product term will force the soft-
ware to choose the complex mode. The software will
choose the simple mode only when all outputs are dedi-
cated combinatorial without OE control. The different de-
vice types can be used to override the automatic device
selection by the software. For further details, refer to the
compiler software manuals.
In registered mode pin 1 and pin 11 are permanently con-
figured as clock and output enable, respectively. These
pins cannot be configured as dedicated inputs in the reg-
istered mode.
In complex mode pin 1 and pin 11 become dedicated in-
puts and use the feedback paths of pin 19 and pin 12 re-
spectively. Because of this feedback path usage, pin 19
and pin 12 do not have the feedback option in this mode.
In simple mode all feedback paths of the output pins are
routed via the adjacent pins. In doing so, the two inner
most pins (pins 15 and 16) will not have the feedback op-
tion as these pins are always configured as dedicated
combinatorial output.
When using compiler software to configure the device, the
user must pay special attention to the following restrictions
in each mode.
ATF16V8B Registered Mode
PAL Device Emulation / PAL Replacement
sum term. When the macrocell is configured as an input,
the output enable is permanently disabled.
The registered mode is used if one or more registers are
required. Each macrocell can be configured as either a
registered or combinatorial output or I/O, or as an input.
For a registered output or I/O, the output is enabled by the
OE pin, and the register is clocked by the CLK pin. Eight
product terms are allocated to the sum term. For a combi-
natorial output or I/O, the output enable is controlled by a
product term, and seven product terms are allocated to the
Any register usage will make the compiler select this
mode. The following registered devices can be emulated
using this mode:
16R8 16RP8
16R6 16RP6
16R4 16RP4
Combinatorial Configuration for
Registered Mode (1, 2)
Registered Configuration
for Registered Mode(1, 2)
Notes:
Notes:
1. Pin 1 and Pin 11 are permanently configured as CLK and
OE.
2. The development software configures all the architecture
control bits and checks for proper pin usage automatically.
1. Pin 1 controls common CLK for the registered outputs.
Pin 11 controls common OE for the registered outputs.
Pin 1 and Pin 11 are permanently configured as CLK and OE.
2. The development software configures all the architecture
control bits and checks for proper pin usage automatically.
1-13
Registered Mode Logic Diagram
1-14
ATF16V8B
ATF16V8B
ATF16V8B Complex Mode
PAL Device Emulation/PAL Replacement
Combinatorial applications with an OE requirement will
make the compiler select this mode. The following devices
can be emulated using this mode:
In the Complex Mode, combinatorial output and I/O func-
tions are possible. Pins 1 and 11 are regular inputs to the
array. Pins 13 through 18 have pin feedback paths back to
the AND-array, which makes full I/O capability possible.
Pins 12 and 19 (outermost macrocells) are outputs only.
They do not have input capability. In this mode, each
macrocell has seven product terms going to the sum term
and one product term enabling the output.
16L8
16H8
16P8
Complex Mode Option
ATF16V8B Simple Mode
PAL Device Emulation / PAL Replacement
The compiler selects this mode when all outputs are com-
binatorial without OE control. The following simple PALs
can be emulated using this mode:
In the Simple Mode, 8 product terms are allocated to the
sum term. Pins 15 and 16 (center macrocells) are perma-
nently configured as combinatorial outputs. Other macro-
cells can be either inputs or combinatorial outputs with pin
feedback to the AND-array. Pins 1 and 11 are regular in-
puts.
10L8
12L6
14L4
16L2
10H8
12H6
14H4
16H2
10P8
12P6
14P4
16P2
Simple Mode Option
1-15
Complex Mode Logic Diagram
1-16
ATF16V8B
ATF16V8B
Simple Mode Logic Diagram
1-17
1-18
ATF16V8B
ATF16V8B
Note: 1. All normalized values referenced to maximum specification in AC Characteristics in the data sheet.
1-19
1-20
ATF16V8B
ATF16V8B
Ordering Information
t
t
t
CO
(ns)
PD
S
Ordering Code
Package
Operation Range
(ns)
(ns)
(1)
(1)
(1)
7.5
5
5
ATF16V8B-7JC
ATF16V8B-7PC
ATF16V8B-7SC
20J
20P3
20S
Commercial
(0°C to 70°C)
10
15
25
7.5
12
15
7
ATF16V8B-10JC
ATF16V8B-10PC
ATF16V8B-10SC
20J
20P3
20S
Commercial
(0°C to 70°C)
ATF16V8B-10JI
ATF16V8B-10PI
ATF16V8B-10SI
20J
20P3
20S
Industrial
(-40°C to 85°C)
10
12
ATF16V8B-15JC
ATF16V8B-15PC
ATF16V8B-15SC
20J
20P3
20S
Commercial
(0°C to 70°C)
ATF16V8B-15JI
ATF16V8B-15PI
ATF16V8B-15SI
20J
20P3
20S
Industrial
(-40°C to 85°C)
ATF16V8B-25JC
ATF16V8B-25PC
ATF16V8B-25SC
20J
20P3
20S
Commercial
(0°C to 70°C)
ATF16V8B-25JI
ATF16V8B-25PI
ATF16V8B-25SI
20J
20P3
20S
Industrial
(-40°C to 85°C)
Note: 1. Recommend ATF16V8C-7.
1-21
Ordering Information
t
t
t
CO
(ns)
PD
S
Ordering Code
Package
Operation Range
(ns)
(ns)
10
7.5
7
ATF16V8BQ-10JC
ATF16V8BQ-10PC
ATF16V8BQ-10SC
20J
20P3
20S
Commercial
(0°C to 70°C)
15
25
12
15
10
12
ATF16V8BQL-15JC
ATF16V8BQL-15PC
ATF16V8BQL-15SC
20J
20P3
20S
Commercial
(0°C to 70°C)
ATF16V8BQL-25JC
ATF16V8BQL-25PC
ATF16V8BQL-25SC
20J
20P3
20S
Commercial
(0°C to 70°C)
ATF16V8BQL-25JI
ATF16V8BQL-25PI
ATF16V8BQL-25SI
20J
20P3
20S
Industrial
(-40°C to 85°C)
Package Type
20J
20 Lead, Plastic J-Leaded Chip Carrier (PLCC)
20P3
20S
20 Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
20 Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
1-22
ATF16V8B
相关型号：
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