ATF22LV10C-10SJ [ATMEL]
Flash PLD, 10ns, CMOS, PDSO24, 0.300 INCH, PLASTIC, SOIC-24;
| 型号： | ATF22LV10C-10SJ |
| 厂家： | 
ATMEL |
| 描述： | Flash PLD, 10ns, CMOS, PDSO24, 0.300 INCH, PLASTIC, SOIC-24 光电二极管 |
| 文件： | 总19页 (文件大小：1813K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• 3.0V to 5.5V Operating Range
• Advanced Low-voltage Electrically-erasable Programmable Logic Device
• User-controlled Power-down Pin Option
• Pin-controlled Standby Power (10µA Typical)
• Well-suited for Battery Powered Systems
• 10ns Maximum Propagation Delay
• CMOS and TTL Compatible Inputs and Outputs
• Latch Feature Hold Inputs to Previous Logic States
• Advanced Electrically-erasable Technology
– Reprogrammable
High-performance
Electrically
Erasable
– 100% Tested
• High-reliability CMOS Process
– 20 year Data Retention
Programmable
Logic Device
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200mA Latchup Immunity
• Industrial Temperature Ranges
• Dual-in-line and Surface Mount Packages in Standard Pinouts
• Inputs are 5V Tolerant
• Green Package Options (Pb/Halide-free/RoHS Compliant) Available
• Applcations include Glue logic for 3.3V systems, DMA Control, State Machine Control,
Graphics processing
Atmel ATF22LV10C
See separate datasheet for Atmel
ATF22LV10C(Q)Z option
1.
Description
The Atmel® ATF22LV10C is a high-performance CMOS (electrically erasable) pro-
grammable logic device (PLD) that utilizes the Atmel proven electrically erasable
Flash memory technology. Speeds down to 10ns and power dissipation as low as
10mA are offered. All speed ranges are specified over the 3.0V to 5.5V range for
industrial and commercial temperature ranges.
The ATF22LV10C provides a low-voltage and user controlled “zero” power CMOS
PLD solution. A user-controlled power-down feature offers “zero” (10µA typical)
standby power. This feature allows the user to manage total system power to meet
specific application requirements and enhance reliability, all without sacrificing speed.
(The Atmel ATF22LV10CQZ provides edge-sensing “zero” standby power (3µA typi-
cal), as well as low voltage operation. See the ATF22LV10CQZ datasheet.)
The ATF22LV10C is capable of operating at supply voltages down to 3.0V. When the
power-down pin is active, the device is placed into a zero standby power-down mode.
When the power-down pin is not used or active, the device operates in a full power
low voltage mode. Pin “keeper” circuits on input and output pins hold pins to their pre-
vious logic levels when idle, which eliminate static power consumed by pull-up
resistors.
The ATF22LV10C macrocell incorporates a variable product term architecture. Each
output is allocated from 8 to 16 product terms which allows highly-complex logic func-
tions to be realized. Two additional product terms are included to provide synchronous
reset and asynchronous reset. These additional product terms are common to all ten
registers and are automatically cleared upon power-up. Register preload simplifies
testing. A security fuse prevents unauthorized copying of programmed fuse patterns.
0780M–PLD–7/10
Figure 1-1. Block Diagram
Figure 1-2. Pin Configurations
Pin Configurations (All Pinouts Top View)
Pin Name
CLK
IN
Function
Clock
Logic Inputs
I/O
Bi-directional Buffers
(3V to 5.5V) Supply
Programmable Power-down
VCC
PD
Figure 1-3. TSSOP
Figure 1-4. DIP/SOIC
CLK/IN
IN
1
2
3
4
5
6
7
8
9
24 VCC
23 I/O
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 IN
CLK/IN
IN
1
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
2
IN
IN
3
IN/PD
IN
IN/PD
IN
4
5
IN
IN
6
IN
IN
7
IN
IN
8
IN
IN
9
IN
10
11
12
IN 10
IN 11
IN
GND
GND 12
Figure 1-5. PLCC
IN/PD
IN
5
6
7
8
9
25 I/O
24 I/O
23 I/O
IN
GND*
IN
22 GND*
21 I/O
20 I/O
19 I/O
IN 10
IN 11
Note:
For PLCC, pins 1, 8, 15, and 22 can be left unconnected. For superior performance, connect
VCC to pin 1 and GND to 8, 15, and 22
2
Atmel ATF22LV10C
0780M–PLD–7/10
Atmel ATF22LV10C
2.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Temperature Under Bias .................. -40°C to +85°C
Storage Temperature...................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground...........................-2.0V to +7.0V(1)
Voltage on Input Pins
Note:
1. Minimum voltage is -0.6V DC, which may undershoot to -
2.0V for pulses of less than 20ns. Maximum output pin volt-
age is VCC + 0.75V DC, which may overshoot to 7.0V for
pulses of less than 20ns.
with Respect to Ground
During Programming......................-2.0V to +14.0V(1)
Programming Voltage with
Respect to Ground.........................-2.0V to +14.0V(1)
3.
DC and AC Operating Conditions
Commercial
Industrial
-40°C - 85°C
3.0V - 5.5V
Operating Temperature (Ambient)
VCC Power Supply
0°C - 70°C
3.0V - 5.5V
3.1
DC Characteristics
Symbol
Parameter
Condition(2)
Min
Typ
Max
Units
µA
IIL
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
0 VIN VIL(Max)
-10
10
IIH
(VCC - 0.2)V VIN VCC
µA
VCC = Max, VIN = Max
Outputs Open
Com.
Ind.
55
60
85
90
mA
mA
ICC
ICC2
IPD
Power Supply Current
VCC = Max
Com.
Ind.
mA
mA
100
105
Clocked Power Supply Current
Outputs Open, f = 15MHz
Power Supply Current,
Power-down Mode
VCC = 3.6V, Max
Com.
Ind.
µA
µA
10
10
100
120
VIN = 0, Outputs Open
(1)
IOS
VIL
VIH
Output Short Circuit Current
Input Low Voltage
VOUT = 0.5V
-130
0.8
mA
V
-0.5
2.0
Input High Voltage
VCC + 0.75
V
VIN = VIH or VIL
VCC = Min
VOL
Output Low Voltage
0.5
V
I
OL = 16mA
VIN = VIH or VIL
VCC = Min
VOH
VOH
Output High Voltage
Output High Voltage
2.4
V
V
I
OH = -2.0mA
IOH = -100µA
VCC - 0.2V
Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec
2. For DC characteristics, the test condition of VCC = Max corresponds to 3.6V
3
0780M–PLD–7/10
3.2
AC Waveforms
3.3
AC Characteristics(1)
-10
-15
Symbol
Parameter
Min
Max
10
Min
Max
15
8
Units
ns
tPD
tCF
tCO
tS
Input or Feedback to Non-Registered Output
Clock to Feedback
Clock to Output
3
3
5
ns
2
7.5
0
6.5
2
12
0
10
ns
Input or Feedback Setup Time
Input Hold Time
ns
tH
ns
tP
Clock Period
12
6
16
8
ns
tW
Clock Width
ns
External Feedback 1/(tS+ tCO
)
71.4
80
45.5
50
MHz
MHz
MHz
ns
fMAX
Internal Feedback 1/(tS + tCF
No Feedback 1/(tP)
)
83.3
12
62.5
15
tEA
tER
Input to Output Enable
Input to Output Disable
3
2
3
2
12
15
ns
tAP
Input or I/O to Asynchronous Reset of Register
Setup Time, Synchronous Preset
3
13
3
15
ns
tSP
10
8
10
8
ns
tAW
tAR
Asychronous Reset Width
ns
Asychronous Reset Recovery Time
6
6
ns
tSPR
Note:
Synchronous Preset to Clock Recovery Time
1. See ordering information for valid part numbers
10
10
ns
4
Atmel ATF22LV10C
0780M–PLD–7/10
Atmel ATF22LV10C
3.4
Power-down AC Characteristics
-10
-15
Symbol
tIVDH
Parameter
Min
10
0
Max
Min
15
0
Max
Units
ns
Valid Input before PD High
Valid OE before PD High
Valid Clock before PD High
Input Don't Care after PD High
OE Don't Care after PD High
Clock Don't Care after PD High
PD Low to Valid Input
tGVDH
tCVDH
tDHIX
ns
0
0
ns
10
10
10
10
25
25
30
15
15
15
15
30
30
35
ns
tDHGX
tDHCX
tDLIV
ns
ns
ns
tDLGV
tDLCV
tDLOV
PD Low to Valid OE
ns
PD Low to Valid Clock
PD Low to Valid Output
ns
ns
3.5
Input Test Waveforms and Measurement Levels
tR, tF < 1.5ns
3.6
Output Test Loads
3.3V
R1 = 316
OUTPUT
PIN
CL = 35pF
R2 = 348
Note:
Similar competitors devices are specified with slightly different loads. These load differences may affect output signals’
delay and slew rate. Atmel® devices are tested with sufficient margins to meet compatible device
specification conditions.
Table 3-1.
Pin Capacitance (f = 1MHz, T = 25°C(1)
Typ
5
Max
8
Units
pF
Conditions
VIN = 0V
CIN
COUT
6
8
pF
VOUT = 0V
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested
5
0780M–PLD–7/10
3.7
Power-up Reset
The registers in the Atmel® ATF22LV10C are designed to reset during power-up. At a point delayed slightly from
V
CC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the
buffer.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the following conditions are required:
1. The VCC rise must be monotonic and start below 0.7V
2. The clock must remain stable during TPR
3. After TPR, all input and feedback setup times must be met before driving the clock pin high
3.8
Preload of Register Outputs
The ATF22LV10C registers are provided with circuitry to allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC
file preload sequence will be done automatically by most of the approved programmers after the programming.
4.
5.
Electronic Signature Word
There are 64-bits of programmable memory that are always available to the user, even if the device is secured.
These bits can be used for user-specific data.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF22LV10C fuse patterns. Once programmed,
fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible.
The security fuse should be programmed last, as its effect is immediate.
6.
7.
Programming/Erasing
Programming/erasing is performed using standard PLD programmers. See CMOS PLD Programming Hardware &
Software Support for information on software/programming.
Table 6-1.
Programming/Erasing
Parameter
TPR
Description
Typ
600
2.5
Max
1,000
3.0
Units
ns
Power-up Reset Time
Power-up Reset Voltage
VRST
V
Input and I/O Pin-keeper
All ATF22V10C family members have internal input and I/O pin-keeper circuits. Therefore, whenever inputs or
I/Os are not being driven externally, they will maintain their last driven state. This ensures that all logic array inputs
and device outputs are at known states. These are relatively weak active circuits that can be easily overridden by
TTL-compatible drivers (see Input and I/O diagrams on page 7).
6
Atmel ATF22LV10C
0780M–PLD–7/10
Atmel ATF22LV10C
8.
Power-down Mode
The Atmel® ATF22LV10C includes an optional pin controlled power-down feature. When this mode is enabled, the
PD pin acts as the power-down pin (Pin 4 on the DIP/SOIC packages and Pin 5 on the PLCC package). When the
PD pin is high, the device supply current is reduced to less than 100mA. During power-down, all output data and
internal logic states are latched and held. Therefore, all registered and combinatorial output data remain valid. Any
outputs which were in an undetermined state at the onset of power-down will remain at the same state. During
power-down, all input signals except the power-down pin are blocked. Input and I/O hold latches remain active to
insure that pins do not float to indeterminate levels, further reducing system power. The power-down pin feature is
enabled in the logic design file. Designs using the power-down pin may not use the PD pin logic array input.
However, all other PD pin macrocell resources may still be used, including the buried feedback and foldback
product term array inputs.
PD pin configuration is controlled by the design file, and appears as a separate fuse bit in the JEDEC file. When
the power-down feature is not specified in the design file, the IN/PD pin will be configured as a regular logic input.
Note:
Some programmers list the 22V10 JEDEC-compatible 22V10C (no PD used) separately from the non-22V10 JEDEC-
compatible 22V10CEX (with PD used).
Figure 8-1. Input Diagram
VCC
100K
INPUT
ESD
PROTECTION
CIRCUIT
Figure 8-2. I/O Diagram
V
CC
OE
DATA
I/O
V
CC
100K
INPUT
7
0780M–PLD–7/10
9.
Compiler Mode Selection
Table 9-1.
Compiler Mode Selection
PAL Mode
(5828 Fuses)
GAL Mode
(5892 Fuses)
Power-down Mode(1)
(5893 Fuses)
Atmel ATF22C10C (DIP)
Atmel ATF22V10C (PLCC)
Atmel ATF22C10C DIO (UES)
Atmel ATF22V10C PLCC (UES)
Atmel ATF22C10C DIP (PWD)
Atmel ATF22C10V PLCC (PWD)
Synario
P22V10
P22V10LCC
G22V10
G22V10LCC
G22V10CP
G22V10CPLCC
WINCUPL
Note:
1. These device types will create a JEDEC file which when programmed in an Atmel ATF22V10C device will enable
the power-down mode feature. All other devices have this feature disabled.
10. Functional Logic Diagram Description
The functional logic diagram describes the Atmel® ATF22LV10C architecture.
The ATF22LV10C has twelve inputs and ten I/O macrocells. Each macrocell can be configured into one of four
output configurations: active high/low, registered/combinatorial output.The universal architecture of the
ATF22LV10C can be programmed to emulate most 24-pin PAL devices.
Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse,
when programmed, protects the contents of the ATF22LV10C. Eight bytes (64-fuses) of User Signature are
accessible to the user for purposes such as storing project name, part number, revision or date. The User
Signature is accessible regardless of the state of the security fuse.
8
Atmel ATF22LV10C
0780M–PLD–7/10
Atmel ATF22LV10C
Figure 10-1. Functional Logic Diagram Atmel ATF22LV10C
Note:
1. *Input not available if the power-down (PD) option is utilized
9
0780M–PLD–7/10
ATMEL ATF22LV10C
SUPPLY CURRENTVS.SUPPLYVOLTAGE (TA =
ATMEL ATF22LV10C
NORMALIZED ICC VS.TEMP.
25°C)
1.10
1.00
0.90
0.80
70.00
60.00
50.00
40.00
30.00
20.00
10.00
0.00
3.00
3.30
3.60
50.00
3.60
-40.00
0.00
25.00
75.00
SUPPLY VOLTAGE (V)
TEMPERATURE (DEG. C)
ATMEL ATF22LV10C SUPPLY CURRENTVS.
INPUT FREQUENCY (VCC = 3.3V,TA = 25°C)
75.00
50.00
25.00
0.00
0.00
10.00
20.00
FREQUENCY (MHz)
ATMEL ATF22LV10C OUTPUT SOURCE
CURRENTVS.SUPPLYVOLTAGE (VOH = 2.4V)
ATMEL ATF22LV10C OUTPUT SOURCE CURRENT
VS. OUTPUTVOLTAGE (VCC = 3.3V, TA = 25°C)
0.00
-2.00
-4.00
-6.00
-8.00
-10.00
0.00
-2.00
-4.00
-6.00
-8.00
-10.00
-12.00
3.00
3.15
3.30
3.45
2.00
2.20
2.40
2.60
2.70
VOH (V)
2.80
3.00
3.20
3.30
SUPPLY VOLTAGE (V)
ATMEL ATF22LV10C
OUTPUT SINK CURRENTVS.SUPPLYVOLTAGE (VOL = 0.5V)
ATMEL ATF22LV10C OUTPUT SINK CURRENTVS.
OUTPUT VOLTAGE (VCC = 3.3V, TA = 25°C)
40.00
39.00
38.00
37.00
36.00
35.00
34.00
33.00
32.00
90.00
80.00
70.00
60.00
50.00
40.00
30.00
20.00
10.00
0.00
3.00
3.15
3.30
3.45
3.60
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.30
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE (V)
10
Atmel ATF22LV10C
0780M–PLD–7/10
Atmel ATF22LV10C
ATMEL ATF22LV10C INPUT CLAMP CURRENTVS.
INPUT VOLTAGE (VCC = 3.3V, TA = 25°C)
ATMEL ATF22LV10C INPUT CURRENTVS.
INPUTVOLTAGE (VCC = 3.3V, TA = 25°C)
20.00
0.00
15.00
10.00
5.00
-20.00
-40.00
-60.00
-80.00
-100.00
0.00
-5.00
0.00
-0.20
-0.40
-0.60
-0.80
-1.00
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
NORMALIZEDTPD VS.VCC
NORMALIZEDTPD VS.TEMP
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
3.00
3.15
3.30
3.45
3.60
-0.40
0.00
25.00
75.00
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
NORMALIZEDTCO VS.VCC
NORMALIZEDTCO VS.TEMP
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
3.00
3.15
3.30
3.45
3.60
-0.40
0.00
25.00
75.00
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
NORMALIZEDTSU VS.VCC
NORMALIZEDTSU VS.TEMP
1.10
1.05
1.00
0.95
0.90
0.85
0.80
1.10
1.05
1.00
0.95
0.90
0.85
0.80
3.00
3.15
3.30
3.45
3.60
-0.40
0.00
25.00
75.00
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
11
0780M–PLD–7/10
ATMEL ATF22LV10C
DELTA TPD VS. OUTPUT LOADING
ATMEL ATF22LV10C
DELTA TCO VS. OUTPUT LOADING
14.00
12.00
10.00
8.00
14.00
12.00
10.00
8.00
6.00
6.00
4.00
4.00
2.00
2.00
0.00
0.00
-2.00
-4.00
-2.00
-4.00
0.00
50.00
100.00
150.00
200.00
250.00
300.00
0.00
50.00
100.00
150.00
200.00
250.00
300.00
OUTPUT LOADING (PF)
OUTPUT LOADING (PF)
ATMEL ATF22LV10C DELTA TPD VS.
NUMBER OF OUTPUT SWITCHING
ATMEL ATF22LV10C DELTATCO VS.
NUMBER OF OUTPUT SWITCHING
0.00
-0.10
-0.20
-0.30
-0.40
-0.50
0.00
-0.10
-0.20
-0.30
-0.40
-0.50
1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00
1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00
NUMBER OF OUTPUTS SWITCHING
NUMBER OF OUTPUTS SWITCHING
12
Atmel ATF22LV10C
0780M–PLD–7/10
Atmel ATF22LV10C
11. Ordering Information
11.1 Ordering Code Detail
tPD
tS
tCO
(ns)
(ns)
(ns)
Ordering Code
Package
Operation Range
ATF22LV10C-10JC
ATF22LV10C-10PC
ATF22LV10C-10SC
ATF22LV10C-10XC
28J
24P3
24S
Commercial
10
10
7.5
7.5
12
7.5
7.5
10
(0C to 70C)
24X
ATF22LV10C-10JI
ATF22LV10C-10PI
ATF22LV10C-10SI
ATF22LV10C-10XI
28J
24P3
24S
Industrial
(0C to 85C)
24X
ATF22LV10C-15JC
ATF22LV10C-15PC
ATF22LV10C-15SC
ATF22LV10C-15XC
28J
24P3
24S
Commercial
(0C to 70C)
24X
15
ATF22LV10C-15JI
ATF22LV10C-15PI
ATF22LV10C-15SI
ATF22LV10C-15XI
28J
24P3
24S
Industrial
12
10
(-40C to +85C)
24X
Note:
Lead based packages will become obsolete, and are not recommended for new designs
11.2 Green Package Options (Pb/Halide-free/RoHS Compliant)
tPD
tS
tCO
(ns)
(ns)
(ns)
Ordering Code
Package
Operation Range
ATF22LV10C-10JU
ATF22LV10C-10PU
ATF22LV10C-10SU
ATF22LV10C-10XU
28J
24P3
24S
Industrial
10
7.5
7.5
(0C to +85C)
24X
11.3 Using “C” Product for Industrial
To use commercial product for industrial temperature ranges, simply de-rate ICC by 15% on the “C” device. No
speed de-rating is necessary.
Package Type
28J
28-lead, Plastic J-leaded Chip Carrier (PLCC)
24P3
24S
24X
24-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)
24-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
24-lead, 4.4mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
13
0780M–PLD–7/10
12. Package Information
12.1 28J – PLCC
1.14(0.045) X 45°
PIN NO. 1
1.14(0.045) X 45°
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
D2/E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45° MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
2.286
0.508
12.319
11.430
12.319
11.430
9.906
0.660
0.330
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
A1
A2
D
–
–
–
–
12.573
D1
E
–
11.582 Note 2
12.573
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AB.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
D2/E2
B
–
11.582 Note 2
10.922
–
–
–
0.813
3. Lead coplanarity is 0.004" (0.102mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
TITLE
Package Drawing Contact:
packagedrawings@atmel.com
28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC)
28J
B
14
Atmel ATF22LV10C
0780M–PLD–7/10
Atmel ATF22LV10C
12.2 24P3 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
C
MIN
–
MAX
5.334
–
NOM
NOTE
SYMBOL
eC
A
–
–
–
–
–
–
–
–
–
–
–
eB
A1
D
0.381
31.623
7.620
6.096
0.356
1.270
2.921
0.203
–
32.131 Note 2
8.255
E
E1
B
7.112 Note 2
0.559
Notes:
1. This package conforms to JEDEC reference MS-001, Variation AF.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25mm (0.010").
B1
L
1.651
3.810
C
0.356
eB
eC
e
10.922
0.000
1.524
2.540 TYP
6/1/04
DRAWING NO. REV.
24P3
TITLE
Package Drawing Contact:
packagedrawings@atmel.com
24P3, 24-lead (0.300"/7.62mm Wide) Plastic Dual
Inline Package (PDIP)
D
15
0780M–PLD–7/10
12.3 24S – SOIC
B
D1
D
PIN 1 ID
PIN 1
e
E
A
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
2.65
0.30
10.65
7.60
15.60
0.51
1.27
0.32
NOM
NOTE
SYMBOL
A
–
A1
A1
D
0.10
10.00
7.40
15.20
0.33
0.40
0.23
–
–
D1
E
–
0
8
–
L1
B
–
L
–
–
L
L1
e
1.27 BSC
06/17/2002
TITLE
DRAWING NO. REV.
Package Drawing Contact:
packagedrawings@atmel.com
24S, 24-lead (0.300" body) Plastic Gull Wing Small
Outline (SOIC)
24S
B
16
Atmel ATF22LV10C
0780M–PLD–7/10
Atmel ATF22LV10C
12.4 24X – TSSOP
Dimensions in Millimeter and (Inches)*
JEDEC STANDARD MO-153 AD
Controlling dimension: millimeters
0.30(0.012)
0.19(0.007)
4.48(0.176)
4.30(0.169)
6.50(0.256)
6.25(0.246)
PIN 1
0.65(0.0256)BSC
7.90(0.311)
7.70(0.303)
1.20(0.047)MAX
0.15(0.006)
0.05(0.002)
0.20(0.008)
0.09(0.004)
0
8
0.75(0.030)
0.45(0.018)
04/11/2001
TITLE
DRAWING NO. REV.
Package Drawing Contact:
packagedrawings@atmel.com
24X, 24-lead (4.4mm body width) Plastic Thin Shrink
24X
A
Small Outline Package (TSSOP)
17
0780M–PLD–7/10
13. Revision History
Doc. Rev.
Date
Comments
Update the standby current parameters for Powerdown mode from 100µA to 120µA.
0780M
07/2010
12/2005
Shade Ordering Package Option table and add note, “Lead based packages will become
obsolete and are not recommended for new designs.”
0780L
Add Green Package options
18
Atmel ATF22LV10C
0780M–PLD–7/10
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