ATF2500C-15JI [ATMEL]
ATF2500C CPLD Family Datasheet; ATF2500C CPLD系列数据表
| 型号： | ATF2500C-15JI |
| 厂家： | 
ATMEL |
| 描述： | ATF2500C CPLD Family Datasheet |
| 文件： | 总20页 (文件大小：343K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High-performance, High-density, Electrically-erasable Programmable Logic Device
• Fully Connected Logic Array with 416 Product Terms
• 15 ns Maximum Pin-to-pin Delay for 5V Operation
• 24 Flexible Output Macrocells
– 48 Flip-flops – Two per Macrocell
– 72 Sum Terms
– All Flip-flops, I/O Pins Feed in Independently
• D- or T-type Flip-flops
• Product Term or Direct Input Pin Clocking
• Registered or Combinatorial Internal Feedback
• Backward Compatible with ATV2500B/BQ and ATV2500H Software
• Advanced Electrically-erasable Technology
– Reprogrammable
ATF2500C
CPLD Family
Datasheet
– 100% Tested
• 44-lead Surface Mount Package and DIP Package
• Flexible Design: Up to 48 Buried Flip-flops and 24 Combinatorial Outputs
Simultaneously
• 8 Synchronous Product Terms
• Individual Asynchronous Reset per Macrocell
• OE Control per Macrocell
ATF2500C
• Functionality Equivalent to ATV2500B/BQ and ATV2500H
• 2000V ESD Protection
• Security Fuse Feature to Protect the Code
• Commercial and Industrial Temperature Range Offered
• 10 Year Data Retention
• Pin Keeper Option
• 200 mA Latch-up Immunity
Block Diagram
PLCC/LCC/JLCC
DIP
Pin Configurations
CLK/IN
IN
1
2
3
4
5
6
7
8
9
40 IN
39 IN
Pin Name
Function
IN
38 IN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
37 IN
IN
Logic Inputs
36 I/O6
35 I/O7
34 I/O8
33 I/O9
32 I/O10
31 I/O11
30 GND
29 I/O23
28 I/O22
27 I/O21
26 I/O20
25 I/O19
24 I/O18
23 IN
I/O2
I/O3
I/O4
7
8
9
39 I/O7
38 I/O8
37 I/O9
36 I/O10
35 I/O11
34 GND
33 GND
32 I/O23
31 I/O22
30 I/O21
29 I/O20
CLK/IN
I/O
Pin Clock and Input
Bi-directional Buffers
“Even” I/O Buffers
“Odd” I/O Buffers
Ground
I/O5 10
VCC 11
VCC 12
I/O17 13
I/O16 14
I/O15 15
I/O14 16
I/O13 17
VCC 10
I/O17 11
I/O16 12
I/O15 13
I/O14 14
I/O13 15
I/O12 16
IN 17
I/O 0,2,4...
I/O 1,3,5...
GND
IN 18
IN 19
22 IN
IN 20
21 IN
VCC
+5V Supply
Note:
(PLCC/LCC/JLCC packages) pin 4 and pin 26
GND connections are not required, but are rec-
ommended for improved noise immunity.
Rev. 0777I–PLD–4/03
Description
The ATF2500C is the highest-density PLD available in a 44-pin package. With its fully con-
nected logic array and flexible macrocell structure, high gate utilization is easily obtainable.
The ATF2500C is a high-performance CMOS (electrically-erasable) programmable logic
device (PLD) that utilizes Atmel’s proven electrically-erasable technology.
The ATF2500C is organized around a single universal array. All pins and feedback terms are
always available to every macrocell. Each of the 38 logic pins are array inputs, as are the out-
puts of each flip-flop.
In the ATF2500C, four product terms are input to each sum term. Furthermore, each macro-
cell’s three sum terms can be combined to provide up to 12 product terms per sum term with
no performance penalty. Each flip-flop is individually selectable to be either D- or T-type, pro-
viding further logic compaction. Also, 24 of the flip-flops may be bypassed to provide internal
combinatorial feedback to the logic array.
Product terms provide individual clocks and asynchronous resets for each flip-flop. The flip-
flops may also be individually configured to have direct input pin clocking. Each output has its
own enable product term. Eight synchronous preset product terms serve local groups of either
four or eight flip-flops. Register preload functions are provided to simplify testing. All registers
automatically reset upon power-up.
Using the
ATF2500C
Family’s Many
Advanced
Features
The ATF2500Cs advanced flexibility packs more usable gates into 44 leads than other PLDs.
Some of the ATF2500Cs key features are:
•
Fully Connected Logic Array – Each array input is always available to every product
term. This makes logic placement a breeze.
•
Selectable D- and T-Type Registers – Each ATF2500C flip-flop can be individually
configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are
also easily created. These options allow more efficient product term usage.
•
•
Buried Combinatorial Feedback – Each macrocell’s Q2 register may be bypassed to
feed its input (D/T2) directly back to the logic array. This provides further logic expansion
capability without using precious pin resources.
Selectable Synchronous/Asynchronous Clocking – Each of the ATF2500Cs flip-flops
has a dedicated clock product term. This removes the constraint that all registers use the
same clock. Buried state machines, counters and registers can all coexist in one device
while running on separate clocks. Individual flip-flop clock source selection further allows
mixing higher performance pin clocking and flexible product term clocking within one
design.
•
•
A Total of 48 Registers – The ATF2500C provides two flip-flops per macrocell – a total of
48. Each register has its own clock and reset terms, as well as its own sum term.
Independent I/O Pin and Feedback Paths – Each I/O pin on the ATF2500C has a
dedicated input path. Each of the 48 registers has its own feedback term into the array as
well. These features, combined with individual product terms for each I/O’s output enable,
facilitate true bi-directional I/O design.
•
•
•
Combinable Sum Terms – Each output macrocell’s three sum terms may be combined
into a single term. This provides a fan in of up to 12 product terms per sum term with no
speed penalty.
Programmable Pin-keeper Circuits – These weak feedback latches are useful for bus
interfacing applications. Floating pins can be set to a known state if the Pin-keepers are
enabled.
User Row (64 bits) – Use to store information such as unit history.
2
ATF2500C Family
0777I–PLD–4/03
ATF2500C Family
Power-up Reset
The registers in the ATF2500Cs are designed to reset during power-up. At a point delayed
slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will
depend on the polarity of the output buffer.
This feature is critical for state as nature of reset and the uncertainty of how VCC actually rises
in the system, the following conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup times must be met before driving the
clock pin or terms high, and
3. The clock pin, and any signals from which clock terms are derived, must remain stable
during tPR
.
Parameter
tPR
Description
Typ
600
3.8
Max
1000
4.5
Units
ns
Power-up Reset Time
VRST
Power-up Reset Voltage
V
Level Forced on
Odd I/O Pin during
PRELOAD Cycle
Q Select Pin
State
Even/Odd
Select
Even Q1 State
after Cycle
Even Q2 State
after Cycle
Odd Q1 State
after Cycle
Odd Q2 State
after Cycle
VIH/VIL
VIH/VIL
VIH/VIL
VIH/VIL
Low
High
Low
High
Low
High/Low
X
X
X
Low
X
X
X
High/Low
X
High/Low
X
X
X
High
High
X
X
High/Low
3
0777I–PLD–4/03
Preload and
Observability of
Registered
Outputs
The ATF2500Cs registers are provided with circuitry to allow loading of each register asyn-
chronously with either a high or a low. This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A VIH level on the odd I/O pins will force the
appropriate register high; a VIL will force it low, independent of the polarity or other configura-
tion bit settings.
The PRELOAD state is entered by placing an 10.25V to 10.75V signal on SMP lead 42. When
the preload clock SMP lead 23 is pulsed high, the data on the I/O pins is placed into the 12
registers chosen by the Q select and even/odd select pins.
Register 2 observability mode is entered by placing an 10.25V to 10.75V signal on pin/lead 2.
In this mode, the contents of the buried register bank will appear on the associated outputs
when the OE control signals are active.
Programming
Software
Support
All family members of the ATF2500C can be designed with Atmel-WinCUPL™. ProChip
Designer® support is expected soon. Check Atmel’s web site for the latest version of ProChip.
Additionally, the ATF2500C may be programmed to perform the ATV2500Hs functional subset
(no T-type flip-flops, pin clocking or D/T2 feedback) using the ATV2500H JEDEC file. In this
case, the ATF2500C becomes a direct replacement or speed upgrade for the ATV2500H. The
ATF2500C are direct replacements for the ATV2500B/BQ and the ATV2500H, including the
lack of extra grounds on P4 and P26.
Security Fuse
Usage
A single fuse is provided to prevent unauthorized copying of ATF2500C fuse patterns. Once
programmed, the outputs will read programmed during verify.
The security fuse should be programmed last, as its effect is immediate.
The security fuse also inhibits Preload and Q2 observability.
Bus-friendly
Pin-keeper
Input and I/O
All ATF2500C family members have programmable internal input and I/O pin-keeper circuits.
The default condition, including when using the AT2500C/CQ family to replace the
AT2500B/BQ or AT2500H, is that the pin-keepers are not activated.
When pin-keepers are active, inputs or I/Os not being driven externally will maintain their last
driven state. This ensures that all logic array inputs and device outputs are known states. Pin-
keepers are relatively weak active circuits that can be easily overridden by TTL-compatible
drivers (see input and I/O diagrams below).
Enabling or disabling of the pin-keeper circuits is controlled by the device type chosen in the
logic compiler device selection menu. Please refer to the Software Compiler Mode Selection
table for more details. Once the pin-keeper circuits are disabled, normal termination proce-
dures required for unused inputs and I/Os.
4
ATF2500C Family
0777I–PLD–4/03
ATF2500C Family
Software Compiler Mode Selection
Device
Atmel - WinCupL Device Mnemonic
Pin-keeper
V2500C
Disabled
Enabled
ATF2500C-DIP
V2500CPPK
V2500LCC
Disabled
Enabled
ATF2500C-PLCC
V2500CPPKLCC
THIRD PARTY PROGRAMMER SUPPORT
Major Third Party Device Programmers support three types of JEDEC files.
Device
Description
V2500 Cross-programming. JEDEC file compatible with standard V2500
JEDEC file (Total fuses in JEDEC file = 71648). The Programmer will
automatically disable the User row fuses and also disable the pin-keeper
feature. The Fuse checksum will be the same as the old ATV2500H/L file.
This Device type is recommended for customers that are directly migrating
from an ATV2500H/L device to an ATF2500C device.
ATF2500C (V2500)
V2500B Cross-programming. JEDEC file compatible with standard
V2500B JEDEC file (Total fuses in JEDEC file = 71745). The Programmer
will automatically disable the User row fuses and also disable the pin-
keeper feature. The Fuse checksum will be the same as the old
ATV2500B/BQ/BQL/BL file. This Device type is recommended for
customers that are directly migrating from an ATV2500B/BQ/BQL/BL
device to an ATF2500C device.
ATF2500C (V2500B)
Programming of User Row bits supported and Pin keeper bit is user-
programmable. (Total fuses in JEDEC file = 71816). This is the default
device type and is recommended for users that have Re-compiled their
Source Design files to specifically target the ATF2500C device.
ATF2500C
Note:
The ATF2500C has 71816 Jedec fuses.
Input Diagram
PROGRAMMABLE
OPTION
5
0777I–PLD–4/03
I/O Diagram
INPUT
PROGRAMMABLE
OPTION
Functional
Logic Diagram
Description
The ATF2500C functional logic diagram describes the interconnections between the input,
feedback pins and logic cells. All interconnections are routed through the single global bus.
The ATF2500Cs are straightforward and uniform PLDs. The 24 macrocells are numbered 0
through 23. Each macrocell contains 17 AND gates. All AND gates have 172 inputs. The five
lower product terms provide AR1, CK1, CK2, AR2, and OE. These are: one asynchronous
reset and clock per flip-flop, and an output enable. The top 12 product terms are grouped into
three sum terms, which are used as shown in the macrocell diagrams.
Eight synchronous preset terms are distributed in a 2/4 pattern. The first four macrocells share
Preset 0, the next two share Preset 1, and so on, ending with the last two macrocells sharing
Preset 7.
The 14 dedicated inputs and their complements use the numbered positions in the global bus
as shown. Each macrocell provides six inputs to the global bus: (left to right) feedback F2(1)
true and false, flip-flop Q1 true and false, and the pin true and false. The positions occupied by
these signals in the global bus are the six numbers in the bus diagram next to each macrocell.
Note:
1. Either the flip-flop input (D/T2) or output (Q2) may be fed back in the ATF2500Cs.
6
ATF2500C Family
0777I–PLD–4/03
ATF2500C Family
Functional Logic Diagram ATF2500C
Notes: 1. Pin 4 and Pin 26 are “ground” connections and are not required for PLCC, LCC and JLCC versions of ATF2500C, making
them compatible with ATV2500H, ATV2500B and ATV2500BQ pinouts.
2. For DIP package, VCC = P10 and GND = P30. For, PLCC, LCC and JLCC packages, VCC = P11 and P12, GND = P33 and
P34, and GND = P4, P26 (See Note 1, above).
7
0777I–PLD–4/03
Output Logic, Registered(1)
S2 = 0
Terms in
S1
0
S0
0
D/T1
D/T2
4
Output Configuration
Registered (Q1); Q2 FB
Registered (Q1); Q2 FB
Registered (Q1); D/T2 FB
8
12
8
1
0
4(1)
4
1
1
Output
S3
0
Configuration
S6
0
Q1 CLOCK
CK1
CK1 • PIN1
Active Low
1
Active High
1
Q2 CLOCK
S4
0
Register 1 Type
S7
0
D
T
CK2
1
1
CK2 • PIN1
S5
0
Register 2 Type
D
T
1
Output Logic, Combinatorial(1)
S2 = 1
S1
Terms in
S5
S0
D/T1
4(1)
D/T2
Output Configuration
Combinatorial (8 Terms);
Q2 FB
X
X
X
1
0
0
1
1
1
0
4
Combinatorial (4 Terms);
Q2 FB
1
0
1
1
4
4
4(1)
4
Combinatorial (12 Terms);
Q2 FB
4(1)
4(1)
4
Combinatorial (8 Terms);
D/T2 FB
Combinatorial (4 Terms);
D/T2 FB
0
4
Note:
1. These four terms are shared with D/T1.
Clock Option
Note:
1. These diagrams show equivalent logic functions, not
necessarily the actual circuit implementation.
8
ATF2500C Family
0777I–PLD–4/03
ATF2500C Family
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias.................................. -40°C to +85°C
Storage Temperature..................................... -65°C to +150°C
Junction Temperature ............................................. 150°C Max
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
Note:
1. Minimum voltage is -0.6V DC which may under-
shoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is VCC + 0.75V DC
which may overshoot to +7.0V for pulses of less
than 20 ns.
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
DC and AC Operating Conditions
Commercial
Industrial
0°C - 70°C
-40°C - 85°C
(Ambient)
Operating Temperature
(Ambient)
V
CC Power Supply
5V ± 5%
5V ± 10%
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
CIN
COUT
8
12
pF
VOUT = 0V
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Test Waveforms and Measurement Levels Output Test Load
9
0777I–PLD–4/03
AC Waveforms(1) Input Pin Clock
AC Waveforms(1) Product Term Clock
AC Waveforms(1) Combinatorial Outputs and Feedback
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
10
ATF2500C Family
0777I–PLD–4/03
ATF2500C
ATF2500C DC Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
IIL
Input Load Current
VIN = -0.1V to VCC + 1V
10
µA
Output Leakage
Current
ILO
VOUT = -0.1V to VCC + 0.1V
10
µA
V
V
V
CC = MAX,
IN = GND or
CC f = 0 MHz,
Com.
80
80
110
130
mA
mA
Power Supply
Current Standby
ICC
ATF2500C
Ind., Mil.
Outputs Open
VIL
VIH
Input Low Voltage
Input High Voltage
MIN ≤ VCC ≤ MAX
-0.6
2.0
0.8
VCC + 0.75
0.5
V
V
V
V
V
I
OL = 8 mA
OL = 6 mA
Com., Ind.
Mil.
Output Low
Voltage
VIN = VIH or VIL,
VOL
V
CC = 4.5V
I
0.5
IOH = -100 µA
OH = -4.0 mA
VCC - 0.3
2.4
Output High
Voltage
VOH
Note:
V
CC = MIN
I
1. See ICC versus frequency characterization curves.
ATF2500C AC Characteristics
-15
-20
Max
20
Symbol
tPD1
tPD2
tPD3
tPD4
tEA1
tER1
tEA2
tER2
tAW
Parameter
Min
Max
15
15
11
11
15
15
15
15
Min
Units
ns
Input to Non-registered Output
Feedback to Non-registered Output
Input to Non-registered Feedback
Feedback to Non-registered Feedback
Input to Output Enable
20
ns
15
ns
15
ns
20
ns
Input to Output Disable
20
ns
Feedback to Output Enable
20
ns
Feedback to Output Disable
Asynchronous Reset Width
20
ns
8
12
ns
tAP
Asynchronous Reset to Registered Output
Asynchronous Reset to Registered Feedback
18
15
22
19
ns
tAPF
ns
ATF2500C Register AC Characteristics, Input Pin Clock
-15
-20
Symbol Parameter
Units
Min
Max
10
5
Min
Max
tCOS
tCFS
tSIS
Clock to Output
11
6
ns
ns
ns
ns
Clock to Feedback
Input Setup Time
0
9
9
0
14
14
tSFS
Feedback Setup Time
11
0777I–PLD–4/03
ATF2500C Register AC Characteristics, Input Pin Clock
-15
-20
Symbol Parameter
Units
ns
Min
0
Max
Min
0
Max
tHS
tWS
tPS
Hold Time
Clock Width
Clock Period
6
7
ns
12
14
ns
External Feedback 1/(tSIS + tCOS
Internal Feedback 1/(tSFS + tCFS
No Feedback 1/(tPS
Asynchronous Reset/Preset Recovery Time
)
52
71
83
40
50
71
MHz
MHz
MHz
ns
FMAXS
)
)
tARS
12
15
ATF2500C Register AC Characteristics, Product Term Clock
-15
-20
Symbol Parameter
Min
Max
15
Min
Max
20
Units
ns
tCOA
tCFA
tSIA
tSFA
tHA
Clock to Output
Clock to Feedback
Input Setup Time
Feedback Setup Time
Hold Time
5
5
12
10
10
8
16
ns
ns
5
ns
5
10
11
22
ns
tWA
tPA
Clock Width
7.5
15
ns
Clock Period
ns
External Feedback 1/(tSIA + tCOA
)
50
58
66
33
38
45
MHz
MHz
MHz
ns
FMAXA
Internal Feedback 1/(tSFA + tCFA
No Feedback 1/(tPS
)
)
tARA
Asynchronous Reset/Preset Recovery Time
8
12
12
ATF2500C
0777I–PLD–4/03
ATF2500C
ATF2500C IV Data 44PLCC
STAND-BY ICC VS. TEMPERATURE (VCC = 5.0V)
100.0
ATF2500C OUTPUT SOURCE CURRENT VS.
90.0
80.0
70.0
60.0
50.0
SUPPLY VOLTAGE (VOH = 2.4V, TA = 25°C)
-10
-20
-30
-40
4.50
4.75
5.00
5.25
5.50
-40.0
25.0
85.0
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
STAND-BY ICC VS.
SUPPLY VOLTAGE (TA = 25°C)
ATF2500C OUTPUT SINK CURRENT VS.
SUPPLY VOLTAGE (VOL = 0.5V, TA = 25°C)
100.0
90.0
80.0
70.0
60.0
50.0
15
14
13
12
11
10
4.50
4.75
5.00
5.25
5.50
SUPPLY VOLTAGE (V)
4.5
4.8
5.0
5.3
5.5
SUPPLY VOLTAGE (V)
ATF2500C OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
ATF2500C INPUT CLAMP CURRENT VS.
INPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
0.0
-10.0
-20.0
-30.0
-40.0
50
0
-50
-100
-150
-200
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
INPUT VOLTAGE (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT VOLTAGE (V)
ATF2500C INPUT CURRENT VS.
ATF2500C OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
INPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
40
30
20
10
0
50
40
30
20
10
0
-10
-20
-30
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
INPUT VOLTAGE (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT VOLTAGE (V)
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0777I–PLD–4/03
NORMALIZED TPD VS. SUPPLY VOLTAGE
(TA = 25°C)
ATF2500C OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
1.2
1.1
1.0
0.9
0.8
0
-2
-4
-6
-8
4.5
4.6
4.7
4.8
4.9
5.0
Output Voltage (V)
4.50
4.75
5.00
5.25
5.50
SUPPLY VOLTAGE (V)
ATF2500C OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
NORMALIZED TPD VS. AMBIENT TEMP (VCC = 5V)
1.1
1.0
0.9
0.8
30
25
20
15
10
5
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
-40.0
25.0
85.0
OUTPUT VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
NORMALIZED TCOS VS. SUPPLY VOLTAGE
(TA = 25°C)
ATF2500C SUPPLY CURRENT VS. SUPPLY
VOLTAGE (Freq. = 0 MHz, TA = 25°C)
1.1
1.0
0.9
100
90
80
70
60
50
4.50
4.75
5.00
5.25
5.50
4.50
4.75
5.00
5.25
5.50
Supply Voltage (V)
SUPPLY VOLTAGE (V)
ATF2500C SUPPLY CURRENT VS.
NORMALIZED TCOS VS. AMBIENT TEMP
(VCC = 5V)
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
120
1.1
100
80
1.0
0.9
0.8
60
0
10
20
30
40
50
60
70
80
90
FREQUENCY (MHz)
-40.0
25.0
85.0
AMBIENT TEMPERATURE (°C)
14
ATF2500C
0777I–PLD–4/03
ATF2500C
NORMALIZED TCOA VS. SUPPLY VOLTAGE
(TA = 25°C)
NORMALIZED TSIS VS. AMBIENT TEMP
(VCC = 5V)
1.3
1.2
1.1
1.0
0.9
0.8
1.2
1.1
1.0
0.9
0.8
-40.0
25.0
85.0
4.50
4.75
5.00
5.25
5.50
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
NORMALIZED TSIA VS. SUPPLY VOLTAGE
(TA = 25°C)
NORMALIZED TCOA VS. AMBIENT TEMP
(VCC = 5V)
1.2
1.1
1.1
1.0
0.9
0.8
1.0
0.9
0.8
-40.0
25.0
85.0
4.50
4.75
5.00
5.25
5.50
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
NORMALIZED TSIS VS. SUPPLY VOLTAGE
(TA = 25°C)
NORMALIZED TSIA VS. AMBIENT TEMP
(VCC = 5V)
1.2
1.1
1.0
0.9
0.8
1.2
1.1
1.0
0.9
0.8
4.50
4.75
5.00
5.25
5.50
-40.0
25.0
85.0
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
15
0777I–PLD–4/03
Ordering Information
tPD
(ns)
tCOS
(ns)
Ext. fMAXS
(MHz)
Ordering Code
Package
Operation Range
Commercial
ATF2500C-15JC
44J
(0°C to 70°C)
15
20
10
11
52
40
Industrial
ATF2500C-15JI
44J
(-40°C to 85°C)
ATF2500C-20JC
ATF2500C-20PC
44J
Commercial
40P6
(0°C to 70°C)
ATF2500C-20JI
ATF2500C-20PI
44J
Industrial
40P6
(-40°C to 85°C)
Package Type
40P6
44J
40-pin, 0.600" Wide, Plastic, Dual Inline Package (PDIP)
44-lead, Plastic J-leaded Chip Carrier (PLCC)
16
ATF2500C
0777I–PLD–4/03
ATF2500C
Packaging Information
44J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
D2/E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
–
A1
A2
D
2.286
–
0.508
–
17.399
16.510
17.399
16.510
–
17.653
D1
E
–
16.662 Note 2
17.653
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
–
16.662 Note 2
16.002
D2/E2 14.986
–
B
0.660
0.330
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
44J
TITLE
2325 Orchard Parkway
San Jose, CA 95131
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
B
R
17
0777I–PLD–4/03
40P6 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
0º ~ 15º REF
C
MIN
–
MAX
4.826
–
NOM
NOTE
SYMBOL
A
–
eB
A1
D
0.381
52.070
15.240
13.462
0.356
1.041
3.048
0.203
15.494
–
–
52.578 Note 2
15.875
E
–
E1
B
–
13.970 Note 2
0.559
–
B1
L
–
1.651
Notes:
1. This package conforms to JEDEC reference MS-011, Variation AC.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
–
3.556
C
–
–
0.381
eB
e
17.526
2.540 TYP
09/28/01
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)
40P6
B
R
18
ATF2500C
0777I–PLD–4/03
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
2325 Orchard Parkway
San Jose, CA 95131
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
Regional Headquarters
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
Tel: 1(719) 576-3300
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
Tel: 1(719) 576-3300
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard
warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any
errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and
does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are
granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use
as critical components in life support devices or systems.
© Atmel Corporation 2003. All rights reserved. Atmel® and combinations thereof, and ProChip Designer®
are the registered trademarks, and Atmel-WinCUPL™ is the trademark of Atmel Corporation or its subsidiaries.
Other terms and product names may be the trademarks of others.
Printed on recycled paper.
0777I–4/03/0M
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
2325 Orchard Parkway
San Jose, CA 95131
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
Regional Headquarters
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
Tel: 1(719) 576-3300
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
Tel: 1(719) 576-3300
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard
warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any
errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and
does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are
granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use
as critical components in life support devices or systems.
Printed on recycled paper.
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