ATM90E32AS-AU-Y [ATMEL]
Enhanced Poly-Phase High-Performance Wide-Span Energy Metering IC;
| 型号： | ATM90E32AS-AU-Y |
| 厂家： | 
ATMEL |
| 描述： | Enhanced Poly-Phase High-Performance Wide-Span Energy Metering IC |
| 文件： | 总84页 (文件大小：789K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Atmel M90E32AS
Enhanced Poly-Phase High-Performance Wide-Span
Energy Metering IC
DATASHEET
FEATURES
Metering Features
• Metering features fully in compliance with the requirements of IEC62052-11,
IEC62053-22 and IEC62053-23, ANSI C12.1 and ANSI C12.20; applicable in poly-
phase class 0.2S, 0.5S or class 1 watt-hour meter or class 2 var-hour meter.
• Accuracy of ±0.1% for active energy and ±0.2% for reactive energy over a
dynamic range of 6000:1.
• Temperature coefficient is 6 ppm/ ℃ (typ.) for on-chip reference voltage. Automati-
cally temperature compensated.
• Single-point calibration on each phase over the whole dynamic range for active
energy; no calibration needed for reactive/ apparent energy.
• ±1 ℃ (typ.) temperature sensor accuracy.
• Flexible piece-wise non-linearity compensation: three current (RMS value)-based
segments with two programmable thresholds for each phase. Independent gain and
phase angle compensation for each segment.
• Electrical parameters measurement: less than ±0.5% fiducial error for Vrms, Irms,
mean active/ reactive/ apparent power, frequency, power factor and phase angle.
• Active (forward/reverse), reactive (forward/reverse), apparent energy with indepen-
dent energy registers.
• Programmable startup and no-load power thresholds.
• 6 dedicated ADCs for phase A/B/C current and voltage sampling circuits. Current
sampled over Current Transformer (CT) or Rogowski coil (di/dt coil); voltage sam-
pled over resistor divider network.
• Programmable power modes: Normal, Idle, Detection and Partial Measurement
mode.
• Fundamental (0.2%) and harmonic (1%) active energy with dedicated energy /
power registers and independent energy outputs.
• Current and voltage instantaneous signal monitoring.
• Enhanced event detection: sag, over voltage, phase loss, over current, reverse V/I
phase sequence, calculated neutral line current I
over-current and frequency
NC
upper and lower threshold.
Other Features
• 3.3V single power supply. Operating voltage range: 2.8V~3.6V. Metering accuracy
guaranteed within 3.0V~3.6V.
• Four-wire SPI interface.
• Programmable voltage sag detection and zero-crossing output.
• Crystal oscillator frequency: 16.384MHz. On-chip two capacitors and no need of
external capacitors.
• Lower power consumption. I=13mA (typ.) in Normal mode.
• TQFP48 package.
• Operating temperature: -40 ℃ ~ +85 ℃ .
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
APPLICATION
• Poly-phase energy meters of class 0.2S, 0.5S and class 1 which are used in three-phase four-wire (3P4W, Y0) or
three-phase three-wire (3P3W, Y or Δ) systems.
• Power monitoring instruments which need to measure voltage, current, mean power, etc.
GENERAL DESCRIPTION
The M90E32AS is a poly-phase high performance wide-dynamic range metering IC. The M90E32AS incorporates 6 inde-
pendent 2nd order sigma-delta ADCs, which could be employed in three voltage channels (phase A, B and C) and three
current channels (phase A, B, C) in a typical three-phase four-wire system.
The M90E32AS has an embedded DSP which executes calculation of active energy, reactive energy, apparent energy, fun-
damental and harmonic active energy over ADC signal and on-chip reference voltage. The DSP also calculates measure-
ment parameters such as voltage and current RMS value as well as mean active/reactive/apparent power.
A four-wire SPI interface is provided between the M90E32AS and the external microcontroller.
The M90E32AS is suitable for poly-phase multi-function meters which could measure active/reactive/apparent energy and
fundamental/harmonic energy either through four independent energy pulse outputs CF1/CF2/CF3/CF4 or through the cor-
responding registers.
The ADC and auto-temperature compensation technology for reference voltage ensure the M90E32AS's long-term stability
over variations in grid and ambient environment conditions.
BLOCK DIAGRAM
OSCI
OSCO
PM1
PM0
Power Mode
Configuration
Crystal Oscillator
VDD18 Regulator
Power On Reset
Current Detector
CF1
CF2
CF3
CF4
RESET
Energy Metering
(Forward/Reverse
Active/Reactive/CF Generator)
CF Out
ADC-I1
ADC-I2
ADC-I3
WarnOut
IRQ0
IRQ1
I1P / I1N
I2P / I2N
I3P / I3N
Warn
Out
Flexible Piece-wise Non-linear
Compensation
DSP
IRQ
ZX0
ZX1
ZX2
Measure and Monitoring
(V/I/rms / SAG / Phase /
Frequency)
Zero
Crossing
ADC-V1
ADC-V2
ADC-V3
V1P / V1N
V2P / V2N
V3P / V3N
CS
Temperature Sensor
SCLK
SDO
SDI
Control Logic
SPI Interface
On-chip
Reference Voltage
Vref
Figure-1 M90E32AS Block Diagram
2
M90E32AS [Datasheet]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
Table of Contents
FEATURES .......................................................................................................................................... 1
APPLICATION ..................................................................................................................................... 2
GENERAL DESCRIPTION................................................................................................................... 2
BLOCK DIAGRAM............................................................................................................................... 2
1 PIN ASSIGNMENT .......................................................................................................................... 7
2 PIN DESCRIPTION .......................................................................................................................... 8
3 FUNCTION DESCRIPTION ........................................................................................................... 10
3.1 POWER SUPPLY ...................................................................................................................................................10
3.2 CLOCK ...................................................................................................................................................................10
3.3 RESET ....................................................................................................................................................................10
3.3.1 RESET Pin .................................................................................................................................................. 10
3.3.2 Power On Reset (POR) ............................................................................................................................. 10
3.3.3 Software Reset .......................................................................................................................................... 10
3.4 ANALOG/DIGITAL CHANNEL MAPPING ............................................................................................................11
3.5 METERING FUNCTION .........................................................................................................................................12
3.5.1 Theory of Energy Registers ..................................................................................................................... 12
3.5.2 Energy Registers ....................................................................................................................................... 13
3.5.3 Energy Pulse Output ................................................................................................................................. 14
3.5.4 Startup and No-load Power ...................................................................................................................... 14
3.6 MEASUREMENT FUNCTION ................................................................................................................................16
3.6.1 Active/ Reactive/ Apparent Power ........................................................................................................... 16
3.6.2 Fundamental / Harmonic Active Power ................................................................................................... 16
3.6.3 Mean Power Factor (PF) ........................................................................................................................... 16
3.6.4 Voltage / Current RMS .............................................................................................................................. 16
3.6.5 Phase Angle ............................................................................................................................................... 17
3.6.6 Frequency .................................................................................................................................................. 17
3.6.7 Temperature .............................................................................................................................................. 17
3.6.8 Peak Value ................................................................................................................................................. 17
3.7 POWER QUALITY MONITORING .........................................................................................................................18
3.7.1 Instantaneous Signal Monitoring ............................................................................................................ 18
3.7.2 Instantaneous Signal Related Status And Events ................................................................................. 19
3.7.3 Frequency Monitoring Related Status And Events ................................................................................ 20
3.7.4 Zero-Crossing Detection .......................................................................................................................... 20
3.7.5 Neutral Line Overcurrent Detection ........................................................................................................ 20
3.7.6 Phase Sequence Error Detection ............................................................................................................ 20
3.8 POWER MODE ......................................................................................................................................................21
3.8.1 Normal Mode (N Mode) ............................................................................................................................. 21
3.8.2 Idle Mode (I Mode) ..................................................................................................................................... 22
3.8.3 Detection Mode (D Mode) ......................................................................................................................... 24
3.8.4 Partial Measurement mode (M Mode) ...................................................................................................... 25
3.8.5 Transition of Power Modes ...................................................................................................................... 26
3.9 EXTERNAL COMPONENT COMPENSATION .....................................................................................................27
3.9.1 Gain Based Compensation ...................................................................................................................... 28
3.9.2 Delay/Phase Based Compensation ......................................................................................................... 29
M90E32AS [DATASHEET]
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3
4 SPI INTERFACE ............................................................................................................................ 30
4.1 INTERFACE DESCRIPTION .................................................................................................................................30
4.2 SPI INTERFACE ....................................................................................................................................................30
4.2.1 SPI Slave Interface Format ....................................................................................................................... 30
4.2.2 Reliability Enhancement Feature ............................................................................................................. 31
5 REGISTER ..................................................................................................................................... 32
5.1 REGISTER LIST ....................................................................................................................................................32
5.2 SPECIAL REGISTERS ..........................................................................................................................................39
5.2.1 Configuration Registers CRC Generation .............................................................................................. 39
5.2.2 IRQ and WarnOut Signal Generation ...................................................................................................... 40
5.2.3 Special Configuration Registers .............................................................................................................. 45
5.3 LOW-POWER MODES REGISTERS ....................................................................................................................48
5.3.1 Detection Mode Registers ........................................................................................................................ 48
5.3.2 Partial Measurement mode Registers ..................................................................................................... 50
5.4 CONFIGURATION AND CALIBRATION REGISTERS .........................................................................................55
5.4.1 Configuration Registers ........................................................................................................................... 55
5.4.2 Energy Calibration Registers ................................................................................................................... 57
5.4.3 Fundamental/Harmonic Energy Calibration registers ........................................................................... 58
5.4.4 Measurement Calibration ......................................................................................................................... 59
5.4.5 EMM Status ................................................................................................................................................ 59
5.5 ENERGY REGISTER .............................................................................................................................................67
5.5.1 Regular Energy Registers ........................................................................................................................ 67
5.5.2 Fundamental / Harmonic Energy Register .............................................................................................. 68
5.6 MEASUREMENT REGISTERS ..............................................................................................................................69
5.6.1 Power and Power Factor Registers ......................................................................................................... 69
5.6.2 Fundamental/ Harmonic Power and Voltage/ Current RMS Registers ................................................. 70
5.6.3 Peak, Frequency, Angle and Temperature Registers ............................................................................ 71
6 ELECTRICAL SPECIFICATION .................................................................................................... 72
6.1 ELECTRICAL SPECIFICATION ............................................................................................................................72
6.2 METERING/ MEASUREMENT ACCURACY .........................................................................................................74
6.2.1 Metering Accuracy .................................................................................................................................... 74
6.2.2 Measurement Accuracy ............................................................................................................................ 75
6.3 INTERFACE TIMING .............................................................................................................................................76
6.3.1 SPI Interface Timing (Slave Mode) .......................................................................................................... 76
6.4 POWER ON RESET TIMING .................................................................................................................................77
6.5 ZERO-CROSSING TIMING ....................................................................................................................................78
6.6 VOLTAGE SAG AND PHASE LOSS TIMING .......................................................................................................79
6.7 ABSOLUTE MAXIMUM RATING ..........................................................................................................................80
ORDERING INFORMATION.............................................................................................................. 81
PACKAGE DIMENSIONS.................................................................................................................. 82
REVISION HISTORY ......................................................................................................................... 83
4
M90E32AS [Datasheet]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
List of Tables
Table-1
Table-2
Table-3
Table-4
Table-5
Table-6
Table-7
Table-8
Table-9
Pin Description .................................................................................................................................................... 8
Power Mode Mapping ....................................................................................................................................... 21
Digital I/O and Power Pin States in Idle Mode .................................................................................................. 22
Compensation Related Registers ..................................................................................................................... 27
Register List ...................................................................................................................................................... 32
Configuration Registers .................................................................................................................................... 55
Calibration Registers ........................................................................................................................................ 57
Fundamental/Harmonic Energy Calibration Registers ...................................................................................... 58
Measurement Calibration Registers ................................................................................................................. 59
Table-10 EMM Status Registers ...................................................................................................................................... 59
Table-11 Regular Energy Registers ................................................................................................................................. 67
Table-12 Fundamental / Harmonic Energy Register ........................................................................................................ 68
Table-13 Power and Power Factor Register .................................................................................................................... 69
Table-14 Fundamental/ Harmonic Power and Voltage/ Current RMS Registers ............................................................. 70
Table-15 Peak, Frequency, Angle and Temperature Registers ....................................................................................... 71
Table-16 Metering Accuracy for Different Energy within the Dynamic Range ................................................................. 74
Table-17 Measurement Parameter Range and Format ................................................................................................... 75
Table-18 SPI Timing Specification ................................................................................................................................... 76
Table-19 Power On Reset Specification .......................................................................................................................... 77
Table-20 Zero-Crossing Specification .............................................................................................................................. 78
M90E32AS [DATASHEET]
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5
List of Figures
Figure-1 M90E32AS Block Diagram ................................................................................................................................. 2
Figure-2 Pin Assignment (Top View) ................................................................................................................................ 7
Figure-3 Channel to Phase Mapping .............................................................................................................................. 11
Figure-4 Energy Accumulation Diagram ......................................................................................................................... 13
Figure-5 CFx Pulse Output Regulation ........................................................................................................................... 14
Figure-6 Active Power Startup/Noload Processing ......................................................................................................... 14
Figure-7 Fundamental Active Power Startup/Noload Processing ................................................................................... 15
Figure-8 Harmonic Active Power Startup/Noload Processing ......................................................................................... 15
Figure-9 Power Quality Monitor in Datapath ................................................................................................................... 18
Figure-10 Block Diagram in Normal Mode ........................................................................................................................ 21
Figure-11 Block Diagram in Idle Mode .............................................................................................................................. 22
Figure-12 Block Diagram in Detection Mode .................................................................................................................... 24
Figure-13 Block Diagram in Partial Measurement mode .................................................................................................. 25
Figure-14 Power Mode Transition ..................................................................................................................................... 26
Figure-15 Segment Gain Compensation ........................................................................................................................... 28
Figure-16 Slave Mode ....................................................................................................................................................... 30
Figure-17 Read Sequence ................................................................................................................................................ 31
Figure-18 Write Sequence ................................................................................................................................................ 31
Figure-19 CRC Checking Diagram ................................................................................................................................... 39
Figure-20 IRQ and WarnOut Generation .......................................................................................................................... 40
Figure-21 Current Detection Register Latching Scheme .................................................................................................. 48
Figure-22 SPI Timing Diagram .......................................................................................................................................... 76
Figure-23 Power On Reset Timing (M90E32AS and MCU are Powered on Simultaneously) .......................................... 77
Figure-24 Power On Reset Timing in Normal & Partial Measurement Mode .................................................................... 77
Figure-25 Zero-Crossing Timing Diagram (per phase) ..................................................................................................... 78
Figure-26 Voltage Sag and Phase Loss Timing Diagram ................................................................................................. 79
M90E32AS [DATASHEET]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
6
1
PIN ASSIGNMENT
1
AVDD
AGND
IC
36
35
2
NC
I1P
I1N
3
34
33
32
PM1
PM0
4
I2P
5
TEST
IRQ1
IRQ0
WarnOut
CF4
6
I2N
I3P
31
30
7
8
I3N
IC
29
28
9
10
11
12
CF3
IC
27
Vref
CF2
26
25
AGND
CF1
Figure-2 Pin Assignment (Top View)
M90E32AS [DATASHEET]
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2
PIN DESCRIPTION
Table-1 Pin Description
Name
Pin No.
I/O
Type
Description
Reset: Reset Pin (active low)
This pin should connect to ground through a 0.1 μF filter capacitor and a
10kΩ resistor to VDD. In application it can also directly connect to one out-
put pin from microcontroller (MCU).
Reset
41
I
LVTTL
AVDD: Analog Power Supply
AVDD
DVDD
VDD18
1
I
I
Power
Power
Power
This pin provides power supply to the analog part. This pin should connect
to DVDD and be decoupled with a 0.1μF capacitor.
DVDD: Digital Power Supply
This pin provides power supply to the digital part. It should be decoupled
with a 10μF capacitor and a 0.1μF capacitor.
48
VDD18: Digital Power Supply (1.8 V)
These two pins should be connected together and connected to ground
through a 10μF capacitor.
42, 43
P
DGND
AGND
19, 44, 47
2, 12
I
I
Power
Power
DGND: Digital Ground
AGND: Analog Ground
I1P: Positive Input for Analog ADC Channel
I1N: Negative Input for Analog ADC Channel
I1P
I1N
3
4
These pins are differential inputs for analog ADC channel.
These 6 analog ADC channels can be flexibly mapped, refer to 3.4 Analog/
digital Channel Mapping.1
I
I
Analog
Analog
I2P: Positive Input for Analog ADC Channel
I2N: Negative Input for Analog ADC Channel
These pins are differential inputs for analog ADC channel.
These 6 analog ADC channels can be flexibly mapped, refer to 3.4 Analog/
digital Channel Mapping.1
I2P
I2N
5
6
I3P: Positive Input for Analog ADC Channel
I3N: Negative Input for Analog ADC Channel
I3P
I3N
7
8
These pins are differential inputs for analog ADC channel.
These 6 analog ADC channels can be flexibly mapped, refer to 3.4 Analog/
digital Channel Mapping.1
I
O
I
Analog
Analog
Analog
Vref: Output Pin for Reference Voltage
This pin should be decoupled with a 4.7μF capacitor, it is better to add a
0.1μF ceramic capacitor.
Vref
11
V1P: Positive Input for Analog ADC Channel
V1N: Negative Input for Analog ADC Channel
These pins are differential inputs for analog ADC channel.
These 6 analog ADC channels can be flexibly mapped, refer to 3.4 Analog/
digital Channel Mapping.1
V1P
V1N
13
14
V2P: Positive Input for Analog ADC Channel
V2N: Negative Input for Analog ADC Channel
V2P
V2N
15
16
These pins are differential inputs for analog ADC channel.
These 6 analog ADC channels can be flexibly mapped, refer to 3.4 Analog/
digital Channel Mapping.1
I
I
Analog
Analog
V3P: Positive Input for Analog ADC Channel
V3N: Negative Input for Analog ADC Channel
These pins are differential inputs for analog ADC channel.
These 6 analog ADC channels can be flexibly mapped, refer to 3.4 Analog/
digital Channel Mapping.1
V3P
V3N
17
18
8
M90E32AS [Datasheet]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
Table-1 Pin Description (Continued)
Name
Pin No.
I/O
Type
Description
OSCI
20
I
OSC
OSCI: External Crystal Input
OSCO: External Crystal Output
A 16.384 MHz crystal is connected between OSCI and OSCO. There are
two on-chip capacitors, therefore no need of external capacitors.
OSCO
21
O
O
OSC
ZX0
ZX1
ZX2
22
23
24
ZX2/ZX1/ZX0:Zero-Crossing Output
These pins are asserted when voltage or current crosses zero. Zero-cross-
ing mode can be configured by the ZXConfig register (07H).
LVTTL
CF1
25
O
O
LVTTL
LVTTL
CF1: (all-phase-sum total) Active Energy Pulse Output
CF2: (all-phase-sum total) Reactive/ Apparent Energy Pulse Output
The output of this pin is determined by the CF2varh bit (b7, MMode0).
CF2
26
CF3
CF4
27
28
O
O
LVTTL
LVTTL
CF3: (all-phase-sum total) Active Fundamental Energy Pulse Output
CF4: (all-phase-sum total) Active Harmonic Energy Pulse Output
WarnOut: Fatal Error Warning
This pin is asserted high when there is metering related parameter check-
sum error. Otherwise this pin stays low. Refer to 5.2.2 IRQ and WarnOut
Signal Generation.
WarnOut
29
O
LVTTL
IRQ0: Interrupt Output 0
This pin is asserted when one or more events in the EMMIntState0 register
(1CCH) occur. It is deasserted when there is no bit set in the EMMIntState0
register (1CCH).
IRQ0
30
O
LVTTL
In Detection mode, the IRQ0 is used to indicate the output of current detec-
tor. The IRQ0 state is cleared when entering or exiting Detection mode.
IRQ1: Interrupt Output 1
This pin is asserted when one or more events in the EMMIntState1 register
(1D0H) occur. It is deasserted when there is no bit set in the EMMIntState1
register (1D0H).
IRQ1
31
O
LVTTL
In Detection mode, the IRQ1 is used to indicate the output of current detec-
tor. The IRQ1 state is cleared when entering or exiting Detection mode.
PM0
PM1
33
34
PM1/0: Power Mode Configuration
These two pins define the power mode of M90E32AS. Refer to Table-2.
I2
I2
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
CS: Chip Select (Active Low)
In SPI mode, this pin must be driven from high to low for each read/ write
operation, and maintain low for the entire operation.
CS
37
38
39
40
SCLK: Serial Clock
This pin is used as the clock for the SPI interface. Refer to 4 SPI Interface.
I2
SCLK
SDO
SDI
SDO: Serial Data Output
This pin is used as the data output for the SPI mode. Refer to 4 SPI Inter-
face.
O
SDI: Serial Data Input
This pin is used as the data input for the SPI mode. Refer to 4 SPI Interface.
I2
I
TEST
IC
32
LVTTL
LVTTL
This pin should be always connected to DGND in system application.
These pins should be always connected to DGND in system application.
NC: These pins should be left open.
9, 10, 36
35, 45, 46
NC
Note 1: The channel mapping is only valid in Normal mode and Patial Measurement mode.
Note 2: All the digital input pins except OSCI are 5 V compatible.
M90E32AS [DATASHEET]
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9
3
FUNCTION DESCRIPTION
3.1
POWER SUPPLY
The M90E32AS works with single power rail 3.3V. An on-chip voltage regulator regulates the 1.8V voltage for the digital
logic.
The regulated 1.8V power is connected to the VDD18 pin. It needs to be bypassed by an external capacitor.
The M90E32AS has four power modes: Normal (N mode), Partial Measurement (M mode), Detection (D mode) and Idle (I
mode). In Idle and Detection modes the 1.8V power regulator is not turned on and the digital logic is not powered. When
the logic is not powered, all the configured register values are not kept (all context lost) except for Detection mode related
registers (10H~13H) for Detection mode configuration.
The registers in Partial Measurement mode or Normal mode have to be re-configured when transiting from Idle or Detec-
tion mode. Refer to 3.8 Power Mode for power mode details.
3.2
CLOCK
The M90E32AS has an on-chip oscillator and can directly connect to an external crystal.
The OSCI pin can also be driven with a clock source.
The oscillator will be powered down in Idle and Detection power modes, as described in 3.8 Power Mode.
3.3
RESET
There are three reset sources for the M90E32AS:
- RESET pin
- On-chip Power On Reset circuit
- Software Reset generated by the SoftReset register
3.3.1
RESET PIN
The RESET pin can be asserted to reset the M90E32AS. The RESET pin has RC filter with typical time constant of 2μs in the
I/O, as well as a 2μs (typical) de-glitch filter.
Any reset pulse that is shorter than 2μs can not reset the M90E32AS.
3.3.2
POWER ON RESET (POR)
The POR circuit resets the M90E32AS at power up.
POR circuit triggers reset when:
- DVDD power up with crossing the power-up threshold. Refer to Figure-24.
- VDD18 regulator changing from disable to enable, i.e. from Idle or Detection mode to Partial Measurement mode or
Normal mode. Refer to Figure-23.
3.3.3
SOFTWARE RESET
Chip reset can be triggered by writing to the SoftReset register in Normal mode. The software reset is the same as the
reset scope generated from the RESET pin or POR.
These three reset sources have the same reset scope.
All digital logics and registers except for some special registers will be subjected to reset.
• Interface logic: clock dividers
• Digital core/ logic: All registers except for some special registers. Refer to 5.3.1 Detection Mode Registers.
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M90E32AS [Datasheet]
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3.4
ANALOG/DIGITAL CHANNEL MAPPING
Analog channel to digital channel mapping:
The 6 analog ADC channels can be flexibly mapped to the 6 digital metering/measuring channels (V/I phase A/B/C). Refer
to the ChannelMapI and ChannelMapU registers for configuration.
Note that channel mapping is only valid in Normal mode and Patial Measurement mode.
V CH_A
Analog
Digital
V CH0
V CH1
V CH2
V CH_B
I CH0
I CH1
I CH2
V CH_C
I CH_A
I CH_B
I CH_C
Flexible Channel mapping
Figure-3 Channel to Phase Mapping
M90E32AS [DATASHEET]
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11
3.5
METERING FUNCTION
Metering is enabled when any of the MeterEn bits are set.
When metering is not enabled, the CF pulse will not be generated and energy accumulator will not accumulate energy. All
energy accumulation related status will be cleared, while startup/noload handling block related status will be still working.
The accumulated energy will be converted to pulse frequency on the CF pins and stored in the corresponding energy reg-
isters.
3.5.1
THEORY OF ENERGY REGISTERS
The energy accumulation runs at 1 MHz clock rate by accumulating the power value calculated by the DSP processor.
The power accumulation process is equivalent to digitally integrating the instantaneous power with a delta-time of about
1us. The accumulated energy is used to calculate the CF pulses and the corresponding internal energy registers.
The accumulated energy is converted to frequency of the CF pulses. One CF usually corresponds to 1KWh / MC (MC is
Meter Constant, e.g. 3200 imp/kWh), and is usually referenced as an energy unit in this datasheet. The internal energy res-
olution for accumulation and conversion is 0.01 CF.
The 0.01 CF pulse energy constant is referenced as 'PL_constant'.
Within 0.01 CF, forward and reverse energy are counteracted. When energy exceeds 0.01 pulse, the respective forward/
reverse energy is increased.
Take the example of active energy. Suppose:
T0: Forward energy register is 12.34 pulses and reverse energy register is 1.23 pulses.
From t0 to t1: 0.005 forward pulses appeared.
From t1 to t2: 0.004 reverse pulses appeared.
From t2 to t3: 0.005 reverse pulses appeared.
From t3 to t4: 0.007 reverse pulses appeared.
The following table illustrates the process of energy accumulation process:
t0
+ 0.005
0.005
0
t1
-0.004
0.001
0
t2
-0.005
-0.004
0
t3
-0.007
-0.001
0
t4
Input energy
Bidirectional energy accumulator
Forward 0.01 CF
Reverse 0.01CF
0
0
0
1
Forward energy register
Reverse energy register
12.34
1.23
12.34
1.23
12.34
1.23
12.34
1.23
12.34
1.24
When forward/reverse energy reaches 0.01 pulse, the respective register is updated. When forward or reverse energy
reaches 1 pulse, CFx pins output pulse and the CFxRevST bits (b3~0, EMMState0) are updated. Refer to Figure-4.
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M90E32AS [Datasheet]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
A/B/C
Phase-A
Phase-B
Phase-C
Per-
phase
Power
Bi-directional
(+)0.01
Energy
accumulator,
Forward
CF
roll over
Energy
Accumulator
[P/Q]Ereg[A/B/C]PST
positive/
(-)0.01
CF
negative @
0.01CF
Backward
Energy
Accumulator
total
Pos-CF
Accumulator
[P/Q]EregTPST
Bi-directional
Energy
accumulator,
roll over
positive/
negative @
0.01CF
(+)0.01
CF
Forward
Energy
Accumulator
All-phase
sum Power
A/B/C
(-)0.01
CF
Backward
Energy
Accumulator
CF Gen
Logic
CF pulse
Neg-CF
Accumulator
CF[1/2/34]RevST
Figure-4 Energy Accumulation Diagram
For all-phase-sum total of active, reactive and (arithmetic sum) apparent energy, the associated power is obtained by sum-
ming the power of the three phases. The accumulation method of all-phase-sum energy is determined by the EnPC/EnPB/
EnPA/ABSEnP/ABSEnQ bits (b0~b4, MMode0).
Note that the direction of all-phase-sum power and single-phase power might be different.
3.5.2
ENERGY REGISTERS
The M90E32AS meters non-decomposed total active, reactive and apparent energy, as well as decomposed active funda-
mental and harmonic energy. The registers are listed as below.
3.5.2.1
Total Energy Registers
Each phase and all-phase-sum has the following registers:
-
-
-
Active forward/ reverse
Reactive forward/ reverse
Apparent energy
Altogether there are 20 energy registers. Those registers are defined in 5.5.1 Regular Energy Registers.
3.5.2.2 Fundamental and Harmonic Energy Registers
The M90E32AS counts decomposed active fundamental and harmonic energy. Reactive energy is not decomposed to fun-
damental and harmonic.
The fundamental/harmonic energy is accumulated in the same way as active energy accumulation method described
above.
Registers:
-
-
-
Fundamental / harmonic
all-phase-sum / phase A / phase B / phase C
Forward / reverse
Altogether there are 16 energy registers. Refer to 5.5.2 Fundamental / Harmonic Energy Register.
M90E32AS [DATASHEET]
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13
3.5.3
ENERGY PULSE OUTPUT
CF1 is fixed to be total active energy output (all-phase-sum). Both forward and reverse energy registers can generate the
CF pulse (change of forward/ reverse direction can generate an interrupt if enabled).
CF2 is reactive energy output (all-phase-sum) by default. It can also be configured to be arithmetic sum apparent energy
output (all-phase-sum).
CF3 is fixed to be active fundamental energy output (all-phase-sum).
CF4 is fixed to be active harmonic energy output (all-phase-sum).
Tp=80ms
Tp=0.5T
CFx
T≥160ms
10ms≤T<160ms
Figure-5 CFx Pulse Output Regulation
For CFx pulse width regulation, refer to Figure-5.
Case1 T>=160ms, Tp=80ms
Case 2 10ms<=T<160ms, Tp=T/2
3.5.4
STARTUP AND NO-LOAD POWER
There are startup power threshold registers (e.g. PStartTh(35H)). Refer to 5.4 Configuration and Calibration Registers. The
power threshold registers are defined for all-phase-sum active, reactive and apparent power. The M90E32AS starts meter-
ing when the corresponding all-phase-sum power is greater than the startup threshold. When the power value is lower than
the startup threshold, energy is not accumulated and it is assumed as in no-load status. Refer to Figure-6.
There are also no-load Current Threshold registers for Active, Reactive and Apparent energy metering participation for
each of the 3 phases. If |P|+|Q| is lower than the corresponding power threshold, that particular phase will not be accumu-
lated. Refer to the PStartTh register and other threshold registers.
There are also no-load status bits (the TPnoload/TQnoload bits (b14~15, Fundamental / Harmonic Energy Register))
defined to reflect the no-load status. The M90E32AS does not output any pulse in no-load status. The power-on state is of
no-load status.
Phase |P| + |Q| >
PPhaseTh?
C
B
Phase |P| + |Q| >
0
0
1
Total Active Power
Total Active
Energy Metering
PPhaseTh?
Phase |P| + |Q| >
A
PPhaseTh?
ABS >
PStartTh?
NoLoad Status
Phase Active
Power from DSP
1
1
Phase Active
Energy Metering
0
0
0
0
Active Power
Startup/Noload handling
Figure-6 Active Power Startup/Noload Processing
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Phase |P| + |Q| >
PPhaseTh?
Total Active Power
C
Total Active Fund
Power
Phase |P| + |Q| >
PPhaseTh?
B
0
0
1
Total Active Fund
Energy Metering
Phase |P| + |Q| >
A
PPhaseTh?
ABS >
PStartTh?
Phase Active
Fundamental
NoLoad Status
1
Power from DSP
1
0
Phase Active
Fund Energy
Metering
0
0
0
Active Power
startup/Noload handling
Figure-7 Fundamental Active Power Startup/Noload Processing
Phase |P| + |Q| >
PPhaseTh?
Phase |P| + |Q| >
PPhaseTh?
Total Active Power
Total Active Harmonic
C
B
Power
Total Active
Harmonic Energy
Metering
0
0
Phase(Active
Total Power -
Active
Phase |P| + |Q| >
1
A
PPhaseTh?
ABS >
PStartTh?
NoLoad Status
1
Fundamental
Power) from DSP
1
0
Phase Active
Harmonic Energy
Metering
0
0
0
Active Power
startup/Noload handling
Figure-8 Harmonic Active Power Startup/Noload Processing
M90E32AS [DATASHEET]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
15
3.6
MEASUREMENT FUNCTION
Measured parameters can be divided to 8 types as follows:
- Active/ Reactive/ Apparent Power
- Fundamental/ Harmonic Power
- RMS for Voltage and Current
- Power Factor
- Phase Angle
- Frequency
- Temperature
- Peak Value
Measured parameters are average values that are averaged among 16 phase-voltage cycles (about 320ms at 50Hz)
except for the temperature. The measured parameter update frequency is approximately 3Hz. Refer to Table-17.
3.6.1
ACTIVE/ REACTIVE/ APPARENT POWER
Active/ Reactive/ Apparent Power measurement registers can be divided as below:
- active, reactive, apparent power
- all-phase-sum / phase A / phase B / phase C
Altogether there are 12 power registers. Refer to 5.6.1 Power and Power Factor Registers.
Per-phase apparent power is defined as the product of measured Vrms and Irms of that phase.
All-phase-sum power is measured by arithmetically summing the per-phase measured power. The summing of phases can
be configured by the MMode0 register.
3.6.2
FUNDAMENTAL / HARMONIC ACTIVE POWER
Fundamental / harmonic active power measurement registers can be divided as below:
- fundamental and harmonic power
- all-phase-sum / phase A / phase B / phase C
Altogether there are 8 power registers. Refer to 5.6.2 Fundamental/ Harmonic Power and Voltage/ Current RMS Registers.
3.6.3
MEAN POWER FACTOR (PF)
Power Factor is defined for those cases: all-phase-sum / phase A / phase B / phase C.
Altogether there are 4 power factor registers. Refer to 5.6.1 Power and Power Factor Registers.
For all-phase:
All_phase_ sum active_pow er
PF_all =
All_phase_ sum apparent_p ower
For each of the phase::
active_power
PF_phase =
apparent_power
3.6.4
VOLTAGE / CURRENT RMS
Voltage/current RMS registers can be divided as follows:
Per-phase: Phase A / Phase B / Phase C
Voltage / Current
Neutral Line Current RMS:
Neutral line current can be calculated by instantaneous value
Altogether there are 7 RMS registers.
.
iN = iA + iB + iC
Refer to 5.6.2 Fundamental/ Harmonic Power and Voltage/ Current RMS Registers.
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3.6.5
PHASE ANGLE
Phase Angle measurement registers can be divided as below:
- phase A / phase B / phase C
- voltage / current
Altogether there are 6 phase angle registers. Refer to 5.6.3 Peak, Frequency, Angle and Temperature Registers.
Phase Angle is measured by the time-difference between the Voltage and Current channel of the same phase.
3.6.6
FREQUENCY
The frequency is measured basing on the zero-crossing point of voltage channels.
The phase A voltage signal zero-crossing will be used to compute the frequency. If phase A is in the SAG condition, phase
C will be used. If phase C is also in SAG condition, phase B will be used.
If all the phases are in the SAG condition, Frequency will be measured based on the channels which are not in phaseLoss
condition (with the same order). If all phases are lost, the frequency will return zero.
The frequency data is not averaged (updated cycle by cycle).
Refer to 5.6.3 Peak, Frequency, Angle and Temperature Registers.
3.6.7
TEMPERATURE
Chip Junction-Temperature is measured roughly every 100 ms by on-chip temperature sensor.
Refer to 5.6.3 Peak, Frequency, Angle and Temperature Registers.
3.6.8
PEAK VALUE
Altogether there are 6 peak value registers. Refer to 5.6.3 Peak, Frequency, Angle and Temperature Registers.
Refer to 3.7.1 Instantaneous Signal Monitoring.
M90E32AS [DATASHEET]
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17
3.7
POWER QUALITY MONITORING
Phase -C
Phase -B
Phase -A
V-channel
offset
PGA
ADC
+
map
ZX
OV
Detector
Peak
Detector
Sag
Detector
PhaseLoss
Detector
Phase Sequence,
Frequency
Frequency
Range
I-channel
offset
+
PGA
ADC
map
ZX
DSP
Freq
based
Comp
50/60
Phase
Angle
Peak
Detector
OI
Detector
Figure-9 Power Quality Monitor in Datapath
INSTANTANEOUS SIGNAL MONITORING
3.7.1
Peak detection function:
Peak value for each channel was detected within timing period configured by the PeakDet_period bits (b15~8, SagPeak-
DetCfg).
The detected peak value is updated on period intersection.
Registers:
The peak value detected can be accessed through register U/I Peak registers. Refer to 5.6.3 Peak, Frequency, Angle and
Temperature Registers.
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3.7.2
INSTANTANEOUS SIGNAL RELATED STATUS AND EVENTS
The registers involved are OVth, OIth, SagTh, PhaseLossTh and SagPeakDetCfg.
The result can be reflected in EMMState0 and EMMState1 registers, as well as EMMIntState0 and EMMIntState1 registers
if the corresponding bits in EMMIntEn0/EMMIntEn1 registers are set.
The threshold value has the following relationship with the RMS register (MSB-16bit):
RmsRegValue∗ 2
xxThRegValue =
VIgain
14
2
Here VIgain is Ugain register value or Igain register value.
3.7.2.1
Sag Detection
Usually in the application the Sag threshold is set to be 78% of the reference voltage. The M90E32AS generates Sag event
when there are less than three 8KHz samples (absolute value) greater than the sag threshold in one detecting period.
Refer to 6.6 Voltage Sag and Phase Loss Timing. The detecting period length can be configured by the Sag_Period bits
(b7~0, SagPeakDetCfg).
Sag status is asserted when there is no voltage instantaneous sample's absolute value goes beyond the Sag threshold in
any phase. Sag status is cleared when there are three samples detected with absolute value above the Sag threshold.
For the computation of Sag threshold register value, refer to application note 46103.
The Sag event is captured by the SagPhaseIntST bits (b14-12, EMMIntState1). If the corresponding IRQ enable bits the
SagPhaseIntEN bits (b14-12, EMMIntEn1) is set, IRQ can be generated. Refer to Figure-26.
3.7.2.2
Phase Loss Detection
The phase loss detection detects if there is one or more phases’ voltage is less than the phase-loss threshold voltage.
The processing and handling is similar to sag detection, only the threshold is different. The threshold computation flow is
also similar. The typical threshold setting could be 10% Un or less.
If any phase line is detected as in phase-loss mode, that phase’s zero-crossing detection function (both voltage and cur-
rent) is disabled.
3.7.2.3
Over Voltage (OV) Detection
When any phase's absolute voltage sample instantaneous value goes beyond the over voltage threshold, the Over Voltage
status is asserted. The status is de-asserted when the voltage sample instantaneous value go back below the over voltage
threshold.
Change of the Over Voltage status can generate interrupt and flagged in the EMMState0 and EMMIntState0 registers.
3.7.2.4
Over Current (OI) Detection
When any phase's absolute current sample instantaneous value go beyond the over current threshold, the Over Current
status is asserted. The status is de-asserted when the current sample instantaneous value go back below the over current
threshold.
Change of the Over Current status can generate interrupt and flagged in the EMMState0 and EMMIntState0 registers.
M90E32AS [DATASHEET]
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19
3.7.3
FREQUENCY MONITORING RELATED STATUS AND EVENTS
The measured frequency is compared with two thresholds configured in the the FreqLoTh register and the FreqHiTh regis-
ter.
If the measured frequency goes beyond the range defined by the two thresholds, the FreqLoST bit (b11, EMMState1) and
FreqHiST bit (b15, EMMState1) will be asserted.
The interrupt status will be updated as well; and if enabled, interrupt signal can be asserted.
3.7.4
ZERO-CROSSING DETECTION
Zero-crossing detector detects the zero-crossing point of the fundamental component of voltage and current for each of the
3 phases. Refer to 6.5 Zero-Crossing Timing.
Zero-crossing signal can be independently configured and output. Refer to the definition of the ZXConfig register.
3.7.5
NEUTRAL LINE OVERCURRENT DETECTION
The neutral line rms current (calculated) I is checked with the threshold defined in the InWarnTh register. If the N Line
NC
current is greater than the threshold, the INOv0ST bit (b7, EMMState0) is set. IRQ0 is generated if the INOv0IntEN bit (b7,
EMMIntEn0) is set.
3.7.6
PHASE SEQUENCE ERROR DETECTION
The phase sequence is detected in two cases: 3P4W and 3P3W, which is defined by the 3P3W bit (b8, MMode0).
3P4W case:
Correct sequence: Voltage/current zero-crossing sequence: phase-A, phase-B and phase-C.
3P3W case:
Correct sequence: Voltage/current zero-crossing between phase-A and phase-C is greater than 180 degree.
If the above mentioned criteria are violated, it is assumed as a phase sequence error, the URevWnST bit (b9, EMMState0)
or the IRevWnST bit (b9, EMMState0) will be set.
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3.8
POWER MODE
The M90E32AS has four power modes. The power mode is solely defined by the PM1 and PM0 pins.
Table-2 Power Mode Mapping
PM1:PM0 Value
Power Mode
11
10
01
00
Normal (N mode)
Partial Measurement (M mode)
Detection (D mode)
Idle (I mode)
3.8.1
NORMAL MODE (N MODE)
In Normal mode, the default is that all function blocks are active except for current detector block. Refer to Figure-10.
The current detector can be enabled and calibrated in normal mode using control bits in DetectCtrl register.
OSCI
OSCO
PM1
PM0
Power Mode
Configuration
Crystal Oscillator
VDD18 Regulator
Power On Reset
Current Detector
CF1
CF2
CF3
CF4
RESET
Energy Metering
(Forward/Reverse
Active/Reactive/CF Generator)
CF Out
ADC-I1
ADC-I2
ADC-I3
WarnOut
IRQ0
IRQ1
I1P / I1N
I2P / I2N
I3P / I3N
Warn
Out
Flexible Piece-wise Non-linear
Compensation
DSP
IRQ
ZX0
ZX1
ZX2
Measure and Monitoring
(V/I/rms / SAG / Phase /
Frequency)
Zero
Crossing
ADC-V1
ADC-V2
ADC-V3
V1P / V1N
V2P / V2N
V3P / V3N
CS
Temperature Sensor
SCLK
SDO
SDI
Control Logic
SPI Interface
On-chip
Reference Voltage
Vref
Disabled
Figure-10 Block Diagram in Normal Mode
M90E32AS [DATASHEET]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
21
3.8.2
IDLE MODE (I MODE)
In Idle mode, all functions are shut off.
The analog blocks' power supply is powered but circuits are set into power-down mode, i.e, power supply applied but all
current paths are shut off. There is very low current since only very low device leakage could exist in this mode.
The digital I/Os' supply is powered.
In I/O and analog interface, the input signals from digital core (which is not powered) will be set to known state as described
in Table-3. The PM1 and PM0 pins which are controlled by external MCU are active and can configure the M90E32AS to
other modes.
OSCI
OSCO
PM1
PM0
Power Mode
Configuration
Crystal Oscillator
VDD18 Regulator
Power On Reset
Current Detector
CF1
CF2
CF3
CF4
RESET
Energy Metering
(Forward/Reverse
Active/Reactive/CF Generator)
CF Out
ADC-I1
ADC-I2
ADC-I3
WarnOut
IRQ0
IRQ1
I1P / I1N
I2P / I2N
I3P / I3N
Warn
Out
Flexible Piece-wise Non-linear
Compensation
DSP
IRQ
ZX0
ZX1
ZX2
Measure and Monitoring
(V/I/rms / SAG / Phase /
Frequency)
Zero
Crossing
ADC-V1
ADC-V2
ADC-V3
V1P / V1N
V2P / V2N
V3P / V3N
CS
Temperature Sensor
SCLK
SDO
SDI
Control Logic
SPI Interface
On-chip
Reference Voltage
Vref
Disabled
Figure-11 Block Diagram in Idle Mode
Please note that since the digital I/O is not shut off, the I/O circuit is active in the Idle mode. The application shall make sure
that valid logic levels are applied to the I/O.
Table-3 lists digital I/O and power pins’ states in Idle mode. It lists the requirements for inputs and the output level for out-
put.
Table-3 Digital I/O and Power Pin States in Idle Mode
Name
I/O type
Type
Pin State in Idle Mode
Input level shall be VDD33.
Reset
I
LVTTL
I/O set in input mode.
Input level shall be VDD33 or VSS.
CS
I
I
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
I/O set in input mode.
Input level shall be VDD33 or VSS.
SCLK
SDO
SDI
I/O set in input mode.
Input level shall be VDD33 or VSS.
O
I
I/O set in input mode.
Input level shall be VDD33 or VSS.
PM1
PM0
I
As defined in Table-2.
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Table-3 Digital I/O and Power Pin States in Idle Mode (Continued)
Name
I/O type
Type
Pin State in Idle Mode
Oscillator powered down.
OSCO stays at fixed (low) level.
OSCI
OSCO
I
O
OSC
ZX0
ZX1
ZX2
O
O
LVTTL
LVTTL
0
CF1
CF2
CF3
CF4
0
WarnOut
O
O
LVTTL
LVTTL
0
0
IRQ0
IRQ1
VDD18
DVDD
AVDD
Test
I
I
I
I
Power
Power
Power
Input
Regulated 1.8V: high impedance
Digital Power Supply: powered by system
Analog Power Supply: powered by system
Always tie to ground in system application
M90E32AS [DATASHEET]
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23
3.8.3
DETECTION MODE (D MODE)
In Detection mode, the current detector is active. The current detector compares whether any phase current exceeds the
configured threshold using low-power comparators.
When the current of one phase or multiple phases exceeds the configured threshold, the M90E32AS asserts the IRQ0 pin
to high and hold it until power mode change. The IRQ0 state is cleared when entering or exiting Detection mode.
When the current of all three current channels exceed the configured threshold, the M90E32AS asserts the IRQ1 pin to
high and hold it until power mode change. The IRQ1 state is cleared when entering or exiting Detection mode.
The threshold registers need to be programmed in Normal mode before entering Detection mode.
The digital I/O state is the same as that in Idle state (except for IRQ0/IRQ1 and PM1/PM0).
The M90E32AS has two comparators for detecting each phase’s positive and negative current. Each comparator’s thresh-
old can be set individually. The two comparators are both active by default, which called ‘double-side detection’. User also
can enable one comparator only to save power consumption, which called ‘single-side detection’.
Double-side detection has faster response and can detect ‘half-wave’ current. But it consumes nearly twice as much power
as single-side detection.
Comparators can be power-down by configuring the DetectCtrl register. The current detector can be enabled and calibrated
in normal mode using control bits in the DetectCtrl register.
OSCI
OSCO
PM1
PM0
Power Mode
Configuration
Crystal Oscillator
VDD18 Regulator
Power On Reset
Current Detector
CF1
CF2
CF3
CF4
RESET
Energy Metering
(Forward/Reverse
Active/Reactive/CF Generator)
CF Out
ADC-I1
ADC-I2
ADC-I3
WarnOut
IRQ0
IRQ1
I1P / I1N
I2P / I2N
I3P / I3N
Warn
Out
Flexible Piece-wise Non-linear
Compensation
DSP
IRQ
ZX0
ZX1
ZX2
Measure and Monitoring
(V/I/rms / SAG / Phase /
Frequency)
Zero
Crossing
ADC-V1
ADC-V2
ADC-V3
V1P / V1N
V2P / V2N
V3P / V3N
CS
Temperature Sensor
SCLK
SDO
SDI
Control Logic
SPI Interface
On-chip
Reference Voltage
Vref
Disabled
Figure-12 Block Diagram in Detection Mode
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3.8.4
PARTIAL MEASUREMENT MODE (M MODE)
In this mode, all the measurements are through the same hardware that does the measurement in the normal mode. To
save power, the energy accumulation block and a portion of the DSP computation code will not be running in this mode.
In this mode, There are configuration bits in the PMPwrCtrl register to get lower power if the application allows:
• Option to turn-off the three analog voltage channel if there is no need to measure voltage and power.
• Option to lower down the digital clock from 16.384Mhz to 8.192MHz
In Partial Measurement mode, CRC checking will be disabled. The interrupts will not be generated.
OSCI
OSCO
PM1
PM0
Power Mode
Configuration
Crystal Oscillator
VDD18 Regulator
Power On Reset
Current Detector
CF1
CF2
CF3
CF4
RESET
Energy Metering
(Forward/Reverse
Active/Reactive/CF Generator)
CF Out
ADC-I1
ADC-I2
ADC-I3
WarnOut
IRQ0
IRQ1
I1P / I1N
I2P / I2N
I3P / I3N
Warn
Out
Flexible Piece-wise Non-linear
Compensation
DSP
IRQ
ZX0
ZX1
ZX2
Measure and Monitoring
(V/I/rms / SAG / Phase /
Frequency)
Zero
Crossing
ADC-V1
ADC-V2
ADC-V3
V1P / V1N
V2P / V2N
V3P / V3N
CS
Temperature Sensor
SCLK
SDO
SDI
Control Logic
SPI Interface
On-chip
Reference Voltage
Vref
Disabled
Figure-13 Block Diagram in Partial Measurement mode
M90E32AS [DATASHEET]
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25
3.8.5
TRANSITION OF POWER MODES
The above power modes are controlled by the PM0 and PM1 pins. In application, the PM0 and PM1 pins are connected to
external MCU. The PM0 and PM1 pins have internal RC- filters.
Generally, the M90E32AS stays in Idle mode most of the time while outage. It enters Detection mode at a certain interval
(for example 5s) as controlled by the MCU. It informs the MCU if the current exceeds the configured threshold. The MCU
then commands the M90E32AS to enter Partial Measurement mode at a certain interval (e.g. 60s) to read related current.
After current reading, the M90E32AS gets back to the Idle mode.
The measured current may be used to count energy according to some metering model (like current RMS multiplying the
rated voltage to compute the power).
Any power mode transition goes through the Idle mode, as shown in Figure-14.
Normal Mode
Idle Mode
Partial
Measurement Mode
Detection Mode
Figure-14 Power Mode Transition
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3.9
EXTERNAL COMPONENT COMPENSATION
The calibrated channel gain and phase-delay offset could be tuned with respect to some reference parameter. This feature
is useful when external component is not ideal and allow low cost sensors used in the system.
There are three reference parameters:
•
•
•
Measured Current RMS (per phase)
Measured line frequency (all phase in common)
Measured temperature
There are two tuning parameters to compensate:
•
•
Channel gain compensation
Channel phase delay compensation
Following are the compensation correspondences:
•
Measured current RMS is per phase. It goes to Igain and Phi for each phase.
• This is to compensate the non-linearity of current sensors, like a Current-Transformer. Non-linearity can be gain-non-
linearity or phase nonlinearity. The gain nonlinearity is compensated by Igain compensation and phase nonlinearity
is compensated by phase compensation.
•
•
Frequency compensation only goes to Phi/Delay (all phases are the same).
Temperature compensation only goes to UGain (per phase).
Table-4 Compensation Related Registers
Parameter
Describtion
Registers
LogIrms
F0
Measured Current RMS
Nominal line frequency
Nominal temperature
LOGIrms0, LOGIrms1
F0
T0
T0
GainAIrms01, GainAIrms2, GainBIrms01, GainBIrms2,
GainCIrms01, GainCIrms2
GainIrms
PhiIrms
Gain compensation for Irms
Phase compensation for Irms
PhiAIrms01, PhiAIrms2, PhiBIrms01, PhiBIrms2, PhiCIrms01,
PhiCIrms2
UGainT
PhiF
Temperature compensation only goes to UGain
Frequency compensation only goes to Phi/Delay
UGainTAB, UGainTC
PhiFreqComp
M90E32AS [DATASHEET]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
27
3.9.1
GAIN BASED COMPENSATION
The channel gain can be tuned automatically according to measured temperature and current RMS.
Channel_Gain
Irms
GainIrms*(Log(
))
Irms_ref
= Gain0* 1+
+ GainIrms_offset
19
2
UGainT *(T -T0)
Channel_Gain_Voltage = UGain0 * 1+
20
2
Here
Log(x) = Log (x)*16, e.g.: Log(2) = 16, Log(16) = 64
2
•
•
•
•
•
•
•
Gain0 is the calibrated Gain at nominal condition,
GainIrms is the gain adjustment per Irms change (8 bit)
Irms_ref is the reference current RMS
GainIrms_offset is the offset for segment calibration
UGain0 is the calibrated Gain at nominal temperature
UGainT is the gain adjustment per temperature degree change,
T0 is the nominal temperature,
If (Irms > Irms0)
GainIrms = GainIrms0,
Irms_ref = Irms0,
GainIrms_offset = 0,
If (Irms1<Irms < Irms0)
GainIrms = GainIrms1,
Irms_ref = Irms0,
GainIrms_offset = 0,
If (Irms < Irms1)
GainIrms = GainIrms2,
Irms_ref = Irms1
Irms1
GainIrms1* (Log(
))
Irms0
GainIrms_offset =
219
Delta-Gain
Delta-Phi
Delta-Gain
Irms1
Irms0
Log(Irms)
Delta-Phi
GainIrms2
PhiIrms2
GainIrms0
PhiIrms0
GainIrms1
PhiIrms1
Figure-15 Segment Gain Compensation
28
M90E32AS [Datasheet]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
3.9.2
DELAY/PHASE BASED COMPENSATION
The Channel phase compensation delay can be tuned according to the measured frequency and current RMS.
Channel_Phi
Irms
PhiIrms* (Log(
))
PhiF* (F - F0)
512
Irms_ref
= Phi0 +
+
+ Phi_offset
256
•
•
•
•
•
•
Phi0 is the calibrated delay between the V/I channel (in terms of 2.048Mhz clock cycles)
PhiF is the delay change per frequency change
F0 is the nominal frequency,
PhiIrms is the delay change per current change
Phi_offset is the offset for segment calibration
Log(x)= Log (x)*16
2
If (Irms > Irms0)
PhiIrms = PhiIrms0, Irms_ref = Irms0,
Phi_offset=0
If (Irms1<Irms < Irms0)
PhiIrms= PhiIrms1, Irms_ref = Irms0,
Phi_offset=0
If (Irms < Irms1)
PhiIrms = PhiIrms2, Irms_ref = Irms1,
Irms1
PhiIrms1 * (Log(
))
Irms0
Phi_offset =
256
Implementation Note:
The channel_phi could be computed at the 8Khz rate. The computed channel_phi (before applied to the delay chain in the
decimator) shall be averaged and updated every 8192 8Khz-samples (about one update per second). This is to attenuate
the fluctuation generated in the computation when the current is small and avoid frequent updating of the delay, which is
assumed to be a fixed value in the decimator.
M90E32AS [DATASHEET]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
29
4
SPI INTERFACE
4.1
INTERFACE DESCRIPTION
Four pins are associated with the interface as below:
•
•
•
•
SDI – Data pin, input.
SDO – Data pin, output.
SCLK – Clock input pin.
CS – Chip select pin Input.
SPI Interface logic
(As slave)
Host controller in
master mode
MOSI
SDI
MOSI
MISO
SCK
MISO
SCK
CS
SDO
SCLK
CS
GPIO1
Figure-16 Slave Mode
4.2
SPI INTERFACE
The interface works in slave mode as shown in Figure-16.
4.2.1 SPI SLAVE INTERFACE FORMAT
In the SPI mode, data on SDI is shifted into the chip on the rising edge of SCLK while data on SDO is shifted out of the chip
on the falling edge of SCLK.
Refer to Figure-17 and Figure-18 below for the timing diagram.
Access type:
The first bit on SDI defines the access type as below:
Instruction
Instruction
Read
Description
read from registers
write to registers
Format
1
0
Write
Address:
Fixed 15-bit, following the access type bits. The lower 10-bit is decoded as address; the higher 5 bits are ‘Don't Care’.
Read/Write data:
Fixed as 16 bits.
Read Sequence:
30
M90E32AS [Datasheet]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
CS
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
27 28 29 30 31 32
23 24 25 26
SCLK
Register Address
X
X
X
X
X
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Don't care
SDI
16-bit data
High Impedance
D10 D9 D8
D5 D4
D0
D15 D14 D13 D12 D11
D7 D6
D3 D2 D1
SDO
Figure-17 Read Sequence
Write Sequence:
CS
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
27 28 29 30 31 32
SCLK
Register Address
16-bit data
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10
X
X
X
X
X
A9 A8
SDI
High Impedance
SDO
Figure-18 Write Sequence
4.2.2
RELIABILITY ENHANCEMENT FEATURE
The SPI read/write transaction is CS-low defined. Each transaction can only access one register.
Within each CS-low defined transaction:
Write: access occurs only when CS goes from low to high and there are exactly 32 SCLK cycles received during CS low
period.
Read: if SCLK>=16 (full address received), data is read out from internal registers and gets to the SDO pin; and the LastS-
PIData register is updated. The R/C registers can only be cleared after the LastSPIData register is updated.
M90E32AS [DATASHEET]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
31
5
REGISTER
5.1
REGISTER LIST
Table-5 Register List
Read/
Write
Type
Register
Address
Register Name
Functional Description
Comment
Page
Status and Special Register
MeterEn
ChannelMapI
ChannelMapU
SagPeakDetCfg
OVth
00H
01H
02H
05H
06H
R/W
R/W
R/W
R/W
R/W
Metering Enable
P 41
P 42
P 42
P 44
P 44
Current Channel Mapping Configuration
Voltage Channel Mapping Configuration
Sag and Peak Detector Period Configuration
Over Voltage Threshold
Configuration of ZX0/1/2 pins’
source
ZXConfig
SagTh
07H
08H
09H
R/W
R/W
R/W
Zero-Crossing Configuration
Voltage Sag Threshold
P 45
P 45
P 45
Similar to Voltage Sag Threshold
register
PhaseLossTh
Voltage Phase Losing Threshold
Neutral Current (Calculated) Warning Thresh-
old
InWarnTh
0AH
R/W
P 46
OIth
0BH
0CH
0DH
0EH
R/W
R/W
R/W
R/W
Over Current Threshold
P 46
P 46
P 46
P 47
FreqLoTh
FreqHiTh
PMPwrCtrl
Low Threshold for Frequency Detection
High Threshold for Frequency Detection
Partial Measurement Mode Power Control
Refer to 4.2.2 Reliability
nhancement Feature
E
0FH
IRQ0MergeCfg
R/W
IRQ0 Merge Configuration
P 47
Low Power Mode Register
DetectCtrl
DetectTh1
10H
11H
R/W
R/W
Current Detect Control
P 48
P 49
Channel 1 Current Threshold in Detection
Mode
Channel 2 Current Threshold in Detection
Mode
DetectTh2
DetectTh3
12H
13H
R/W
R/W
P 49
P 49
Channel 3 Current Threshold in Detection
Mode
IDCoffsetA
IDCoffsetB
IDCoffsetC
UDCoffsetA
UDCoffsetB
UDCoffsetC
14H
15H
16H
17H
18H
19H
R/W
R/W
R/W
R/W
R/W
R/W
Phase A Current DC offset
Phase B Current DC offset
P 50
P 50
P 50
P 50
P 50
P 51
Phase C Current DC offset
Voltage DC offset for Channel A
Voltage DC offset for Channel B
Voltage DC offset for Channel C
Voltage Gain Temperature Compensation for
Phase A/B
UGainTAB
1AH
R/W
P 51
Voltage Gain Temperature Compensation for
Phase C
UGainTC
PhiFreqComp
LOGIrms0
1BH
1CH
20H
R/W
R/W
R/W
P 51
P 51
P 51
Phase Compensation for Frequency
Current (Log Irms0) Configuration for Seg-
ment Compensation
Current (Log Irms1) Configuration for Seg-
ment Compensation
LOGIrms1
21H
R/W
P 51
32
M90E32AS [Datasheet]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
Table-5 Register List (Continued)
Read/
Register
Address
Write
Type
Register Name
Functional Description
Nominal Frequency
Comment
Page
P 52
P 52
F0
T0
22H
23H
R/W
R/W
Nominal Temperature
Phase A Phase Compensation for Current
Segment 0 and 1
PhiAIrms01
PhiAIrms2
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P 52
P 52
P 53
P 53
P 53
P 54
P 53
P 54
P 54
P 54
P 54
P 54
Phase A Phase Compensation for Current
Segment 2
Phase A Gain Compensation for Current Seg-
ment 0 and 1
GainAIrms01
GainAIrms2
PhiBIrms01
PhiBIrms2
Phase A Gain Compensation for Current Seg-
ment 2
Phase B Phase Compensation for Current
Segment 0 and 1
Phase B Phase Compensation for Current
Segment 2
Phase B Gain Compensation for Current Seg-
ment 0 and 1
GainBIrms01
GainBIrms2
PhiCIrms01
PhiCIrms2
Phase B Gain Compensation for Current Seg-
ment 2
Phase C Phase Compensation for Current
Segment 0 and 1
Phase C Phase Compensation for Current
Segment 2
Phase C Gain Compensation for Current Seg-
ment 0 and 1
GainCIrms01
GainCIrms2
Phase C Gain Compensation for Current Seg-
ment 2
Configuration Registers
High Word of PL_Constant
Low Word of PL_Constant
31H
32H
33H
34H
35H
36H
37H
PLconstH
PLconstL
MMode0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P 55
P 56
P 56
P 57
Metering Method Configuration
MMode1
PGA Gain Configuration
PStartTh
QStartTh
SStartTh
Active Startup Power Threshold
Reactive Startup Power Threshold
Apparent Startup Power Threshold
Refer to Table-6.
Startup Power Threshold for Any Phase
(Active Energy Accumulation)
38H
39H
3AH
PPhaseTh
QPhaseTh
SPhaseTh
R/W
R/W
R/W
Startup Power Threshold for Any Phase
(ReActive Energy Accumulation)
Startup Power Threshold for Any Phase
(Apparent Energy Accumulation)
M90E32AS [DATASHEET]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
33
Table-5 Register List (Continued)
Read/
Register
Address
Write
Type
Register Name
Functional Description
Calibration Registers
Comment
Page
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
PoffsetA
QoffsetA
PoffsetB
QoffsetB
PoffsetC
QoffsetC
PQGainA
PhiA
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Phase A Active Power offset
P 57
P 58
Phase A Reactive Power offset
Phase B Active Power offset
Phase B Reactive Power offset
Phase C Active Power offset
Phase C Reactive Power offset
Phase A Calibration Gain
Refer to Table-7.
P 58
P 58
Phase A Calibration Phase Angle
Phase B Calibration Gain
PQGainB
PhiB
Phase B Calibration Phase Angle
Phase C Calibration Gain
PQGainC
PhiC
Phase C Calibration Phase Angle
Fundamental/ Harmonic Energy Calibration Registers
PoffsetAF
PoffsetBF
PoffsetCF
PGainAF
PGainBF
PGainCF
51H
52H
53H
54H
55H
56H
R/W
Phase A Fundamental Active Power offset
Phase B Fundamental Active Power offset
Phase C Fundamental Active Power offset
Phase A Fundamental Calibration Gain
Phase B Fundamental Calibration Gain
Phase C Fundamental Calibration Gain
Measurement Calibration Registers
Phase A Voltage RMS Gain
R/W
R/W
R/W
R/W
R/W
Refer to Table-8.
UgainA
IgainA
61H
62H
63H
64H
65H
66H
67H
68H
69H
6AH
6BH
6CH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Phase A Current RMS Gain
UoffsetA
IoffsetA
UgainB
IgainB
Phase A Voltage RMS offset
Phase A Current RMS offset
Phase B Voltage RMS Gain
Phase B Current RMS Gain
Refer to Table-9.
UoffsetB
IoffsetB
UgainC
IgainC
Phase B Voltage RMS offset
Phase B Current RMS offset
Phase C Voltage RMS Gain
Phase C Current RMS Gain
UoffsetC
IoffsetC
Phase C Voltage RMS offset
Phase C Current RMS offset
34
M90E32AS [Datasheet]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
Table-5 Register List (Continued)
Read/
Register
Address
Write
Type
Register Name
Functional Description
EMM Status Registers
Comment
Page
70H
71H
72H
73H
74H
75H
76H
78H
79H
7AH
7FH
SoftReset
EMMState0
EMMState1
EMMIntState0
EMMIntState1
EMMIntEn0
EMMIntEn1
LastSPIData
CRCErrStatus
CRCDigest
R/W
R
Software Reset
P 59
P 60
P 61
P 62
P 63
P 64
P 65
P 65
P 66
P 66
P 66
EMM State 0
EMM State 1
R
R/W1C EMM Interrupt Status 0
R/W1C EMM Interrupt Status 1
R/W
R/W
R
EMM Interrupt Enable 0
EMM Interrupt Enable 1
Last Read/Write SPI Value
R
CRC Error Status
R/W
R/W
CRC Digest
CfgRegAccEn
Configure Register Access Enable
Energy Register
APenergyT
APenergyA
APenergyB
APenergyC
ANenergyT
ANenergyA
ANenergyB
ANenergyC
RPenergyT
RPenergyA
RPenergyB
RPenergyC
RNenergyT
RNenergyA
RNenergyB
RNenergyC
SAenergyT
SenergyA
80H
81H
82H
83H
84H
85H
86H
87H
88H
89H
8AH
8BH
8CH
8DH
8EH
8FH
90H
91H
92H
93H
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
Total Forward Active Energy
Phase A Forward Active Energy
Phase B Forward Active Energy
Phase C Forward Active Energy
Total Reverse Active Energy
Phase A Reverse Active Energy
Phase B Reverse Active Energy
Phase C Reverse Active Energy
Total Forward Reactive Energy
Phase A Forward Reactive Energy
Phase B Forward Reactive Energy
Phase C Forward Reactive Energy
Total Reverse Reactive Energy
Phase A Reverse Reactive Energy
Phase B Reverse Reactive Energy
Phase C Reverse Reactive Energy
Total (Arithmetic Sum) Apparent Energy
Phase A Apparent Energy
P 67
Refer to Table-11.
SenergyB
Phase B Apparent Energy
SenergyC
Phase C Apparent Energy
M90E32AS [DATASHEET]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
35
Table-5 Register List (Continued)
Read/
Register
Address
Write
Type
Register Name
Functional Description
Comment
Page
Fundamental / Harmonic Energy Register
Total Forward Active Fundamental Energy
Phase A Forward Active Fundamental Energy
Phase B Forward Active Fundamental Energy
Phase C Forward Active Fundamental Energy
Total Reverse Active Fundamental Energy
Phase A Reverse Active Fundamental Energy
Phase B Reverse Active Fundamental Energy
Phase C Reverse Active Fundamental Energy
Total Forward Active Harmonic Energy
APenergyTF
APenergyAF
APenergyBF
APenergyCF
ANenergyTF
ANenergyAF
ANenergyBF
ANenergyCF
APenergyTH
APenergyAH
APenergyBH
APenergyCH
ANenergyTH
ANenergyAH
ANenergyBH
ANenergyCH
A0H
A1H
A2H
A3H
A4H
A5H
A6H
A7H
A8H
A9H
AAH
ABH
ACH
ADH
AEH
AFH
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
P 68
Refer to Table-12.
Phase A Forward Active Harmonic Energy
Phase B Forward Active Harmonic Energy
Phase C Forward Active Harmonic Energy
Total Reverse Active Harmonic Energy
Phase A Reverse Active Harmonic Energy
Phase B Reverse Active Harmonic Energy
Phase C Reverse Active Harmonic Energy
36
M90E32AS [Datasheet]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
Table-5 Register List (Continued)
Read/
Register
Address
Write
Type
Register Name
Functional Description
Power and Power Factor Registers
Total (all-phase-sum) Active Power
Phase A Active Power
Comment
Page
PmeanT
PmeanA
PmeanB
PmeanC
QmeanT
QmeanA
QmeanB
QmeanC
SmeanT
SmeanA
SmeanB
SmeanC
PFmeanT
PFmeanA
PFmeanB
PFmeanC
B0H
B1H
B2H
B3H
B4H
B5H
B6H
B7H
B8H
B9H
BAH
BBH
BCH
BDH
BEH
BFH
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
P 69
Phase B Active Power
Phase C Active Power
Total (all-phase-sum) Reactive Power
Phase A Reactive Power
Phase B Reactive Power
Phase C Reactive Power
Total (Arithmetic Sum) Apparent Power
Phase A Apparent Power
Phase B Apparent Power
Phase C Apparent Power
Total Power Factor
Phase A Power Factor
Phase B Power Factor
Refer to Table-13.
Phase C Power Factor
Lower Word of Total (all-phase-sum) Active
Power
C0H
PmeanTLSB
R
C1H
C2H
C3H
PmeanALSB
PmeanBLSB
PmeanCLSB
R
R
R
Lower Word of Phase A Active Power
Lower Word of Phase B Active Power
Lower Word of Phase C Active Power
Lower Word of Total (all-phase-sum) Reactive
Power
C4H
QmeanTLSB
R
C5H
C6H
C7H
QmeanALSB
QmeanBLSB
QmeanCLSB
R
R
R
Lower Word of Phase A Reactive Power
Lower Word of Phase B Reactive Power
Lower Word of Phase C Reactive Power
Lower Word of Total (Arithmetic Sum) Appar-
ent Power
C8H
SAmeanTLSB
R
C9H
CAH
CBH
SmeanALSB
SmeanBLSB
SmeanCLSB
R
R
R
Lower Word of Phase A Apparent Power
Lower Word of Phase B Apparent Power
Lower Word of Phase C Apparent Power
Fundamental / Harmonic Power and Voltage / Current RMS Registers
PmeanTF
PmeanAF
PmeanBF
PmeanCF
PmeanTH
PmeanAH
PmeanBH
PmeanCH
UrmsA
D0H
D1H
D2H
D3H
D4H
D5H
D6H
D7H
D9H
DAH
DBH
R
R
R
R
R
R
R
R
R
R
R
Total Active Fundamental Power
Phase A Active Fundamental Power
Phase B Active Fundamental Power
Phase C Active Fundamental Power
Total Active Harmonic Power
Phase A Active Harmonic Power
Phase B Active Harmonic Power
Phase C Active Harmonic Power
Phase A Voltage RMS
Refer to Table-14.
P 70
UrmsB
Phase B Voltage RMS
UrmsC
Phase C Voltage RMS
M90E32AS [DATASHEET]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
37
Table-5 Register List (Continued)
Read/
Register
Address
Write
Type
Register Name
IrmsN
Functional Description
N Line Calculated Current RMS
Phase A Current RMS
Comment
Page
DCH
DDH
DEH
DFH
R
R
R
R
IrmsA
IrmsB
Phase B Current RMS
IrmsC
Phase C Current RMS
Lower Word of Total Active Fundamental
Power
E0H
E1H
E2H
PmeanTFLSB
PmeanAFLSB
PmeanBFLSB
R
R
R
Lower Word of Phase A Active Fundamental
Power
Lower Word of Phase B Active Fundamental
Power
Lower Word of Phase C Active Fundamental
Power
E3H
E4H
E5H
PmeanCFLSB
PmeanTHLSB
PmeanAHLSB
R
R
R
Lower Word of Total Active Harmonic Power
Lower Word of Phase A Active Harmonic
Power
Lower Word of Phase B Active Harmonic
Power
E6H
E7H
PmeanBHLSB
PmeanCHLSB
R
R
Lower Word of Phase C Active Harmonic
Power
E9H
EAH
EBH
EDH
EEH
EFH
UrmsALSB
UrmsBLSB
UrmsCLSB
IrmsALSB
IrmsBLSB
IrmsCLSB
R
R
R
R
R
R
Lower Word of Phase A Voltage RMS
Lower Word of Phase B Voltage RMS
Lower Word of Phase C Voltage RMS
Lower Word of Phase A Current RMS
Lower Word of Phase B Current RMS
Lower Word of Phase C Current RMS
Peak, Frequency, Angle and Temperature Registers
Channel A Voltage Peak
Channel B Voltage Peak
Channel C Voltage Peak
Channel A Current Peak
Channel B Current Peak
Channel C Current Peak
Frequency
F1H
F2H
F3H
F5H
F6H
F7H
F8H
F9H
FAH
FBH
FCH
FDH
FEH
FFH
UPeakA
UPeakB
UPeakC
IPeakA
IPeakB
IPeakC
Freq
R
R
R
R
R
R
R
R
R
R
R
R
R
R
P 71
P 71
Refer to Table-15.
PAngleA
PAngleB
PAngleC
Temp
Phase A Mean Phase Angle
Phase B Mean Phase Angle
Phase C Mean Phase Angle
Measured Temperature
UangleA
UangleB
UangleC
Phase A Voltage Phase Angle
Phase B Voltage Phase Angle
Phase C Voltage Phase Angle
38
M90E32AS [Datasheet]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
5.2
SPECIAL REGISTERS
5.2.1
CONFIGURATION REGISTERS CRC GENERATION
The registers between address ‘0H’ to ‘6FH’ are considered as user configuration registers. CRC-16 with the following
polynomial was used to compute the CRC digest:
16
12
5
Polynomial = x + x + x +1
The CRC computation rate is every 16 bit word per 125us. The result can be read from the CRC result register.
The device can automatically monitor the CRC changes versus a golden CRC which is latched after the first time the CRC
computation is done. The latching event is triggered by none "0x55AA" value written to the CfgRegAccEn register (which
means configuration done), followed by a new CRC result available event. Once golden CRC is latched, the CRC_CMP
signal is enabled. Subsequent CRC result will be compared with the latched CRC to generate the CRC error status. CRC
error status can be read, and if configured, can goes to WARN or IRQ0 pins to alert the MCU in the case of CRC error.
RegAccEn !=
0x55AA?
00H
01H
02H
03H
...
Y
6CH
6DH
6EH
6FH
CRC_CMP
AND
CRC Err
CRC engine
Error
User Read
CRC digest
(computed)
Compare
CRC digest
(Golden)
Figure-19 CRC Checking Diagram
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5.2.2
IRQ AND WARNOUT SIGNAL GENERATION
The interrupt generation scheme is consistent for all the interrupt sources. For any interrupt source, there is an interrupt
status register and an interrupt enable register. Interrupt status register latches the interrupt event and is always available
for polling. If the interrupt enable register is set, that interrupt can go to IRQ pin to notify the processor.
The interrupt status register is write-1-to-clear. It captures the interrupt event which is usually an internal state change. The
(real time) internal state for that event is also available for read at any time.
The following diagram illustrates how the status bits, enable bits and IRQ/ WarnOut pins work together.
Internal Err
WarnOut
CfgCRC Err
AND
WarnIrqEn
Reg
Change
event gen
Int Status
Reg
State 1
State 2
State Reg
AND
Int En Reg
Change
event gen
Int Status
Reg
State Reg
State Reg
Status Reg
AND
AND
AND
IRQ0/1
Int En Reg
State 3
Change
event gen
Int Status
Reg
Int En Reg
Status 4
Change
event gen
Int Status
Reg
Int En Reg
Figure-20 IRQ and WarnOut Generation
There are two interrupt output pins: IRQ0 and IRQ1.
The IRQ 0 is associated with interrupt sources defined in EMMState0 register.
The IRQ 1 is associated with interrupt sources defined in EMMState1 register.
If configured, IRQ 1 state can be ORed together with IRQ0 state and output to IRQ0, in that case MCU need only process
one IRQ pin. It is up to system designer to trade off between conveniences of locating interrupt source and saving GPIO
pins.
The Warn pin will be asserted when there is a configuration register CRC check error. The Warn signal can be merged to
IRQ0 if configured.
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MeterEn
Metering Enable
Address: 00H
Type: Read/Write
Default Value: 00H
Bit
Name
MeterEn[7:0]
Description
Metering is enabled when any bit in this register is set.
7:0
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ChannelMapI
Current Channel Mapping Configuration
Address: 01H
Type: Read/Write
Default Value: 0210H
Bit
Name
Description
15:11
-
Reserved.
ADC Input source for phase C current channel
Code
000
001
010
011
100
101
110
111
ADC Input Source
I0
I1
I2
10:8
IC_SRC
Fixed-0
U0
U1
U2
Fixed-0
7
-
Reserved.
ADC Input source for phase B current channel
Code
000
001
010
011
100
101
110
111
ADC Input Source
I0
I1
I2
6:4
IB_SRC
Fixed-0
U0
U1
U2
Fixed-0
3
-
Reserved.
ADC Input source for phase A current channel
Code
000
001
010
011
100
101
110
111
ADC Input Source
I0
I1
I2
2:0
IA_SRC
Fixed-0
U0
U1
U2
Fixed-0
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ChannelMapU
Voltage Channel Mapping Configuration
Address: 02H
Type: Read/Write
Default Value: 0654H
Bit
Name
Description
-
15:11
Reserved.
ADC Input source for phase C voltage channel
Code
000
001
010
011
100
101
110
111
ADC Input Source
I0
I1
I2
10:8
UC_SRC
Fixed-0
U0
U1
U2
Fixed-0
7
-
Reserved.
ADC Input source for phase B voltage channel
Code
000
001
010
011
100
101
110
111
ADC Input Source
I0
I1
I2
6:4
UB_SRC
Fixed-0
U0
U1
U2
Fixed-0
3
-
Reserved.
ADC Input source for phase A voltage channel
Code
000
001
010
011
100
101
110
111
ADC Input Source
I0
I1
I2
2:0
UA_SRC
Fixed-0
U0
U1
U2
Fixed-0
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SagPeakDetCfg
Sag and Peak Detector Period Configuration
Address: 05H
Type: Read/Write
Default Value: 143FH
Bit
Name
Description
PeakDet_peri
od
15:8
Period in which the peak detector detects the U/I peak. Unit is ms.
Period in which the phase voltage needs to stay below the SagTh before to assert the Sag status. Unit is
7:0
Sag_Period ms.
The Phase Loss detector also uses this parameter in detecting Phase Loss.
OVth
Over Voltage Threshold
Address: 06H
Type: Read/Write
Default Value: C000H
Bit
Name
Description
Over Voltage threshold.
0xFFFF maps to ADC output full-scale peak.
15:0
OVth
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5.2.3
SPECIAL CONFIGURATION REGISTERS
ZXConfig
Zero-Crossing Configuration
Address: 07H
Type: Read/Write
Default Value: 0001H
Bit
Name
Description
15:13
12:10
ZX2Src[2:0] These bits select the signal source for the ZX2, ZX1 or ZX0 pins.
ZX1Src[2:0]
Code
011
000
001
010
111
Source
Fixed-0
Ua
Ub
Uc
9:7
ZX0Src[2:0]
Fixed-0
Ia
100
101
110
Ib
Ic
6:5
4:3
ZX2Con[1:0] These bits configure zero-crossing type for the ZX2, ZX1 and ZX0 pins.
ZX1Con[1:0]
Code
00
Zero-Crossing Configuration
Positive Zero-crossing
Negative Zero-crossing
All Zero-crossing
01
2:1
0
ZX0Con[1:0]
ZXdis
10
No Zero-crossing Output
11
This bit determines whether to disable the ZX signals:
0: enable
1: disable all the ZX signals to ‘0’ (default).
SagTh
Voltage Sag Threshold
Address: 08H
Type: Read/Write
Default Value: 1000H
Bit
Name
Description
Voltage sag threshold level.
0xFFFF map to ADC output full-scale peak.
15:0
SagTh
PhaseLossTh
Voltage Phase Losing Threshold
Address: 09H
Type: Read/Write
Default Value: 0400H
Bit
Name
Description
PhaseLoss threshold level
0xFFFF map to ADC output full-scale peak.
15:0
PhaseLossTh
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InWarnTh
Neutral Current (Calculated) Warning Threshold
Address: 0AH
Type: Read/Write
Default Value: FFFFH
Bit
Name
Description
Neutral current (calculated) warning threshold.
Threshold for calculated (Ia + Ib +Ic) N line rms current. Unsigned 16 bit, unit 1mA.
If N line rms current is greater than the threshold, the INOv0ST bit (b7, EMMState0) bit is asserted if
enabled. Refer to 3.7.5 Neutral Line Overcurrent Detection.
15:0
INWarnTh0
OIth
Over Current Threshold
Address: 0BH
Type: Read/Write
Default Value: C000H
Bit
Name
Description
Over Current threshold.
0xFFFF maps to ADC output full-scale peak.
15:0
OIth
FreqLoTh
Low Threshold for Frequency Detection
Address: 0CH
Type: Read/Write
Default Value: 1324H
Bit
Name
Description
15:0
FreqLoTh Low threshold for frequency detection.
FreqHiTh
High Threshold for Frequency Detection
Address: 0DH
Type: Read/Write
Default Value: 13ECH
Bit
Name
Description
15:0
FreqHiTh
High threshold for frequency detection.
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PMPwrCtrl
Partial Measurement Mode Power Control
Address: 0EH
Type: Read/Write
Default Value: 010FH
Bit
Name
Description
15:9
-
Reserved.
In Partial Measurement Mode the V0/V1/V2 analog channel can be powered off to save power
PMPwrDown- 0: Power on
8
Vch
1: Power off
This feature can be used when voltage measurement is not required in partial mode.
Power off the clock of analog control block to save power.
0: Power on
1: Power off
ACTRL_CLK_
GATE
3
2
1
Power off the clock of DSP register to save power.
0: Power on
1: Power off
DSP_CLK_G
ATE
Power off the metering and measuring block to save power.
0: Power on
1: Power off
MTMS_CLK_
GATE
In Partial Measurement Mode the main clock can be reduced to 8.192MHz to save power.
0: 16.384MHz
1: 8.192MHz
0
PMClkLow
In this low rate mode, the SPI interface only support half the access rate at normal mode.
IRQ0MergeCfg
IRQ0 Merge Configuration
Address: 0FH
Type: Read/Write
Default Value: 0000H
Bit
Name
Description
15:2
-
Reserved.
The WARN state can be ORed to IRQ0 output
1
0
WARN_OR 0: normal
1: ORed
The IRQ1 state can be ORed to IRQ0 output
IRQ1_OR 0: normal
1: ORed
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5.3
LOW-POWER MODES REGISTERS
5.3.1
DETECTION MODE REGISTERS
Current Detection register latching scheme is:
When any of the 4 current detection registers (0x10 - 0x13) were programmed, all the 4 current detection registers (includ-
ing the registers that not being programmed) will be automatically latched into the current detector's internal configuration
latches at the same time. Those latched configuration values are not subject to digital reset signals and will be kept in all
the 4 power modes. The power up value of those latches is not deterministic, so user needs to program the current detec-
tion registers to update.
Current detector
register Write
update
Current Detector block
latch
registers
0x10
0x11
0x12
0x13
latch
latch
latch
Figure-21 Current Detection Register Latching Scheme
DetectCtrl
Current Detect Control
Address: 10H
Type: Read/Write
Default Value: xxxxH
Bit
Name
Description
Must be written ‘3’.
15:7
-
Detector calibration in Normal mode is enabled if this bit is set. The default written value is ‘0’.
6
DetCalEn If set, current detectors are enabled and IRQ0/1 are assigned to current detector outputs as if in Detect
mode. The current detector can be calibrated.
Detector power-down, active high:
[5:3]: Power-down for negative detector of channel 3/2/1;
[2:0]: Power-down for positive detector of channel 3/2/1.
5:0
DetectCtrl
The default written value is ‘0’.
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DetectTh1
Channel 1 Current Threshold in Detection Mode
Address: 11H
Type: Read/Write
Default Value: 0000H
Bit
Name
Description
Channel 1 current negative detector calculation code.
Code mapping:
15:8
CalCodeN 8'b0000-0000, Vc = -1.2mV = --0.85mVrms (Vc is the threshold of low power computation)
8'b1111-1111, Vc = 9mV = 6.35mVrms
DAC typical resolution is [9- (-1.2)]/256 = 40μV = 28μVrms
Channel 1 current positive detector calculation code.
Code mapping:
7:0
CalCodeP 8'b0000-0000, Vc = -1.2mV = --0.85mVrms (Vc is the threshold of low power computation)
8'b1111-1111, Vc = 9mV = 6.35mVrms
DAC typical resolution is [9- (-1.2)]/256 = 40μV = 28μVrms
DetectTh2
Channel 2 Current Threshold in Detection Mode
Address: 12H
Type: Read/Write
Default Value: 0000H
Bit
Name
Description
Channel 2 current negative detector calculation code.
Code mapping:
15:8
CalCodeN 8'b0000-0000, Vc = -1.2mV = --0.85mVrms (Vc is the threshold of low power computation)
8'b1111-1111, Vc = 9mV = 6.35mVrms
DAC typical resolution is [9- (-1.2)]/256 = 40μV = 28μVrms
Channel 2 current positive detector calculation code.
Code mapping:
7:0
CalCodeP 8'b0000-0000, Vc = -1.2mV = --0.85mVrms (Vc is the threshold of low power computation)
8'b1111-1111, Vc = 9mV = 6.35mVrms
DAC typical resolution is [9- (-1.2)]/256 = 40μV = 28μVrms
DetectTh3
Channel 3 Current Threshold in Detection Mode
Address: 13H
Type: Read/Write
Default Value: 0000H
Bit
Name
Description
Channel 3 current negative detector calculation code.
Code mapping:
15:8
CalCodeN 8'b0000-0000, Vc = -1.2mV = --0.85mVrms (Vc is the threshold of low power computation)
8'b1111-1111, Vc = 9mV = 6.35mVrms
DAC typical resolution is [9- (-1.2)]/256 = 40μV = 28μVrms
Channel 3 current positive detector calculation code.
8'b0000-0000, Vc = -1.2mV = --0.85mVrms (Vc is the threshold of low power computation)
8'b1111-1111, Vc = 9mV = 6.35mVrms
7:0
CalCodeP
DAC typical resolution is [9- (-1.2)]/256 = 40μV = 28μVrms
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5.3.2
PARTIAL MEASUREMENT MODE REGISTERS
IDCoffsetA
Phase A Current DC offset
Address: 14H
Type: Read/Write
Default Value: 0000H
Bit
Name
Description
15:0
IDCoffsetA Phase A current DC offset in decimator, signed with complement format.
IDCoffsetB
Phase B Current DC offset
Address: 15H
Type: Read/Write
Default Value: 0000H
Bit
Name
Description
15:0
IDCoffsetB Phase B current DC offset in decimator, signed with complement format.
IDCoffsetC
Phase C Current DC offset
Address: 16H
Type: Read/Write
Default Value: 0000H
Bit
Name
Description
15:0
IDCoffsetC Phase C current DC offset in decimator, signed with complement format.
UDCoffsetA
Voltage DC offset for Channel A
Address: 17H
Type: Read/Write
Default Value: 0000H
Bit
Name
Description
15:0
UDCoffsetA Phase A voltage DC offset in decimator, signed with complement format.
UDCoffsetB
Voltage DC offset for Channel B
Address: 18H
Type: Read/Write
Default Value: 0000H
Bit
Name
Description
15:0
UDCoffsetB Phase B voltage DC offset in decimator, signed with complement format.
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UDCoffsetC
Voltage DC offset for Channel C
Address: 19H
Type: Read/Write
Default Value: 0000H
Bit
Name
Description
15:0
UDCoffsetC Phase C voltage DC offset in decimator, signed with complement format.
UGainTAB
Voltage Gain Temperature Compensation for Phase A/B
Address: 1AH
Type: Read/Write
Default Value: 0000H
Bit
15:8
7:0
Name
Description
Voltage gain temperature compensation for phase B.
Voltage gain temperature compensation for phase A.
UGainTB
UGainTA
UGainTC
Voltage Gain Temperature Compensation for Phase C
Address:1BH
Type: Read/Write
Default Value: 0000H
Bit
15:8
7:0
Name
-
Description
Reserved.
Voltage gain temperature compensation for phase C.
UGainTC
PhiFreqComp
Phase Compensation for Frequency
Address: 1CH
Type: Read/Write
Default Value: 0000H
Bit
15:8
7:0
Name
-
Description
Reserved.
PhiF
Phase compensation for frequency.
LOGIrms0
Current (Log Irms0) Configuration for Segment Compensation
Address: 20H
Type: Read/Write
Default Value: 0000H
Bit
15:8
7:0
Name
-
Description
Reserved.
= log2(Irms0), Irms0 is the nominal RMS current at calibration.
LogIrms0
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LOGIrms1
Current (Log Irms1) Configuration for Segment Compensation
Address: 21H
Type: Read/Write
Default Value: 0000H
Bit
15:8
7:0
Name
-
Description
Reserved.
LogIrms1
= log2(Irms1), Irms1 is the nominal RMS current at calibration.
F0
Nominal Frequency
Address: 22H
Type: Read/Write
Default Value: 5000
Bit
Name
F0
Description
Nominal frequency.
For example, 5000 corresponds to 50.00Hz.
15:0
T0
Nominal Temperature
Address: 23H
Type: Read/Write
Default Value: 25
Bit
15:8
7:0
Name
Description
-
Reserved.
T0
Signed, Nominal temperature in degree C.
PhiAIrms01
Phase A Phase Compensation for Current Segment 0 and 1
Address: 24H
Type: Read/Write
Default Value: 0000H
Bit
Name
Description
Phase compensation for current segment 1(Irms1<Irms < Irms0). Refer to 3.9.2 Delay/Phase Based
Compensation.
15:8
PhiIrms1
Phase compensation for current segment 0 (Irms > Irms0). Refer to 3.9.2 Delay/Phase Based Compen-
sation.
7:0
PhiIrms0
PhiAIrms2
Phase A Phase Compensation for Current Segment 2
Address: 25H
Type: Read/Write
Default Value: 0000H
Bit
Name
Description
15:8
-
Reserved.
Phase compensation for current segment 2 (Irms < Irms1). Refer to 3.9.2 Delay/Phase Based Compen-
sation.
7:0
PhiIrms2
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GainAIrms01
Phase A Gain Compensation for Current Segment 0 and 1
Address: 26H
Type: Read/Write
Default Value: 0000H
Bit
15:8
7:0
Name
Description
Gain compensation for current segment 1 (Irms1<Irms < Irms0). Refer to 3.9.1 Gain Based Compensa-
tion.
GainIrms1
GainIrms0 Gain compensation for current segment 0 (Irms > Irms0). Refer to 3.9.1 Gain Based Compensation.
GainAIrms2
Phase A Gain Compensation for Current Segment 2
Address: 27H
Type: Read/Write
Default Value: 0000H
Bit
15:8
7:0
Name
Description
-
Reserved.
GainIrms2 Gain compensation for current segment 2 (Irms < Irms1). Refer to 3.9.1 Gain Based Compensation.
PhiBIrms01
Phase B Phase Compensation for Current Segment 0 and 1
Address: 28H
Type: Read/Write
Default Value: 0000H
Bit
Name
Description
Phase compensation for current segment 1 (Irms1<Irms < Irms0). Refer to 3.9.2 Delay/Phase Based
Compensation.
15:8
PhiIrms1
Phase compensation for current segment 0 (Irms > Irms0). Refer to 3.9.2 Delay/Phase Based Compen-
sation.
7:0
PhiIrms0
PhiBIrms2
Phase B Phase Compensation for Current Segment 2
Address: 29H
Type: Read/Write
Default Value: 0000H
Bit
Name
Description
15:8
-
Reserved.
Phase compensation for current segment 2 (Irms < Irms1). Refer to 3.9.2 Delay/Phase Based Compen-
sation.
7:0
PhiIrms2
GainBIrms01
Phase B Gain Compensation for Current Segment 0 and 1
Address: 2AH
Type: Read/Write
Default Value: 0000H
Bit
15:8
7:0
Name
Description
Gain compensation for current segment 1 (Irms1<Irms < Irms0). Refer to 3.9.1 Gain Based Compensa-
tion.
GainIrms1
GainIrms0 Gain compensation for current segment 0 (Irms > Irms0). Refer to 3.9.1 Gain Based Compensation.
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GainBIrms2
Phase B Gain Compensation for Current Segment 2
Address: 2BH
Type: Read/Write
Default Value: 0000H
Bit
15:8
7:0
Name
Description
-
Reserved.
GainIrms2 Gain compensation for current segment 2 (Irms < Irms1). Refer to 3.9.1 Gain Based Compensation.
PhiCIrms01
Phase C Phase Compensation for Current Segment 0 and 1
Address: 2CH
Type: Read/Write
Default Value: 0000H
Bit
Name
Description
Phase compensation for current segment 1 (Irms1<Irms < Irms0). Refer to 3.9.2 Delay/Phase Based
Compensation.
15:8
PhiIrms1
Phase compensation for current segment 0 (Irms > Irms0). Refer to 3.9.2 Delay/Phase Based Compen-
sation.
7:0
PhiIrms0
PhiCIrms2
Phase C Phase Compensation for Current Segment 2
Address: 2DH
Type: Read/Write
Default Value: 0000H
Bit
Name
Description
15:8
-
Reserved.
Phase compensation for current segment 2 (Irms < Irms1). Refer to 3.9.2 Delay/Phase Based Compen-
sation.
7:0
PhiIrms2
GainCIrms01
Phase C Gain Compensation for Current Segment 0 and 1
Address: 2EH
Type: Read/Write
Default Value: 0000H
Bit
15:8
7:0
Name
Description
Gain compensation for current segment 1 (Irms1<Irms < Irms0). Refer to 3.9.1 Gain Based Compensa-
tion.
GainIrms1
GainIrms0 Gain compensation for current segment 0 (Irms > Irms0). Refer to 3.9.1 Gain Based Compensation.
GainCIrms2
Phase C Gain Compensation for Current Segment 2
Address: 2FH
Type: Read/Write
Default Value: 0000H
Bit
15:8
7:0
Name
Description
-
Reserved.
GainIrms2 Gain compensation for current segment 2 (Irms < Irms1). Refer to 3.9.1 Gain Based Compensation.
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5.4
CONFIGURATION AND CALIBRATION REGISTERS
5.4.1
CONFIGURATION REGISTERS
Table-6 Configuration Registers
Register
Read/Write
Type
Address
Register Name
Functional Description
Configuration Registers
Power-on Value and Comments
31H
32H
PLconstH
PLconstL
R/W
R/W
High Word of PL_Constant
Low Word of PL_Constant
0861H
C468H
HPF/Integrator On/Off, CF and all-phase
energy computation configuration
33H
34H
MMode0
MMode1
R/W
R/W
0087H
Pga Gain Configuration
0000H
0000H.
35H
36H
37H
PStartTh
QStartTh
SStartTh
R/W
R/W
R/W
Active Startup Power Threshold.
16 bit unsigned integer, Unit:
0.00032 Watt
0000H
Reactive Startup Power Threshold.
Apparent Startup Power Threshold.
16 bit unsigned integer, Unit:
0.00032 var
0000H
16 bit unsigned integer, Unit:
0.00032 VA
Startup power threshold (for |P|+|Q| of a
phase) for any phase participating Active E
nergy Accumulation. Common for phase A/
B/C.
0000H
16 bit unsigned integer,
Unit: 0.00032 Watt/var
38H
39H
PPhaseTh
QPhaseTh
SPhaseTh
R/W
R/W
RW
Startup power threshold (for |P|+|Q| of a
phase) for any phase participating ReAc-
tive Energy Accumulation. Common for
phase A/B/C.
0000H
16bit unsigned integer,
Unit: 0.00032 Watt/var
Startup power threshold (for |P|+|Q| of a
phase) for any phase participating Appar-
ent Energy Accumulation. Common for
phase A/B/C.
0000H
16 bit unsigned integer,
Unit: 0.00032 Watt/var
3AH
PLconstH
High Word of PL_Constant
Address: 31H
Type: Read/Write
Default Value: 0861H
Bit
Name
Description
The PLconstH[15:0] and PLconstL[15:0] bits are high word and low word of PL_Constant respectively.
PL_Constant is a constant which is proportional to the sampling ratios of voltage and current, and
inversely proportional to the Meter Constant. PL_Constant is a threshold for energy calculated inside the
chip, i.e., energy larger than PL_Constant will be accumulated as 0.01CFx in the corresponding energy
registers and then output on CFx if one CF reaches.
PLcon-
stH[15:0]
15:0
It is suggested to set PL_constant as a multiple of 4 so as to double or redouble Meter Constant in low
current state to save verification time.
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PLconstL
Low Word of PL_Constant
Address: 32H
Type: Read/Write
Default Value: C468H
Bit
Name
Description
PLcon-
stL[15:0]
The PLconstH[15:0] and PLconstL[15:0] bits are high word and low word of PL_Constant respectively.
It is suggested to set PL_constant as a multiple of 4.
15:0
MMode0
Metering Method Configuration
Address: 33H
Type: Read/Write
Default Value: 0087H
Bit
Name
Description
15-13
-
Reserved.
Current Grid operating line frequency.
12
11
10
9
Freq60Hz 0: 50Hz (default)
1: 60Hz
HPFoff
didtEn
-
Disable HPF in the signal processing path.
Enable Integrator for didt current sensor.
0: disable (default)
1: enable
Reserved.
This bit defines the voltage/current phase sequence detection mode:
0: 3P4W (default)
8
3P3W
1: 3P3W (Ua is Uab, Uc is Ucb, Ub is not used)
CF2 pin source:
7
CF2varh
-
0: apparent energy
1: reactive energy (default)
6-5
Reserved.
These bits configure the calculation method of total (all-phase-sum) reactive/active energy and power:
0: Arithmetic sum: (default)
ET=EA*EnPA+ EB*EnPB+ EC*EnPC
PT= PA*EnPA+ PB*EnPB+ PC*EnPC
1: Absolute sum:
ET=|EA|*EnPA+ |EB|*EnPB+ |EC|*EnPC
PT=|PA|*EnPA+ |PB|*EnPB+ |PC|*EnPC
Note: ET is the total (all-phase-sum) energy, EA/EB/EC are the signed phase A/B/C energy respectively.
Reverse energy is negative. PT is the total (all-phase-sum) power, PA/PB/PC are the signed phase A/B/C
power respectively. Reverse power is negative.
4
3
ABSEnQ
ABSEnP
2
1
0
EnPA
EnPB
EnPC
These bits configure whether Phase A/B/C are counted into the all-phase sum energy/power (P/Q/S).
1: Corresponding Phase A/B/C to be counted into the all-phase sum energy/power (P/Q/S) (default)
0: Corresponding Phase A/B/C not counted into the all-phase sum energy/power (P/Q/S)
56
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MMode1
PGA Gain Configuration
Address: 34H
Type: Read/Write
Default Value: 0000H
Bit
Name
Description
15-6
-
Reserved.
PGA gain for all ADC channels.
Mapping:
[5:4]: I3
[3:2]: I2
[1:0]: I1
5-0
PGA_GAIN
Encoding:
00: 1X (default)
01: 2X
10: 4X
11: N/A
5.4.2
ENERGY CALIBRATION REGISTERS
Table-7 Calibration Registers
Register
Read/Write
Type
Address
Register Name
Functional Description
Power-on Value
Calibration Registers
41H
42H
43H
44H
45H
46H
PoffsetA
QoffsetA
PoffsetB
QoffsetB
PoffsetC
QoffsetC
R/W
R/W
R/W
R/W
R/W
R/W
Phase A Active Power Offset
Phase A Reactive Power Offset
Phase B Active Power Offset
Phase B Reactive Power Offset
Phase C Active Power Offset
Phase C Reactive Power Offset
0000H
0000H
0000H
0000H
0000H
0000H
Phase A Active/reactive Energy Cali-
bration Gain
47H
48H
49H
4AH
4BH
4CH
PQGainA
PhiA
R/W
R/W
R/W
R/W
R/W
R/W
0000H
0000H
0000H
0000H
0000H
0000H
Phase A Calibration Phase Angle
Phase B Active/reactive Energy Cali-
bration Gain
PQGainB
PhiB
Phase B Calibration Phase Angle
Phase C Active/reactive Energy Cali-
bration Gain
PQGainC
PhiC
Phase C Calibration Phase Angle
PoffsetA
Phase A Active Power offset
Address: 41H
Type: Read/Write
Default Value: 0000H
Bit
Name
Description
15-0
offset
Phase A active power offset, signed with complement format.
M90E32AS [DATASHEET]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
57
QoffsetA
Phase A Reactive Power offset
Address: 42H
Type: Read/Write
Default Value: 0000H
Bit
Name
Description
15-0
offset
Phase A reactive power offset, signed with complement format.
PQGainA
Phase A Active/Reactive Energy Calibration Gain
Address: 47H
Type: Read/Write
Default Value: 0000H
Bit
Name
Description
Phase A energy gain, signed with complement format.
15-0
Gain
PhiA
Phase A Calibration Phase Angle
Address: 48H
Type: Read/Write
Default Value: 0000H
Bit
15
Name
DelayV
-
Description
0: Delay Cycles are applied to current channel. (default)
1: Delay Cycles are applied to voltage channel.
14:8
7:0
Reserved.
Number of delay cycles calculated in phase compensation.
Unit is 2.048MHz cycle. It is an unsigned 8 bit integer.
DelayCycles
5.4.3
FUNDAMENTAL/HARMONIC ENERGY CALIBRATION REGISTERS
Table-8 Fundamental/Harmonic Energy Calibration Registers
Register
Address
Read/Write
Type
Register Name
Functional Description
Power-on Value
Phase A Fundamental Active Power
offset
51H
52H
53H
54H
55H
56H
PoffsetAF
R/W
R/W
R/W
R/W
R/W
R/W
0000H
Phase B Fundamental Active Power
offset
PoffsetBF
PoffsetCF
PGainAF
PGainBF
PGainCF
0000H
0000H
0000H
0000H
0000H
Phase C Fundamental Active Power
offset
Phase A Fundamental Calibration
Gain
Phase B Fundamental Calibration
Gain
Phase C Fundamental Calibration
Gain
58
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5.4.4
MEASUREMENT CALIBRATION
Table-9 Measurement Calibration Registers
Register
Address
Read/Write
Type
Register Name
UgainA
Functional Description
Phase A Voltage RMS Gain
Phase A Current RMS Gain
Phase A Voltage RMS offset
Phase A Current RMS offset
Phase B Voltage RMS Gain
Phase B Current RMS Gain
Phase B Voltage RMS offset
Phase B Current RMS offset
Phase C Voltage RMS Gain
Phase C Current RMS Gain
Phase C Voltage RMS offset
Phase C Current RMS offset
Power-on Value
8000H
61H
62H
63H
64H
65H
66H
67H
68H
69H
6AH
6BH
6CH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IgainA
8000H
UoffsetA
IoffsetA
UgainB
0000H
0000H
8000H
IgainB
8000H
UoffsetB
IoffsetB
UgainC
IgainC
0000H
0000H
8000H
8000H
UoffsetC
IoffsetC
0000H
0000H
5.4.5
EMM STATUS
Table-10 EMM Status Registers
Register
Read/Write
Type
Address
Register Name
Functional Description
Software Reset
Power-on Value
70H
SoftReset
W
R
EMM State 0
71H
EMMState0
EMMState1
EMMIntState0
EMMIntState1
EMMIntEn0
EMMIntEn1
LastSPIData
CRCErrStatus
CRCDigest
EMM State 1
72H
R
EMM Interrupt Status 0
EMM Interrupt Status 1
EMM Interrupt Enable 0
EMM Interrupt Enable 1
Last Read/Write SPI Value
CRC Error Status
73H
R/W1C
R/W1C
R/W
R/W
R/W1C
R
74H
75H
76H
78H
79H
CRC Digest
7AH
7FH
R/W
R/W
CfgRegAccEn
Configure Register Access Enable
SoftReset
Software Reset
Address: 70H
Type: Write
Default Value: 0000H
Bit
Name
Description
SoftRe-
set[15:0]
Software reset register. The M90E32AS resets if 789AH is written to this register. The reset domain is the
same as the RESET pin or Power On Reset. Reading this register always return 0.
15:0
M90E32AS [DATASHEET]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
59
EMMState0
EMM State 0
Address: 71H
Type: Read
Default Value: 0000H
Bit
15
14
13
12
11
10
9
Name
Description
OIPhaseAST
OIPhaseBST
OIPhaseCST
OVPhaseAST
OVPhaseBST
OVPhaseCST
URevWnST
Set to 1: if there is over current on phase A
Set to 1: if there is over current on phase B
Set to 1: if there is over current on phase C
Set to 1: if there is over voltage on phase A
Set to 1: if there is over voltage on phase B
Set to 1: if there is over voltage on phase C
Voltage Phase Sequence Error status
8
IRevWnST
Current Phase Sequence Error status
When the calculated N line current is greater than the threshold set by the INWarnTh register, this bit is
set.
7
INOv0ST
6
5
4
TQNoloadST
TPNoloadST
TASNoloadST
All phase sum reactive power no-load condition status
All phase sum active power no-load condition status
All phase arithmetic sum apparent power no-load condition status
Energy for CF1 Forward/Reverse status:
3
2
1
0
CF1RevST
CF2RevST
CF3RevST
CF4RevST
0: Forward
1: Reverse
Energy for CF2 Forward/Reverse status:
0: Forward
1: Reverse
Energy for CF3 Forward/Reverse status:
0: Forward
1: Reverse
Energy for CF4 Forward/Reverse status:
0: Forward
1: Reverse
60
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EMMState1
EMM State 1
Address: 72H
Type: Read
Default Value: 0000H
Bit
Name
Description
15
FreqHiST
This bit indicates whether frequency is greater than the high threshold
SagPhase-
AST
14
13
This bit indicates whether there is voltage sag on phase A
This bit indicates whether there is voltage sag on phase B
Sag-
PhaseBST
SagPha-
seCST
12
11
10
This bit indicates whether there is voltage sag on phase C
This bit indicates whether frequency is lesser than the low threshold
This bit indicates whether there is a phase loss in Phase A
FreqLoST
PhaseLos-
sAST
PhaseLoss-
BST
9
8
This bit indicates whether there is a phase loss in Phase B
This bit indicates whether there is a phase loss in Phase C
PhaseLoss-
CST
ReActive (Q) Energy (E) Register (Reg) of all channel total sum (T) Positive (P) Status (ST):
7
QERegTPST
0: Positive,
1: Negative
6
5
4
QERegAPST
QERegBPST
QERegCPST
ReActive (Q) Energy (E) Register (Reg) of Channel (A/B/C) Positive (P) Status (ST):
0: Positive,
1: Negative
Active (P) Energy (E) Register (Reg) of all channel total sum (T) Positive (P) Status (ST)
3
PERegTPST
0: Positive,
1: Negative
2
1
0
PERegAPST
PERegBPST
PERegCPST
Active (P) Energy (E) Register (Reg) of Channel (A/B/C) Positive (P) Status (ST)
0: Positive,
1: Negative
M90E32AS [DATASHEET]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
61
EMMIntState0
EMM Interrupt Status 0
Address: 73H
Type: Read/ Write 1 Clear
Default Value: 0000H
Bit
Name
Description
OIPhaseAIntS
T
15
Over current on phase A status change flag
Over current on phase B status change flag
Over current on phase C status change flag
Over Voltage on phase A status change flag
Over Voltage on phase B status change flag
Over Voltage on phase C status change flag
OIPhaseBIntS
T
14
13
12
11
10
OIPhaseCInt
ST
OVPhaseAInt
ST
OVPhaseBInt
ST
OVPhaseCInt
ST
URevWn-
IntST
9
8
7
Voltage Phase Sequence Error status change flag
Current Phase Sequence Error status change flag
Neutral line over current status change flag
IRevWnIntST
INOv0IntST
TQNoload-
IntST
6
5
4
All phase sum reactive power no-load condition status change flag
All phase sum active power no-load condition status change flag
All phase arithmetic sum apparent power no-load condition status change flag
TPNoload-
IntST
TASNoload-
IntST
3
2
1
0
CF1RevIntST
CF2RevIntST
CF3RevIntST
CF4RevIntST
Energy for CF1 Forward/Reverse status change flag
Energy for CF2 Forward/Reverse status change flag
Energy for CF3 Forward/Reverse status change flag
Energy for CF4 Forward/Reverse status change flag
62
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EMMIntState1
EMM Interrupt Status 1
Address: 74H
Type: Read/ Write 1 Clear
Default Value: 0000H
Bit
Name
Description
15
FreqHiIntST
FreqHiST change flag
SagPhase-
AIntST
14
13
Voltage sag on phase A status change flag
SagPhase-
BIntST
Voltage sag on phase B status change flag
SagPhase-
CIntST
12
11
10
Voltage sag on phase C status change flag
FreqLoST change flag
FreqLoIntST
PhaseLos-
sAIntST
Voltage PhaseLoss on phase A status change flag
PhaseLoss-
BIntST
9
8
7
6
5
4
3
2
1
0
Voltage PhaseLoss on phase B status change flag
PhaseLoss-
CIntST
Voltage PhaseLoss on phase C status change flag
QERegT-
PIntST
ReActive (Q) Energy (E) Register (Reg) of all channel total sum (T) Positive (P) status change flag (IntST)
QERegAP-
IntST
QERegB-
PIntST
ReActive (Q) Energy (E) Register (Reg) of all channel (A/B/C) Positive (P) status change flag (IntST)
Active (P) Energy (E) Register (Reg) of all channel total sum (T) Positive (P) status change flag (IntST)
Active (P) Energy(E) Register (Reg) of Channel (A/B/C) Positive (P) status change flag (IntST)
QE
RegCPIntST
PERegT-
PIntST
PERegAP-
IntST
PERegB-
PIntST
PE
RegCPIntST
M90E32AS [DATASHEET]
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63
EMMIntEn0
EMM Interrupt Enable 0
Address: 75H
Type: Read/ Write
Default Value: 0000H
Bit
Name
Description
OIPhaseAIntE
N
15
Phase A Over current status change interrupt generation enable
OIPhaseBIntE
N
14
13
12
11
10
9
Phase B Over current status change interrupt generation enable
OIPhaseCInt
EN
Phase C Over current status change interrupt generation enable
OVPhaseAInt
EN
Phase A Over Voltage status change interrupt generation enable
OVPhaseBInt
EN
Phase B Over Voltage status change interrupt generation enable
OVPhaseCInt
EN
Phase C Over Voltage status change interrupt generation enable
URevWnIntE
N
Voltage Phase Sequence Error Status Change Interrupt Generation Enable
Current Phase Sequence Error Status Change Interrupt Generation Enable
Neutral line over current Status Change Interrupt Generation Enable
8
IRevWnIntEN
INOv0IntEN
7
TQNoloadIntE
N
6
All phase sum reactive power no-load condition Status Change Interrupt Generation Enable
All phase sum active power no-load condition Status Change Interrupt Generation Enable
All phase arithmetic sum apparent power no-load condition Status Change Interrupt Generation Enable
Energy for CF1 Forward/Reverse Status Change Interrupt Generation Enable
Energy for CF2 Forward/Reverse Status Change Interrupt Generation Enable
Energy for CF3 Forward/Reverse Status Change Interrupt Generation Enable
Energy for CF4 Forward/Reverse Status Change Interrupt Generation Enable
TPNoloadIntE
N
5
TASNoload-
IntEN
4
3
CF1RevIntEN
CF2RevIntEN
CF3RevIntEN
CF4RevIntEN
2
1
0
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EMMIntEn1
EMM Interrupt Enable 1
Address: 76H
Type: Read/ Write
Default Value: 0000H
Bit
Name
Description
FreqHiIntST status change interrupt generation enable
15
FreqHiIntEn
SagPhase-
AIntEN
14
13
Phase A Sag status change interrupt generation enable
Phase B Sag status change interrupt generation enable
SagPhase-
BIntEN
SagPhase-
CIntEN
12
11
10
Phase C Sag status change interrupt generation enable
FreqLoIntST status change interrupt generation enable
Phase A Phase Loss status change interrupt generation enable
FreqLoIntEn
PhaseLos-
sAIntEN
PhaseLoss-
BIntEN
9
8
Phase B Phase Loss status change interrupt generation enable
Phase C Phase Loss status change interrupt generation enable
PhaseLoss-
CIntEN
QERegTPIntE
N
7
QERegAP-
IntEN
6
ReActive (Q) Energy(E) Register (Reg) of all channel totoal sum (T) Positive (P) Status Change Interrupt
Generation Enable (IntEN)
QERegB-
PIntEN
5
QE
RegCPIntEN
4
PERegTPIntE
N
3
PERegAPIntE
N
2
Active (P) Energy (E) Register (Reg) of Channel A (A) Positive (P) Status Change Interrupt Generation E
nable (ST)
PERegBPIntE
N
1
PERegCPIntE
N
0
LastSPIData
Last Read/Write SPI Value
Address: 78H
Type: Read
Default Value: 0000H
Bit
Name
Description
This register is a special register which logs data of the previous SPI Read or Write access especially for
Read/Clear registers. This register is useful when the user wants to check the integrity of the last SPI
access.
LastSPI-
Data[15:0]
15:0
M90E32AS [DATASHEET]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
65
CRCErrStatus
CRC Error Status
Address: 79H
Type: Read
Default Value: 0000H
Bit
15:2
1
Name
Description
-
Reserved.
INT_ERR
Internal register CRC error
CFG_CRC_E
RR
0
Configuration registers CRC error
CRCDigest
CRC Digest
Address: 7AH
Type: Read/ Write
Default Value: 0000H
Bit
Name
Description
This register returns the computed CRC remainder (Digest) value of the public configuration register upon
read operation.
This register can be conditionally written as the portal to update the golden CRC that internally latched.
Refer to register CfgRegAccEn for the details.
15:0
CRCDigest
CfgRegAccEn
Configure Register Access Enable
Address: 7FH
Type: Read/ Write
Default Value: 0000H
Bit
Name
Description
Enable register access configuration.
‘0x55AA’ : Allow register configuration access (configuration operation).
‘0xAA55’: Allow write to the "Golden CRC" register at the address of CRCDigest, on top of normal
operation/CRC checking mode. This is just for validation of this feature.
15:0
CfgRegAccEn
other: Normal operation. The device will start to compute a CRC digest/checksum and latch it the golden
CRC register, then continuously running to check with it.
66
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5.5
ENERGY REGISTER
5.5.1
REGULAR ENERGY REGISTERS
Table-11 Regular Energy Registers
Register
Read/Write
Type
Address
80H
81H
82H
83H
84H
85H
86H
87H
88H
89H
8AH
8BH
8CH
8DH
8EH
8FH
Register Name
APenergyT
APenergyA
APenergyB
APenergyC
ANenergyT
ANenergyA
ANenergyB
ANenergyC
RPenergyT
RPenergyA
RPenergyB
RPenergyC
RNenergyT
RNenergyA
RNenergyB
RNenergyC
Functional Description
Total Forward Active Energy
Comment
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
Phase A Forward Active Energy
Phase B Forward Active Energy
Phase C Forward Active Energy
Total Reverse Active Energy
Phase A Reverse Active Energy
Phase B Reverse Active Energy
Phase C Reverse Active Energy
Total Forward Reactive Energy
Phase A Forward Reactive Energy
Phase B Forward Reactive Energy
Phase C Forward Reactive Energy
Total Reverse Reactive Energy
Phase A Reverse Reactive Energy
Phase B Reverse Reactive Energy
Phase C Reverse Reactive Energy
Resolution is 0.01CF. Cleared after
read.
Total (Arithmetic Sum) Apparent E
nergy
90H
SAenergyT
R/C
91H
92H
93H
SenergyA
SenergyB
SenergyC
R/C
R/C
R/C
Phase A Apparent Energy
Phase B Apparent Energy
Phase C Apparent Energy
M90E32AS [DATASHEET]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
67
5.5.2
FUNDAMENTAL / HARMONIC ENERGY REGISTER
Table-12 Fundamental / Harmonic Energy Register
Register
Address
Read/Write
Type
Register Name
Functional Description
Comment
Total Forward Active Fundamental E
nergy
A0H
A1H
A2H
A3H
A4H
A5H
A6H
APenergyTF
R/C
R/C
R/C
R/C
R/C
R/C
R/C
Phase A Forward Active Fundamental
Energy
APenergyAF
APenergyBF
APenergyCF
ANenergyTF
ANenergyAF
ANenergyBF
Phase B Forward Active Fundamental
Energy
Phase C Forward Active Fundamen-
tal Energy
Total Reverse Active Fundamental E
nergy
Phase A Reverse Active Fundamen-
tal Energy
Phase B Reverse Active Fundamen-
tal Energy
Phase C Reverse Active Fundamental
Energy
Resolution is 0.01CF. Cleared after
read.
A7H
A8H
A9H
ANenergyCF
APenergyTH
APenergyAH
R/C
R/C
R/C
Total Forward Active Harmonic Energy
Phase A Forward Active Harmonic E
nergy
Phase B Forward Active Harmonic E
nergy
AAH
APenergyBH
R/C
Phase C Forward Active Harmonic E
nergy
ABH
ACH
ADH
APenergyCH
ANenergyTH
ANenergyAH
R/C
R/C
R/C
Total Reverse Active Harmonic Energy
Phase A Reverse Active Harmonic E
nergy
Phase B Reverse Active Harmonic E
nergy
AEH
AFH
ANenergyBH
ANenergyCH
R/C
R/C
Phase C Reverse Active Harmonic E
nergy
68
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5.6
MEASUREMENT REGISTERS
5.6.1
POWER AND POWER FACTOR REGISTERS
Table-13 Power and Power Factor Register
Register
Address
Read/Write
Type
Register Name
PmeanT
Functional Description
Total (All-phase-sum) Active Power
Phase A Active Power
Comment
B0H
B1H
B2H
B3H
B4H
B5H
B6H
B7H
R
R
R
R
R
R
R
R
PmeanA
Complement,
Power=32-bit register value* 0.00032 W
PmeanB
Phase B Active Power
PmeanC
QmeanT
QmeanA
QmeanB
QmeanC
Phase C Active Power
Total (All-phase-sum) Reactive Power
Phase A Reactive Power
Phase B Reactive Power
Phase C Reactive Power
Complement,
Power=32-bit register value* 0.00032
var
Total (Arithmetic Sum) Apparent
Power
B8H
SAmeanT
R
Complement,
B9H
BAH
BBH
BCH
BDH
BEH
BFH
SmeanA
SmeanB
R
R
R
R
R
R
R
Phase A Apparent Power
Phase B Apparent Power
Phase C Apparent Power
Total Power Factor
Power=32-bit register value* 0.00032
VA
SmeanC
PFmeanT
PFmeanA
PFmeanB
PFmeanC
Signed with complement format,
Phase A Power Factor
Phase B Power Factor
Phase C Power Factor
X.XXX
LSB is 0.001. Range from -1000 to
+1000
Lower Word of Total (All-phase-sum)
Active Power
C0H
PmeanTLSB
R
Lower word of Active Powers.
Lower word of Active Powers.
Lower word of ReActive Powers.
C1H
C2H
C3H
PmeanALSB
PmeanBLSB
PmeanCLSB
R
R
R
Lower Word of Phase A Active Power
Lower Word of Phase B Active Power
Lower Word of Phase C Active Power
Lower Word of Total (All-phase-sum)
Reactive Power
C4H
C5H
C6H
C7H
C8H
C9H
CAH
CBH
QmeanTLSB
QmeanALSB
QmeanBLSB
QmeanCLSB
SAmeanTLSB
SmeanALSB
SmeanBLSB
SmeanCLSB
R
R
R
R
R
R
R
R
Lower Word of Phase A Reactive
Power
Lower Word of Phase B Reactive
Power
Lower word of ReActive Powers.
Lower word of Apparent Powers.
Lower word of Apparent Powers.
Lower Word of Phase C Reactive
Power
Lower Word of Total (Arithmetic Sum)
Apparent Power
Lower Word of Phase A Apparent
Power
Lower Word of Phase B Apparent
Power
Lower Word of Phase C Apparent
Power
Note: The power regisiters are all of 32-bit. The C0H~CBH registers are the lower words of the B0H~BFH registers.
M90E32AS [DATASHEET]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
69
5.6.2
FUNDAMENTAL/ HARMONIC POWER AND VOLTAGE/ CURRENT RMS REGISTERS
Table-14 Fundamental/ Harmonic Power and Voltage/ Current RMS Registers
Register
Address
Read/Write
Type
Register Name
Functional Description
Comment
Complement,
Power=32-bit register value* 0.00032 W
D0H
PmeanTF
R
Total Active Fundamental Power
D1H
D2H
D3H
PmeanAF
PmeanBF
PmeanCF
R
R
R
Phase A Active Fundamental Power
Phase B Active Fundamental Power
Phase C Active Fundamental Power
Complement,
Power=32-bit register value* 0.00032 W
Complement,
Power=32-bit register value* 0.00032 W
D4H
PmeanTH
R
Total Active Harmonic Power
D5H
D6H
D7H
D9H
DAH
DBH
DCH
DDH
DEH
DFH
PmeanAH
PmeanBH
PmeanCH
UrmsA
UrmsB
UrmsC
IrmsN
R
R
R
R
R
R
R
R
R
R
Phase A Active Harmonic Power
Phase B Active Harmonic Power
Phase C Active Harmonic Power
Phase A Voltage RMS
Complement,
Power=32-bit register value* 0.00032 W
Phase B Voltage RMS
Unsigned, 1LSB corresponds to 0.01 V
Phase C Voltage RMS
N Line Calculated Current RMS
Phase A Current RMS
Unsigned 16-bit integer with unit of
0.001A
IrmsA
IrmsB
Phase B Current RMS
1LSB corresponds to 0.001 A
IrmsC
Phase C Current RMS
Lower Word of Total Active Funda-
mental Power
E0H
E1H
E2H
E3H
PmeanTFLSB
PmeanAFLSB
PmeanBFLSB
PmeanCFLSB
R
R
R
R
Lower word of D0H register.
Lower Word of Phase A Active Funda-
mental Power
Lower Word of Phase B Active Funda- Lower word of registers from D1H to
mental Power
D3H.
Lower Word of phase C active funda-
mental Power
E9H
EAH
EBH
EDH
EEH
EFH
UrmsALSB
UrmsBLSB
UrmsCLSB
IrmsALSB
IrmsBLSB
IrmsCLSB
R
R
R
R
R
R
Lower Word of Phase A Voltage RMS
Lower Word of Phase B Voltage RMS
Lower Word of Phase C Voltage RMS
Lower Word of Phase A Current RMS
Lower Word of Phase B Current RMS
Lower Word of Phase C Current RMS
Lower word of registers from D9H to
DBH.
Lower word of registers from DDH to
DFH.
Note: The power regisiters are all of 32-bit. The E0H~EFH registers are the lower words of the D0H~DFH registers.
70
M90E32AS [Datasheet]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
5.6.3
PEAK, FREQUENCY, ANGLE AND TEMPERATURE REGISTERS
Table-15 Peak, Frequency, Angle and Temperature Registers
Register
Address
Read/Write
Type
Register Name
UPeakA
UPeakB
UPeakC
IPeakA
Functional Description
Channel A Voltage Peak
Channel B Voltage Peak
Channel C Voltage Peak
Channel A Current Peak
Channel B Current Peak
Channel C Current Peak
Frequency
Comment
F1H
F2H
F3H
F5H
F6H
F7H
F8H
F9H
FAH
FBH
R
R
R
R
R
R
R
R
R
R
IPeakB
IPeakC
Freq
1LSB corresponds to 0.01 Hz
PAngleA
PAngleB
PAngleC
Phase A Mean Phase Angle
Phase B Mean Phase Angle
Phase C Mean Phase Angle
Unsigned,
1LSB corresponds to 0.1 degree,
0°~+360.0°
1LSB corresponds to 1 °C
Signed, MSB as the sign bit
FCH
Temp
R
Measured Temperature
FDH
FEH
UangleA
UangleB
R
R
Phase A Voltage Phase Angle
Phase B Voltage Phase Angle
Always ‘0’
Unsigned,
1LSB corresponds to 0.1 degree,
0°~+360.0°
FFH
UangleC
R
Phase C Voltage Phase Angle
UPeakA
Channel A Voltage Peak
Address: F1H
Type: Read
Default Value: 0000H
Bit
Name
Description
Channel A voltage peak data detected in the configured period.
Component. Unit is V.
UPeak is calculated as below:
15:0
UPeakDataA
UgainRegValue
UPeak=UPeakRegValue×
13
100×2
Here UgainRegValue is the register value of the Ugain (61H/65H/69H) register.
IPeakA
Channel A Current Peak
Address: F5H
Type: Read
Default Value: 0000H
Bit
Name
Description
Channel A current peak data detected in the configured period.
Component. Unit is A.
IPeak is calculated as below:
15:0
IPeakDataA
IgainRegValue
IPeak = IPeakRegValue×
13
1000 ×2
Here IgainRegValue is the register value of the Igain (62H/66H/6AH) register.
M90E32AS [DATASHEET]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
71
6
ELECTRICAL SPECIFICATION
6.1
ELECTRICAL SPECIFICATION
Parameter
Min
Typ
Max
Unit
Test Condition/ Comments
Accuracy
VDD=3.3V±0.3V, I=5A, V=220V, CT 1000:1,
sampling resistor 4.8Ω
DC Power Supply Rejection Ratio (PSRR)note1
%
±0.1
VDD=3.3V superimposes 400mVrms, I=5A,
V=220V, CT 1000:1, sampling resistor 4.8Ω
AC Power Supply Rejection Ratio (PSRR)note1
Active Energy Error (Dynamic Range 6000:1)
%
%
±0.1
±0.1
CT 1000:1, sampling resistor 4.8Ω
ADC Channel
720m
Channel Differential Inputnote1
PGA=1
120μ
Vrms
Voltage Channel Input Impedance
120
PGA=1
PGA=1
KΩ
120
80
50
Current Channel Input Impedance
KΩ PGA=2
PGA=4
Channel Sampling Frequency
Channel Sampling Bandwidth
8
2
kHz
kHz
Temperature Sensor and Reference
Temperature Sensor Accuracy
Reference voltage
1
°C
V
3.3 V, 25 °C
1.2
ppm/
°C
Reference voltage temperature coefficientnote1
15
From -40 to 85 °C
6
Current detectors
4
Current Detector threshold range
3.3 V, 25 °C
3.3 V, 25 °C
1.5
mVrms
mVrms
Current Detector threshold setting step/ resolu-
tion
0.05
Current Detector detection time (single-side)
Current Detector detection time (double-side)
32
17
ms
ms
Crystal Oscillator
16.384
The Accuracy of crystal or external clock is
±20 ppm, 10pF ~ 20pF crystal load capacitor
integrated.
Oscillator Frequency (f
)
MHz
sys_clk
Power Supply
AVDD
DVDD
VDD18
2.8
2.8
3.3
3.3
1.8
3.6
3.6
V
V
V
Operating Currents
13
Normal mode operating current (I-Normal)
Idle mode operating current (I-Idle)
3.3 V, 25 °C
mA
<0.1
1
μA
Double-side detection
Single-side detection
200
100
230
115
Detection mode operating current (I-Detection)
μA
Partial Measurement mode operating current
(I-Measurement)
3.3 V, 25°C
7
mA
72
M90E32AS [Datasheet]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
Parameter
Min
400
Typ
SPI
Max
Unit
bps
Test Condition/ Comments
1100knote2
Slave mode (SPI) bit rate
ESD
Charged Device Model (CDM)
Human Body Model (HBM)
Latch Up
500
V
V
JESD22-C101
JESD22-A114
4000
mA JESD78A
±100
Latch Up
5.4
V
V
JESD78A
DC Characteristics
Digital Input High Level (all digital pins except
OSCI)
2.0
5.5
VDD=3.3V, 5V digital input compatible
Digital Input Low Level (all digital pins except
OSCI)
0.8
±1
0.4
V
μA
V
VDD=3.3V
Digital Input Leakage Current
VDD=3.6V, VI=VDD or GND
VDD=3.3V, IOL=8mA
Digital Output Low Level (CF1, CF2, CF3, CF4,
ZX0, ZX1, ZX2, SDO)
Digital Output Low Level (IRQ0, IRQ1, War-
nOut)
VDD=3.3V, IOL=5mA
0.4
V
V
V
Digital Output High Level (CF1, CF2, CF3, CF4,
ZX0, ZX1, ZX2, SDO)
VDD=3.3V, IOH=-8mA, by separately
VDD=3.3V, IOH=-5mA, by separately
VDD-0.4
VDD-0.4
Digital Output High Level (IRQ0, IRQ1, War-
nOut)
note1: Guaranteed by characterization, not production tested.
note2: The maximum SPI bit rate during current detector calibration is 900k bps.
M90E32AS [DATASHEET]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
73
6.2
METERING/ MEASUREMENT ACCURACY
6.2.1
METERING ACCURACY
Metering accuracy or energy accuracy is calculated with relative error:
Emea −Ereal
γ =
×100%
Ereal
Where E
is the energy measured by the meter, E
is the actual energy measured by a high accurate normative meter.
mea
real
Table-16 Metering Accuracy for Different Energy within the Dynamic Range
ADC Range
Metering Accuracynote
Energy Type
Energy Pulse
When Gain=1
PF=1.0 120μV-720mV
PF=0.5L, 180μV-720mV
PF=0.8C, 150μV-720mV
sinФ=1.0 120μV-720mV
sinФ=0.5L, 180μV-720mV
sinФ=0.8C, 150μV-720mV
Active energy
(Per phase and all-phase-sum)
CF1
0.1%
Reactive energy
(Per phase and all-phase-sum)
CF2
CF2
CF3
0.2%
0.2%
0.2%
Apparent energy
(Per phase and arithmetic all-phase-
sum)
600μV-720mVnote 2
PF=1.0 120μV-720mV
PF=0.5L, 180μV-720mV
PF=0.8C, 150μV-720mV
PF=1.0 120μV-720mV
PF=0.5L, 180μV-720mV
PF=0.8C, 150μV-720mV
Fundamental active energy
(Per phase and all-phase-sum)
Harmonic active energy
(Per phase and all-phase-sum)
CF4
0.5%
Note 1: All the parameters in this table is tested on Atmel test platform.
Note 2: Apparent energy is tested using active energy with unity power factor since there’s no standard for apparent energy. Signal
below 600 μV is not tested.
74
M90E32AS [Datasheet]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
6.2.2
MEASUREMENT ACCURACY
The measurements are all calculated with fiducial error except for frequency.
Fiducial error is calculated as follows:
Umea - Ureal
Fiducial_Error =
* 100%
UFV
Where U
means the measured data of one measurement parameter, and U
means the real/actual data of the
real
mea
parameter,
U
means the fiducial value of this measurement parameter, which can be defined as Table-17.
FV
Table-17 Measurement Parameter Range and Format
M90E32AS
Defined
Format
Measurement
Fiducial Value (FV)
Range
Comment
Voltage
reference voltage Un
XXX.XX
0 ~ 655.35V
Unsigned integer with unit of 0.01V
maximum
current
Imax (4×In is recom-
mended)
Current
XX.XXX
0 ~ 65.535A
Unsigned integer with unit of 0.001A
Voltage rms
Un
XXX.XX
XX.XXX
0 ~ 655.35V
0 ~ 65.535A
Unsigned integer with unit of 0.01V
Unsigned integer with unit of 0.001A
Current rms note 1
Ib/In
Reference Fre-
quency 50 Hz
Signed integer with unit/LSB of
0.01Hz
Frequency
XX.XX
45.00~65.00 Hz
Power Factor
1.000
X.XXX
XXX.X
-1.000 ~ +1.000
Signed integer, LSB/Unit = 0.001
Phase Anglenote 2
180°
-180° ~ +180°
Signed integer, unit/LSB = 0.1°
Note 1:
All registers are of 16-bit. For cases when the current or active/reactive/apparent power goes beyond the above range, it is suggested
to be handled by MCU in application. For example, register value can be calibrated to 1/2 of the actual value during calibration, then
multiply 2 in application.
Note 2:
Phase angle is obtained when voltage/current crosses zero at the sampling frequency of 256kHz.
For the above mentioned parameters, the measurement accuracy requirement is 0.5% maximum.
For frequency, temperature:
Parameter Accuracy
Frequency: 0.01Hz
Temperature: 1 °C
Accuracy of all orders of harmonics: 5% relative error
M90E32AS [DATASHEET]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
75
6.3
INTERFACE TIMING
6.3.1
SPI INTERFACE TIMING (SLAVE MODE)
The SPI interface timing is as shown in Figure-22 and Table-18.
t
CSH
t
CYC
CS
t
t
t
t
t
CSD
CLD
CLH
CSS
CLL
SCLK
SDI
t
t
DIS
DIH
Valid Input
t
DW
t
t
PD
DF
High Impedance
High Impedance
Valid Output
SDO
Figure-22 SPI Timing Diagram
Table-18 SPI Timing Specification
Symbol
Description
Min.
Typical
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2T note 1+10
2T+10
3T+10
1T
tCSH
tCSS
tCSD
tCLD
tCYC
tCLH
tCLL
tDIS
tDIH
tDW
tPD
Minimum CS High Level Time
CS Setup Time
CS Hold Time
Clock Disable Time
SCLK cycle
7T+10
5T+10
2T+10
2T+10
1T+10
3T+10
Clock High Level Time
Clock Low Level Time
Data Setup Time
Data Hold Time
Minimum Data Width
Output Delay
2T+20
2T+20
tDF
Output Disable Time
Note:
1. T means system clock cycle. T=1/f
sys_clk
76
M90E32AS [Datasheet]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
6.4
POWER ON RESET TIMING
In most case, the power of M90E32AS and MCU are both derived from 220V power lines. To make sure M90E32AS is
reset and can work properly, MCU must force M90E32AS into idle mode firstly and then into normal mode. In this opera-
tion, RESET is held to high in idle mode and de-asserted by delay T1 after idle-normal transition. Refer to Figure-23.
DVDD
T0
Idle Mode
PM[1:0]
MCU startup
Normal Mode
T1
Internal
POR
Figure-23 Power On Reset Timing (M90E32AS and MCU are Powered on Simultaneously)
VH
DVDD
T1
Internal POR
Figure-24 Power On Reset Timing in Normal & Partial Measurement Mode
Table-19 Power On Reset Specification
Symbol
Description
Min
Typ
Max
Unit
V
Power On Trigger Voltage
2.5
2.7
V
H
Duration forced in idle mode after power
on
T
1
5
ms
ms
0
Delay time after power on or exit idle
mode
T
16
40
1
M90E32AS [DATASHEET]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
77
6.5
ZERO-CROSSING TIMING
V
TZX
ZX
(Positive zero-crossing)
TD
ZX
(Negative zero-crossing)
ZX
(All zero-crossing)
Figure-25 Zero-Crossing Timing Diagram (per phase)
Table-20 Zero-Crossing Specification
Symbol
Description
High Level Width
Delay Time
Min
Typ
5
Max
Unit
ms
T
ZX
T
0.2
0.5
ms
D
78
M90E32AS [Datasheet]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
6.6
VOLTAGE SAG AND PHASE LOSS TIMING
Voltage
+ threshold
time
- threshold
Sag/Phase Loss condition found
in configured period
configured period
Assert of
Voltage Sag / Phase Loss
IRQ (if enabled)
Figure-26 Voltage Sag and Phase Loss Timing Diagram
M90E32AS [DATASHEET]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
79
6.7
ABSOLUTE MAXIMUM RATING
Parameter
Maximum Limit
-0.3V~4.5V
Relative Voltage Between AVDD and AGND
Relative Voltage Between DVDD and DGND
-0.3V~4.5V
Analog Input Voltage
(I1P, I1N, I2P, I2N, I3P, I3N, V1P, V1N, V2P, V2N, V3P, V3N)
-0.6V~AVDD
-0.3V~DVDD
Digital Input Voltage
-0.3V~5.5V, for 5V tolerance pins
-50~120 °C
Operating Temperature Range
Maximum Junction Temperature
150 °C
Thermal Resistance θJA
Package Type
Unit
°C/W
Condition
TQFP48
58.5
No Airflow
80
M90E32AS [Datasheet]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
ORDERING INFORMATION
Atmel Ordering Code
Package
TQFP48
TQFP48
Carrier
Tape&Reel
Tray
Temperature Range
Industry (-40°C to +85°C)
Industry (-40°C to +85°C)
ATM90E32AS-AU-R
ATM90E32AS-AU-Y
M90E32AS [DATASHEET]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
81
PACKAGE DIMENSIONS
82
M90E32AS [Datasheet]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
REVISION HISTORY
Doc. Rev.
Date
Comments
46003A
05/20/2014
Initial document release in Atmel.
Changed from Preliminary Datasheet to Datasheet.
Added notes to section 6.1.
46003B
02/12/2015
M90E32AS [DATASHEET]
Atmel-46003B-SE-M90E32AS-Datasheet_02122015
83
X
X
X X
Atmel Corporation
1600 Technology Drive, San Jose, CA 95110 USA
T: (+1)(408) 441.0311
F: (+1)(408) 436.4200
|
www.atmel.com
© 2015 Atmel Corporation. All rights reserved. / Rev.: Atmel-46003B-SE-M90E32AS-Datasheet_02122015.
Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation or its
subsidiaries. Other terms and product names may be trademarks of others.
DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right
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