ATMEGA103L-4AC_技术文档

Features

• Utilizes the AVR^®Enhanced RISC Architecture

• 121 Powerful Instructions - Most Single Clock Cycle Execution

• 128K bytes of In-System Reprogrammable Flash ATmega103/L

64K bytes of In-System Reprogrammable Flash ATmega603/L

– SPI Interface for In-System Programming

– Endurance: 1,000 Write/Erase Cycles

• 4K bytes EEPROM ATmega103/L

2K bytes of EEPROM ATmega603/L

– Endurance: 100,000 Write/Erase Cycles

• 4K bytes Internal SRAM

• 32 x 8 General Purpose Working Registers + Peripheral Control Registers

• 32 Programmable I/O Lines, 8 Output Lines, 8 Input Lines

• Programmable Serial UART + SPI Serial Interface

• V_CCSupply

– 2.7 - 3.6V ATmega603L/ATmega103L

– 4.0 - 5.5V ATmega603/ATmega103

• Fully Static Operation

– 0 - 6 MHz ATmega603/ATmega103

– 0 - 4 MHz ATmega603L/ATmega103L

• Up to 6 MIPS Throughput at 6 MHz

• RTC with Separate Oscillator

• Two 8-Bit Timer/Counters with Separate Prescaler and PWM

• One 16-Bit Timer/Counter with Separate Prescaler, Compare, Capture Modes and

Dual 8-, 9- or 10-Bit PWM

8-Bit

Microcontroller

with 64K/128K

BytesIn-System

Programmable

Flash

• Programmable Watchdog Timer with On-Chip Oscillator

• On-Chip Analog Comparator

• 8-Channel, 10-Bit ADC

• Low Power Idle, Power Save and Power Down Modes

• Software Selectable Clock Frequency

• Programming Lock for Software Security

ATmega603

ATmega603L

ATmega103

ATmega103L

Preliminary

ATmega103/L

Pin Configuration

TQFP

Rev. 0945BS–09/98

Note:

This is a summary document. For the complete 92

page document, please visit our web site at

www.atmel.com or e-mail at literature@atmel.com

and request literature #0945B.

1

Block Diagram

Figure 1. The ATmega603/103 Block Diagram

PF0 - PF7

PA0 - PA7

PC0 - PC7

VCC

GND

PORTF BUFFERS

PORTA DRIVER/BUFFERS

PORTC DRIVERS

AVCC

DATA REGISTER

PORTC

DATA REGISTER

PORTA

DATA DIR.

REG. PORTA

ANALOG MUX

ADC

8-BIT DATA BUS

AGND

AREF

XTAL1

INTERNAL

OSCILLATOR

XTAL1

PROGRAM

COUNTER

STACK

POINTER

WATCHDOG

TIMER

TOSC2

OSCILLATOR

TIMING AND

CONTROL

PROGRAM

FLASH

MCU CONTROL

REGISTER

TOSC1

SRAM

RESET

ALE

INSTRUCTION

REGISTER

TIMER/

COUNTERS

GENERAL

PURPOSE

REGISTERS

WR

RD

X

Y

Z

INSTRUCTION

DECODER

INTERRUPT

UNIT

CONTROL

LINES

ALU

EEPROM

PEN

STATUS

REGISTER

PROGRAMMING

LOGIC

SPI

UART

DATA REGISTER

PORTE

DATA DIR.

REG. PORTE

DATA REGISTER

PORTB

DATA DIR.

REG. PORTB

DATA REGISTER

PORTD

DATA DIR.

REG. PORTD

VCC

GND

PORTE DRIVER/BUFFERS

PORTB DRIVER/BUFFERS

PORTD DRIVER/BUFFERS

PE0 - PE7

PB0 - PB7

PD0 - PD7

Description

The ATmega603/103 is a low-power CMOS 8-bit microcon-

troller based on the AVR enhanced RISC architecture. By

executing powerful instructions in a single clock cycle, the

ATmega603/103 achieves throughputs approaching 1

MIPS per MHz allowing the system designer to optimize

power consumption versus processing speed.

is more code efficient while achieving throughputs up to ten

times faster than conventional CISC microcontrollers.

The ATmega603/103 provides the following features:

64K/128K bytes of In-system Programmable Flash, 2K/4K

bytes EEPROM, 4K bytes SRAM, 32 general purpose I/O

lines, 8 Input lines, 8 Output lines, 32 general purpose

working registers, 4 flexible timer/counters with compare

modes and PWM, UART, programmable Watchdog Timer

with internal oscillator, an SPI serial port and three software

selectable power saving modes. The Idle Mode stops the

CPU while allowing the SRAM, timer/counters, SPI port

and interrupt system to continue functioning. The Power

The AVR core is based on an enhanced RISC architecture

that combines a rich instruction set with 32 general purpose

working registers. All the 32 registers are directly con-

nected to the Arithmetic Logic Unit (ALU), allowing two

independent registers to be accessed in one single instruc-

tion executed in one clock cycle. The resulting architecture

ATmega603(L) and ATmega103(L)

2

ATmega603(L) and ATmega103(L)

Down mode saves the register contents but freezes the

oscillator, disabling all other chip functions until the next

interrupt or hardware reset. In Power Save mode, the timer

oscillator continues to run, allowing the user to maintain a

timer base while the rest of the device is sleeping.

Port A serves as Multiplexed Address/Data bus when using

external SRAM.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O pins with internal pull-up

resistors. The Port B output buffers can sink 20 mA. As

inputs, Port B pins that are externally pulled low, will source

current if the pull-up resistors are activated.

The device is manufactured using Atmel’s high-density

non-volatile memory technology. The on-chip ISP Flash

allows the program memory to be reprogrammed in-system

through a serial interface or by a conventional nonvolatile

memory programmer. By combining an 8-bit RISC CPU

with a large array of ISP Flash on a monolithic chip, the

Atmel ATmega603/103 is a powerful microcontroller that

provides a highly flexible and cost effective solution to

many embedded control applications.

Port B also serves the functions of various special features.

Port C (PC7..PC0)

Port C is an 8-bit Output port. The Port C output buffers can

sink 20 mA.

Port C also serves as Address output when using external

SRAM.

The ATmega603/103 AVR is supported with a full suite of

program and system development tools including: C com-

pilers, macro assemblers, program debugger/simulators,

in-circuit emulators, and evaluation kits.

Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up

resistors. The Port D output buffers can sink 20 mA. As

inputs, Port D pins that are externally pulled low will source

current if the pull-up resistors are activated.

Comparison Between ATmega 603 and

ATmega 103

Port D also serves the functions of various special features.

Port E (PE7..PE0)

The ATmega603 has 64K bytes of In-System Programma-

ble Flash, 2K bytes of EEPROM, and 4K bytes of internal

SRAM. The ATmega603 does not have the ELPM instruc-

tion.

Port E is an 8-bit bi-directional I/O port with internal pull-up

resistors. The Port E output buffers can sink 20 mA. As

inputs, Port E pins that are externally pulled low will source

current if the pull-up resistors are activated.

The ATmega103 has 128K bytes of In-System Program-

mable Flash, 4K bytes of EEPROM, and 4K bytes of inter-

nal SRAM. The ATmega103 has the ELPM instruction,

necessary to reach the upper half of the Flash memory for

constant table lookup.

Port E also serves the functions of various special features.

Port F (PF7..PF0)

Port F is an 8-bit Input port. Port F also serves as the ana-

log inputs for the ADC.

RESET

Table 1 summarizes the different memory sizes for the two

devices.

input. A low on this pin for two machine cycles while the

oscillator is running resets the device.

Table 1. Memory Size Summary

XTAL1

Part

Flash

EEPROM

2K bytes

4K bytes

SRAM

Input to the inverting oscillator amplifier and input to the

internal clock operating circuit.

ATmega603

ATmega103

64K bytes

128K bytes

4K bytes

XTAL2

Output from the inverting oscillator amplifier

TOSC1

Pin Descriptions

VCC

Input to the inverting Timer/Counter oscillator amplifier

TOSC2

Supply voltage

GND

Output from the inverting Timer/Counter oscillator amplifier

WR

Ground

External SRAM Write Strobe.

Port A (PA7..PA0)

RD

Port A is an 8-bit bi-directional I/O port. Port pins can pro-

vide internal pull-up resistors (selected for each bit). The

Port A output buffers can sink 20 mA and can drive LED

displays directly. When pins PA0 to PA7 are used as inputs

and are externally pulled low, they will source current if the

internal pull-up resistors are activated.

External SRAM Read Strobe.

ALE

ALE is the Address Latch Enable used when the External

Memory is enabled. The ALE strobe is used to latch the

low-order address (8 bits) into an address latch during the

3

first access cycle, and the AD0-7 pins are used for data

during the second access cycle.

Figure 3. External Clock Drive Configuration

AV_CC

NC

XTAL2

This is the supply voltage to the A/D Converter. It should be

externally connected to V_CCvia a low-pass filter. See

page 53 for details on operation of the ADC.

EXTERNAL

OSCILLATOR

SIGNAL

AREF

XTAL1

GND

This is the analog reference input for the ADC converter.

For ADC operations, a voltage in the range AGND to AVCC

must be applied to this pin.

AGND

If the board has a separate analog ground plane, this pin

should be connected to this ground plane. Otherwise, con-

nect to GND.

PEN

ATmega603/103 Architectural Overview

The fast-access register file contains 32 x 8-bit general pur-

pose working registers with a single clock cycle access

time. This means that during one single clock cycle, one

ALU (Arithmetic Logic Unit) operation is executed. Two

operands are output from the register file, the operation is

executed, and the result is stored back in the register file -

in one clock cycle.

This is a programming enable pin for the low-voltage serial

programming mode. By holding this pin low during a power-

on reset, the device will enter the serial programming

mode.

Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an

inverting amplifier which can be configured for use as an

on-chip oscillator, as shown in Figure 2. Either a quartz

crystal or a ceramic resonator may be used. To drive the

device from an external clock source, XTAL2 should be left

unconnected while XTAL1 is driven as shown in Figure 3.

For the Timer Oscillator pins, OSC1 and OSC2, the crystal

is connected directly between the pins. No external capaci-

tors are needed. The oscillator is optimized for use with a

32,768Hz watch crystal. An external clock signal applied to

this pin goes through the same amplifier having a band-

width of 256kHz. The external clock signal should therefore

be in the interval 0Hz - 256kHz.

Six of the 32 registers can be used as three 16-bit indirect

address register pointers for Data Space addressing -

enabling efficient address calculations. One of the three

address pointers is also used as the address pointer for the

constant table look up function. These added function reg-

isters are the 16-bit X-register, Y-register and Z-register.

The ALU supports arithmetic and logic functions between

registers or between a constant and a register. Single reg-

ister operations are also executed in the ALU. Figure 4

shows the ATmega603/103 AVR Enhanced RISC micro-

controller architecture.

In addition to the register operation, the conventional mem-

ory addressing modes can be used on the register file as

well. This is enabled by the fact that the register file is

assigned the 32 lowermost Data Space addresses, allow-

ing them to be accessed as though they were ordinary

memory locations.

Figure 2. Oscillator Connections

C2

XTAL2

The I/O memory space contains 64 addresses for CPU

peripheral functions as Control Registers, Timer/Counters,

A/D-converters, and other I/O functions. The I/O Memory

can be accessed directly, or as the Data Space locations

following those of the register file, $20 - $5F.

C1

XTAL1

GND

ATmega603(L) and ATmega103(L)

4

ATmega603(L) and ATmega103(L)

Figure 4. The ATmega603/103 AVR Enhanced RISC Architecture

AVR ATmega603/103 Architecture

Data Bus 8-bit

Program

Counter

Status

and Test

32K/64K x 16

Program

Memory

32 x 8

General

Purpose

Registers

Instruction

Register

Instruction

Decoder

Peripherals

ALU

Control Lines

4K x 8

Data

SRAM

2K/4K x 8

EEPROM

The AVR uses a Harvard architecture concept - with sepa-

rate memories and buses for program and data. The pro-

gram memory is executed with a single level pipelining.

While one instruction is being executed, the next instruction

is pre-fetched from the program memory. This concept

enables instructions to be executed in every clock cycle.

The program memory is in-system programmable Flash

memory. With a few exceptions, AVR instructions have a

single 16-bit word format, meaning that every program

memory address contains a single 16-bit instruction.

The 4000 bytes data SRAM can be easily accessed

through the five different addressing modes supported in

the AVR architecture.

A flexible interrupt module has its control registers in the

I/O space with an additional global interrupt enable bit in

the status register. All the different interrupts have a sepa-

rate interrupt vector in the interrupt vector table at the

beginning of the program memory. The different interrupts

have priority in accordance with their interrupt vector posi-

tion. The lower the interrupt vector address, the higher the

priority.

During interrupts and subroutine calls, the return address

program counter (PC) is stored on the stack. The stack is

effectively allocated in the general data SRAM, and conse-

quently the stack size is only limited by the total SRAM size

and the usage of the SRAM. All user programs must initial-

ize the SP in the reset routine (before subroutines or inter-

rupts are executed). The 16-bit stack pointer SP is

read/write accessible in the I/O space.

The memory spaces in the AVR architecture are all linear

and regular memory maps.

The General Purpose Register File

Figure 5 shows the structure of the 32 general purpose

working registers in the CPU.

5

ATmega603/103 Register Summary

Address

$3F ($5F)

$3E ($5E)

$3D ($5D)

$3C ($5C)

$3B ($5B)

$3A ($5A)

$39 ($59)

$38 ($58)

$37 ($57)

$36 ($56)

$35 ($55)

$34 ($54)

$33 ($53)

$32 ($52)

$31 ($51)

$30 ($50)

$2F ($4F)

$2E ($4E)

$2D ($4D)

$2C ($4C)

$2B ($4B)

$2A ($4A)

$29 ($49)

$28 ($48)

$27 ($47)

$26 ($46)

$25 ($45)

$24 ($44)

$23 ($43)

$21 ($47)

$1F ($3F)

$1E ($3E)

$1D ($3D)

$1C ($3C)

$1B ($3B)

$1A ($3A)

$19 ($39)

$18 ($38)

$17 ($37)

$16 ($36)

$15 ($35)

$12 ($32)

$11 ($31)

$10 ($30)

$0F ($2F)

$0E ($2E)

$0D ($2D)

$0C ($2C)

$0B ($2B)

$0A ($2A)

$09 ($29)

$08 ($28)

$07 ($27)

$06 ($26)

$05 ($25)

$04 ($24)

$03 ($23)

$02 ($22)

$01 ($21)

$00 ($20)

Name

SREG

Bit7

I

Bit6

T

Bit5

H

Bit4

S

Bit3

V

Bit2

N

Bit1

Z

Bit0

C

Page

page 14

page 16

page 15

page 23

page 22

page 23

page 24

page 15

page 21

page 28

page 30

page 32

page 34

page 37

page 36

page 37

page 28

page 30

page 40

page 41

page 57

page 59

page 65

page 66

page 46

page 45

page 49

page 50

page 51

page 52

page 54

page 55

page 69

page 73

SPH

SP15

SP7

XDIVEN

-

SP14

SP6

XDIV6

-

SP13

SP5

XDIV5

-

SP12

SP4

SP11

SP3

XDIV3

-

SP10

SP2

XDIV2

-

SP9

SP1

XDIV1

-

SP8

SPL

SP0

XDIV

XDIV4

-

XDIV0

RAMPZ0

ISC40

INT0

-

RAMPZ

EICR

ISC71

INT7

INTF7

OCIE2

OCF2

SRE

-

ISC70

INT6

INTF6

TOIE2

TOV2

SRW

-

ISC61

INT5

INTF5

TICIE1

ICF1

SE

ISC60

INT4

INTF4

OCIE1A

OCF1A

SM1

-

ISC51

INT3

-

ISC50

INT2

-

ISC41

INT1

-

EIMSK

EIFR

TIMSK

TIFR

OCIE1B

OCF1B

SM0

-

TOIE1

TOV1

-

OCIE0

OCF0

-

TOIE0

TOV0

-

MCUCR

MCUSR

TCCR0

TCNT0

OCR0

ASSR

-

EXTRF

CS01

PORF

CS00

-

PWM0

COM01

COM00

CTC0

CS02

Timer/Counter0 (8 Bit)

Timer/Counter0 Output Compare Register

-

AS0

-

TCN0UB

OCR0UB

PWM11

CS11

TCR0UB

PWM10

CS10

TCCR1A

TCCR1B

TCNT1H

TCNT1L

OCR1AH

OCR1AL

OCR1BH

OCR1BL

ICR1H

ICR1L

TCCR2

TCNT2

OCR2

WDTCR

EEARH

EEARL

EEDR

EECR

PORTA

DDRA

PINA

COM1A1

ICNC1

COM1A0

ICES1

COM1B1

-

COM1B0

-

CTC1

CS12

Timer/Counter1 - Counter Register High Byte

Timer/Counter1 - Counter Register Low Byte

Timer/Counter1 - Output Compare Register A High Byte

Timer/Counter1 - Output Compare Register A Low Byte

Timer/Counter1 - Output Compare Register B High Byte

Timer/Counter1 - Output Compare Register B Low Byte

Timer/Counter1 - Input Capture Register High Byte

Timer/Counter1 - Input Capture Register Low Byte

-

PWM2

COM21

COM20

CTC2

CS22

CS21

CS20

Timer/Counter2 (8 Bit)

Timer/Counter2 Output Compare Register

-

WDTOE

-

WDE

WDP2

WDP1

WDP0

-

EEAR11

EEAR10

EEAR9

EEAR8

EEPROM Address Register L

EEPROM Data Register

-

EERIE

PORTA3

DDA3

EEMWE

PORTA2

DDA2

EEWE

PORTA1

DDA1

EERE

PORTA0

DDA0

PORTA7

DDA7

PORTA6

DDA6

PORTA5

DDA5

PORTA4

DDA4

PINA7

PORTB7

DDB7

PINA6

PORTB6

DDB6

PINA5

PORTB5

DDB5

PINA4

PORTB4

DDB4

PINA3

PINA2

PINA1

PINA0

PORTB

DDRB

PINB

PORTB3

DDB3

PORTB2

DDB2

PORTB1

DDB1

PORTB0

DDB0

PINB7

PORTC7

PORTD7

DDD7

PINB6

PORTC6

PORTD6

DDD6

PINB5

PORTC5

PORTD5

DDD5

PINB4

PORTC4

PORTD4

DDD4

PINB3

PINB2

PINB1

PINB0

PORTC

PORTD

DDRD

PIND

PORTC3

PORTD3

DDD3

PORTC2

PORTD2

DDD2

PORTC1

PORTD1

DDD1

PORTC0

PORTD0

DDD0

PIND7

PIND6

PIND5

PIND4

PIND3

PIND2

PIND1

PIND0

SPDR

SPSR

SPI Data Register

SPIF

SPIE

WCOL

SPE

-

SPCR

UDR

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

UART I/O Data Register

USR

RXC

TXC

UDRE

UDRIE

FE

OR

-

UCR

RXCIE

TXCIE

RXEN

TXEN

CHR9

RXB8

TXB8

UBRR

ACSR

UART Baud Rate Register

ACD

-

ACO

-

ACI

-

ACIE

-

ACIC

MUX2

ADPS2

-

ACIS1

MUX1

ADPS1

ADC9

ACIS0

MUX0

ADPS0

ADC8

ADMUX

ADCSR

ADCH

ADCL

ADES

-

ABSY

-

ADRF

-

ADIF

-

ADIE

-

ADC7

PORTE7

DDE7

PINE7

PINF7

ADC6

PORTE6

DDE6

PINE6

PINF6

ADC5

PORTE5

DDE5

PINE5

PINF5

ADC4

PORTE4

DDE4

PINE4

PINF4

ADC3

PORTE3

DDE3

PINE3

PINF3

ADC2

PORTE2

DDE2

PINE2

PINF2

ADC1

ADC0

PORTE

DDRE

PINE

PORTE1

DDE1

PORTE0

DDE0

PINE1

PINF1

PINE0

PINF0

PINF

ATmega603(L) and ATmega103(L)

6

ATmega603(L) and ATmega103(L)

ATmega603/103 Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

ADC

ADIW

SUB

SUBI

SBC

SBCI

SBIW

AND

ANDI

OR

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Rd ← Rd + Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

Rd ← Rd • K

Rd ← Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd v K

Z,N,V

EOR

COM

NEG

SBR

CBR

INC

Rd ← Rd

Rr

Z,N,V

Rd ← $FF - Rd

Rd ← $00 - Rd

Rd ← Rd v K

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd,K

Rd

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Rd ← Rd

•

($FF - K)

Z,N,V

Rd ← Rd + 1

Rd ← Rd - 1

Rd ← Rd • Rd

Z,N,V

DEC

TST

Rd

Decrement

Z,N,V

Rd

Test for Zero or Minus

Clear Register

Z,N,V

CLR

SER

Rd

Rd ← Rd

Rd ← $FF

Rd

Z,N,V

Rd

Set Register

None

BRANCH INSTRUCTIONS

RJMP

IJMP

k

Relative Jump

PC ← PC + k + 1

PC ← Z

PC ← k

PC ← PC + k + 1

PC ← Z

PC ← k

PC ← STACK

None

I

2

Indirect Jump to (Z)

2

JMP

k

Direct Jump

3

RCALL

ICALL

CALL

RET

Relative Subroutine Call

Indirect Call to (Z)

3

k

Direct Subroutine Call

Subroutine Return

4

RETI

Interrupt Return

4

CPSE

CP

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd - Rr

None

Z, N,V,C,H

None

1 / 2

1

Rd,Rr

CPC

Rd,Rr

Compare with Carry

Rd - Rr - C

1

CPI

Rd,K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd - K

1

SBRC

SBRS

SBIC

SBIS

Rr, b

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (P(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC+k + 1

if (SREG(s) = 0) then PC←PC+k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

1 / 2

Rr, b

P, b

s, k

k

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

BRID

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

if (N

V= 0) then PC ← PC + k + 1

V= 1) then PC ← PC + k + 1

k

if (N

k

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

k

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

k

7

ATmega603/103 Instruction Set Summary (Continued)

DATA TRANSFER INSTRUCTIONS

ELPM⁽⁾

MOV

LDI

LD

Extended Load Program Memory

Move Between Registers

Load Immediate

R0 ← (Z+RAMPZ)

Rd ← Rr

Rd ← K

None

3

1

2

3

1

2

Rd, Rr

Rd, K

Rd, X

Load Indirect

Rd ← (X)

LD

Rd, X+

Rd, - X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

LD

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

LD

LDD

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

LD

LDD

LDS

ST

X, Rr

(X) ← Rr

ST

X+, Rr

- X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

ST

STD

ST

(Z) ← Rr

ST

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

In Port

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

(k) ← Rr

R0 ← (Z)

Rd ← P

P ← Rr

STACK ← Rr

Rd ← STACK

ST

STD

STS

LPM

IN

Rd, P

P, Rr

Rr

OUT

PUSH

POP

Out Port

Push Register on Stack

Pop Register from Stack

Rd

BIT AND BIT-TEST INSTRUCTIONS

SBI

P,b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

I/O(P,b) ← 0

Rd(n+1) ← Rd(n), Rd(0) ← 0

Rd(n) ← Rd(n+1), Rd(7) ← 0

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Rd(n) ← Rd(n+1), n=0..6

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

C ← 0

N ← 1

N ← 0

Z ← 1

Z ← 0

I ← 1

I ← 0

S ← 1

S ← 0

V ← 1

V ← 0

T ← 1

None

2

1

3

1

CBI

None

LSL

Z,C,N,V

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Logical Shift Right

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

Z,C,N,V

None

Flag Set

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

T

None

C

Clear Carry

C

Set Negative Flag

N

Clear Negative Flag

Set Zero Flag

N

Z

Clear Zero Flag

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

I

CLI

I

SES

CLS

SEV

CLV

S

V

SET

CLT

T

Clear T in SREG

T ← 0

H ← 1

H ← 0

T

SEH

CLH

NOP

SLEEP

WDR

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

No Operation

H

None

Sleep

(see specific descr. for Sleep function)

(see specific descr. for WD timer)

Watchdog Reset

ATmega603(L) and ATmega103(L)

8

ATmega603(L) and ATmega103(L)

Ordering Information

Speed (MHz)

Power Supply

Ordering Code

Package

Operation Range

4

2.7 - 3.6V

4.0 - 5.5V

2.7 - 3.6V

4.0 - 5.5V

ATmega603L-4AC

64A

Commercial

(0°C to 70°C)

ATmega603L-4AI

ATmega603-6AC

ATmega603-6AI

ATmega103L-4AC

ATmega103L-4AI

ATmega103-6AC

ATmega103-6AI

64A

Industrial

(-40°C to 85°C)

6

4

6

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Package Type

64-Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

64A

9

Packaging Information

64A, 64-Lead, Thin (1.0 mm) Plastic Gull Wing Quad

Flat Package (TQFP)

Dimensions in Millimeters and (Inches)*

16.25(0.640)

SQ

15.75(0.620)

PIN 1 ID

0.45(0.018)

0.30(0.012)

0.80(0.031) BSC

14.10(0.555)

SQ

1.20 (.047) MAX

13.90(0.547)

0.20(0.008)

0-7

0.10(0.004)

0.15(0.006)

0.05(0.002 )

0.75(0.030)

0.45(0.018)

*Controlling dimension: millimeters

ATmega603(L) and ATmega103(L)

10


型号：	ATMEGA103L-4AC
厂家：	ATMEL
描述：	8-Bit Microcontroller with 64K/128K Bytes In-System Programmable Flash 8位微控制器与64K / 128K字节的系统内可编程闪存闪存微控制器
文件：	总10页 (文件大小：284K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ATMEGA103L-4AC [ATMEL]

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