ATSAMA5D35A-CU_技术文档

AT91SAM ARM-based Embedded MPU

SAMA5D3 Series

PRELIMINARY SUMMARY DATASHEET

Description

The Atmel SAMA5D3 series is a high-performance, power-efficient embedded MPU

based on the ARM^®Cortex^™-A5 processor, achieving 536 MHz with power

consumption levels below 0.5 mW in low-power mode. The device features a floating

point unit for high-precision computing and accelerated data processing, and a high

data bandwidth architecture. It integrates advanced user interface and connectivity

peripherals and security features.

The SAMA5D3 series features an internal multi-layer bus architecture associated with

39 DMA channels to sustain the high bandwidth required by the processor and the

high-speed peripherals. The device offers support for DDR2/LPDDR/LPDDR2 and

MLC NAND Flash memory with 24-bit ECC.

The comprehensive peripheral set includes an LCD controller with overlays for

hardware-accelerated image composition, a touchscreen interface and a CMOS

sensor interface. Connectivity peripherals include Gigabit EMAC with IEEE1588,

10/100 EMAC, multiple CAN, UART, SPI and I2C. With its secure boot mechanism,

hardware accelerated engines for encryption (AES, TDES) and hash function (SHA),

the SAMA5D3 ensures anti-cloning, code protection and secure external data

transfers.

The SAMA5D3 series is optimized for control panel/HMI applications and applications

that require high levels of connectivity in the industrial and consumer markets. Its low-

power consumption levels make the SAMA5D3 particularly suited for battery-powered

devices.

There are four SAMA5D3 devices in this series. The following table shows the

differences in the embedded features. All other features are available on all derivatives;

this includes the three USB ports as well as the encryption engine and secure boot

features.

This is a summary document.

The complete document is

available on the Atmel website

at www.atmel.com.

11121AS–ATARM–31-Jan-13

1.

Features

z

Core

z

ARM^®Cortex^™-A5 Processor with ARM v7-A Thumb2^®Instruction Set

CPU Frequency up to 536 MHz

z

32 Kbyte Data Cache, 32 Kbyte Instruction Cache, Virtual Memory System Architecture (VMSA)

Fully Integrated MMU and Floating Point Unit (VFPv4)

z

Memories

z

One 160 Kbyte Internal ROM Single-cycle Access at System Speed, Embedded Boot Loader: Boot on

NAND Flash, SDCard, eMMC, serial DataFlash^®, selectable Order

z

One 128 Kbyte Internal SRAM, Single-cycle Access at System Speed

High Bandwidth 32-bit Multi-port Dynamic Ram Controller supporting 512 Mbyte 8 bank

DDR2/LPDDR/LPDDR2

z

Independent Static Memory Controller with SLC/MLC NAND Support with up to 24-bit Error Correcting Code

(PMECC)

z

System running up to 166 MHz

z

Power-on Reset Cells, Reset Controller, Shut Down Controller, Periodic Interval Timer, Watchdog Timer and

Real Time Clock

z

Boot Mode Select Option, Remap Command

Internal Low-power 32 kHz RC Oscillator and Fast 12 MHz RC Oscillators

Selectable 32768 Hz Low-power Oscillator and 12 MHz Oscillator

One 400 to 1000 MHz PLL for the System and one PLL at 480 MHz optimized for USB High Speed

39 DMA Channels including two 8-channel 64-bit Central DMA Controllers

64-bit Advanced Interrupt Controller

Three Programmable External Clock Signals

Programmable Fuse Box with 256 fuse bits, 192 of them available for Customer

z

Low Power Management

z

Shut Down Controller

Battery Backup Registers

Clock Generator and Power Management Controller

Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities

Peripherals

z

LCD TFT Controller with Overlay, Alpha-blending, Rotation, Scaling and Color Space Conversion

ITU-R BT. 601/656 Image Sensor Interface

Three HS/FS/LS USB Ports with On-Chip Transceivers

z

One Device Controller

One Host Controller with Integrated Root Hub (3 Downstream Ports)

z

One 10/100/1000 Mbps Gigabit Ethernet Mac Controller (GMAC) with IEEE1588 support

One 10/100 Mbps Ethernet Mac Controller (EMAC)

Two CAN Controllers with 8 Mailboxes, fully Compliant with CAN 2.0 Part A and 2.0 Part B

Softmodem Interface

Three High Speed Memory Card Hosts (eMMC 4.3 and SD 2.0)

Two Master/Slave Serial Peripheral Interface

Two Synchronous Serial Controllers

Three Two-wire Interface up to 400 Kbits supporting I2C Protocol and SMBUS

Four USARTs, two UARTs, one DBGU

Two Three-channel 32-bit Timer/Counters

SAMA5D3 Series [SUMMARY DATASHEET]

2

11121AS–ATARM–31-Jan-13

z

One Four-channel 16-bit PWM Controller

One 12-channel 12-bit Analog-to-Digital Converter with Resistive Touch-Screen function

Write Protected Registers

z

Security

z

TRNG: True Random Number Generator

Encryption Engine

z

AES: 256-bit, 192-bit, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications

TDES: Two-key or Three-key Algorithms, Compliant with FIPS PUB 46-3 Specifications

SHA: Supports Secure Hash Algorithm (SHA1, SHA224, SHA256, SHA384, SHA512)

z

Atmel^®Secure Boot Solution

I/O

z

Five 32-bit Parallel Input/Output Controllers

160 I/Os

Input Change Interrupt Capability on Each I/O Line, Selectable Schmitt Trigger Input

Individually Programmable Open-drain, Pull-up and Pull-down Resistor, Synchronous Output, Filtering

Slew Rate Control on High Speed I/Os

Impedance Control on DDR I/Os

Package

324-ball LFBGA, pitch 0.8 mm

z

Table 1-1. SAMA5D3 Devices

SAMA5D31

SAMA5D33

SAMA5D34

SAMA5D35

LCDC

X

GMAC

X

EMAC

X

CAN0, CAN1

HSMCI2

UART0

UART1

TC1

X

SAMA5D3 Series [SUMMARY DATASHEET]

3

11121AS–ATARM–31-Jan-13

2.

Block Diagram

Figure 2-1. SAMA5D3 Block Diagram

T23

A

O

A

V

,

LCD_HSYNC

,

ISI_VSYNC

,

ERXER

V

T0-LCD_D

A

,

GMDIO

,

GCOL

TST

BMS

EREFECTKXEENCRSEDRX0E-TEXR0X-E1TX1

LCD-L

ISI_P SKI_HSYNC

ISI_DO-ISI_CID11

DS_PPWM

DHSD

D

P

H/HSHDSMD/HPHSDMAGTXC

G125CK-G125CK

G

K

T

-

X

G

E

R

G

N

X

C-

C

GR

K

TSG

X

R

E

X

R

E

G

R

R-GX0R-XGDRX7

GTX0-GGMTXD7C

D

CD_

L

V

C

S

D

Y

_

NL

P

CC

C

D

K

_

,

D

L

E

C

N

D

,

_

L

D

C

I

NTRST TDI TDO TMS/TSCW

KD/SIOWCLK

HHSDHPHCSDMC

HHSDPB

HHSDMB

HS

Trans

DDR_VREF

DDR_A0-DDR_A13

DDR_D0-DDR_D31

SysC

JTAG / SWD

PIO

Trans Trans

FIQ

IRQ

AIC

In-Circuit Emulator

DDR_DQM[3..0]

DDR_DQS[3..0]

DDR_DQSN[3..0]

DDR_CS

PA

PC PB

HS EHCI

DRXD

DTXD

DBGU

VFP

Cortex-A5

GMAC

10/100/1000

EMAC

10/100

DDR2

LPDDR2

512 MB

LCD

ISI

PCK0-PCK2

HS USB

Device

USB HOST

DCache

32 KB

ICache

32 KB

PLLA

PLLUTMI

Osc12 MHz

DDR_CLK,DDR_CLKN

DDR_CKE

MMU

BIU

DMA

PMC

PIT

XIN

XOUT

DDR_RAS, DDR_CAS

DDR_WE

I/D

12 MHZ

RC Osc

DDR_BA[2..0]

EBI

D0-D15

A21/NANDALE

A22/NANDCLE

NRD/NANDOE

NWE/NWR0/NANDWE

NCS3/NANDCS

NANDRDY

WDT

RC

4

GPBR

XIN32

XOUT32

SHDN

WKUP

NAND Flash

Controller

MCL/SLC

ECC

OSC 32K

Multi-Layer Matrix

RTC

SHDC

POR

(4 KB SRAM)

VDDBU

NRST

A0/NBS0

RSTC

A1-A20

A23-A25

SHA

AES

TDES

Reduced

Static

Memory

Controller

POR

PIOA

PIOC

TRNG

Peripheral

Bridge

NWR1/NBS1

NCS0,NCS1,NCS2

SRAM0

64 KB

SRAM1

64 KB

PIOB

PIOD

ROM

160 KB

8-CH

DMA0

8-CH

DMA1

DMA

NWAIT

PIOE

DMA

12-CH

12-bit ADC

TouchScreen

DMA

Real-time

Events

USART0

TC0, TC1

TC2, TC3

TC4, TC5

CAN0

CAN1

TWI0

TWI1

TWI2

MCI0/MCI1/MCI2

SD/SDIO

eMMC

4-CH

PWM

UART0

UART1

SSC0

SSC1

SPI0

SPI1

USART1

USART2

USART3

SMD

PIO

A

DIBP

DIBN

A5

TS0-3

-3

MOSMI ISO

A[7..0A] [3..0A] [3..0]

SPCK

CTS0

R

TXD0-3

SCK0-3

RDX0-3

NPCS0

TF0-TF1

TK0-TK1

MCI0M_CCIK1M_CKI2_CK

RK0-RK1

TD0-TD1RF0-RF1

RD0-RD1

A0-TIO

MCI0M_CCDI1M_CCID2_CD

TWD0-TWD2

SPI0_, SPI1_

TIO TIOB0-TIOB5

MCI0_MDCI1_MDCI2_D

TCLK0-TCLK5

PWMH0-PWMH3

PWMFI0-PWMFI3

UTXD0-UTXD1

URDX0-URDX1

TWCK0-TWCK2

CANTX0-CANTX1

PWML0-PWML3

AD2LL

AD1UR

CANRX0-CANRX1

TSADTRIG

NPCS1,NPCS2,NPCS3

SAMA5D3 Series [SUMMARY DATASHEET]

4

11121AS–ATARM–31-Jan-13

3.

Signal Description

Table 3-1 gives details on the signal names classified by peripheral.

Table 3-1. Signal Description List

Signal Name

Frequency

(MHz)

Active

Level

Function

Type

Comments

Clocks, Oscillators and PLLs

XIN

Main Oscillator Input

Input

Output

Input

XOUT

Main Oscillator Output

XIN32

Slow Clock Oscillator Input

XOUT32

VBG

Slow Clock Oscillator Output

Bias Voltage Reference for USB

Programmable Clock Output

Output

Analog

Output

PCK0 - PCK2

Shutdown, Wakeup Logic

SHDN

WKUP

Shut-Down Control

Wake-Up Input

Output

Input

ICE and JTAG

TCK/SWCLK

TDI

Test Clock/Serial Wire Clock

Test Data In

Input

Output

I/O

TDO

Test Data Out

TMS/SWDIO

JTAGSEL

Test Mode Select/Serial Wire Input/Output

JTAG Selection

Input

Reset/Test

NRST

TST

Microcontroller Reset

Test Mode Select

Test Reset Signal

Boot Mode Select

I/O

Low

Input

NTRST

BMS

Debug Unit - DBGU

DRXD

DTXD

Debug Receive Data

Debug Transmit Data

Input

Output

Advanced Interrupt Controller - AIC

IRQ

FIQ

External Interrupt Input

Fast Interrupt Input

Input

PIO Controller - PIOA - PIOB - PIOC - PIOD - PIOE

PA0 - PAxx

PB0 - PBxx

PC0 - PCxx

PD0 - PDxx

PE0 - PExx

Parallel IO Controller A

I/O

Parallel IO Controller B

Parallel IO Controller C

Parallel IO Controller D

Parallel IO Controller E

SAMA5D3 Series [SUMMARY DATASHEET]

5

11121AS–ATARM–31-Jan-13

Table 3-1. Signal Description List (Continued)

Frequency

(MHz)

Active

Level

Signal Name

Function

Type

Comments

External Bus Interface - EBI

D0 - D15

A0 - A25

NWAIT

Data Bus

I/O

Address Bus

Output

External Wait Signal

Input

Low

Static Memory Controller - HSMC

NCS0 - NCS3

NWR0 - NWR1

NRD

Chip Select Lines

Write Signal

Output

Low

Read Signal

NWE

Write Enable

NBS0 - NBS1

NANDOE

NANDWE

Byte Mask Signal

NAND Flash Output Enable

NAND Flash Write Enable

Output

DDR2/LPDDR Controller

DDR_VREF

DDR_CALP

DDR_CALN

Reference Voltage

Input

Positive Calibration Reference

Negative Calibration Reference

DDR_CK,

DDR_CKN

DDR2 differential clock

Output

DDR_CKE

DDR_CS

DDR2 Clock Enable

DDR2 Controller Chip Select

Bank Select

Output

High

Low

DDR_BA[2..0]

DDR_WE

DDR2 Write Enable

DDR_RAS,

DDR_CAS

Row and Column Signal

Output

Low

DDR_A[13..0]

DDR_D[31..0]

DQS[3..0]

DDR2 Address Bus

DDR2 Data Bus

Output

I/O/-PD

I/O- PD

Differential Data Strobe

DQSN must be connected to DDR_VREF for

DDR2 memories

DQSN[3..0]

DQM[3..0]

I/O- PD

Output

Write Data Mask

High Speed Multimedia Card Interface - HSMCI0-2

MCI0_CK,

MCI1_CK, MCI2_CK

Multimedia Card Clock

I/O

MCI0_CDA,MCI1_C

DA, MCI2_CDA

Multimedia Card Command

MCI0_DA[7..0]

MCI1_DA[3..0]

MCI2_DA[3..0)

Multimedia Card 0 Data

Multimedia Card 1 Data

Multimedia Card 2 Data

I/O

SAMA5D3 Series [SUMMARY DATASHEET]

6

11121AS–ATARM–31-Jan-13

Table 3-1. Signal Description List (Continued)

Frequency

(MHz)

Active

Level

Signal Name

Function

Type

Comments

Universal Synchronous Asynchronous Receiver Transmitter- USART0-3

SCKx

TXDx

RXDx

RTSx

CTSx

USARTx Serial Clock

I/O

USARTx Transmit Data

USARTx Receive Data

USARTx Request To Send

USARTx Clear To Send

Output

Input

Output

Input

Universal Asynchronous Receiver Transmitter - UARTx [1..0]

UTXDx

URXDx

UARTx Transmit Data

UARTx Receive Data

Output

Input

Synchronous Serial Controller - SSCx [1..0]

TDx

RDx

TKx

RKx

TFx

RFx

SSC Transmit Data

SSC Receive Data

Output

Input

SSC Transmit Clock

I/O

SSC Receive Clock

SSC Transmit Frame Sync

SSC Receive Frame Sync

Timer/Counter - TCx [5..0]

TCLKx

TIOAx

TIOBx

TC Channel x External Clock Input

TC Channel x I/O Line A

Input

I/O

TC Channel x I/O Line B

I/O

Serial Peripheral Interface - SPIx [1..0]

SPIx_MISO

Master In Slave Out

Master Out Slave In

SPI Serial Clock

I/O

SPIx_MOSI

SPIx_SPCK

SPIx_NPCS0

SPIx_NPCS[3..1]

SPI Peripheral Chip Select 0

SPI Peripheral Chip Select

I/O

Low

Output

Two-Wire Interface -TWIx [2..0]

TWDx

Two-wire Serial Data

Two-wire Serial Clock

I/O

TWCKx

I/O

CAN controller - CANx

CANRXx

CANTXx

CAN input

Input

CAN output

Output

Soft Modem - SMD

DIBN

DIBP

Soft Modem Signal

I/O

SAMA5D3 Series [SUMMARY DATASHEET]

7

11121AS–ATARM–31-Jan-13

Table 3-1. Signal Description List (Continued)

Frequency

(MHz)

Active

Level

Signal Name

Function

Type

Comments

Pulse Width Modulation Controller- PWMC

PWMH[3..0]

PWML[3..0]

PWMFIx

PWM Waveform Output High

Output

Input

PWM Waveform Output LOW

PWM Fault Input

USB Host High Speed Port - UHPHS

HHSDPA

HHSDMA

HHSDPB

HHSDMB

HHSDPC

HHSDMC

USB Host Port A High Speed Data +

Analog

USB Host Port A High Speed Data -

USB Host Port B High Speed Data +

USB Host Port B High Speed Data -

USB Host Port C High Speed Data +

USB Host Port C High Speed Data -

USB Device High Speed Port - UDPHS

DHSDP

DHSDM

USB Device High Speed Data +

USB Device High Speed Data -

Analog

GIgabit Ethernet 10/100/1000 - GMAC

GTXCK

G125CK

G125CKO

GTXEN

GTX[7..0]

GTXER

GRXCK

GRXDV

GRX[7..0]

GRXER

GCRS

Transmit Clock or Reference Clock

Input

125 MHz input Clock

125 MHz output Clock

Transmit Enable

Output

Input

Transmit Data

Transmit Coding Error

Receive Clock

Receive Data Valid

Receive Data

Input

Receive Error

Input

Carrier Sense and Data Valid

Collision Detect

Input

GCOL

Input

GMDC

Management Data Clock

Management Data Input/Output

Output

I/O

GMDIO

RMII Ethernet 10/100 - EMAC

EREFCK

ETXEN

Transmit Clock or Reference Clock

Input

Output

Input

Transmit Enable

Transmit Data

ETX[1..0]

ECRSDV

ERX[1..0]

ERXER

Carrier Sense/Data Valid

Receive Data

Input

Receive Error

Input

SAMA5D3 Series [SUMMARY DATASHEET]

8

11121AS–ATARM–31-Jan-13

Table 3-1. Signal Description List (Continued)

Frequency

(MHz)

Active

Level

Signal Name

EMDC

Function

Management Data Clock

Type

Output

I/O

Comments

EMDIO

Management Data Input/Output

LCD Controller - LCDC

LCDDAT[23..0]

LCDVSYNC

LCDHSYNC

LCDPCK

LCD Data Bus

Output

LCD Vertical Synchronization

LCD Horizontal Synchronization

LCD pixel Clock

LCDDEN

LCD Data Enable

LCDPWM

LCDPWM for Contrast Control

LCD Display ON/OFF

LCDDISP

Image Sensor Interface - ISI

ISI_D[11..0]

ISI_HSYNC

ISI_VSYNC

ISI_PCK

Image Sensor Data

Input

Image Sensor Horizontal Synchro

Image Sensor Vertical Synchro

Image Sensor Data clock

input

Touch Screen Analog-to-Digital Converter - ADC

AD0_UL

Upper Left Touch Panel

Analog

Input

AD1_UR

Upper Right Touch Panel

Lower Left Touch Panel

Lower Right Touch Panel

Panel Input

AD2_LL

AD3_LR

AD4_PI

AD5-AD11

ADTRG

ADVREF

7 Analog Inputs

ADC Trigger

ADC Reference

Analog

SAMA5D3 Series [SUMMARY DATASHEET]

9

11121AS–ATARM–31-Jan-13

4.

Package and Pinout

The SAMA5D3 product is available in a 324-ball LFBGA package.

4.1

Mechanical Overview of the 324-ball LFBGA Package

Figure 4-1 shows the orientation of the 324-ball BGA Package.

Figure 4-1. Orientation of the 324-ball LFBGA Package

Bottom VIEW

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1

2

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

SAMA5D3 Series [SUMMARY DATASHEET]

10

11121AS–ATARM–31-Jan-13

4.2

324-ball LFBGA Package Pinout

Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package

Primary

Alternate

PIO Peripheral A

PIO Peripheral B

PIO Peripheral C

Reset State

Signal, Dir,

PU, PD, HiZ,

ST

E3

F5

D2

F4

D1

J10

G4

J9

Power Rail

VDDIOP0

VDDIOP1

I/O Type

GPIO

GPIO_CLK2

GPIO

GMAC

Signal

Dir

I/O

Signal

Dir

Signal

LCDDAT0

LCDDAT1

LCDDAT2

LCDDAT3

LCDDAT4

LCDDAT5

LCDDAT6

LCDDAT7

LCDDAT8

LCDDAT9

LCDDAT10

LCDDAT11

LCDDAT12

LCDDAT13

LCDDAT14

LCDDAT15

LCDDAT16

LCDDAT17

LCDDAT18

LCDDAT19

LCDDAT20

LCDDAT21

LCDDAT22

LCDDAT23

LCDPWM

LCDDISP

LCDVSYNC

LCDHSYNC

LCDPCK

LCDDEN

TWD0

Dir

Signal

Dir

Signal

Dir

PA0

PA1

O

I/O

O

I

PIO, I, PU, ST

PA2

PA3

PA4

PA5

PA6

PA7

F3

J8

PA8

PA9

E2

K8

F2

G6

E1

H5

H3

H6

H4

H7

H2

J6

PA10

PA11

PA12

PA13

PA14

PA15

PA16

PA17

PA18

PA19

PA20

PA21

PA22

PA23

PA24

PA25

PA26

PA27

PA28

PA29

PA30

PA31

PB0

ISI_D0

ISI_D1

ISI_D2

ISI_D3

ISI_D4

ISI_D5

ISI_D6

ISI_D7

I

TWD2

TWCK2

PWMH0

PWML0

PWMH1

PWML1

I/O

O

G2

J5

O

F1

J4

G3

J3

G1

K4

H1

K3

T2

N7

T3

N6

P5

T4

R4

U1

R5

P3

URXD1

UTXD1

PWMH0

PWML0

TK1

I

O

I/O

O

I

ISI_VSYNC

ISI_HSYNC

I

TWCK0

GTX0

PB1

GTX1

PB2

GTX2

PB3

GTX3

TF1

PB4

GRX0

PWMH1

PWML1

TD1

PB5

GRX1

I

PB6

GRX2

I

PB7

GRX3

I

RK1

PB8

GTXCK

I

PWMH2

PWML2

O

PB9

GTXEN

O

SAMA5D3 Series [SUMMARY DATASHEET]

11

11121AS–ATARM–31-Jan-13

Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package (Continued)

Primary

Alternate

PIO Peripheral A

PIO Peripheral B

PIO Peripheral C

Reset State

Signal, Dir,

PU, PD, HiZ,

ST

R6

V3

P6

V1

R7

U3

P7

V2

V5

T6

N8

U4

M7

U5

M8

T5

N9

V4

M9

P8

M10

R9

D8

A4

E8

A3

A2

F8

B3

G8

B4

F7

A1

D7

C6

E7

B2

F6

B1

E6

C3

D6

C4

D5

Power Rail

VDDIOP1

VDDIOP0

I/O Type

GMAC

GPIO

Signal

Dir

I/O

Signal

Dir

Signal

GTXER

GRXCK

GRXDV

GRXER

GCRS

Dir

Signal

RF1

Dir

Signal

Dir

PB10

PB11

PB12

PB13

PB14

PB15

PB16

PB17

PB18

PB19

PB20

PB21

PB22

PB23

PB24

PB25

PB26

PB27

PB28

PB29

PB30

PB31

PC0

O

I

I/O

I

PIO, I, PU, ST

RD1

I

PWMH3

PWML3

CANRX1

CANTX1

O

I

GCOL

I

O

GMDC

O

I/O

I

GMDIO

G125CK

MCI1_CDA

MCI1_DA0

MCI1_DA1

MCI1_DA2

MCI1_DA3

MCI1_CK

SCK1

I/O

I

GTX4

GTX5

O

I

GTX6

GTX7

GRX4

GRX5

GRX6

GRX7

G125CKO

I

CTS1

I

RTS1

O

I

O

GPIO

RXD1

GPIO

TXD1

O

I

GPIO

DRXD

GPIO

DTXD

O

I

GPIO

ETX0

TIOA3

TIOB3

TCLK3

TIOA4

TIOB4

TCLK4

TIOA5

TIOB5

TCLK5

I/O

I

GPIO

PC1

ETX1

GPIO

PC2

ERX0

GPIO

PC3

ERX1

I

I/O

I

GPIO

PC4

ETXEN

ECRSDV

ERXER

EREFCK

EMDC

O

I

GPIO

PC5

GPIO

PC6

I

I/O

I

GPIO

PC7

I

GPIO

PC8

O

I/O

O

I/O

I

GPIO

PC9

EMDIO

MCI2_CDA

MCI2_DA0

MCI2_DA1

MCI2_DA2

MCI2_DA3

MCI2_CK

TK0

GPIO

PC10

PC11

PC12

PC13

PC14

PC15

PC16

PC17

PC18

PC19

PC20

PC21

LCDDAT20

LCDDAT19

LCDDAT18

LCDDAT17

LCDDAT16

LCDDAT21

O

GPIO

TIOA1

TIOB1

TCLK1

PCK2

I/O

I

GPIO

MCI_CLK

GPIO

O

GPIO

TF0

GPIO

TD0

GPIO

RK0

GPIO

RF0

GPIO

RD0

SAMA5D3 Series [SUMMARY DATASHEET]

12

11121AS–ATARM–31-Jan-13

Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package (Continued)

Primary

Alternate

PIO Peripheral A

PIO Peripheral B

PIO Peripheral C

Reset State

Signal, Dir,

PU, PD, HiZ,

ST

C2

G9

C1

H10

H9

D4

H8

G5

D3

E4

K5

P1

K6

R1

L7

Power Rail

VDDIOP0

VDDIOP1

VDDANA

VDDIOM

I/O Type

GPIO

Signal

Dir

I/O

Signal

Dir

Signal

SPI1_MISO

SPI1_MOSI

SPI1_SPCK

SPI1_NPCS0

SPI1_NPCS1

SPI1_NPCS2

SPI1_NPCS3

URXD0

Dir

Signal

Dir

Signal

Dir

PC22

PC23

PC24

PC25

PC26

PC27

PC28

PC29

PC30

PC31

PD0

I/O

O

I

PIO, I, PU, ST

A,I, PD, ST

GPIO

GPIO_CLK

GPIO

TWD1

TWCK1

PWMFI0

PWMFI2

I/O

ISI_D11

ISI_D10

ISI_D9

I

GPIO

O

I

GPIO

I

GPIO

I

ISI_D8

I

GPIO

UTXD0

O

I

ISI_PCK

O

GPIO

FIQ

PWMFI1

I

GPIO

MCI0_CDA

MCI0_DA0

MCI0_DA1

MCI0_DA2

MCI0_DA3

MCI0_DA4

MCI0_DA5

MCI0_DA6

MCI0_DA7

MCI0_CK

SPI0_MISO

SPI0_MOSI

SPI0_SPCK

SPI0_NPCS0

SCK0

I/O

I

GPIO

PD1

GPIO

PD2

GPIO

PD3

GPIO

PD4

P2

L8

GPIO

PD5

TIOA0

TIOB0

TCLK0

I/O

I

PWMH2

PWML2

PWMH3

PWML3

O

GPIO

PD6

R2

K7

U2

K9

M5

K10

N4

L9

GPIO

PD7

GPIO

PD8

MCI_CLK

GPIO

PD9

PD10

PD11

PD12

PD13

PD14

PD15

PD16

PD17

PD18

PD19

PD20

PD21

PD22

PD23

PD24

PD25

PD26

PD27

PD28

PD29

PD30

PD31

PE0

GPIO

GPIO_CLK

GPIO

SPI0_NPCS1

SPI0_NPCS2

SPI0_NPCS3

O

CANRX0

CANTX0

PWMFI3

I

O

I

N3

L10

N5

M6

T1

GPIO

CTS0

GPIO

RTS0

O

I

GPIO

RXD0

GPIO

TXD0

O

I

GPIO

ADTRG

AD0

N2

M3

M2

L3

GPIO_ANA

EBI

I

AD1

I

AD2

I

AD3

I

M1

N1

L1

AD4

I

AD5

I

AD6

I

L2

AD7

I

K1

K2

J1

AD8

I

AD9

I

AD10

I

PCK0

PCK1

O

J2

AD11

I

P13

R14

A0/NBS0

A1

O

EBI

PE1

A,I, PD, ST

SAMA5D3 Series [SUMMARY DATASHEET]

13

11121AS–ATARM–31-Jan-13

Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package (Continued)

Primary

Alternate

PIO Peripheral A

PIO Peripheral B

PIO Peripheral C

Reset State

Signal, Dir,

PU, PD, HiZ,

ST

R13

V18

P14

U18

T18

R15

P17

P15

P18

R16

N16

R17

N17

R18

N18

P16

M18

N15

M15

N14

M17

M13

M16

N12

M14

M12

L13

L15

L14

L16

U15

U9

Power Rail

VDDIOM

VDDBU

I/O Type

EBI

Signal

Dir

I/O

I

Signal

Dir

Signal

Dir

Signal

Dir

Signal

Dir

PE2

PE3

A2

O

I

A,I, PD, ST

PIO,I, PD, ST

PIO, I, PD, ST

PIO,I, PD, ST

I, PD,

EBI

A3

A4

EBI

PE4

EBI

PE5

A5

EBI

PE6

A6

EBI

PE7

A7

EBI

PE8

A8

EBI

PE9

A9

EBI

PE10

PE11

PE12

PE13

PE14

PE15

PE16

PE17

PE18

PE19

PE20

PE21

PE22

PE23

PE24

PE25

PE26

PE27

PE28

PE29

PE30

PE31

TST

A10

EBI

A11

EBI

A12

EBI

A13

EBI

A14

EBI

A15

SCK3

CTS3

RTS3

RXD3

TXD3

SCK2

I/O

I

EBI

A16

EBI

A17

O

I

EBI

A18

EBI

A19

O

I/O

EBI

A20

EBI

A21/NANDALE

A22/NANDCLE

A23

EBI

CTS2

RTS2

RXD2

TXD2

TIOA2

TIOB2

TCLK2

I

O

I

EBI

A24

EBI

A25

EBI

NCS0

NCS1

NCS2

NWR1/NBS1

NWAIT

IRQ

O

I/O

I

EBI

LCDDAT22

LCDDAT23

O

EBI

I

PWML1

O

SYSC

CLOCK

SYSC

RSTJTAG

VDDIOP0

VDDBU

BMS

I

U8

XIN

I

V8

XOUT

XIN32

XOUT32

SHDN

WKUP

NRST

NTRST

TDI

O

U16

V16

T12

T10

V9

I

VDDBU

O

VDDBU

O

O, PU

VDDBU

I

I, ST

VDDIOP0

I/O

I

I, PU, ST

I, ST

P11

R8

I

M11

N10

P9

TDO

O

TMS

I

SWDIO

SWCLK

I/O

I

I, ST

TCK

I

I, ST

SAMA5D3 Series [SUMMARY DATASHEET]

14

11121AS–ATARM–31-Jan-13

Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package (Continued)

Primary

Alternate

PIO Peripheral A

PIO Peripheral B

PIO Peripheral C

Reset State

Signal, Dir,

PU, PD, HiZ,

ST

T9

Power Rail

VDDBU

I/O Type

SYSC

DIB

EBI

Signal

Dir

I

Signal

Dir

Signal

Dir

Signal

Dir

Signal

Dir

JTAGSEL

DIBP

I, PD

O, PU

I, PD

O, PU

I, PU

O, PU

I

V6

VDDIOP0

VDDIOM

O

U6

DIBN

O

K12

K15

K14

K16

K13

K17

J12

K18

J14

J16

J13

J17

J15

J18

H16

H18

L12

L18

L17

K11

C13

B10

C11

A9

D0

I/O

O

VDDIOM

EBI

D1

VDDIOM

EBI

D2

VDDIOM

EBI

D3

VDDIOM

EBI

D4

VDDIOM

EBI

D5

VDDIOM

EBI

D6

VDDIOM

EBI

D7

VDDIOM

EBI

D8

VDDIOM

EBI

D9

VDDIOM

EBI

D10

VDDIOM

EBI

D11

VDDIOM

EBI

D12

VDDIOM

EBI

D13

VDDIOM

EBI

D14

VDDIOM

EBI

D15

VDDIOM

EBI

NCS3/NANDCS

NANDRDY

NRD/NANDOE

NWE/NANDWE

DDR_VREF

DDR_A0

DDR_A1

DDR_A2

DDR_A3

DDR_A4

DDR_A5

DDR_A6

DDR_A7

DDR_A8

DDR_A9

DDR_A10

DDR_A11

DDR_A12

DDR_A13

DDR_D0

DDR_D1

DDR_D2

DDR_D3

DDR_D4

DDR_D5

VDDIOM

EBI

I

VDDIOM

EBI

O

VDDIOM

EBI

O

VDDIODDR

I

DDR_IO

O

D11

B9

O

E10

D10

A8

O

C10

B8

O

F11

A7

O

D9

O

A6

O

H12

H17

H13

G17

G16

H15

I/O

HiZ

SAMA5D3 Series [SUMMARY DATASHEET]

15

11121AS–ATARM–31-Jan-13

Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package (Continued)

Primary

Alternate

PIO Peripheral A

PIO Peripheral B

PIO Peripheral C

Reset State

Signal, Dir,

PU, PD, HiZ,

ST

F17

G15

F16

E17

G14

E16

D17

C18

D16

C17

B16

B18

C15

A18

C16

C14

D15

B14

A15

A14

E12

A11

B11

F12

A10

E11

G12

E15

B15

D12

E18

G18

B17

B13

D18

F18

A17

A13

C8

Power Rail

VDDIODDR

I/O Type

DDR_IO

Signal

Dir

I/O

O

Signal

Dir

Signal

Dir

Signal

Dir

Signal

Dir

DDR_D6

DDR_D7

HiZ

O

DDR_D8

DDR_D9

DDR_D10

DDR_D11

DDR_D12

DDR_D13

DDR_D14

DDR_D15

DDR_D16

DDR_D17

DDR_D18

DDR_D19

DDR_D20

DDR_D21

DDR_D22

DDR_D23

DDR_D24

DDR_D25

DDR_D26

DDR_D27

DDR_D28

DDR_D29

DDR_D30

DDR_D31

DDR_DQM0

DDR_DQM1

DDR_DQM2

DDR_DQM3

DDR_DQS0

DDR_DQS1

DDR_DQS2

DDR_DQS3

DDR_DQSN0

DDR_DQSN1

DDR_DQSN2

DDR_DQSN3

DDR_CS

O

I/O

O

I, PD

I, PU

O

B12

A12

B7

DDR_CLK

DDR_CLKN

DDR_CKE

DDR_CALN

DDR_CALP

O

C12

E13

I

O

I

O

SAMA5D3 Series [SUMMARY DATASHEET]

16

11121AS–ATARM–31-Jan-13

Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package (Continued)

Primary

Alternate

PIO Peripheral A

PIO Peripheral B

PIO Peripheral C

Reset State

Signal, Dir,

PU, PD, HiZ,

ST

G11

A5

Power Rail

VDDIODDR

VBG

I/O Type

DDR_IO

VBG

Signal

Dir

O

Signal

Dir

Signal

Dir

Signal

Dir

Signal

Dir

DDR_RAS

DDR_CAS

DDR_WE

DDR_BA0

DDR_BA1

DDR_BA2

VBG

O

B5

O

E9

O

B6

O

F9

O

R11

U14

V14

U12

V12

U10

V10

V15

T13

I

VDDUTMII

VDDBU

USBHS

power supply

ground

HHSDPC

HHSDMC

HHSDPB

HHSDMB

HHSDPA

HHSDMA

VDDBU

I/O

I

O, PD

I

DHSDP

DHSDM

GNDBU

I

C5,

C7,

D14,

T15,

T7,

U17,

V7

VDDCORE

GNDCORE

power supply

VDDCORE

GNDCORE

I

A16,

C9,

N13,

T14,

T8,

ground

V17

D13,

F14,

G10,

G13,

H11

VDDIODDR

GNDIODDR

power supply

ground

VDDIODDR

GNDIODDR

I

E14,

F10,

F13,

F15,

H14

P12,

T16

VDDIOM

GNDIOM

VDDIOP0

VDDIOP1

power supply

ground

VDDIOM

GNDIOM

VDDIOP0

VDDIOP1

I

J11,

T17

G7,

V11

power supply

L11,

M4

E5,

J7,

N11,

U7

GNDIOP

ground

GNDIOP

I

V13

U13

R12

R10

P10

U11

T11

VDDUTMIC

VDDUTMII

GNDUTMI

VDDPLLA

GNDPLL

power supply

ground

VDDUTMIC

VDDUTMII

GNDUTMI

VDDPLLA

GNDPLL

I

power supply

ground

VDDOSC

GNDOSC

power supply

ground

VDDOSC

GNDOSC

SAMA5D3 Series [SUMMARY DATASHEET]

17

11121AS–ATARM–31-Jan-13

Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package (Continued)

Primary

Alternate

PIO Peripheral A

PIO Peripheral B

PIO Peripheral C

Reset State

Signal, Dir,

PU, PD, HiZ,

ST

L6

Power Rail

VDDANA

I/O Type

power supply

ground

Signal

Dir

Signal

Dir

Signal

Dir

Signal

Dir

Signal

Dir

VDDANA

GNDANA

ADVREF

I

L4

GNDANA

L5

VDDANA

power supply

ground

R3

P4

VDDFUSE

GNDFUSE

VDDFUSE

GNDFUSE

SAMA5D3 Series [SUMMARY DATASHEET]

18

11121AS–ATARM–31-Jan-13

5.

Mechanical Characteristics

Figure 5-1. 324-ball LFBGA Package Drawing

TITLE

Low Proﬁle Fine Pitch Ball Grid Array

324

Table 5-1. 324-ball LFBGA Package Characteristics

Moisture Sensitivity Level

3

Table 5-2. Device and 324-ball LFBGA Package Maximum Weight

400

mg

Table 5-3. Package Reference

JEDEC Drawing Reference

JESD97 Classification

MO-275-KAAE-1

e8

Table 5-4. Package Information

Ball Land

0.350 mm ± 0.05

0.275 mm ± 0.05

SMD

Solder Mask Opening

Solder Mask Definition

SAMA5D3 Series [SUMMARY DATASHEET]

19

11121AS–ATARM–31-Jan-13

6.

SAMA5D3 Ordering Information

Table 6-1. SAMA5D3 Ordering Information

Ordering Code

Package

Package Type

Temperature Operating Range

Industrial

-40°C to 85°C

ATSAMA5D31A-CU

BGA324

Green

Industrial

ATSAMA5D33A-CU

ATSAMA5D34A-CU

ATSAMA5D35A-CU

Green

-40°C to 85°C

Industrial

BGA324

-40°C to 85°C

Industrial

-40°C to 85°C

SAMA5D3 Series [SUMMARY DATASHEET]

20

11121AS–ATARM–31-Jan-13

Revision History

In the table that follows, the most recent version of the document appears first.

“rfo” indicates changes requested during the document review and approval loop.

Table 6-2.

Change

Doc. Rev

Comments

Request Ref.

11121AS

First issue

SAMA5D3 Series [SUMMARY DATASHEET]

21

11121AS–ATARM–31-Jan-13

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型号：	ATSAMA5D35A-CU
厂家：	ATMEL
描述：	The Atmel SAMA5D3 series is a high-performance, power-efficient embedded MPU based on the ARMÂ® Cortexâ¢-A5 processor, achieving 536 MHz with power consumption levels below 0.5 mW in low-power mode. 爱特梅尔SAMA5D3系列是一款高性能，低功耗的嵌入式基础上， ARMÂ® Cortexâ ?? ¢ -A5处理器MPU，实现536 MHz的低于0.5毫瓦的功耗水平，低功耗模式。
文件：	总22页 (文件大小：534K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ATSAMA5D35A-CU [ATMEL]

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