ATTINY13_10 [ATMEL]
8-bit Microcontroller with 1K Bytes In-System Programmable Flash; 8 -bit微控制器1K字节的系统内可编程闪存
| 型号： | ATTINY13_10 |
| 厂家： | 
ATMEL |
| 描述： | 8-bit Microcontroller with 1K Bytes In-System Programmable Flash |
| 文件： | 总22页 (文件大小：560K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Througput at 20 MHz
• High Endurance Non-volatile Memory segments
– 1K Bytes of In-System Self-programmable Flash program memory
– 64 Bytes EEPROM
8-bit
– 64 Bytes Internal SRAM
Microcontroller
with 1K Bytes
In-System
Programmable
Flash
– Write/Erase cyles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C (see page 6)
– Programming Lock for Self-Programming Flash & EEPROM Data Security
• Peripheral Features
– One 8-bit Timer/Counter with Prescaler and Two PWM Channels
– 4-channel, 10-bit ADC with Internal Voltage Reference
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
ATtiny13
ATtiny13V
• I/O and Packages
Summary
– 8-pin PDIP/SOIC: Six Programmable I/O Lines
– 20-pad MLF: Six Programmable I/O Lines
• Operating Voltage:
– 1.8 - 5.5V for ATtiny13V
– 2.7 - 5.5V for ATtiny13
• Speed Grade
– ATtiny13V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
– ATtiny13: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
• Industrial Temperature Range
• Low Power Consumption
– Active Mode:
• 1 MHz, 1.8V: 240 µA
– Power-down Mode:
• < 0.1 µA at 1.8V
Rev. 2535JS–AVR–08/10
1. Pin Configurations
Figure 1-1. Pinout ATtiny13/ATtiny13V
8-PDIP/SOIC
(PCINT5/RESET/ADC0/dW) PB5
(PCINT3/CLKI/ADC3) PB3
(PCINT4/ADC2) PB4
GND
1
2
3
4
8
7
6
5
VCC
PB2 (SCK/ADC1/T0/PCINT2)
PB1 (MISO/AIN1/OC0B/INT0/PCINT1)
PB0 (MOSI/AIN0/OC0A/PCINT0)
20-QFN/MLF
(PCINT5/RESET/ADC0/dW) PB5
(PCINT3/CLKI/ADC3) PB3
DNC
1
15
VCC
2
3
4
5
14
13
12
11
PB2 (SCK/ADC1/T0/PCINT2)
DNC
DNC
PB1 (MISO/AIN1/OC0B/INT0/PCINT1)
PB0 (MOSI/AIN0/OC0A/PCINT0)
(PCINT4/ADC2) PB4
NOTE: Bottom pad should be soldered to ground.
DNC: Do Not Connect
10-QFN/MLF
(PCINT5/RESET/ADC0/dW) PB5
(PCINT3/CLKI/ADC3) PB3
DNC
1
2
3
4
5
10
9
VCC
PB2 (SCK/ADC1/T0/PCINT2)
DNC
8
(PCINT4/ADC2) PB4
GND
7
PB1 (MISO/AIN1/OC0B/INT0/PCINT1)
PB0 (MOSI/AIN0/OC0A/PCINT0)
6
NOTE: Bottom pad should be soldered to ground.
DNC: Do Not Connect
2
ATtiny13
2535JS–AVR–08/10
ATtiny13
1.1
Pin Descriptions
1.1.1
VCC
Digital supply voltage.
1.1.2
1.1.3
GND
Ground.
Port B (PB5:PB0)
Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny13 as listed on page 54.
1.1.4
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 18-1 on page
115. Shorter pulses are not guaranteed to generate a reset.
The reset pin can also be used as a (weak) I/O pin.
3
2535JS–AVR–08/10
2. Overview
The ATtiny13 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATtiny13 achieves
throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con-
sumption versus processing speed.
2.1
Block Diagram
Figure 2-1. Block Diagram
8-BIT DATABUS
STACK
POINTER
CALIBRATED
INTERNAL
OSCILLATOR
WATCHDOG
OSCILLATOR
SRAM
WATCHDOG
TIMER
TIMING AND
CONTROL
VCC
GND
MCU CONTROL
REGISTER
PROGRAM
COUNTER
MCU STATUS
REGISTER
PROGRAM
FLASH
TIMER/
COUNTER0
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTERS
INTERRUPT
UNIT
X
Y
Z
PROGRAMMING
LOGIC
INSTRUCTION
DECODER
DATA
EEPROM
CONTROL
LINES
ALU
STATUS
REGISTER
ADC /
ANALOG COMPARATOR
DATA REGISTER
PORT B
DATA DIR.
REG.PORT B
PORT B DRIVERS
RESET
CLKI
PB0-PB5
4
ATtiny13
2535JS–AVR–08/10
ATtiny13
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATtiny13 provides the following features: 1K byte of In-System Programmable Flash, 64
bytes EEPROM, 64 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working reg-
isters, one 8-bit Timer/Counter with compare modes, Internal and External Interrupts, a 4-
channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three soft-
ware selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM,
Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The
Power-down mode saves the register contents, disabling all chip functions until the next Inter-
rupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules
except ADC, to minimize switching noise during ADC conversions.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code
running on the AVR core.
The ATtiny13 AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation kits.
5
2535JS–AVR–08/10
3. General Information
3.1
Resources
A comprehensive set of drivers, application notes, data sheets and descriptions on development
tools are available for download at http://www.atmel.com/avr.
3.2
Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. These code examples assume that the part specific header file is included before
compilation. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-
tation for more details.
3.3
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
6
ATtiny13
2535JS–AVR–08/10
ATtiny13
4. Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x3F
0x3E
0x3D
0x3C
0x3B
0x3A
0x39
0x38
0x37
0x36
0x35
0x34
0x33
0x32
0x31
0x30
0x2F
0x2E
0x2D
0x2C
0x2B
0x2A
0x29
0x28
0x27
0x26
0x25
0x24
0x23
0x22
0x21
0x20
0x1F
0x1E
0x1D
0x1C
0x1B
0x1A
0x19
0x18
0x17
0x16
0x15
0x14
0x13
0x12
0x11
0x10
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
SREG
Reserved
SPL
I
T
–
H
–
S
–
V
–
N
–
Z
–
C
–
page 9
–
SP[7:0]
–
page 11
Reserved
GIMSK
–
–
–
–
–
INT0
PCIE
–
–
–
–
–
–
–
page 46
page 47
page 74
page 75
page 97
page 74
page 32
page 41
page 72
page 73
page 27
GIFR
INTF0
PCIF
–
–
–
–
–
TIMSK0
TIFR0
–
–
–
–
–
–
OCIE0B
OCF0B
RFLB
OCIE0A
OCF0A
PGWRT
TOIE0
TOV0
PGERS
–
–
SELFPR-
SPMCSR
OCR0A
MCUCR
MCUSR
TCCR0B
TCNT0
CTPB
Timer/Counter – Output Compare Register A
–
–
PUD
–
SE
–
SM1
SM0
–
ISC01
EXTRF
CS01
ISC00
PORF
CS00
–
–
WDRF
WGM02
BORF
CS02
FOC0A
FOC0B
–
Timer/Counter (8-bit)
OSCCAL
Reserved
TCCR0A
DWDR
Oscillator Calibration Register
–
COM0A1
COM0A0
COM0B1
COM0B0
DWDR[7:0]
–
–
WGM01
WGM00
page 69
page 96
Reserved
Reserved
Reserved
Reserved
OCR0B
GTCCR
Reserved
CLKPR
–
–
–
–
Timer/Counter – Output Compare Register B
page 74
page 77
TSM
–
–
–
–
–
–
–
–
PSR10
–
CLKPCE
–
CLKPS3
CLKPS2
CLKPS1
CLKPS0
page 28
Reserved
Reserved
Reserved
Reserved
WDTCR
Reserved
Reserved
EEARL
–
–
–
–
WDTIF
WDTIE
WDP3
WDCE
WDE
WDP2
WDP1
EEPE
WDP0
EERE
page 41
–
–
–
–
–
–
EEPROM Address Register
EEPROM Data Register
page 20
page 20
page 21
EEDR
EECR
EEPM1
EEPM0
EERIE
EEMPE
Reserved
Reserved
Reserved
PORTB
DDRB
–
–
–
–
–
–
–
–
–
–
–
–
–
PORTB5
DDB5
PORTB4
DDB4
PORTB3
DDB3
PORTB2
DDB2
PORTB1
DDB1
PORTB0
DDB0
page 56
page 56
PINB
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
page 57
PCMSK
DIDR0
PCINT5
ADC0D
PCINT4
ADC2D
PCINT3
ADC3D
PCINT2
ADC1D
PCINT1
AIN1D
PCINT0
AIN0D
page 47
page 80, page 94
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ACSR
–
–
–
–
–
–
–
–
–
–
–
ACD
–
ACBG
REFS0
ADSC
ACO
ACI
–
ACIE
–
–
–
ACIS1
MUX1
ADPS1
ACIS0
MUX0
ADPS0
page 79
page 91
page 92
page 93
page 93
page 94
ADMUX
ADCSRA
ADCH
ADLAR
ADATE
ADEN
ADIF
ADIE
ADPS2
ADC Data Register High Byte
ADC Data Register Low Byte
ADCL
ADCSRB
Reserved
Reserved
Reserved
–
ACME
–
–
–
ADTS2
ADTS1
ADTS0
–
–
–
7
2535JS–AVR–08/10
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.ome of the Status Flags are
cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation
the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work
with registers 0x00 to 0x1F only.
8
ATtiny13
2535JS–AVR–08/10
ATtiny13
5. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
ADC
ADIW
SUB
SUBI
SBC
SBCI
SBIW
AND
ANDI
OR
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add two Registers
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Rd ← Rd + Rr
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
Rd ← Rd • K
Z,N,V
Rd ← Rd v Rr
Z,N,V
ORI
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Rd ← Rd v K
Z,N,V
EOR
COM
NEG
SBR
CBR
INC
Rd ← Rd ⊕ Rr
Rd ← 0xFF − Rd
Rd ← 0x00 − Rd
Rd ← Rd v K
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Rd
Two’s Complement
Rd,K
Rd,K
Rd
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Rd ← Rd • (0xFF - K)
Rd ← Rd + 1
Z,N,V
Z,N,V
DEC
TST
Rd
Decrement
Rd ← Rd − 1
Z,N,V
Rd
Test for Zero or Minus
Clear Register
Rd ← Rd • Rd
Rd ← Rd ⊕ Rd
Rd ← 0xFF
Z,N,V
CLR
SER
Rd
Z,N,V
Rd
Set Register
None
BRANCH INSTRUCTIONS
RJMP
IJMP
k
k
Relative Jump
Indirect Jump to (Z)
PC ← PC + k + 1
PC ← Z
None
None
None
None
None
I
2
2
RCALL
ICALL
RET
Relative Subroutine Call
Indirect Call to (Z)
PC ← PC + k + 1
3
PC ← Z
3
Subroutine Return
PC ← STACK
4
RETI
Interrupt Return
PC ← STACK
4
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1/2/3
1
Rd,Rr
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
1
CPI
Rd,K
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd − K
1
SBRC
SBRS
SBIC
Rr, b
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
Rr, b
P, b
P, b
s, k
s, k
k
SBIS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
k
Branch if Not Equal
k
Branch if Carry Set
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
k
k
k
Branch if Minus
k
Branch if Plus
k
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
k
k
k
k
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
k
k
k
BRID
k
BIT AND BIT-TEST INSTRUCTIONS
SBI
CBI
P,b
P,b
Rd
Rd
Rd
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
I/O(P,b) ← 1
I/O(P,b) ← 0
None
None
2
2
1
1
1
LSL
LSR
ROL
Rd(n+1) ← Rd(n), Rd(0) ← 0
Rd(n) ← Rd(n+1), Rd(7) ← 0
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
Z,C,N,V
Z,C,N,V
Logical Shift Right
Rotate Left Through Carry
9
2535JS–AVR–08/10
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Rd
Rd
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
Rd
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
s
Flag Set
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C ← 1
SREG(s)
s
Flag Clear
SREG(s)
Rr, b
Rd, b
Bit Store from Register to T
Bit load from T to Register
Set Carry
T
None
C
C
N
N
Z
Clear Carry
C ← 0
Set Negative Flag
N ← 1
Clear Negative Flag
Set Zero Flag
N ← 0
Z ← 1
Clear Zero Flag
Z ← 0
Z
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
I ← 1
I
CLI
I ← 0
I
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
S ← 1
S
S ← 0
S
V ← 1
V
V ← 0
V
T ← 1
T
Clear T in SREG
T ← 0
T
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H ← 1
H
H
H ← 0
DATA TRANSFER INSTRUCTIONS
MOV
MOVW
LDI
LD
Rd, Rr
Rd, Rr
Rd, K
Move Between Registers
Copy Register Word
Rd ← Rr
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
Rd+1:Rd ← Rr+1:Rr
Load Immediate
Rd ← K
Rd ← (X)
Rd, X
Load Indirect
LD
Rd, X+
Rd, - X
Rd, Y
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
LD
LD
LD
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Y + q)
Rd ← (Z)
LD
LDD
LD
LD
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Rd ← (Z), Z ← Z+1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
Rd ← (k)
LD
LDD
LDS
ST
X, Rr
(X) ← Rr
ST
X+, Rr
- X, Rr
Y, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
ST
ST
ST
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Y + q) ← Rr
ST
STD
ST
(Z) ← Rr
ST
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
Load Program Memory
Load Program Memory and Post-Inc
Store Program Memory
In Port
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
ST
STD
STS
LPM
LPM
LPM
SPM
IN
(k) ← Rr
R0 ← (Z)
Rd, Z
Rd ← (Z)
Rd, Z+
Rd ← (Z), Z ← Z+1
(z) ← R1:R0
Rd, P
P, Rr
Rr
Rd ← P
1
1
2
2
OUT
PUSH
POP
Out Port
P ← Rr
Push Register on Stack
Pop Register from Stack
STACK ← Rr
Rd ← STACK
Rd
MCU CONTROL INSTRUCTIONS
NOP
SLEEP
WDR
No Operation
Sleep
None
None
None
None
1
1
(see specific descr. for Sleep function)
(see specific descr. for WDR/Timer)
For On-chip Debug Only
Watchdog Reset
Break
1
BREAK
N/A
10
ATtiny13
2535JS–AVR–08/10
ATtiny13
6. Ordering Information
Speed (MHz) (3)
Power Supply (V)
Ordering Code (4)
Package (2)
Operation Range
ATtiny13V-10PU
ATtiny13V-10SU
ATtiny13V-10SUR
ATtiny13V-10SSU
ATtiny13V-10SSUR
ATtiny13V-10MU
ATtiny13V-10MUR
ATtiny13V-10MMU
ATtiny13V-10MMUR
8P3
8S2
8S2
S8S1
S8S1
20M1
20M1
10M1
10M1
Industrial
10
1.8 - 5.5
(-40°C to +85°C)(1)
ATtiny13-20PU
ATtiny13-20SU
8P3
8S2
ATtiny13-20SUR
ATtiny13-20SSU
ATtiny13-20SSUR
ATtiny13-20MU
ATtiny13-20MUR
ATtiny13-20MMU
ATtiny13-20MMUR
8S2
S8S1
S8S1
20M1
20M1
10M1
10M1
Industrial
20
2.7 - 5.5
(-40°C to +85°C)(1)
Notes: 1. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa-
tion and minimum quantities.
2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazard-
ous Substances (RoHS).
3. For Speed vs. VCC, see “Speed Grades” on page 117.
4. Code indicators:
– U: matte tin
– R: tape & reel
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S2
8-lead, 0.209" Wide, Plastic Small Outline Package (EIAJ SOIC)
S8S1
20M1
10M1
8-lead, 0.150" Wide, Plastic Gull-Wing Small Outline (JEDEC SOIC)
20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF)
10-pad, 3 x 3 x 1 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF)
11
2535JS–AVR–08/10
7. Packaging Information
7.1
8P3
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
MAX
NOM
NOTE
SYMBOL
D1
A2 A
A
0.210
0.195
0.022
0.070
0.045
0.014
0.400
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.325
0.280
b
E1
e
0.100 BSC
0.300 BSC
0.130
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
12
ATtiny13
2535JS–AVR–08/10
ATtiny13
7.2
8S2
C
1
E
E1
L
N
θ
TOP VVIIEEWW
ENDD VVIIEEWW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.70
0.05
0.35
0.15
5.13
5.18
7.70
0.51
0°
MAX
2.16
0.25
0.48
0.35
5.35
5.40
8.26
0.85
8°
NOM
NOTE
SYMBOL
A1
A
A1
b
4
4
C
D
E1
E
D
2
L
SIDDE VIEW
θ
e
1.27 BSC
3
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs aren't included.
3. Determines the true geometric position.
4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.
4/15/08
GPC
DRAWING NO.
TITLE
REV.
8S2, 8-lead, 0.208” Body, Plastic Small
Outline Package (EIAJ)
Package Drawing Contact:
packagedrawings@atmel.com
STN
8S2
F
13
2535JS–AVR–08/10
7.3
S8S1
1
3
2
H
N
Top View
e
B
A
D
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
MIN
–
MAX
1.75
0.51
0.25
5.00
4.00
NOM
NOTE
SYMBOL
A
B
C
D
E
e
–
A2
L
–
–
–
–
C
–
–
–
–
1.27 BSC
E
H
L
–
–
–
–
6.20
1.27
End View
Note:
This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.
10/10/01
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
A
R
Small Outline (JEDEC SOIC)
14
ATtiny13
2535JS–AVR–08/10
ATtiny13
7.4
20M1
D
1
2
Pin 1 ID
SIDE VIEW
E
3
TOP VIEW
A2
A1
D2
A
0.08
C
1
2
3
Pin #1
Notch
(0.20 R)
COMMON DIMENSIONS
(Unit of Measure = mm)
E2
MIN
0.70
–
MAX
0.80
0.05
b
NOM
0.75
NOTE
SYMBOL
A
A1
A2
b
0.01
L
0.20 REF
0.23
0.18
2.45
2.45
0.35
0.30
2.75
2.75
0.55
e
D
4.00 BSC
2.60
D2
E
BOTTOM VIEW
4.00 BSC
2.60
E2
e
0.50 BSC
0.40
Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5.
Note:
L
10/27/04
DRAWING NO. REV.
20M1
TITLE
2325 Orchard Parkway
San Jose, CA 95131
20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm,
A
R
2.6 mm Exposed Pad, Micro Lead Frame Package (MLF)
15
2535JS–AVR–08/10
7.5
10M1
D
y
Pin 1 ID
E
SIDE VIEW
TOP VIEW
A1
A
D1
K
COMMON DIMENSIONS
(Unit of Measure = mm)
1
2
MIN
MAX
NOM
NOTE
SYMBOL
A
0.80
0.90
1.00
A1
b
0.00
0.18
2.90
1.40
2.90
2.20
0.02
0.25
3.00
–
0.05
0.30
3.10
1.75
3.10
2.70
b
E1
D
D1
E
e
3.00
–
E1
e
0.50
–
L
0.30
–
0.50
0.08
–
L
BOTTOM VIEW
y
–
K
0.20
–
Notes: 1. This package conforms to JEDEC reference MO-229C, Variation VEED-5.
2. The terminal #1 ID is a Lasser-marked Feature.
7/7/06
DRAWING NO. REV.
10M1
TITLE
2325 Orchard Parkway
San Jose, CA 95131
10M1, 10-pad, 3 x 3 x 1.0 mm Body, Lead Pitch 0.50 mm,
A
R
1.64 x 2.60 mm Exposed Pad, Micro Lead Frame Package
16
ATtiny13
2535JS–AVR–08/10
ATtiny13
8. Errata
The revision letter in this section refers to the revision of the ATtiny13 device.
8.1
ATtiny13 Rev. D
• EEPROM can not be written below 1.9 Volt
1. EEPROM can not be written below 1.9 Volt
Writing the EEPROM at VCC below 1.9 volts might fail.
Problem Fix/Workaround
Do not write the EEPROM when VCC is below 1.9 volts.
8.2
8.3
ATtiny13 Rev. C
Revision C has not been sampled.
ATtiny13 Rev. B
• Wrong values read after Erase Only operation
• High Voltage Serial Programming Flash, EEPROM, Fuse and Lock Bits may fail
• Device may lock for further programming
• debugWIRE communication not blocked by lock-bits
• Watchdog Timer Interrupt disabled
• EEPROM can not be written below 1.9 Volt
8.3.1
Wrong values read after Erase Only operation
At supply voltages below 2.7 V, an EEPROM location that is erased by the Erase Only oper-
ation may read as programmed (0x00).
Problem Fix/Workaround
If it is necessary to read an EEPROM location after Erase Only, use an Atomic Write opera-
tion with 0xFF as data in order to erase a location. In any case, the Write Only operation can
be used as intended. Thus no special considerations are needed as long as the erased loca-
tion is not read before it is programmed.
8.3.2
8.3.3
High Voltage Serial Programming Flash, EEPROM, Fuse and Lock Bits may fail
Writing to any of these locations and bits may in some occasions fail.
Problem Fix/Workaround
After a writing has been initiated, always observe the RDY/BSY signal. If the writing should
fail, rewrite until the RDY/BSY verifies a correct writing. This will be fixed in revision D.
Device may lock for further programming
Special combinations of fuse bits will lock the device for further programming effectively
turning it into an OTP device. The following combinations of settings/fuse bits will cause this
effect:
– 128 kHz internal oscillator (CKSEL[1..0] = 11), shortest start-up time
(SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled RSTDISBL = 0.
– 9.6 MHz internal oscillator (CKSEL[1..0] = 10), shortest start-up time
(SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled RSTDISBL = 0.
17
2535JS–AVR–08/10
– 4.8 MHz internal oscillator (CKSEL[1..0] = 01), shortest start-up time
(SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled RSTDISBL = 0.
Problem fix/ Workaround
Avoid the above fuse combinations. Selecting longer start-up time will eliminate the problem.
8.3.4
8.3.5
debugWIRE communication not blocked by lock-bits
When debugWIRE on-chip debug is enabled (DWEN = 0), the contents of program memory
and EEPROM data memory can be read even if the lock-bits are set to block further reading
of the device.
Problem fix/ Workaround
Do not ship products with on-chip debug of the tiny13 enabled.
Watchdog Timer Interrupt disabled
If the watchdog timer interrupt flag is not cleared before a new timeout occurs, the watchdog
will be disabled, and the interrupt flag will automatically be cleared. This is only applicable in
interrupt only mode. If the Watchdog is configured to reset the device in the watchdog time-
out following an interrupt, the device works correctly.
Problem fix / Workaround
Make sure there is enough time to always service the first timeout event before a new
watchdog timeout occurs. This is done by selecting a long enough time-out period.
8.3.6
EEPROM can not be written below 1.9 Volt
Writing the EEPROM at VCC below 1.9 volts might fail.
Problem Fix/Workaround
Do not write the EEPROM when VCC is below 1.9 volts.
8.4
ATtiny13 Rev. A
Revision A has not been sampled.
18
ATtiny13
2535JS–AVR–08/10
ATtiny13
9. Datasheet Revision History
Please note that the referring page numbers in this section refer to the complete document.
9.1
9.2
Rev. 2535J-08/10
Added tape and reel part numbers in “Ordering Information” on page 160. Removed text “Not
recommended for new design” from cover page. Updated last page.
Rev. 2535I-05/08
1. Updated document template, layout and paragraph formats.
2. Updated “Features” on page 1.
3. Created Sections:
– “Calibrated Internal RC Oscillator Accuracy” on page 118
– “Analog Comparator Characteristics” on page 119
4. Updated Sections:
– “System Clock and Clock Options” on page 23
– “Calibrated Internal 4.8/9.6 MHz Oscillator” on page 25
– “External Interrupts” on page 45
– “Analog Noise Canceling Techniques” on page 88
– “Limitations of debugWIRE” on page 96
– “Reading Fuse and Lock Bits from Firmware” on page 99
– “Fuse Bytes” on page 103
– “Calibration Bytes” on page 104
– “High-Voltage Serial Programming” on page 108
– “Ordering Information” on page 160
5. Updated Figure:
– “Analog Input Circuitry” on page 87
– “High-voltage Serial Programming Timing” on page 122
6. Moved Figures:
– “Serial Programming Timing” on page 121
– “Serial Programming Waveform” on page 121
– “High-voltage Serial Programming Timing” on page 122
7. Updated Tables:
– “DC Characteristics, TA = -40°C to +85°C” on page 115
– “Serial Programming Characteristics, TA = -40°C to +85°C, VCC = 1.8 - 5.5V (Unless
Otherwise Noted)” on page 121
8. Moved Tables:
– “Serial Programming Instruction Set” on page 107
– “Serial Programming Characteristics, TA = -40°C to +85°C, VCC = 1.8 - 5.5V (Unless
Otherwise Noted)” on page 121
– “High-voltage Serial Programming Characteristics TA = 25°C, VCC = 5.0V ± 10%
(Unless otherwise noted)” on page 122
9. Updated Register Description for Sections:
19
2535JS–AVR–08/10
– “TCCR0A – Timer/Counter Control Register A” on page 69
– “DIDR0 – Digital Input Disable Register 0” on page 94
10. Updated description in Step 1. on page 106.
11. Changed device status to “Not Recommended for New Designs”.
9.3
Rev. 2535H-10/07
1.
Updated “Features” on page 1.
2.
3.
4.
5.
6.
7.
8.
9.
Updated “Pin Configurations” on page 2.
Added “Data Retention” on page 6.
Updated “Assembly Code Example(1)” on page 39.
Updated Table 21 in “Alternate Functions of Port B” on page 54.
Updated Bit 5 description in “GIMSK – General Interrupt Mask Register” on page 46.
Updated “ADC Voltage Reference” on page 87.
Updated “Calibration Bytes” on page 104.
Updated “Read Calibration Byte” on page 108.
10. Updated Table 51 in “Serial Programming Characteristics” on page 121.
11. Updated Algorithm in “High-Voltage Serial Programming Algorithm” on page 109.
12. Updated “Read Calibration Byte” on page 112.
13. Updated values in “External Clock Drive” on page 118.
14. Updated “Ordering Information” on page 160.
15. Updated “Packaging Information” on page 161.
9.4
Rev. 2535G-01/07
1.
Removed Preliminary.
2.
3.
4.
5.
6.
7.
8.
9.
Updated Table 7-1 on page 30, Table 8-1 on page 42,Table 18-8 on page 121.
Removed Note from Table 7-1 on page 30.
Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page 79.
Updated “Prescaling and Conversion Timing” on page 83.
Updated Figure 18-4 on page 121.
Updated “DC Characteristics” on page 115.
Updated “Ordering Information” on page 160.
Updated “Packaging Information” on page 161.
9.5
9.6
Rev. 2535F-04/06
1.
Revision not published.
Rev. 2535E-10/04
1.
2.
3.
2.
4.
5.
6.
7.
Bits EEMWE/EEWE changed to EEMPE/EEPE in document.
Updated “Pinout ATtiny13/ATtiny13V” on page 2.
Updated “Write Fuse Low Bits” in Table 17-13 on page 110, Table 18-3 on page 118.
Added “Pin Change Interrupt Timing” on page 45.
Updated “GIMSK – General Interrupt Mask Register” on page 46.
Updated “PCMSK – Pin Change Mask Register” on page 47.
Updated item 4 in “Serial Programming Algorithm” on page 106.
Updated “High-Voltage Serial Programming Algorithm” on page 109.
20
ATtiny13
2535JS–AVR–08/10
ATtiny13
8.
9.
Updated “DC Characteristics” on page 115.
Updated “Typical Characteristics” on page 122.
10. Updated “Ordering Information” on page 160.
11. Updated “Packaging Information” on page 161.
12. Updated “Errata” on page 166.
9.7
9.8
Rev. 2535D-04/04
1.
Maximum Speed Grades changed: 12MHz to 10MHz, 24MHz to 20MHz
Updated “Serial Programming Instruction Set” on page 107.
Updated “Speed Grades” on page 117
2.
3.
4.
Updated “Ordering Information” on page 160
Rev. 2535C-02/04
1.
2.
3.
4.
5.
6.
7.
8.
9.
C-code examples updated to use legal IAR syntax.
Replaced occurrences of WDIF with WDTIF and WDIE with WDTIE.
Updated “Stack Pointer” on page 11.
Updated “Calibrated Internal 4.8/9.6 MHz Oscillator” on page 25.
Updated “OSCCAL – Oscillator Calibration Register” on page 27.
Updated typo in introduction on “Watchdog Timer” on page 37.
Updated “ADC Conversion Time” on page 86.
Updated “Serial Programming” on page 105.
Updated “Electrical Characteristics” on page 115.
10. Updated “Ordering Information” on page 160.
11. Removed rev. C from “Errata” on page 166.
9.9
Rev. 2535B-01/04
1.
Updated Figure 2-1 on page 4.
2.
3.
4.
5.
6.
Updated Table 7-1, Table 8-1, Table 14-2 and Table 18-3.
Updated “Calibrated Internal 4.8/9.6 MHz Oscillator” on page 25.
Updated the whole “Watchdog Timer” on page 37.
Updated Figure 17-1 on page 105 and Figure 17-2 on page 108.
Updated registers “MCUCR – MCU Control Register”, “TCCR0B – Timer/Counter Con-
trol Register B” and “DIDR0 – Digital Input Disable Register 0”.
Updated Absolute Maximum Ratings and DC Characteristics in “Electrical Characteris-
tics” on page 115.
7.
8.
9.
Added “Speed Grades” on page 117
Updated “” on page 120.
10. Updated “Typical Characteristics” on page 123.
11. Updated “Ordering Information” on page 160.
12. Updated “Packaging Information” on page 161.
13. Updated “Errata” on page 166.
14. Changed instances of EEAR to EEARL.
9.10 Rev. 2535A-06/03
1.
Initial Revision.
21
2535JS–AVR–08/10
Headquarters
International
Atmel Corporation
2325 Orchard Parkway
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USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
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Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-
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marks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
2535JS–AVR–08/10
相关型号：
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RISC Microcontroller, 8-Bit, FLASH, 1.6MHz, CMOS, PDIP8, 0.300 INCH, PLASTIC, DIP-8
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