ATTINY2313V-10PU [ATMEL]
8-bit Microcontroller with 2K Bytes In-System Programmable Flash; 8位微控制器与2K字节的系统内可编程闪存
| 型号： | ATTINY2313V-10PU |
| 厂家： | 
ATMEL |
| 描述： | 8-bit Microcontroller with 2K Bytes In-System Programmable Flash |
| 文件： | 总17页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Utilizes the AVR® RISC Architecture
• AVR – High-performance and Low-power RISC Architecture
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
• Data and Non-volatile Program and Data Memories
– 2K Bytes of In-System Self Programmable Flash
Endurance 10,000 Write/Erase Cycles
– 128 Bytes In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– 128 Bytes Internal SRAM
8-bit
Microcontroller
with 2K Bytes
In-System
Programmable
Flash
– Programming Lock for Flash Program and EEPROM Data Security
• Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes
– Four PWM Channels
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– USI – Universal Serial Interface
– Full Duplex USART
• Special Microcontroller Features
– debugWIRE On-chip Debugging
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low-power Idle, Power-down, and Standby Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
ATtiny2313/V
Preliminary
Summary
• I/O and Packages
– 18 Programmable I/O Lines
– 20-pin PDIP, 20-pin SOIC, 20-pad QFN/MLF
• Operating Voltages
– 1.8 - 5.5V (ATtiny2313V)
– 2.7 - 5.5V (ATtiny2313)
• Speed Grades
– ATtiny2313V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
– ATtiny2313: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
• Typical Power Consumption
– Active Mode
1 MHz, 1.8V: 230 µA
32 kHz, 1.8V: 20 µA (including oscillator)
– Power-down Mode
< 0.1 µA at 1.8V
Rev. 2543IS–AVR–04/06
Pin Configurations
Figure 1. Pinout ATtiny2313
PDIP/SOIC
VCC
(RESET/dW) PA2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PB7 (UCSK/SCL/PCINT7)
PB6 (MISO/DO/PCINT6)
PB5 (MOSI/DI/SDA/PCINT5)
PB4 (OC1B/PCINT4)
PB3 (OC1A/PCINT3)
PB2 (OC0A/PCINT2)
PB1 (AIN1/PCINT1)
PB0 (AIN0/PCINT0)
PD6 (ICP)
(RXD) PD0
(TXD) PD1
(XTAL2) PA1
(XTAL1) PA0
(CKOUT/XCK/INT0) PD2
(INT1) PD3
(T0) PD4
(OC0B/T1) PD5
GND
MLF
(TXD) PD1
XTAL2) PA1
1
2
3
4
5
15
14
13
12
11
PB5 (MOSI/DI/SDA/PCINT5)
PB4 (OC1B/PCINT4)
PB3 (OC1A/PCINT3)
PB2 (OC0A/PCINT2)
PB1 (AIN1/PCINT1)
(XTAL1) PA0
(CKOUT/XCK/INT0) PD2
(INT1) PD3
NOTE: Bottom pad should be soldered to ground.
Overview
The ATtiny2313 is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle,
the ATtiny2313 achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
2
ATtiny2313/V
2543IS–AVR–04/06
ATtiny2313/V
Block Diagram
Figure 2. Block Diagram
XTAL1
XTAL2
PA0 - PA2
PORTA DRIVERS
DATA DIR.
REG. PORTA
DATA REGISTER
PORTA
INTERNAL
CALIBRATED
OSCILLATOR
VCC
GND
8-BIT DATA BUS
INTERNAL
OSCILLATOR
OSCILLATOR
STACK
POINTER
TIMING AND
CONTROL
PROGRAM
COUNTER
WATCHDOG
TIMER
RESET
MCU CONTROL
REGISTER
PROGRAM
FLASH
SRAM
ON-CHIP
DEBUGGER
MCU STATUS
REGISTER
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTER
TIMER/
COUNTERS
INSTRUCTION
DECODER
INTERRUPT
UNIT
EEPROM
USI
CONTROL
LINES
ALU
STATUS
REGISTER
PROGRAMMING
LOGIC
SPI
USART
DATA DIR.
REG. PORTB
DATA DIR.
REG. PORTD
DATA REGISTER
PORTB
DATA REGISTER
PORTD
PORTB DRIVERS
PORTD DRIVERS
PB0 - PB7
PD0 - PD6
3
2543IS–AVR–04/06
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
The ATtiny2313 provides the following features: 2K bytes of In-System Programmable
Flash, 128 bytes EEPROM, 128 bytes SRAM, 18 general purpose I/O lines, 32 general
purpose working registers, a single-wire Interface for On-chip Debugging, two flexible
Timer/Counters with compare modes, internal and external interrupts, a serial program-
mable USART, Universal Serial Interface with Start Condition Detector, a programmable
Watchdog Timer with internal Oscillator, and three software selectable power saving
modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, and
interrupt system to continue functioning. The Power-down mode saves the register con-
tents but freezes the Oscillator, disabling all other chip functions until the next interrupt
or hardware reset. In Standby mode, the crystal/resonator Oscillator is running while the
rest of the device is sleeping. This allows very fast start-up combined with low-power
consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology.
The On-chip ISP Flash allows the program memory to be reprogrammed In-System
through an SPI serial interface, or by a conventional non-volatile memory programmer.
By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a mono-
lithic chip, the Atmel ATtiny2313 is a powerful microcontroller that provides a highly
flexible and cost effective solution to many embedded control applications.
The ATtiny2313 AVR is supported with a full suite of program and system development
tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Cir-
cuit Emulators, and Evaluation kits.
4
ATtiny2313/V
2543IS–AVR–04/06
ATtiny2313/V
Pin Descriptions
VCC
Digital supply voltage.
Ground.
GND
Port A (PA2..PA0)
Port A is a 3-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port A output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port A pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port A also serves the functions of various special features of the ATtiny2313 as listed
on page 53.
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny2313 as listed
on page 53.
Port D (PD6..PD0)
Port D is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port D output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATtiny2313 as listed
on page 56.
RESET
XTAL1
Reset input. A low level on this pin for longer than the minimum pulse length will gener-
ate a reset, even if the clock is not running. The minimum pulse length is given in Table
15 on page 34. Shorter pulses are not guaranteed to generate a reset. The Reset Input
is an alternate function for PA2 and dW.
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
XTAL1 is an alternate function for PA0.
XTAL2
Output from the inverting Oscillator amplifier. XTAL2 is an alternate function for PA1.
Resources
A comprehensive set of development tools, application notes and datasheets are avail-
able for downloadon http://www.atmel.com/avr.
5
2543IS–AVR–04/06
Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x3F (0x5F)
0x3E (0x5E)
0x3D (0x5D)
0x3C (0x5C)
0x3B (0x5B)
0x3A (0x5A)
0x39 (0x59)
0x38 (0x58)
0x37 (0x57)
0x36 (0x56)
0x35 (0x55)
0x34 (0x54)
0x33 (0x53)
0x32 (0x52)
0x31 (0x51)
0x30 (0x50)
0x2F (0x4F)
0x2E (0x4E)
0x2D (0x4D)
0x2C (0x4C)
0x2B (0x4B)
0x2A (0x4A)
0x29 (0x49)
0x28 (0x48)
0x27 (0x47)
0x26 (0x46)
0x25 (0x45)
0x24 (0x44)
0x23 (0x43)
0x22 (ox42)
0x21 (0x41)
0x20 (0x40)
0x1F (0x3F)
0x1E (0x3E)
0x1D (0x3D)
0x1C (0x3C)
0x1B (0x3B)
0x1A (0x3A)
0x19 (0x39)
0x18 (0x38)
0x17 (0x37)
0x16 (0x36)
0x15 (0x35)
0x14 (0x34)
0x13 (0x33)
0x12 (0x32)
0x11 (0x31)
0x10 (0x30)
0x0F (0x2F)
0x0E (0x2E)
0x0D (0x2D)
0x0C (0x2C)
0x0B (0x2B)
0x0A (0x2A)
0x09 (0x29)
0x08 (0x28)
0x07 (0x27)
0x06 (0x26)
0x05 (0x25)
0x04 (0x24)
0x03 (0x23)
0x02 (0x22)
0x01 (0x21)
0x00 (0x20)
SREG
Reserved
SPL
I
–
T
–
H
–
S
–
V
–
N
–
Z
–
C
–
7
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
10
78
OCR0B
GIMSK
EIFR
Timer/Counter0 – Compare Register B
INT1
INTF1
TOIE1
TOV1
–
INT0
INTF0
OCIE1A
OCF1A
–
PCIE
PCIF
–
–
–
–
–
–
60
–
–
–
–
–
62
TIMSK
OCIE1B
OCF1B
–
ICIE1
ICF1
RFLB
OCIE0B
OCF0B
PGWRT
TOIE0
TOV0
PGERS
OCIE0A
OCF0A
SELFPRGEN
79, 110
79
TIFR
–
SPMCSR
OCR0A
MCUCR
MCUSR
TCCR0B
TCNT0
OSCCAL
TCCR0A
TCCR1A
TCCR1B
TCNT1H
TCNT1L
OCR1AH
OCR1AL
OCR1BH
OCR1BL
Reserved
CLKPR
ICR1H
CTPB
156
78
Timer/Counter0 – Compare Register A
PUD
–
SM1
–
SE
–
SM0
ISC11
WDRF
WGM02
ISC10
BORF
CS02
ISC01
EXTRF
CS01
ISC00
PORF
CS00
53
–
–
37
FOC0A
FOC0B
–
77
Timer/Counter0 (8-bit)
78
–
CAL6
COM0A0
COM1A0
ICES1
CAL5
COM0B1
COM1B1
–
CAL4
CAL3
CAL2
–
CAL1
WGM01
WGM11
CS11
CAL0
WGM00
WGM10
CS10
25
COM0A1
COM1A1
ICNC1
COM0B0
COM1BO
WGM13
–
–
74
–
105
108
109
109
109
109
110
110
WGM12
CS12
Timer/Counter1 – Counter Register High Byte
Timer/Counter1 – Counter Register Low Byte
Timer/Counter1 – Compare Register A High Byte
Timer/Counter1 – Compare Register A Low Byte
Timer/Counter1 – Compare Register B High Byte
Timer/Counter1 – Compare Register B Low Byte
–
–
–
–
–
–
–
–
–
–
–
CLKPCE
CLKPS3
CLKPS2
CLKPS1
CLKPS0
27
110
110
82
Timer/Counter1 - Input Capture Register High Byte
Timer/Counter1 - Input Capture Register Low Byte
ICR1L
GTCCR
TCCR1C
WDTCSR
PCMSK
Reserved
EEAR
–
FOC1A
WDIF
PCINT7
–
–
–
–
–
–
–
–
–
–
–
–
PSR10
–
FOC1B
WDIE
PCINT6
–
109
42
WDP3
PCINT5
–
WDCE
PCINT4
–
WDE
PCINT3
–
WDP2
PCINT2
–
WDP1
PCINT1
–
WDP0
PCINT0
–
62
–
EEPROM Address Register
EEPROM Data Register
15
16
EEDR
EECR
–
–
EEPM1
EEPM0
EERIE
EEMPE
PORTA2
DDA2
EEPE
PORTA1
DDA1
EERE
PORTA0
DDA0
16
PORTA
DDRA
–
–
–
–
–
–
–
–
–
–
58
58
PINA
–
–
–
–
–
PINA2
PINA1
PINA0
58
PORTB
DDRB
PORTB7
DDB7
PINB7
PORTB6
DDB6
PINB6
PORTB5
DDB5
PINB5
PORTB4
DDB4
PINB4
PORTB3
DDB3
PINB3
PORTB2
DDB2
PORTB1
DDB1
PORTB0
DDB0
58
58
PINB
PINB2
PINB1
PINB0
58
GPIOR2
GPIOR1
GPIOR0
PORTD
DDRD
General Purpose I/O Register 2
General Purpose I/O Register 1
General Purpose I/O Register 0
20
20
20
–
–
–
PORTD6
DDD6
PORTD5
DDD5
PORTD4
DDD4
PORTD3
DDD3
PORTD2
DDD2
PORTD1
DDD1
PORTD0
DDD0
58
58
PIND
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
58
USIDR
USI Data Register
145
146
147
130
130
132
134
150
USISR
USISIF
USISIE
USIOIF
USIOIE
USIPF
USIDC
USICNT3
USICS1
USICNT2
USICS0
USICNT1
USICLK
USICNT0
USITC
USICR
USIWM1
USIWM0
UDR
UART Data Register (8-bit)
UCSRA
UCSRB
UBRRL
ACSR
RXC
TXC
UDRE
UDRIE
FE
DOR
UPE
U2X
MPCM
TXB8
RXCIE
TXCIE
RXEN
TXEN
UCSZ2
RXB8
UBRRH[7:0]
ACD
ACBG
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
Reserved
Reserved
Reserved
Reserved
UCSRC
UBRRH
DIDR
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
UMSEL
UPM1
UPM0
USBS
UCSZ1
UCSZ0
UCPOL
133
134
151
UBRRH[11:8]
–
–
–
–
–
–
–
–
–
–
–
–
–
AIN1D
–
AIN0D
–
Reserved
6
ATtiny2313/V
2543IS–AVR–04/06
ATtiny2313/V
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses.
7
2543IS–AVR–04/06
Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
ADC
ADIW
SUB
SUBI
SBC
SBCI
SBIW
AND
ANDI
OR
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add two Registers
Rd ← Rd + Rr
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
Rd ← Rd • K
Z,N,V
Rd ← Rd v Rr
Z,N,V
ORI
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Rd ← Rd v K
Z,N,V
EOR
COM
NEG
SBR
CBR
INC
Rd ← Rd ⊕ Rr
Rd ← 0xFF − Rd
Rd ← 0x00 − Rd
Rd ← Rd v K
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Rd
Two’s Complement
Rd,K
Rd,K
Rd
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Rd ← Rd • (0xFF - K)
Rd ← Rd + 1
Z,N,V
Z,N,V
DEC
TST
Rd
Decrement
Rd ← Rd − 1
Z,N,V
Rd
Test for Zero or Minus
Clear Register
Rd ← Rd • Rd
Rd ← Rd ⊕ Rd
Rd ← 0xFF
Z,N,V
CLR
SER
Rd
Z,N,V
Rd
Set Register
None
BRANCH INSTRUCTIONS
RJMP
IJMP
k
k
Relative Jump
PC ← PC + k + 1
None
None
None
None
None
I
2
2
Indirect Jump to (Z)
PC ← Z
RCALL
ICALL
RET
Relative Subroutine Call
Indirect Call to (Z)
PC ← PC + k + 1
3
PC ← Z
3
Subroutine Return
PC ← STACK
4
RETI
Interrupt Return
PC ← STACK
4
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1/2/3
1
Rd,Rr
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
1
CPI
Rd,K
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd − K
1
SBRC
SBRS
SBIC
Rr, b
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
Rr, b
P, b
P, b
s, k
s, k
k
SBIS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
BRID
k
Branch if Not Equal
k
Branch if Carry Set
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
k
k
k
Branch if Minus
k
Branch if Plus
k
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
k
k
k
k
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
k
k
k
k
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
P,b
Rd
Rd
Rd
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
I/O(P,b) ← 1
None
2
2
1
1
1
CBI
LSL
LSR
ROL
I/O(P,b) ← 0
None
Rd(n+1) ← Rd(n), Rd(0) ← 0
Rd(n) ← Rd(n+1), Rd(7) ← 0
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
Z,C,N,V
Z,C,N,V
Logical Shift Right
Rotate Left Through Carry
8
ATtiny2313/V
2543IS–AVR–04/06
ATtiny2313/V
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ROR
Rd
Rotate Right Through Carry
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Rd
Rd
s
Arithmetic Shift Right
Swap Nibbles
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
Flag Set
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C ← 1
SREG(s)
s
Flag Clear
SREG(s)
Rr, b
Rd, b
Bit Store from Register to T
Bit load from T to Register
Set Carry
T
None
C
C
N
N
Z
Clear Carry
C ← 0
Set Negative Flag
N ← 1
Clear Negative Flag
Set Zero Flag
N ← 0
Z ← 1
Clear Zero Flag
Z ← 0
Z
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
I ← 1
I
CLI
I ← 0
I
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
S ← 1
S
S
V
V
T
S ← 0
V ← 1
V ← 0
T ← 1
Clear T in SREG
T ← 0
T
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H ← 1
H
H
H ← 0
DATA TRANSFER INSTRUCTIONS
MOV
MOVW
LDI
LD
Rd, Rr
Rd, Rr
Rd, K
Move Between Registers
Copy Register Word
Rd ← Rr
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
-
Rd+1:Rd ← Rr+1:Rr
Load Immediate
Rd ← K
Rd, X
Load Indirect
Rd ← (X)
LD
Rd, X+
Rd, - X
Rd, Y
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
LD
LD
LD
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Y + q)
Rd ← (Z)
LD
LDD
LD
LD
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Rd ← (Z), Z ← Z+1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
Rd ← (k)
LD
LDD
LDS
ST
X, Rr
(X) ← Rr
ST
X+, Rr
- X, Rr
Y, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
ST
ST
ST
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Y + q) ← Rr
ST
STD
ST
(Z) ← Rr
ST
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
Load Program Memory
Load Program Memory and Post-Inc
Store Program Memory
In Port
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
ST
STD
STS
LPM
LPM
LPM
SPM
IN
(k) ← Rr
R0 ← (Z)
Rd, Z
Rd ← (Z)
Rd, Z+
Rd ← (Z), Z ← Z+1
(Z) ← R1:R0
Rd, P
P, Rr
Rr
Rd ← P
1
1
2
2
OUT
PUSH
POP
Out Port
P ← Rr
Push Register on Stack
Pop Register from Stack
STACK ← Rr
Rd ← STACK
Rd
MCU CONTROL INSTRUCTIONS
NOP
No Operation
Sleep
None
None
None
None
1
1
SLEEP
WDR
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
For On-chip Debug Only
Watchdog Reset
Break
1
BREAK
N/A
9
2543IS–AVR–04/06
Ordering Information
Speed (MHz)(3)
Power Supply
Ordering Code
Package(1)
Operation Range
ATtiny2313V-10PI
20P3
20P3
20S
20S
20M1
ATtiny2313V-10PU(2)
ATtiny2313V-10SI
Industrial
(-40°C to 85°C)
10
1.8 - 5.5V
2.7 - 5.5V
ATtiny2313V-10SU(2)
ATtiny2313V-10MU(2)
ATtiny2313-20PI
20P3
20P3
20S
20S
20M1
ATtiny2313-20PU(2)
ATtiny2313-20SI
Industrial
(-40°C to 85°C)
20
ATtiny2313-20SU(2)
ATtiny2313-20MU(2)
Note:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-
tive).Also Halide free and fully Green.
3. For Speed vs. VCC, see Figure 82 on page 181 and Figure 83 on page 181.
Package Type
20P3
20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
20S
20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC)
20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (MLF)
20M1
10
ATtiny2313/V
2543IS–AVR–04/06
ATtiny2313/V
Packaging Information
20P3
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
C
MIN
–
MAX
5.334
–
NOM
NOTE
SYMBOL
eC
A
–
–
–
–
–
–
–
–
–
–
–
eB
A1
D
0.381
25.493
7.620
6.096
0.356
1.270
2.921
0.203
–
25.984 Note 2
8.255
E
E1
B
7.112 Note 2
0.559
B1
L
1.551
Notes:
1. This package conforms to JEDEC reference MS-001, Variation AD.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
3.810
C
0.356
eB
eC
e
10.922
0.000
1.524
2.540 TYP
1/12/04
DRAWING NO. REV.
20P3
TITLE
2325 Orchard Parkway
San Jose, CA 95131
20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual
Inline Package (PDIP)
C
R
11
2543IS–AVR–04/06
20S
C
1
H
E
N
A1
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
MIN
MAX
NOM
NOTE
SYMBOL
e
b
A
A1
b
0.0926
0.0040
0.0130
0.0091
0.4961
0.2914
0.3940
0.0160
0.1043
0.0118
0.0200
0.0125
0.5118
0.2992
0.4190
0.050
A
4
C
D
E
H
L
D
1
2
Side View
3
e
0.050 BSC
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AC for additional information.
2. Dimension "D" does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006") per side.
3. Dimension "E" does not include inter-lead Flash or protrusion. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010") per side.
4. "L" is the length of the terminal for soldering to a substrate.
5. The lead width "b", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm
1/9/02
(0.024") per side.
TITLE
DRAWING NO.
REV.
20S2, 20-lead, 0.300" Wide Body, Plastic Gull
Wing Small Outline Package (SOIC)
2325 Orchard Parkway
San Jose, CA 95131
A
20S2
R
12
ATtiny2313/V
2543IS–AVR–04/06
ATtiny2313/V
20M1
D
1
2
Pin 1 ID
SIDE VIEW
E
3
TOP VIEW
A2
A1
D2
A
0.08
C
1
2
3
Pin #1
Notch
(0.20 R)
COMMON DIMENSIONS
(Unit of Measure = mm)
E2
MIN
0.70
–
MAX
0.80
0.05
b
NOM
0.75
NOTE
SYMBOL
A
A1
A2
b
0.01
L
0.20 REF
0.23
0.18
2.45
2.45
0.35
0.30
2.75
2.75
0.55
e
D
4.00 BSC
2.60
D2
E
BOTTOM VIEW
4.00 BSC
2.60
E2
e
0.50 BSC
0.40
Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5.
Note:
L
10/27/04
DRAWING NO. REV.
20M1
TITLE
2325 Orchard Parkway
San Jose, CA 95131
20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm,
A
R
2.6 mm Exposed Pad, Micro Lead Frame Package (MLF)
13
2543IS–AVR–04/06
Errata
The revision in this section refers to the revision of the ATtiny2313 device.
ATtiny2313 Rev B
• Wrong values read after Erase Only operation
• Parallel Programming does not work
• Watchdog Timer Interrupt disabled
• EEPROM can not be written below 1.9 volts
1. Wrong values read after Erase Only operation
At supply voltages below 2.7 V, an EEPROM location that is erased by the Erase
Only operation may read as programmed (0x00).
Problem Fix/Workaround
If it is necessary to read an EEPROM location after Erase Only, use an Atomic Write
operation with 0xFF as data in order to erase a location. In any case, the Write Only
operation can be used as intended. Thus no special considerations are needed as
long as the erased location is not read before it is programmed.
2. Parallel Programming does not work
Parallel Programming is not functioning correctly. Because of this, reprogramming
of the device is impossible if one of the following modes are selected:
–
–
In-System Programming disabled (SPIEN unprogrammed)
Reset Disabled (RSTDISBL programmed)
Problem Fix/Workaround
Serial Programming is still working correctly. By avoiding the two modes above, the
device can be reprogrammed serially.
3. Watchdog Timer Interrupt disabled
If the watchdog timer interrupt flag is not cleared before a new timeout occurs, the
watchdog will be disabled, and the interrupt flag will automatically be cleared. This is
only applicable in interrupt only mode. If the Watchdog is configured to reset the
device in the watchdog time-out following an interrupt, the device works correctly.
Problem fix / Workaround
Make sure there is enough time to always service the first timeout event before a
new watchdog timeout occurs. This is done by selecting a long enough time-out
period.
4. EEPROM can not be written below 1.9 volts
Writing the EEPROM at VCC below 1.9 volts might fail.
Problem fix / Workaround
Do not write the EEPROM when VCC is below 1.9 volts.
ATtiny2313 Rev A
Revision A has not been sampled.
14
ATtiny2313/V
2543IS–AVR–04/06
ATtiny2313/V
Datasheet Revision
History
Please note that the referring page numbers in this section are referred to this docu-
ment. The referring revision in this section are referring to the document revision.
Changes from Rev.
2514H-02/05 to Rev.
2514I-04/06
1.
2.
3
Updated typos.
Updated Figure 1 on page 2.
Added “Resources” on page 6.
4.
5.
6.
7.
Updated “Default Clock Source” on page 25.
Updated “128 kHz Internal Oscillator” on page 30.
Updated “Power Management and Sleep Modes” on page 33
Updated Table 3 on page 25,Table 13 on page 33, Table 14 on page 34,
Table 19 on page 45, Table 31 on page 63, Table 79 on page 180.
8.
9.
Updated “External Interrupts” on page 62.
Updated “Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0” on page
65.
10.
Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page
153.
11.
12.
13.
14.
15.
Updated “Calibration Byte” on page 164.
Updated “DC Characteristics” on page 181.
Updated “Register Summary” on page 6.
Updated “Ordering Information” on page 10.
Changed occurences of OCnA to OCFnA, OCnB to OCFnB and OC1x to
OCF1x.
Changes from Rev.
2514G-10/04 to Rev.
2514H-02/05
1.
2.
3.
Updated Table 6 on page 24, Table 15 on page 34, Table 68 on page 161
and Table 80 on page 180.
Changed CKSEL default value in “Default Clock Source” on page 22 to
8 MHz.
Updated “Programming the Flash” on page 166, “Programming the
EEPROM” on page 168 and “Enter Programming Mode” on page 164.
4.
5.
Updated “DC Characteristics” on page 178.
MLF option updated to “Quad Flat No-Lead/Micro Lead Frame
(QFN/MLF)”
Changes from Rev.
2514F-08/04 to Rev.
2514G-10/04
1.
2.
3.
4.
5.
Updated “Features” on page 1.
Updated “Pinout ATtiny2313” on page 2.
Updated “Ordering Information” on page 10.
Updated “Packaging Information” on page 11.
Updated “Errata” on page 14.
Changes from Rev.
2514E-04/04 to Rev.
2514F-08/04
1.
2.
3.
Updated “Features” on page 1.
Updated “Alternate Functions of Port B” on page 53.
Updated “Calibration Byte” on page 161.
15
2543IS–AVR–04/06
4.
Moved Table 69 on page 161 and Table 70 on page 162 to “Page Size”
on page 161.
5.
Updated “Enter Programming Mode” on page 164.
Updated “Serial Programming Algorithm” on page 174.
Updated Table 78 on page 175.
6.
7.
8.
Updated “DC Characteristics” on page 178.
9.
Updated “ATtiny2313 Typical Characteristics” on page 182.
10.
Changed occurences of PCINT15 to PCINT7, EEMWE to EEMPE and
EEWE to EEPE in the document.
Changes from Rev.
2514D-03/04 to Rev.
2514E-04/04
1.
Speed Grades changed
- 12MHz to 10MHz
- 24MHz to 20MHz
2.
3.
4.
5.
Updated Figure 1 on page 2.
Updated “Ordering Information” on page 10.
Updated “Maximum Speed vs. VCC” on page 181.
Updated “ATtiny2313 Typical Characteristics” on page 182.
Changes from Rev.
2514C-12/03 to Rev.
2514D-03/04
1.
2.
3.
4.
5.
6.
Updated Table 2 on page 22.
Replaced “Watchdog Timer” on page 39.
Added “Maximum Speed vs. VCC” on page 181.
“Serial Programming Algorithm” on page 174 updated.
Changed mA to µA in preliminary Figure 136 on page 208.
“Ordering Information” on page 10 updated.
MLF package option removed
7.
8.
9.
Package drawing “20P3” on page 11 updated.
Updated C-code examples.
Renamed instances of SPMEN to SELFPRGEN, Self Programming
Enable.
Changes from Rev.
2514B-09/03 to Rev.
2514C-12/03
1.
Updated “Calibrated Internal RC Oscillator” on page 24.
Changes from Rev.
2514A-09/03 to Rev.
2514B-09/03
1.
Fixed typo from UART to USART and updated Speed Grades and Power
Consumption Estimates in “Features” on page 1.
2.
3.
4.
5.
6.
7.
8.
9.
Updated “Pin Configurations” on page 2.
Updated Table 15 on page 34 and Table 80 on page 180.
Updated item 5 in “Serial Programming Algorithm” on page 174.
Updated “Electrical Characteristics” on page 178.
Updated Figure 82 on page 181 and added Figure 83 on page 181.
Changed SFIOR to GTCCR in “Register Summary” on page 6.
Updated “Ordering Information” on page 10.
Added new errata in “Errata” on page 14.
16
ATtiny2313/V
2543IS–AVR–04/06
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Regional Headquarters
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
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38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
Literature Requests
www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-
TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications
and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided
otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use
as components in applications intended to support or sustain life.
© Atmel Corporation 2006. All rights reserved. Atmel®, logo and combinations thereof, Everywhere You Are®, AVR®, AVR Studio®, and others,
are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
2543IS–AVR–04/06
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SI9137LG
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SI9122E
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