ATV750-20SC [ATMEL]

High Density UV Erasable Programmable Logic Device; 高密度的紫外线可擦除可编程逻辑器件


型号：	ATV750-20SC
厂家：	ATMEL
描述：	High Density UV Erasable Programmable Logic Device 高密度的紫外线可擦除可编程逻辑器件可编程逻辑器件
文件：	总14页 (文件大小：548K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Features

• Third Generation Programmable Logic Structure

– High-Density Replacement for Discrete Logic

• High-Speed — Plus a New, Low-Power Version

• Increased Logic Flexibility

– 42 Inputs and 20 Sum Terms

• Flexible Output Logic

– 20 Flip-Flops - 10 Extra

– All Can Be Individually Buried or 10 Output Directly

– Each has Individual Asynchronous Reset and Clock Terms

• Multiple Feedback Paths Provide for Buried State Machines

and I/O Bus Compatibility

• Proven and Reliable High-Speed CMOS EPROM Process

– 2000V ESD Protection

High Density UV

Erasable

– 200 mA Latchup Immunity

Programmable

Logic Device

• Reprogrammable

– Tested 100% for Programmability

• 24-pin, 300-mil Dual-In-line and 28-Lead Surface Mount Packages

Logic Diagram

ATV750

ATV750L

Description

The ATV750(L) is 100% more powerful than most other programmable logic devices

in 24-pin packages. Increased product terms, sum terms, and flip-flops translate into

more usable gates.

Each of the ATV750(L)’s twenty-two logic pins can be used as an input. Ten of these

can be used as input, output, or bi-directional I/O pins. All twenty flip-flops can be fed

back into the array independently. This flexibility allows burying all of the sum terms

and flip-flops.

There are 171 product terms available. A variable format is used to assign between

four and eight product terms per sum term. There are two sum terms per output, pro-

viding added flexibility.

(continued)

DIP/SOIC

PLCC/LCC

(Top View)

Pin Configurations

24 VCC

23 I/O

22 I/O

21 I/O

20 I/O

19 I/O

18 I/O

17 I/O

16 I/O

15 I/O

14 I/O

13 IN

Pin Name Function

Logic Inputs

25 I/O

24 I/O

23 I/O

I/O

Bidirectional Buffers

No Internal Connection

+5V Supply

21 I/O

20 I/O

19 I/O

IN 10

IN 11

IN 10

IN 11

Rev. 0024E–05/98

VCC

GND 12

The ATV750(L) has more flip-flops available than other

PLDs in this density range. Complex state machines are

easily implemented.

one clock term are provided per flip-flop, with one enable

term per output. One product term provides a global syn-

chronous preset. Register preload simplifies testing. The

device has an internal power up clear function.

Product terms are available providing asynchronous

resets, flip-flop clocks, and output enables. One reset and

Absolute Maximum Ratings

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Temperature Under Bias............................... -55°C to + 125°C

Storage Temperature.................................... -65°C to + 150°C

Voltage on Any Pin with

Respect to Ground .........................................-2.0V to +7.0V⁽¹⁾

Voltage on Input Pins

with Respect to Ground

During Programming.....................................-2.0V to +14.0V⁽¹⁾

Note:

1. Minimum voltage is -0.6V DC, which may under-

shoot to -2.0V for pulses of less than 20 ns. Max-

imum output pin voltage is Vcc + 0.75V DC,

which may overshoot to 7.0V for pulses of less

than 20 ns.

Programming Voltage with

Respect to Ground .......................................-2.0V to +14.0V⁽¹⁾

Integrated UV Erase Dose..............................7258 W.sec/cm²

Logic Options

Combined Terms

Separate Terms

Combined Terms

Separate Terms

Output Options

ATV750/L

DC and AC Operating Conditions

ATV750-20

0°C - 70°C

ATV750/750L-25

Com.

0°C - 70°C

-40°C - 85°C

-55°C - 125°C

5V ± 10%

Operating Temperature (Case)

Ind.

Mil.

-40°C - 85°C

-55°C - 125°C

5V ± 10%

V_CCPower Supply

DC Characteristics

Symbol Parameter

Condition

Min

Typ

Max

Units

Input Load

Current

µA

I_LI

V_IN= -0.1V to V_CC+ 1V

Output Leakage

Current

µA

I_LO

V_OUT= -0.1V to V_CC+ 0.1V

Com.

120

140

ATV750

V_CC= MAX,

V_IN= GND,

Outputs Open

Ind.,Mil.

Com.

Power Supply

Current

I_CC

1.0

ATV750L

Ind.,Mil.

(1)

I_OS

V_IL

Output Short Circuit Current V_OUT= 0.5V

-120

0.8

Input Low Voltage

Input High Voltage

-0.6

2.0

V_CC

V_IH

0.75

0.5

1.0

I_OL= 12 mA Com.,Ind.

I_OL= 8 mA Mil.

V_IN= V_IHor V_IL,

_CC= MIN

V_OL

Output Low Voltage

_OL= 24 mA, Com.

_OH= -100 µA

V_CC- 0.3

2.4

V_IN= V_IHor V_IL,

_CC= MIN

V_OH

Output High Voltage

I_OH= -4.0 mA

Note:

1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.

AC Waveforms⁽¹⁾

Note:

1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.

ATV750/L

AC Characteristics

ATV750-20

ATV750/750L-25

Symbol

t_PD

t_EA

Parameter

Min

Max

Min

Max

Units

Input or Feedback to Non-Registered Output

Input to Output Enable

Input to Output Disable

Clock to Output

t_ER

t_CO

t_CF

Clock to Feedback

t_S

Input Setup Time

t_SF

Feedback Setup Time

Hold Time

t_H

t_P

Clock Period

t_W

Clock Width

F_MAX

t_AW

t_AR

t_AP

Maximum Frequency

MHz

Asynchronous Reset Width

Asynchronous Reset Recovery Time

Asynchronous Reset to Registered Output Reset

Setup Time, Synchronous Preset

t_SP

Input Test Waveforms and

Measurement Levels

Output Test Loads

t_R, t_F< 5 ns (10% to 90%)

Functional Logic Diagram ATV750, Upper Half

ATV750/L

Functional Logic Diagram ATV750, Lower Half

Preload of Registered Outputs

The ATV750's registers are provided with circuitry to allow

loading of each register asynchronously with either a high

or a low. This feature will simplify testing since any state

can be forced into the registers to control test sequencing.

A V_IHlevel on the I/O pin will force the register high; a V_IL

will force it low, independent of the output polarity. The pre-

load state is entered by placing an 10.5V to 11.5V signal on

pin 8 on DIPs, and pin 10 on SMPs. When the clock term is

pulsed high, the data on the I/O pin is placed into the regis-

ter chosen by the Select Pin.

Level forced on registered output pin

during PRELOAD cycle

Select

Pin State

after cycle

V_IH

V_IL

V_IH

V_IL

Low

High

Low

High

Low

High

Power-Up Reset

The registers in the ATV750(L) are designed to reset dur-

ing power up. At a point delayed slightly from V_CCcrossing

3.8V, all registers will be reset to the low state. The output

state will depend on the polarity of the output buffer.

This feature is critical for state machine initialization. How-

ever, due to the asynchronous nature of reset and the

uncertainty of how V_CCactually rises in the system, the fol-

lowing conditions are required:

1. The V_CCrise must be monotonic,

2. After reset occurs, all input and feedback setup

times must be met before driving the clock term

high, and

Parameter Description

Min

Typ

Max

Units

t_PR

Power-Up

600

1000

3. The signals from which the clock is derived must

remain stable during t_PR.

Reset Time

(1)

Pin Capacitance (f = 1 MHz, T = 25°C)

Typ

Max

Units

Conditions

_IN= 0V

V_OUT= 0V

C_IN

C_OUT

Note:

1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.

ATV750/L

Using the ATV750's Many Advanced Features

The ATV750's flexibility puts more usable gates in 24-pins

than other PLDs. The ATV750(L) starts with an architecture

similar to the popular AT22V10, and adds several features:

Security Fuse Usage

A single fuse is provided to prevent unauthorized copying

of the ATV750(L) fuse patterns. Once programmed, the

output buffers will remain in a high impedance state during

verify.

• Asynchronous Clocks -

Each of the flip-flops in the ATV750(L) has a dedicated

product term driving the clock. The user is no longer

constrained to using one clock for all the registers.

Buried state machines, counters, and registers can all

coexist in one device, while running on separate clocks.

The ATV750(L) clock period matches that of similar

synchronous devices.

The security fuse should be programmed last, as its effect

is immediate.

Erasure Characteristics

The entire memory array of an ATV750(L) is erased after

exposure to ultraviolet light at a wavelength of 2537 Å.

Complete erasure is assured after a minimum of 20 min-

utes exposure using 12,000 µW/cm²intensity lamps

spaced one inch away from the chip. Minimum erase time

for lamps at other intensity ratings can be calculated from

the minimum integrated erasure dose of 15 W^•sec/cm². To

prevent unintentional erasure, an opaque label is recom-

mended to cover the clear window on any UV erasable

PLD which will be subjected to continuous fluorescent

indoor lighting or sunlight.

• A Full Bank of 10 More Registers -

The ATV750(L) provides two flip-flops for each output

macrocell - a total of 20. Each register has its own clock

and reset product terms, as well as its own SUM term.

• Independent I/O Pin and Feedback Paths -

Each I/O pin on the ATV750(L) has a dedicated input

path. Each of the 20 registers has individual feedback

terms into the array. This feature, combined with

individual product terms for each I/O's output enable,

facilitates designs using bi-directional I/O buses.

• Combinable Sum Terms -

Atmel CMOS PLDs

Each output macrocell’s two SUM terms can be

combined in an OR gate before the output or the register.

This provides up to 16 product terms per output or flip-

flop. This architecture increases the number of usable

gates available.

Atmel’s Programmable Logic Devices utilize an advanced

1.5-micron CMOS EPROM technology. This technology's

state of the art features are the optimum combination for

PLDs:

• CMOS technology provides high speed, low power, and

high noise immunity.

Programming Software Support

• EPROM technology is the most cost effective method for

producing PLDs - surpassing bipolar fusible link

technology in low cost, while providing the necessary

reprogrammability.

Software which is capable of transforming Boolean equa-

tions, state machine descriptions and truth tables into

JEDEC files for the ATV750(L) is available from several

PLD software vendors. Please refer to the Software Sup-

port Information table in the Programmable Logic Develop-

ment Tools section for more information.

• EPROM reprogrammability, which is 100% tested before

shipment, provides inherently better programmability and

reliability than one-time fusible PLDs.

Synchronous Preset and

Asynchronous Reset

One synchronous preset line is provided for all 20 registers

in the ATV750(L). The appropriate input signals to cause

the internal clocks to go to a high state must be received

during a synchronous preset. Appropriate setup and hold

times must be met, as shown in the switching waveform

diagram.

• Atmel's EPROM process has proven extremely reliable

in the volume production of a full line of advanced

EPROM memory products, from 64K to one-megabit

devices.

An individual asynchronous reset line is provided for each

of the 20 flip-flops. Both master and slave halves of the flip-

flops are reset when the input signals received combine so

as to force the internal resets high.

ATV750/L

Ordering Information

t_PD

t_CO

f_MAX

(ns)

(MHz)

Ordering Code

Package

Operation Range

ATV750-20JC

ATV750-20PC

ATV750-20SC

28J

Commercial

24P3

24S

(0°C to 70°C)

ATV750-20JI

ATV750-20PI

ATV750-20SI

28J

Industrial

24P3

24S

(-40°C to 85°C)

ATV750-20DM

ATV750-20GM

ATV750-20LM

ATV750-20NM

24DW3

24D3

28LW

28L

Military

(-55°C to 125°C)

ATV750-20DM/883

ATV750-20GM/883

ATV750-20LM/883

ATV750-20NM/883

24DW3

24D3

28LW

28L

Military/883C

(-55°C to 125°C)

ATV750-25JC

ATV750-25PC

ATV750-25SC

28J

Commercial

24P3

24S

(0°C to 70°C)

ATV750-25JI

ATV750-25PI

ATV750-25SI

28J

Industrial

24P3

24S

(-40°C to 85°C)

ATV750-25DM

ATV750-25GM

ATV750-25LM

ATV750-25NM

24DW3

24D3

28LW

28L

Military

(-55°C to 125°C)

ATV750-25DM/883

ATV750-25GM/883

ATV750-25LM/883

ATV750-25NM/883

24DW3

24D3

28LW

28L

Military/883C

(-55°C to 125°C)

Class B, Fully Compliant

5962-88726 04 LA

5962-88726 04 3X

5962-94524 03 MLA

5962-94524 03 M3X

24DW3

28LW

24D3

28L

Military/883C

(-55°C to 125°C)

Class B, Fully Compliant

5962-88726 03 LA

5962-88726 03 3X

5962-94524 02 MLA

5962-94524 02 M3X

24DW3

28LW

24D3

28L

Military/883C

(-55°C to 125°C)

Class B, Fully Compliant

Ordering Information (Continued)

t_PD

t_CO

f_MAX

(ns)

(MHz)

Ordering Code

Package

Operation Range

ATV750L-25JC

ATV750L-25PC

ATV750L-25SC

28J

Commercial

24P3

24S

(0°C to 70°C)

ATV750L-25JI

ATV750L-25PI

ATV750L-25SI

28J

Industrial

24P3

24S

(-40°C to 85°C)

ATV750L-25DM

ATV750L-25GM

ATV750L-25LM

ATV750L-25NM

24DW3

24D3

28LW

28L

Military

(-55°C to 125°C)

ATV750L-25DM/883

ATV750L-25GM/883

ATV750L-25LM/883

ATV750L-25NM/883

24DW3

24D3

28LW

28L

Military/883C

(-55°C to 125°C)

Class B, Fully Compliant

5962-88726 07 LX

5962-88726 07 3X

5962-94524 05 MLA

5962-94524 05 M3X

24DW3

28LW

24D3

28L

Military/883C

(-55°C to 125°C)

Class B, Fully Compliant

Package Type

24DW3

24D3

28J

24-Lead, 0.300" Wide, Windowed, Ceramic Dual In-line Package (Cerdip)

24-Lead, 0.300" Wide, Non-Windowed (OTP) Ceramic Dual In-line Package (Cerdip)

28-Lead, Plastic J-Leaded Chip Carrier OTP (PLCC)

28LW

28L

28-Pad, Windowed, Ceramic Leadless Chip Carrier (LCC)

28-Pad, Non-Windowed, Ceramic Leadless Chip Carrier OTP (LCC)

24-Lead, 0.300" Wide, Plastic Dual In-line Package OTP (PDIP)

24-Lead, 0.300" Wide, Plastic Gull Wing Small Outline OTP (SOIC)

24P3

24S

ATV750/L

Packaging Information

24DW3, 24-Lead, 0.300" Wide, Windowed, Ceramic

Dual In-line Package (Cerdip)

24D3, 24-Lead, 0.300" Wide, Non-Windowed (OTP)

Ceramic Dual In-line Package (Cerdip)

Dimensions in Inches and (Millimeters)

1.28(32.5)

1.24(31.5)

.310(7.87)

.285(7.24)

.098(2.49)

MAX

.005(.127)

MIN

1.100(27.94) REF

.200(5.08)

MAX

SEATING

PLANE

.060(1.52)

.015(.381)

.023(.584)

.200(5.08)

.125(3.18)

.065(1.65)

.045(1.14)

.014(.356)

.110(2.79)

.090(2.29)

.325(8.25)

.300(7.62)

REF

.015(.381)

.008(.203)

.400(10.2) MAX

28J, 28-Lead, Plastic J-Leaded

Chip Carrier OTP (PLCC)

Dimensions in Inches and (Millimeters)

28LW, 28-Pad, Windowed,

Ceramic Leadless Chip Carrier (LCC)

Dimensions in Inches and (Millimeters)

.045(1.14) X 30° - 45°

.045(1.14) X 45° PIN NO. 1

IDENTIFY

.012(.305)

.008(.203)

.430(10.9)

.390(9.91)

.021(.533)

.013(.330)

.456(11.6)

.450(11.4)

.032(.813)

.026(.660)

.495(12.6)

.485(12.3)

.050(1.27) TYP

.043(1.09)

.300(7.62) REF SQ

.020(.508)

.120(3.05)

.090(2.29)

.180(4.57)

.165(4.19)

.022(.559) X 45° MAX (3X)

Packaging Information

28L, 28-Pad, Non-Windowed, Ceramic Leadless

Chip Carrier OTP (LCC)

24P3, 24-Lead, 0.300" Wide, Plastic Dual Inline

Package OTP (PDIP)

Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-001 AF

1.27(32.3)

1.25(31.7)

.266(6.76)

.250(6.35)

.090(2.29)

MAX

1.100(27.94) REF

.200(5.06)

MAX

.005(.127)

MIN

SEATING

PLANE

.070(1.78)

.020(.508)

.023(.584)

.014(.356)

.151(3.84)

.125(3.18)

.065(1.65)

.040(1.02)

.110(2.79)

.090(2.29)

.325(8.26)

.300(7.62)

REF

.012(.305)

.008(.203)

.400(10.2) MAX

24S, 24-Lead, 0.300" Wide, Plastic Gull Wing Small

Outline OTP (SOIC)

Dimensions in Inches and (Millimeters)

.020(.508)

.013(.330)

.299(7.60) .420(10.7)

.291(7.39) .393(9.98)

PIN 1 ID

.050(1.27) BSC

.616(15.6)

.105(2.67)

.598(15.2)

.092(2.34)

.012(.305)

.003(.076)

.013(.330)

.009(.229)

.050(1.27)

REF

.015(.381)

ATV750/L

ATV750-20SC [ATMEL]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E