ATXMEGA16D4-MH-SL383 [ATMEL]
Microcontroller;型号: | ATXMEGA16D4-MH-SL383 |
厂家: | ATMEL |
描述: | Microcontroller 微控制器 |
文件: | 总109页 (文件大小:3680K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Features
• High-performance, Low-power 8/16-bit Atmel® AVR® XMEGA® Microcontroller
• Non-volatile Program and Data Memories
– 16 KB - 128 KB of In-System Self-Programmable Flash
– 4 KB - 8 KB Boot Code Section with Independent Lock Bits
– 1 KB - 2 KB EEPROM
– 2 KB - 8 KB Internal SRAM
• Peripheral Features
– Four-channel Event System
– Four 16-bit Timer/Counters
8/16-bit
XMEGA D4
Microcontroller
Three Timer/Counters with 4 Output Compare or Input Capture channels
One Timer/Counter with 2 Output Compare or Input Capture channels
High-Resolution Extensions on two Timer/Counters
Advanced Waveform Extension on one Timer/Counter
– Two USARTs
IrDA Extension on one USART
– Two Two-Wire Interfaces with dual address match (I2C and SMBus compatible)
– Two SPIs (Serial Peripheral Interfaces) peripherals
– 16-bit Real Time Counter with Separate Oscillator
– One Twelve-channel, 12-bit, 200 ksps Analog to Digital Converter
– Two Analog Comparators with Window compare function
– External Interrupts on all General Purpose I/O pins
– Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator
• Special Microcontroller Features
ATxmega128D4
ATxmega64D4
ATxmega32D4
ATxmega16D4
– Power-on Reset and Programmable Brown-out Detection
– Internal and External Clock Options with PLL
– Programmable Multi-level Interrupt Controller
– Sleep Modes: Idle, Power-down, Standby, Power-save, Extended Standby
– Advanced Programming, Test and Debugging Interface
PDI (Program and Debug Interface) for programming, test and debugging
• I/O and Packages
Preliminary
– 34 Programmable I/O Lines
– 44-lead TQFP
– 44-pad VQFN/QFN
– 49-ball VFBGA
• Operating Voltage
– 1.6 – 3.6V
• Speed performance
– 0 – 12 MHz @ 1.6 – 3.6V
– 0 – 32 MHz @ 2.7 – 3.6V
Typical Applications
• Industrial control
• Factory automation
• Building control
• Board control
• Climate control
• ZigBee
• Hand-held battery applications
• Power tools
• HVAC
• Metering
• Medical Applications
• Motor control
• Networking
• Optical
• White Goods
8135I–AVR–10/10
XMEGA D4
1. Ordering Information
Ordering Code
Flash
E2
SRAM
8 KB
4 KB
4 KB
2 KB
8 KB
4 KB
4 KB
2 KB
4 KB
2 KB
Speed (MHz) Power Supply Package(1)(2)(3)
Temp
ATxmega128D4- AU
ATxmega64D4-AU
ATxmega32D4-AU
ATxmega16D4-AU
ATxmega128D4- MH
ATxmega64D4-MH
ATxmega32D4-MH
ATxmega16D4-MH
ATxmega32D4-CU
ATxmega16D4-CU
128 KB + 8 KB
64 KB + 4 KB
32 KB + 4 KB
16 KB + 4 KB
128 KB + 8 KB
64 KB + 4 KB
32 KB + 4 KB
16 KB + 4 KB
32 KB + 4 KB
16 KB + 4 KB
2 KB
2 KB
1 KB
1 KB
2 KB
2 KB
1 KB
1 KB
1 KB
1 KB
32
32
32
32
32
32
32
32
32
32
1.6 - 3.6V
1.6 - 3.6V
1.6 - 3.6V
1.6 - 3.6V
1.6 - 3.6V
1.6 - 3.6V
1.6 - 3.6V
1.6 - 3.6V
1.6 - 3.6V
1.6 - 3.6V
44A
-40°C - 85°C
44M1
49C2
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For packaging information see ”Packaging information” on page 55.
Package Type
44A
44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
44-pad, 7 x 7 x 1.0 mm Body, Lead Pitch 0.50 mm, 5.20 mm Exposed Pad, Thermally Enhanced Plastic Very Thin Quad No
Lead Package (VQFN)
44M1
49C2
49-ball (7 x 7 Array), 0.65 mm Pitch, 5.0 x 5.0 x 1.0 mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA)
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XMEGA D4
2. Pinout/Block Diagram
Figure 2-1. Bock Diagram and TQFP/QFN pinout
INDEX CORNER
33
32
31
30
29
28
27
26
25
24
23
PE3
PE2
VCC
GND
PE1
PE0
PD7
PD6
PD5
PD4
PD3
PA5
PA6
1
Port R
DATA BU S
2
OSC/CLK
Control
ADC A
AC A0
AC A1
PA7
3
BOD
TEMP
VREF
POR
OCD
PB0
PB1
PB2
PB3
GND
VCC
PC0
PC1
4
RTC
Power
Control
FLASH
5
RAM
Reset
Control
CPU
6
E2PROM
Interrupt Controller
Event System ctrl
DATA BU S
7
Watchdog
8
EVENT ROUTING NETWORK
9
10
11
Port C
Port D
Port E
Notes: 1. For full details on pinout and pin functions refer to ”Pinout and Pin Functions” on page 46.
2. The large center pad underneath the QFN/MLF package should be soldered to ground on the board to ensure good
mechanical stability.
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XMEGA D4
Figure 2-2. VFBGA pinout
Top view
Bottom view
1 2 3 4 5 6 7
7 6 5 4 3 2 1
A
B
C
D
E
F
A
B
C
D
E
F
G
G
Table 2-1.
VFBGA pinout
1
2
3
4
5
PR0
6
A
B
C
D
E
F
PA3
PA4
PA5
PB1
GND
VCC
PC1
AVCC
PA1
GND
PA0
PA6
PB3
PC3
PC4
PC5
PR1
GND
PA7
PB0
GND
PC6
PC7
PDI
PE3
RESET/PDI
GND
PE2
PE1
PD7
PD5
PD1
VCC
VCC
PA2
GND
PE0
PD6
PD3
PD2
PB2
GND
PC0
PC2
GND
PD4
PD0
G
GND
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XMEGA D4
3. Overview
The Atmel® AVR® XMEGA® D4 is a family of low power, high performance and peripheral rich
CMOS 8/16-bit microcontrollers based on the AVR® enhanced RISC architecture. By executing
powerful instructions in a single clock cycle, the XMEGA D4 achieves throughputs approaching
1 Million Instructions Per Second (MIPS) per MHz allowing the system designer to optimize
power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction, executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs many times faster than conven-
tional single-accumulator or CISC based microcontrollers.
The XMEGA D4 devices provide the following features: In-System Programmable Flash with
Read-While-Write capabilities, Internal EEPROM and SRAM, four-channel Event System, Pro-
grammable Multi-level Interrupt Controller, 34 general purpose I/O lines, 16-bit Real Time
Counter (RTC), four flexible 16-bit Timer/Counters with compare modes and PWM, two
USARTs, two Two-Wire Interfaces (TWIs), two Serial Peripheral Interfaces (SPIs), one Twelve-
channel 12-bit ADC with optional differential input with programmable gain, two analog compar-
ators with window mode, programmable Watchdog Timer with separate Internal Oscillator,
accurate internal oscillators with PLL and prescaler and programmable Brown-Out Detection.
The Program and Debug Interface (PDI), a fast 2-pin interface for programming and debugging,
is available.
The XMEGA D4 devices have five software selectable power saving modes. The Idle mode
stops the CPU while allowing the SRAM, Event System, Interrupt Controller and all peripherals
to continue functioning. The Power-down mode saves the SRAM and register contents but stops
the oscillators, disabling all other functions until the next TWI or pin-change interrupt, or Reset.
In Power-save mode, the asynchronous Real Time Counter continues to run, allowing the appli-
cation to maintain a timer base while the rest of the device is sleeping. In Standby mode, the
Crystal/Resonator Oscillator is kept running while the rest of the device is sleeping. This allows
very fast start-up from external crystal combined with low power consumption. In Extended
Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. To further
reduce power consumption, the peripheral clock to each individual peripheral can optionally be
stopped in Active mode and in Idle sleep mode.
The device is manufactured using Atmel's high-density nonvolatile memory technology. The pro-
gram Flash memory can be reprogrammed in-system through the PDI. A Bootloader running in
the device can use any interface to download the application program to the Flash memory. The
Bootloader software in the Boot Flash section will continue to run while the Application Flash
section is updated, providing true Read-While-Write operation. By combining an 8/16-bit RISC
CPU with In-System Self-Programmable Flash, the Atmel XMEGA D4 is a powerful microcon-
troller family that provides a highly flexible and cost effective solution for many embedded
applications.
The XMEGA D4 devices are supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, programmers,
and evaluation kits.
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XMEGA D4
3.1
Block Diagram
Figure 3-1. XMEGA D4 Block Diagram
PR[0..1]
XTAL1/
TOSC1
XTAL2/
TOSC2
Oscillator
Circuits/
Clock
Watchdog
Oscillator
Real Time
Counter
PORT R (2)
Generation
Watchdog
Timer
DATA BUS
VCC
GND
Event System
Controller
Oscillator
Control
Power
Supervision
POR/BOD &
RESET
A[0..7]
PORT A (8)
SRAM
Sleep
Controller
ACA
ADCA
RESET/
PDI_CLK
BUS
Controller
Prog/Debug
Controller
PDI
AREFA
VCC/10
Int. Refs.
Tempref
AREFB
PDI_DATA
OCD
CPU
Interrupt
Controller
B[0..7]
PORT B (8)
NVM Controller
Flash
EEPROM
IRCOM
DATA BUS
EVENT ROUTING NETWORK
PORT C (8)
PORT D (8)
PORT E (4)
PC[0..7]
PD[0..7]
PE[0..3]
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XMEGA D4
4. Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
4.1
Recommended reading
• XMEGA D Manual
• XMEGA Application Notes
This device datasheet only contains part specific information and a short description of each
peripheral and module. The XMEGA D Manual describes the modules and peripherals in depth.
The XMEGA application notes contain example code and show applied use of the modules and
peripherals.
The XMEGA Manual and Application Notes are available from http://www.atmel.com/avr.
5. Disclaimer
For devices that are not available yet, typical values contained in this datasheet are based on
simulations and characterization of other AVR XMEGA microcontrollers manufactured on the
same process technology. Min. and Max values will be available after the device is
characterized.
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XMEGA D4
6. AVR CPU
6.1
Features
• 8/16-bit high performance AVR RISC Architecture
– 138 instructions
– Hardware multiplier
• 32x8-bit registers directly connected to the ALU
• Stack in RAM
• Stack Pointer accessible in I/O memory space
• Direct addressing of up to 16M Bytes of program and data memory
• True 16/24-bit access to 16/24-bit I/O registers
• Support for for both 8-, 16- and 32-bit Arithmetic
• Configuration Change Protection of system critical features
6.2
Overview
The XMEGA D4 uses the 8/16-bit AVR CPU. The main function of the CPU is program execu-
tion. The CPU must therefore be able to access memories, perform calculations and control
peripherals. Interrupt handling is described in a separate section. Figure 6-1 on page 8 shows
the CPU block diagram.
Figure 6-1. CPU block diagram
DATA BUS
Flash
Program
Program
Counter
Memory
32 x 8 General
Purpose
Registers
Instruction
Register
OCD
STATUS/
CONTROL
Instruction
Decode
Multiplier
ALU
DATA BUS
Peripheral
Module 1
Peripheral
Module 2
SRAM
EEPROM
PMIC
The AVR uses a Harvard architecture - with separate memories and buses for program and
data. Instructions in the program memory are executed with a single level pipeline. While one
instruction is being executed, the next instruction is pre-fetched from the program memory.
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8135I–AVR–10/10
XMEGA D4
This concept enables instructions to be executed in every clock cycle. The program memory is
In-System Re-programmable Flash memory.
6.3
6.4
Register File
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-
ical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File - in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing - enabling efficient address calculations. One of these address pointers can
also be used as an address pointer for look up tables in Flash program memory.
ALU - Arithmetic Logic Unit
The high performance Arithmetic Logic Unit (ALU) supports arithmetic and logic operations
between registers or between a constant and a register. Single register operations can also be
executed. Within a single clock cycle, arithmetic operations between general purpose registers
or between a register and an immediate are executed. After an arithmetic or logic operation, the
Status Register is updated to reflect information about the result of the operation.
The ALU operations are divided into three main categories – arithmetic, logical, and bit-func-
tions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for easy
implementation of 32-bit arithmetic. The ALU also provides a powerful multiplier supporting both
signed and unsigned multiplication and fractional format.
6.5
Program Flow
When the device is powered on, the CPU starts to execute instructions from the lowest address
in the Flash Program Memory ‘0’. The Program Counter (PC) addresses the next instruction to
be fetched. After a reset, the PC is set to location ‘0’.
Program flow is provided by conditional and unconditional jump and call instructions, capable of
addressing the whole address space directly. Most AVR instructions use a 16-bit word format,
while a limited number uses a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the Stack. The Stack
is effectively allocated in the general data SRAM, and consequently the Stack size is only limited
by the total SRAM size and the usage of the SRAM. After reset the Stack Pointer (SP) points to
the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory
space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can
easily be accessed through the five different addressing modes supported in the AVR CPU.
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8135I–AVR–10/10
XMEGA D4
7. Memories
7.1
Features
• Flash Program Memory
– One linear address space
– In-System Programmable
– Self-Programming and Bootloader support
– Application Section for application code
– Application Table Section for application code or data storage
– Boot Section for application code or bootloader code
– Separate lock bits and protection for all sections
• Data Memory
– One linear address space
– Single cycle access from CPU
– SRAM
– EEPROM
Byte and page accessible
Optional memory mapping for direct load and store
– I/O Memory
Configuration and Status registers for all peripherals and modules
Four bit-accessible General Purpose Register for global variables or flags
• Production Signature Row Memory for factory programmed data
Device ID for each microcontroller device type
Serial number for each device
Oscillator calibration bytes
ADC and temperature sensor calibration data
• User Signature Row
One flash page in size
Can be read and written from software
Content is kept after chip erase
7.2
Overview
The AVR architecture has two main memory spaces, the Program Memory and the Data Mem-
ory. In addition, the XMEGA D4 features an EEPROM Memory for non-volatile data storage. All
three memory spaces are linear and require no paging. The available memory size configura-
tions are shown in ”Ordering Information” on page 2. In addition each device has a Flash
memory signature row for calibration data, device identification, serial number etc.
Non-volatile memory spaces can be locked for further write or read/write operations. This pre-
vents unrestricted access to the application software.
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8135I–AVR–10/10
XMEGA D4
7.3
In-System Programmable Flash Program Memory
The XMEGA D4 devices contain On-chip In-System Programmable Flash memory for program
storage, see Figure 7-1 on page 11. Since all AVR instructions are 16- or 32-bits wide, each
Flash address location is 16 bits.
The Program Flash memory space is divided into Application and Boot sections. Both sections
have dedicated Lock Bits for setting restrictions on write or read/write operations.
The Store Program Memory (SPM) instruction must reside in the Boot Section when used to
write to the Flash memory.
A third section inside the Application section is referred to as the Application Table section which
has separate Lock bits for storage of write or read/write protection. The Application Table sec-
tion can be used for storing non-volatile data or application software.
Figure 7-1. Flash Program Memory (Hexadecimal address)
Word Address
0
Application Section
(128K/64 KB/32 KB/16 KB)
...
EFFF
F000
/
/
/
/
/
77FF
7800
7FFF
8000
87FF
/
/
/
/
/
37FF
3800
3FFF
4000
47FF
/
/
/
/
/
17FF
1800
1FFF
2000
27FF
Application Table Section
(4 KB/4 KB/4 KB/4 KB)
FFFF
10000
10FFF
Boot Section
(8 KB/4 KB/4 KB/4 KB)
The Application Table Section and Boot Section can also be used for general application
software.
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XMEGA D4
7.4
Data Memory
The Data Memory containts the I/O Memory, EEPROM and SRAM memories, all within one lin-
ear address space, see Figure 7-2 on page 12. To simplify development, the memory map for all
devices in the family is identical and with empty, reserved memory space for smaller devices.
Figure 7-2. Data Memory Map (Hexadecimal address)
Byte Address
ATxmega64D4
Byte Address
ATxmega32D4
Byte Address
ATxmega16D4
0
0
0
I/O Registers
(4KB)
I/O Registers
(4KB)
I/O Registers
(4KB)
FFF
1000
17FF
FFF
1000
13FF
FFF
1000
13FF
EEPROM
(2K)
EEPROM
(1 KB)
EEPROM
(1 KB)
RESERVED
RESERVED
RESERVED
2000
2FFF
2000
2FFF
2000
27FF
Internal SRAM
(4 KB)
Internal SRAM
(4 KB)
Internal SRAM
(2 KB)
Byte Address
ATxmega128D4
0
FFF
I/O Registers
(4 KB)
1000
17FF
EEPROM
(2K)
RESERVED
2000
3FFF
Internal SRAM
(8K)
7.4.1
I/O Memory
All peripherals and modules are addressable through I/O memory locations in the data memory
space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store
(ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the
CPU and the I/O Memory.
The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F
directly.
I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and
CBI instructions. The value of single bits can be checked by using the SBIS and SBIC instruc-
tions on these registers.
The I/O memory address for all peripherals and modules in XMEGA D4 is shown in the ”Periph-
eral Module Address Map” on page 50.
7.4.2
SRAM Data Memory
The XMEGA D4 devices have internal SRAM memory for data storage.
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XMEGA D4
7.4.3
EEPROM Data Memory
The XMEGA D4 devices have internal EEPROM memory for non-volatile data storage. It is
addressable either in a separate data space or it can be memory mapped into the normal data
memory space. The EEPROM memory supports both byte and page access.
7.5
Production Signature Row
The Production Signature Row is a separate memory section for factory programmed data. It
contains calibration data for functions such as oscillators and analog modules.
The production signature row also contains a device ID that identify each microcontroller device
type, and a serial number that is unique for each manufactured device. The device ID for the
available XMEGA A4 devices is shown in Table 7-1 on page 13. The serial number consist of
the production LOT number, wafer number, and wafer coordinates for the device.
The production signature row can not be written or erased, but it can be read from both applica-
tion software and external programming.
Table 7-1.
Device ID bytes for XMEGA D4 devices.
Device
Byte 2
42
Device ID bytes
Byte 1
94
Byte 0
1E
ATxmega16D4
ATxmega32D4
ATxmega64D4
42
95
1E
47
96
1E
ATxmega128D4
47
97
1E
7.6
7.7
User Signature Row
The User Signature Row is a separate memory section that is fully accessible (read and write)
from application software and external programming. The user signature row is one flash page
in size, and is meant for static user parameter storage, such as calibration data, custom serial
numbers or identification numbers, random number seeds etc. This section is not erased by
Chip Erase commands that erase the Flash, and requires a dedicated erase command. This
ensures parameter storage during multiple program/erase session and on-chip debug sessions.
Flash and EEPROM Page Size
The Flash Program Memory and EEPROM data memory are organized in pages. The pages are
word accessible for the Flash and byte accessible for the EEPROM.
Table 7-2 on page 14 shows the Flash Program Memory organization. Flash write and erase
operations are performed on one page at the time, while reading the Flash is done one byte at
the time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant
bits in the address (FPAGE) give the page number and the least significant address bits
(FWORD) give the word in the page.
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XMEGA D4
Table 7-2.
Number of words and Pages in the Flash.
Devices
Flash
Page Size
FWORD
FPAGE
Application
Boot
Size
(words)
128
Size
No of Pages
Size
4 KB
4 KB
4 KB
8 KB
No of Pages
ATxmega16D4
ATxmega32D4
ATxmega64D4
ATxmega128D4
16 KB + 4 KB
32 KB + 4 KB
64 KB + 4 KB
128 KB + 8 KB
Z[6:0]
Z[6:0]
Z[6:0]
Z[7:0]
Z[13:7]
Z[14:7]
Z[15:7]
Z[16:8]
16 KB
32 KB
64 KB
128 KB
64
16
16
16
16
128
128
256
256
128
256
Table 7-3 on page 14 shows EEPROM memory organization for the XMEGA D4 devices.
EEPROM write and erase operations can be performed one page or one byte at the time, while
reading the EEPROM is done one byte at the time. For EEPROM access the NVM Address
Register (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE)
give the page number and the least significant address bits (E2BYTE) give the byte in the page.
Table 7-3.
EEPROM
Size
Number of Bytes and Pages in the EEPROM.
Devices
Page Size
E2BYTE
E2PAGE
No of Pages
(Bytes)
32
ATxmega16D4
ATxmega32D4
ATxmega64D4
ATxmega128D4
1 KB
ADDR[4:0]
ADDR[4:0]
ADDR[4:0]
ADDR[4:0]
ADDR[10:5]
ADDR[10:5]
ADDR[10:5]
ADDR[10:5]
32
32
64
64
1 KB
32
2 KB
32
2 KB
32
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XMEGA D4
8. Event System
8.1
Features
• Inter-peripheral communication and signalling with minimum latency
• CPU independent operation
• 4 Event Channels allow for up to 4 signals to be routed at the same time
• 100% predictable timing between peripherals
• Events can be generated by
– TImer/Counters (TCxn)
– Real Time Counter (RTC)
– Analog to Digital Converter (ADCx)
– Analog Comparator (ACx)
– Ports (PORTx)
– System Clock (ClkSYS
)
– Software (CPU)
• Events can be used by
– TImer/Counters (TCxn)
– Analog to Digital Converter (ADCx)
– Ports (PORTx)
– IR Communication Module (IRCOM)
• The same event can be used by multiple peripherals for synchronized timing
• Advanced Features
– Manual Event Generation from software (CPU)
– Quadrature Decoding
– Digital Filtering
• Functiond in Active and Idle mode
8.2
Overview
The Event System is a set of features for inter-peripheral communication. It enables the possibil-
ity for a change of state in one peripheral to automatically trigger actions in other peripherals.
The change of state in a peripheral that will trigger actions in other peripherals is configurable in
software. It is a simple, but powerful system as it allows for autonomous control of peripherals
without any use of interrupt, CPU resource.
The indication of a change in a peripheral is referred to as an event, and is usually the same as
the interrupt conditions for that peripheral. Events are passed between peripherals using a dedi-
cated routing network called the Event Routing Network. Figure 8-1 on page 16 shows a basic
block diagram of the Event System with the Event Routing Network and the peripherals to which
it is connected. This highly flexible system can be used for simple routing of signals, pin func-
tions or for sequencing of events.
The maximum latency is two CPU clock cycles from when an event is generated in one periph-
eral, until the actions are triggered in one or more other peripherals.
The Event System is functional in both Active and Idle modes.
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XMEGA D4
Figure 8-1. Event System Block Diagram
ClkSYS
CPU
PORTx
RTC
ACx
Event Routing
Network
ADCx
IRCOM
T/Cxn
The Event Routing Network can directly connect together ADCs, Analog Comparators (ACx),
I/O ports (PORTx), the Real-time Counter (RTC), Timer/Counters (T/C) and the IR Communica-
tion Module (IRCOM). Events can also be generated from software (CPU).
All events from all peripherals are always routed into the Event Routing Network. This consist of
eight multiplexers where each can be configured in software to select which event to be routed
into that event channel. All eight event channels are connected to the peripherals that can use
events, and each of these peripherals can be configured to use events from one or more event
channels to automatically trigger a software selectable action.
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9. System Clock and Clock options
9.1
Features
• Fast start-up time
• Safe run-time clock switching
• Internal Oscillators:
– 32 MHz run-time calibrated RC oscillator
– 2 MHz run-time calibrated RC oscillator
– 32.768 kHz calibrated RC oscillator
– 32 kHz Ultra Low Power (ULP) oscillator with 1 kHz output
• External clock options
– 0.4 - 16 MHz Crystal Oscillator
– 32.768 kHz Crystal Oscillator
– External clock
• PLL with internal and external clock options with 1 to 31x multiplication
• Clock Prescalers with 1 to 2048x division
• Fast peripheral clock running at time the CPU clock speed
• Automatic Run-Time Calibration of internal oscillators
• Crystal Oscillator failure detection
9.2
Overview
XMEGA D4 has an advanced clock system, supporting a large number of clock sources. It incor-
porates both accurate integrated oscillators, external crystal oscillators and resonators. A high
frequency Phase Locked Loop (PLL) and clock prescalers can be used to generate a wide range
of clock frequencies. A calibration feature (DFLL) is available, and can be used for automatic
run-time calibration of the internal oscillators. A Crystal Oscillator Failure Monitor can be enabled
to issue a Non-Maskable Interrupt and switch to internal oscillator if the external oscillator fails.
After reset, the device will always start up running from the 2 MHz internal oscillator. During nor-
mal operation, the System Clock source and prescalers can be changed from software at any
time.
A Crystal Oscillator Failure Monitor can be enabled to issue a Non-Maskable Interrupt and
switch to internal oscillator if the external oscillator fails. Figure 9-1 on page 18 shows the princi-
pal clock system in XMEGA D4.
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Figure 9-1. Clock system overview
clkULP
clkRTC
WDT/BOD
RTC
32 kHz ULP
Internal Oscillator
32.768 kHz
Calibrated Internal
Oscillator
PERIPHERALS
ADC
2 MHz
Run-Time Calibrated
Internal Oscillator
PORTS
...
CLOCK CONTROL
UNIT
32 MHz
Run-time Calibrated
Internal Oscillator
clkPER
with PLL and
Prescaler
INTERRUPT
EVSYS
32.768 KHz
Crystal Oscillator
RAM
0.4 - 16 MHz
Crystal Oscillator
CPU
NVM MEMORY
FLASH
clkCPU
External
Clock Input
EEPROM
Each clock source is briefly described in the following sub-sections.
9.3
Clock Options
9.3.1
32 kHz Ultra Low Power Internal Oscillator
The 32 kHz Ultra Low Power (ULP) Internal Oscillator is a very low power consumption clock
source. It is used for the Watchdog Timer, Brown-Out Detection and as an asynchronous clock
source for the Real Time Counter. This oscillator cannot be used as the system clock source,
and it cannot be directly controlled from software.
9.3.2
32.768 kHz Calibrated Internal Oscillator
The 32.768 kHz Calibrated Internal Oscillator is a high accuracy clock source that can be used
as the system clock source or as an asynchronous clock source for the Real Time Counter. It is
calibrated during production to provide a default frequency which is close to its nominal
frequency.
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9.3.3
9.3.4
9.3.5
32.768 kHz Crystal Oscillator
The 32.768 kHz Crystal Oscillator is a low power driver for an external watch crystal. It can be
used as system clock source or as asynchronous clock source for the Real Time Counter.
0.4 - 16 MHz Crystal Oscillator
The 0.4 - 16 MHz Crystal Oscillator is a driver intended for driving both external resonators and
crystals ranging from 400 kHz to 16 MHz.
2 MHz Run-time Calibrated Internal Oscillator
The 2 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated
during production to provide a default frequency which is close to its nominal frequency. The
oscillator can use the 32 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator as a
source for calibrating the frequency run-time to compensate for temperature and voltage drift
hereby optimizing the accuracy of the oscillator.
9.3.6
32 MHz Run-time Calibrated Internal Oscillator
The 32 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated
during production to provide a default frequency which is close to its nominal frequency. The
oscillator can use the 32.768 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator
as a source for calibrating the frequency run-time to compensate for temperature and voltage
drift hereby optimizing the accuracy of the oscillator.
9.3.7
9.3.8
External Clock input
The external clock input gives the possibility to connect a clock from an external source.
PLL with Multiplication factor 1 - 31x
The PLL provides the possibility of multiplying a frequency by any number from 1 to 31. In com-
bination with the prescalers, this gives a wide range of output frequencies from all clock sources.
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10. Power Management and Sleep Modes
10.1 Features
• 5 sleep modes
– Idle
– Power-down
– Power-save
– Standby
– Extended standby
• Power Reduction registers to disable clocks to unused peripherals
10.2 Overview
XMEGA provides various sleep modes and software controlled clock gating in order to tailor
power consumption to the application's requirement. Sleep modes enables the microcontroller to
shut down unused modules to save power. When the device enters sleep mode, program exe-
cution is stopped and interrupts or reset is used to wake the device again. The individual clock to
unused peripherals can be stopped during normal operation or in sleep, enabling a much more
fine tuned power management than sleep modes alone
10.3 Sleep Modes
Sleep modes are used to shut down modules and clock domains in the microcontroller in order
to save power. XMEGA has five different sleep modes. A dedicated Sleep instruction (SLEEP) is
available to enter sleep. Before executing SLEEP, the selected sleep mode to enter must be
configured. The available interrupt wake-up sources is dependent on the selected sleep mode.
When an enabled interrupt occurs the device will wake up and execute the interrupt service rou-
tine before continuing normal program execution from the first instruction after the SLEEP
instruction. If other higher priority interrupts are pending when the wake-up occurs, their interrupt
service routines will be executed according to their priority before the interrupt service routine for
the wake-up interrupt is executed. After wake-up the CPU is halted for four cycles before execu-
tion starts.
10.3.1
10.3.2
Idle Mode
In Idle mode the CPU and Non-Volatile Memory are stopped, but all peripherals including the
Interrupt Controller and Event System are kept running. Interrupt requests from all enabled inter-
rupts will wake the device.
Power-down Mode
In Power-down mode all system clock sources, and the asynchronous Real Time Counter (RTC)
clock source, are stopped. This allows operation of asynchronous modules only. The only inter-
rupts that can wake up the MCU are the Two Wire Interface address match interrupts, and
asynchronous port interrupts.
10.3.3
Power-save Mode
Power-save mode is identical to Power-down, with one exception:
If the Real Time Counter (RTC) is enabled, it will keep running during sleep and the device can
also wake up from either RTC Overflow or Compare Match interrupt.
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10.3.4
10.3.5
Standby Mode
Standby mode is identical to Power-down with the exception that all enabled system clock
sources are kept running, while the CPU, Peripheral and RTC clocks are stopped. This reduces
the wake-up time when external crystals or resonators are used.
Extended Standby Mode
Extended Standby mode is identical to Power-save mode with the exception that all enabled
system clock sources are kept running while the CPU and Peripheral clocks are stopped. This
reduces the wake-up time when external crystals or resonators are used.
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11. System Control and Reset
11.1 Features
• Multiple reset sources for safe operation and device reset
– Power-On Reset
– External Reset
– Watchdog Reset
The Watchdog Timer runs from separate, dedicated oscillator
– Brown-Out Reset
Accurate, programmable Brown-Out levels
– PDI reset
– Software reset
• Asynchronous reset
– No running clock in the device is required for reset
• Reset status register
11.2 Resetting the AVR
During reset, all I/O registers are set to their initial values. The SRAM content is not reset. Appli-
cation execution starts from the Reset Vector. The instruction placed at the Reset Vector should
be an Absolute Jump (JMP) instruction to the reset handling routine. By default the Reset Vector
address is the lowest Flash program memory address, ‘0’, but it is possible to move the Reset
Vector to the first address in the Boot Section.
The I/O ports of the AVR are immediately tri-stated when a reset source goes active.
The reset functionality is asynchronous, so no running clock is required to reset the device.
After the device is reset, the reset source can be determined by the application by reading the
Reset Status Register.
11.3 Reset Sources
11.3.1
11.3.2
11.3.3
Power-On Reset
The MCU is reset when the supply voltage VCC is below the Power-on Reset threshold voltage.
External Reset
The MCU is reset when a low level is present on the RESET pin.
Watchdog Reset
The MCU is reset when the Watchdog Timer period expires and the Watchdog Reset is enabled.
The Watchdog Timer runs from a dedicated oscillator independent of the System Clock. For
more details see ”WDT - Watchdog Timer” on page 23.
11.3.4
Brown-Out Reset
The MCU is reset when the supply voltage VCC is below the Brown-Out Reset threshold voltage
and the Brown-out Detector is enabled. The Brown-out threshold voltage is programmable.
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11.3.5
11.3.6
PDI reset
The MCU can be reset through the Program and Debug Interface (PDI).
Software reset
The MCU can be reset by the CPU writing to a special I/O register through a timed sequence.
12. WDT - Watchdog Timer
12.1 Features
• 11 selectable timeout periods, from 8 ms to 8s.
• Two operation modes
– Standard mode
– Window mode
• Runs from the 1 kHz output of the 32 kHz Ultra Low Power oscillator
• Configuration lock to prevent unwanted changes
12.2 Overview
The XMEGA D4 has a Watchdog Timer (WDT). The WDT will run continuously when turned on
and if the Watchdog Timer is not reset within a software configurable time-out period, the micro-
controller will be reset. The Watchdog Reset (WDR) instruction must be run by software to reset
the WDT, and prevent microcontroller reset.
The WDT has a Window mode. In this mode the WDR instruction must be run within a specified
period called a window. Application software can set the minimum and maximum limits for this
window. If the WDR instruction is not executed inside the window limits, the microcontroller will
be reset.
A protection mechanism using a timed write sequence is implemented in order to prevent
unwanted enabling, disabling or change of WDT settings.
For maximum safety, the WDT also has an Always-on mode. This mode is enabled by program-
ming a fuse. In Always-on mode, application software can not disable the WDT.
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13. PMIC - Programmable Multi-level Interrupt Controller
13.1 Features
• Separate interrupt vector for each interrupt
• Short, predictable interrupt response time
• Programmable Multi-level Interrupt Controller
– 3 programmable interrupt levels
– Selectable priority scheme within low level interrupts (round-robin or fixed)
– Non-Maskable Interrupts (NMI)
• Interrupt vectors can be moved to the start of the Boot Section
13.2 Overview
XMEGA D4 has a Programmable Multi-level Interrupt Controller (PMIC). All peripherals can
define three different priority levels for interrupts; high, medium or low. Medium level interrupts
may interrupt low level interrupt service routines. High level interrupts may interrupt both low-
and medium level interrupt service routines. Low level interrupts have an optional round robin
scheme to make sure all interrupts are serviced within a certain amount of time.
The built in oscillator failure detection mechanism can issue a Non-Maskable Interrupt (NMI).
13.3 Interrupt vectors
When an interrupt is serviced, the program counter will jump to the interrupt vector address. The
interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for
specific interrupts in each peripheral. The base addresses for the XMEGA D4 devices are
shown in Table 13-1. Offset addresses for each interrupt available in the peripheral are
described for each peripheral in the XMEGA A manual. For peripherals or modules that have
only one interrupt, the interrupt vector is shown in Table 13-1. The program address is the word
address.
Table 13-1. Reset and Interrupt Vectors
Program Address
(Base Address)
Source
Interrupt Description
0x000
0x002
0x004
0x008
0x014
0x018
0x01C
0x028
0x030
0x032
0x040
0x044
0x056
RESET
OSCF_INT_vect
PORTC_INT_base
PORTR_INT_base
RTC_INT_base
TWIC_INT_base
TCC0_INT_base
TCC1_INT_base
SPIC_INT_vect
USARTC0_INT_base
NVM_INT_base
PORTB_INT_base
PORTE_INT_base
Crystal Oscillator Failure Interrupt vector (NMI)
Port C Interrupt base
Port R Interrupt base
Real Time Counter Interrupt base
Two-Wire Interface on Port C Interrupt base
Timer/Counter 0 on port C Interrupt base
Timer/Counter 1 on port C Interrupt base
SPI on port C Interrupt vector
USART 0 on port C Interrupt base
Non-Volatile Memory Interrupt base
Port B Interrupt base
Port E Interrupt base
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Table 13-1. Reset and Interrupt Vectors (Continued)
Program Address
(Base Address)
Source
Interrupt Description
0x05A
TWIE_INT_base
TCE0_INT_base
PORTD_INT_base
PORTA_INT_base
ACA_INT_base
ADCA_INT_base
TCD0_INT_base
SPID_INT_vector
USARTD0_INT_base
Two-Wire Interface on Port E Interrupt base
Timer/Counter 0 on port E Interrupt base
Port D Interrupt base
0x05E
0x080
0x084
Port A Interrupt base
0x088
Analog Comparator on Port A Interrupt base
0x08E
Analog to Digital Converter on Port A Interrupt base
Timer/Counter 0 on port D Interrupt base
SPI on port D Interrupt vector
0x09A
0x0AE
0x0B0
USART 0 on port D Interrupt base
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14. I/O Ports
14.1 Features
• Selectable input and output configuration for each pin individually
• Flexible pin configuration through dedicated Pin Configuration Register
• Synchronous and/or asynchronous input sensing with port interrupts and events
– Sense both edges
– Sense rising edges
– Sense falling edges
– Sense low level
• Asynchronous wake-up from all input sensing configurations
• Highly configurable output driver and pull settings:
–
–
–
–
–
–
Totem-pole
Pull-up/-down
Wired-AND
Wired-OR
Bus keeper
Inverted I/O
• Flexible pin masking
• Configuration of multiple pins in a single operation
• Read-Modify-Write (RMW) support
• Toggle/clear/set registers for Output and Direction registers
• Clock output on port pin
• Event Channel 0 output on port pin 7
• Mapping of port registers (virtual ports) into bit accessible I/O memory space
14.2 Overview
The XMEGA D4 devices have flexible General Purpose I/O Ports. A port consists of up to 8 pins,
ranging from pin 0 to pin 7. The ports implement several functions, including synchronous/asyn-
chronous input sensing, pin change interrupts and configurable output settings. All functions are
individual per pin, but several pins may be configured in a single operation.
14.3 I/O configuration
All port pins (Pn) have programmable output configuration. In addition, all port pins have an
inverted I/O function. For an input, this means inverting the signal between the port pin and the
pin register. For an output, this means inverting the output signal between the port register and
the port pin. The inverted I/O function can be used also when the pin is used for alternate
functions.
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14.3.1
Push-pull
Figure 14-1. I/O configuration - Totem-pole
DIRn
OUTn
INn
Pn
14.3.2
Pull-down
Figure 14-2. I/O configuration - Totem-pole with pull-down (on input)
DIRn
OUTn
INn
Pn
14.3.3
Pull-up
Figure 14-3. I/O configuration - Totem-pole with pull-up (on input)
DIRn
OUTn
INn
Pn
14.3.4
Bus-keeper
The bus-keeper’s weak output produces the same logical level as the last output level. It acts as
a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’.
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Figure 14-4. I/O configuration - Totem-pole with bus-keeper
DIRn
OUTn
INn
Pn
14.3.5
Others
Figure 14-5. Output configuration - Wired-OR with optional pull-down
OUTn
Pn
INn
Figure 14-6. I/O configuration - Wired-AND with optional pull-up
INn
Pn
OUTn
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14.4 Input sensing
• Sense both edges
• Sense rising edges
• Sense falling edges
• Sense low level
Input sensing is synchronous or asynchronous depending on the enabled clock for the ports,
and the configuration is shown in Figure 14-7 on page 29.
Figure 14-7. Input sensing system overview
Asynchronous sensing
EDGE
DETECT
Interrupt
Control
IREQ
Synchronous sensing
Pn
Synchronizer
INn
EDGE
DETECT
Q
Q
D
D
Event
INVERTED I/O
R
R
When a pin is configured with inverted I/O, the pin value is inverted before the input sensing.
14.5 Port Interrupt
Each port has two interrupts with separate priority and interrupt vector. All pins on the port can
be individually selected as source for each of the interrupts. The interrupts are then triggered
according to the input sense configuration for each pin configured as source for the interrupt.
14.6 Alternate Port Functions
In addition to the input/output functions on all port pins, most pins have alternate functions. This
means that other modules or peripherals connected to the port can use the port pins for their
functions, such as communication or pulse-width modulation. ”Pinout and Pin Functions” on
page 46 shows which modules on peripherals that enable alternate functions on a pin, and
which alternate function is available on a pin.
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15. T/C - 16-bit Timer/Counter
15.1 Features
• Four 16-bit Timer/Counters
– Three Timer/Counters of type 0
– One Timer/Counters of type 1
• Three Compare or Capture (CC) Channels in Timer/Counter 0
• Two Compare or Capture (CC) Channels in Timer/Counter 1
• Double Buffered Timer Period Setting
• Double Buffered Compare or Capture Channels
• Waveform Generation:
– Single Slope Pulse Width Modulation
– Dual Slope Pulse Width Modulation
– Frequency Generation
• Input Capture:
– Input Capture with Noise Cancelling
– Frequency capture
– Pulse width capture
– 32-bit input capture
• Event Counter with Direction Control
• Timer Overflow and Timer Error Interrupts and Events
• One Compare Match or Capture Interrupt and Event per CC Channel
• Hi-Resolution Extension (Hi-Res)
• Advanced Waveform Extension (AWEX)
15.2 Overview
XMEGA D4 has four Timer/Counters, three Timer/Counter 0 and one Timer/Counter 1. The dif-
ference between them is that Timer/Counter 0 has four Compare/Capture channels, while
Timer/Counter 1 has two Compare/Capture channels.
The Timer/Counters (T/C) are 16-bit and can count any clock, event or external input in the
microcontroller. A programmable prescaler is available to get a useful T/C resolution. Updates of
Timer and Compare registers are double buffered to ensure glitch free operation. Single slope
PWM, dual slope PWM and frequency generation waveforms can be generated using the Com-
pare Channels.
Through the Event System, any input pin or event in the microcontroller can be used to trigger
input capture, hence no dedicated pins are required for this. The input capture has a noise can-
celler to avoid incorrect capture of the T/C, and can be used to do frequency and pulse width
measurements.
A wide range of interrupt or event sources are available, including T/C Overflow, Compare
match and Capture for each Compare/Capture channel in the T/C.
PORTC has one Timer/Counter 0 and one Timer/Counter1. PORTD and PORTE each have one
Timer/Conter0. Notation of these are TCC0 (Time/Counter C0), TCC1, TCD0 and TCE0,
respectively.
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Figure 15-1. Overview of a Timer/Counter and closely related peripherals
Timer/Counter
Base Counter
Prescaler
clkPER
Timer Period
Counter
Control Logic
Event
System
clkPER4
Compare/Capture Channel D
Compare/Capture Channel C
Compare/Capture Channel B
Compare/Capture Channel A
AWeX
Pattern
Generation
Fault
DTI
Dead-Time
Insertion
Capture
Comparator
Control
Protection
Waveform
Buffer
Generation
The Hi-Resolution Extension can be enabled to increase the waveform generation resolution by
2 bits (4x). This is available for all Timer/Counters. See ”Hi-Res - High Resolution Extension” on
page 33 for more details.
The Advanced Waveform Extension can be enabled to provide extra and more advanced fea-
ture for the Timer/Counter. This is only available for Timer/Counter 0. See ”AWEX - Advanced
Waveform Extension” on page 32 for more details.
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16. AWEX - Advanced Waveform Extension
16.1 Features
• Output with complementary output from each Capture channel
• Four Dead Time Insertion (DTI) Units, one for each Capture channel
• 8-bit DTI Resolution
• Separate High and Low Side Dead-Time Setting
• Double Buffered Dead-Time
• Event Controlled Fault Protection
• Single Channel Multiple Output Operation (for BLDC motor control)
• Double Buffered Pattern Generation
16.2 Overview
The Advanced Waveform Extension (AWEX) provides extra features to the Timer/Counter in
Waveform Generation (WG) modes. The AWEX enables easy and safe implementation of for
example, advanced motor control (AC, BLDC, SR, and Stepper) and power control applications.
Any WG output from a Timer/Counter 0 is split into a complimentary pair of outputs when any
AWEX feature is enabled. These output pairs go through a Dead-Time Insertion (DTI) unit that
enables generation of the non-inverted Low Side (LS) and inverted High Side (HS) of the WG
output with dead time insertion between LS and HS switching. The DTI output will override the
normal port value according to the port override setting. Optionally the final output can be
inverted by using the invert I/O setting for the port pin.
The Pattern Generation unit can be used to generate a synchronized bit pattern on the port it is
connected to. In addition, the waveform generator output from Compare Channel A can be dis-
tributed to, and override all port pins. When the Pattern Generator unit is enabled, the DTI unit is
bypassed.
The Fault Protection unit is connected to the Event System. This enables any event to trigger a
fault condition that will disable the AWEX output. Several event channels can be used to trigger
fault on several different conditions.
The AWEX is available for TCC0. The notation of this is AWEXC.
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17. Hi-Res - High Resolution Extension
17.1 Features
• Increases Waveform Generator resolution by 2-bits (4x)
• Supports Frequency, single- and dual-slope PWM operation
• Supports the AWEX when this is enabled and used for the same Timer/Counter
17.2 Overview
The Hi-Resolution (Hi-Res) Extension is able to increase the resolution of the waveform genera-
tion output by a factor of 4. When enabled for a Timer/Counter, the Fast Peripheral clock running
at four times the CPU clock speed will be as input to the Timer/Counter.
The High Resolution Extension can also be used when an AWEX is enabled and used with a
Timer/Counter.
XMEGA D4 devices have one Hi-Res Extension that can be enabled for each Timer/Counter on
PORTC. The notation of this is HIRESC.
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18. RTC - 16-bit Real-Time Counter
18.1 Features
• 16-bit Timer
• Flexible Tick resolution ranging from 1 Hz to 32.768 kHz
• One Compare register
• One Period register
• Clear timer on Overflow or Compare Match
• Overflow or Compare Match event and interrupt generation
18.2 Overview
The XMEGA D4 includes a 16-bit Real-time Counter (RTC). The RTC can be clocked from an
accurate 32.768 kHz Crystal Oscillator, the 32.768 kHz Calibrated Internal Oscillator, or from the
32 kHz Ultra Low Power Internal Oscillator. The RTC includes both a Period and a Compare
register. For details, see Figure 18-1.
A wide range of Resolution and Time-out periods can be configured using the RTC. With a max-
imum resolution of 30.5 µs, time-out periods range up to 2000 seconds. With a resolution of 1
second, the maximum time-out period is over 18 hours (65536 seconds).
Figure 18-1. Real Time Counter overview
Period
Overflow
32.768 kHz
=
=
10-bit
prescaler
Counter
1.024 kHz
Compare Match
Compare
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19. TWI - Two-Wire Interface
19.1 Features
• Two identical TWI peripherals
• Simple yet Powerful and Flexible Communication Interface
• Both Master and Slave Operation Supported
• Device can Operate as Transmitter or Receiver
• 7-bit Address Space Allows up to 128 Different Slave Addresses
• Multi-master Arbitration Support
• Up to 400 kHz Data Transfer Speed
• Slew-rate Limited Output Drivers
• Noise Suppression Circuitry Rejects Spikes on Bus Lines
• Fully Programmable Slave Address with General Call Support
• Address Recognition Causes Wake-up when in Sleep Mode
• I2C and System Management Bus (SMBus) compatible
19.2 Overview
The Two-Wire Interface (TWI) is a bi-directional wired-AND bus with only two lines, the clock
(SCL) line and the data (SDA) line. The protocol makes it possible to interconnect up to 128 indi-
vidually addressable devices. Since it is a multi-master bus, one or more devices capable of
taking control of the bus can be connected.
The only external hardware needed to implement the bus is a single pull-up resistor for each of
the TWI bus lines. Mechanisms for resolving bus contention are inherent in the TWI protocol.
PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE,
respectively.
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20. SPI - Serial Peripheral Interface
20.1 Features
• Two Identical SPI peripherals
• Full-duplex, Three-wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Seven Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
• Double Speed (CK/2) Master SPI Mode
20.2 Overview
The Serial Peripheral Interface (SPI) allows high-speed full-duplex, synchronous data transfer
between different devices. Devices can communicate using a master-slave scheme, and data is
transferred both to and from the devices simultaneously.
PORTC and PORTD each has one SPI. Notation of these peripherals are SPIC and SPID,
respectively.
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21. USART
21.1 Features
• Two Identical USART peripherals
• Full Duplex Operation (Independent Serial Receive and Transmit Registers)
• Asynchronous or Synchronous Operation
• Master or Slave Clocked Synchronous Operation
• High-resolution Arithmetic Baud Rate Generator
• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
• Odd or Even Parity Generation and Parity Check Supported by Hardware
• Data OverRun Detection
• Framing Error Detection
• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
• Multi-processor Communication Mode
• Double Speed Asynchronous Communication Mode
• Master SPI mode for SPI communication
• IrDA support through the IRCOM module
21.2 Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication module. The USART supports full duplex communication,
and both asynchronous and clocked synchronous operation. The USART can also be set in
Master SPI mode to be used for SPI communication.
Communication is frame based, and the frame format can be customized to support a wide
range of standards. The USART is buffered in both direction, enabling continued data transmis-
sion without any delay between frames. There are separate interrupt vectors for receive and
transmit complete, enabling fully interrupt driven communication. Frame error and buffer over-
flow are detected in hardware and indicated with separate status flags. Even or odd parity
generation and parity check can also be enabled.
One USART can use the IRCOM module to support IrDA 1.4 physical compliant pulse modula-
tion and demodulation for baud rates up to 115.2 kbps.
PORTC and PORTD each has one USART. Notation of these peripherals are USARTC0, and
USARTD0, respectively.
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8135I–AVR–10/10
XMEGA D4
22. IRCOM - IR Communication Module
22.1 Features
• Pulse modulation/demodulation for infrared communication
• Compatible to IrDA 1.4 physical for baud rates up to 115.2 kbps
• Selectable pulse modulation scheme
– 3/16 of baud rate period
– Fixed pulse period, 8-bit programmable
– Pulse modulation disabled
• Built in filtering
• Can be connected to and used by one USART at a time
22.2 Overview
XMEGA contains an Infrared Communication Module (IRCOM) for IrDA communication with
baud rates up to 115.2 kbps. This supports three modulation schemes: 3/16 of baud rate period,
fixed programmable pulse time based on the Peripheral Clock speed, or pulse modulation dis-
abled. There is one IRCOM available which can be connected to any USART to enable infrared
pulse coding/decoding for that USART.
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XMEGA D4
23. ADC - 12-bit Analog to Digital Converter
23.1 Features
• One ADC with 12-bit resolution
• 200 ksps sample rate
• Signed and Unsigned conversions
• 12 single ended inputs
• 8x4 differential inputs
• 3 internal inputs:
–
–
–
Integrated Temperature Sensor
VCC voltage divided by 10
Bandgap voltage
• Software selectable gain of 2, 4, 8, 16, 32 or 64
• Software Selectable accuracy of 8- or 12-bit.
• Internal or External Reference selection
• Event triggered conversion for accurate timing
• Interrupt/Event on compare result
23.2 Overview
XMEGA D4 devices have one Analog to Digital Converter (ADC), see Figure 23-1 on page 40.
The ADC converts analog voltages to digital values. The ADC has 12-bit resolution and is
capable of converting up to 200K samples per second. The input selection is flexible, and both
singleended and differential measurements can be done. For differential measurements an
optional gain stage is available to increase the dynamic range. In addition several internal signal
inputs are available. The ADC can provide both signed and unsigned results.
ADC measurements can either be started by application software or an incoming event from
another peripheral in the device. The latter ensure the ADC measurements can be started with
predictable timing, and without software intervention. The ADC has one channel, meaning there
is one input selection (MUX selection) and one result register available.
Both internal and external analog reference voltages can be used. A very accurate internal
1.00V reference is available.
An integrated temperature sensor is available and the output from this can be measured with the
ADC. A VCC/10 signal and the Bandgap voltage can also be measured by the ADC.
39
8135I–AVR–10/10
XMEGA D4
Figure 23-1. ADC overview
Channel A MUX selection
Configuration
Reference selection
Channel A
Register
ADC
Event
Trigger
1-64 X
The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (prop-
agation delay) from 0.5 µs for 12-bit to 3.7 µs for 8-bit result.
ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This
eases calculation when the result is represented as a signed integer (signed 16-bit number).
PORTA has one ADC. Notation of this peripheral is ADCA.
40
8135I–AVR–10/10
XMEGA D4
24. AC - Analog Comparator
24.1 Features
• Two Analog Comparators
• Selectable hysteresis
– No, Small or Large
• Analog Comparator output available on pin
• Flexible Input Selection
– All pins on the port
– Bandgap reference voltage.
– Voltage scaler that can perform a 64-level scaling of the internal VCC voltage.
• Interrupt and event generation on
– Rising edge
– Falling edge
– Toggle
• Window function interrupt and event generation on
– Signal above window
– Signal inside window
– Signal below window
24.2 Overview
XMEGA D4 features two Analog Comparators (AC). An Analog Comparator compares two volt-
ages, and the output indicates which input is largest. The Analog Comparator may be configured
to give interrupt requests and/or events upon several different combinations of input change.
Hysteresis can be adjusted in order to find the optimal operation for each application.
A wide range of input selection is available, both external pins and several internal signals can
be used.
The Analog Comparators are always grouped in pairs (AC0 and AC1) on each analog port. They
have identical behavior but separate control registers.
Optionally, the state of the comparator is directly available on a pin.
PORTA and has one AC pair. Notations of this peripheral is ACA.
41
8135I–AVR–10/10
XMEGA D4
Figure 24-1. Analog comparator overview
Pin inputs
Internal inputs
+
-
Pin 0 output
Interrupts
AC0
Pin inputs
Internal inputs
VCC scaled
Interrupt
sensitivity
control
Events
Pin inputs
Internal inputs
+
-
AC1
Pin inputs
Internal inputs
VCC scaled
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8135I–AVR–10/10
XMEGA D4
24.3 Input Selection
The Analog comparators have a very flexible input selection and the two comparators grouped
in a pair may be used to realize a window function. One pair of analog comparators is shown in
Figure 24-1 on page 42.
• Input selection from pin
– Pin 0, 1, 2, 3, 4, 5, 6 selectable to positive input of analog comparator
– Pin 0, 1, 3, 5, 7 selectable to negative input of analog comparator
• Internal signals available on positive analog comparator inputs
• Internal signals available on negative analog comparator inputs
– 64-level scaler of the VCC, available on negative analog comparator input
– Bandgap voltage reference
24.4 Window Function
The window function is realized by connecting the external inputs of the two analog comparators
in a pair as shown in Figure 24-2.
Figure 24-2. Analog comparator window function
+
AC0
Upper limit of window
-
Interrupts
Events
Interrupt
sensitivity
control
Input signal
+
AC1
Lower limit of window
-
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XMEGA D4
25. OCD - On-chip Debug
25.1 Features
• Complete Program Flow Control
– Go, Stop, Reset, Step into, Step over, Step out, Run-to-Cursor
• Debugging on C and high-level language source code level
• Debugging on Assembler and disassembler level
• 1 dedicated program address or source level breakpoint for AVR Studio / debugger
• 4 Hardware Breakpoints
• Unlimited Number of User Program Breakpoints
• Unlimited Number of User Data Breakpoints, with break on:
– Data location read, write or both read and write
– Data location content equal or not equal to a value
– Data location content is greater or less than a value
– Data location content is within or outside a range
– Bits of a data location are equal or not equal to a value
• Non-Intrusive Operation
– No hardware or software resources in the device are used
• High Speed Operation
– No limitation on debug/programming clock frequency versus system clock frequency
25.2 Overview
The XMEGA D4 has a powerful On-Chip Debug (OCD) system that - in combination with Atmel’s
development tools - provides all the necessary functions to debug an application. It has support
for program and data breakpoints, and can debug an application from C and high level language
source code level, as well as assembler and disassembler level. It has full Non-Intrusive Opera-
tion and no hardware or software resources in the device are used. The ODC system is
accessed through an external debugging tool which connects to the PDI physical interface.
Refer to ”PDI - Program and Debug Interface” on page 45.
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XMEGA D4
26. PDI - Program and Debug Interface
26.1 Features
• PDI - Program and Debug Interface (Atmel proprietary 2-pin interface)
• Access to the OCD system
• Programming of Flash, EEPROM, Fuses and Lock Bits
26.2 Overview
The programming and debug facilities are accessed through PDI physical interface. The PDI
physical interface uses one dedicated pin together with the Reset pin, and no general purpose
pins are used.
26.3 PDI - Program and Debug Interface
The PDI is an Atmel proprietary protocol for communication between the microcontroller and
Atmel’s development tools.
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8135I–AVR–10/10
XMEGA D4
27. Pinout and Pin Functions
The pinout of XMEGA D4 is shown in ”Pinout/Block Diagram” on page 3. In addition to general
I/O functionality, each pin may have several functions. This will depend on which peripheral is
enabled and connected to the actual pin. Only one of the alternate pin functions can be used at
time.
27.1 Alternate Pin Functions Description
The tables below shows the notation for all pin functions available and describe their functions.
Operation/Power Supply
27.1.1
VCC
Digital supply voltage
Analog supply voltage
Ground
AVCC
GND
27.1.2
27.1.3
Port Interrupt functions
SYNC
Port pin with full synchronous and limited asynchronous interrupt function
Port pin with full synchronous and full asynchronous interrupt function
ASYNC
Analog functions
ACn
Analog Comparator input pin n
Analog Comparator 0 Output
Analog to Digital Converter input pin n
Analog Reference input pin
AC0OUT
ADCn
AREF
27.1.4
Timer/Counter and AWEX functions
OCnx
Output Compare Channel x for Timer/Counter n
OCnx
Inverted Output Compare Channel x for Timer/Counter n
Output Compare Channel x Low Side for Timer/Counter n
Output Compare Channel x High Side for Timer/Counter n
OCnxLS
OCnxHS
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XMEGA D4
27.1.5
Communication functions
SCL
Serial Clock for TWI
SDA
Serial Data for TWI
XCKn
RXDn
TXDn
SS
Transfer Clock for USART n
Receiver Data for USART n
Transmitter Data for USART n
Slave Select for SPI
MOSI
MISO
SCK
Master Out Slave In for SPI
Master In Slave Out for SPI
Serial Clock for SPI
27.1.6
27.1.7
Oscillators, Clock and Event
TOSCn
XTALn
Timer Oscillator pin n
Input/Output for inverting Oscillator pin n
Debug/System functions
RESET
Reset pin
PDI_CLK
PDI_DATA
Program and Debug Interface Clock pin
Program and Debug Interface Data pin
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XMEGA D4
27.2 Alternate Pin Functions
The tables below shows the main and alternate pin functions for all pins on each port. It also
shows which peripheral which make use of or enable the alternate pin function.
Table 27-1. Port A - Alternate functions
ADCA
GAINPOS
ADCA
GAINNEG
PORTA
GND
AVCC
PA0
PIN #
38
39
40
41
42
43
44
1
INTERRUPT
ADCA POS
ADCA NEG
ACA POS
ACA NEG
ACA OUT
REF
SYNC
SYNC
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC0
ADC1
ADC2
ADC3
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
AC0
AC1
AC2
AC3
AC4
AC5
AC6
AC0
AC1
AREF
PA1
PA2
SYNC/ASYNC
SYNC
PA3
AC3
AC5
AC7
PA4
SYNC
ADC4
ADC5
ADC6
ADC7
PA5
SYNC
PA6
2
SYNC
PA7
3
SYNC
AC0 OUT
Table 27-2. Port B - Alternate functions
PORTB
PIN #
INTERRUPT
ADCA POS
REF
PB0
4
5
6
7
SYNC
ADC8
AREF
PB1
SYNC
ADC9
PB2
SYNC/ASYNC
SYNC
ADC10
ADC11
PB3
Table 27-3. Port C - Alternate functions
EVENTOUT
PORTC
GND
VCC
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PIN #
8
INTERRUPT
TCC0
AWEXC
TCC1
USARTC0
SPI
TWIC
CLOCKOUT
9
10
11
12
13
14
15
16
17
SYNC
SYNC
OC0A
OC0B
OC0C
OC0D
OC0ALS
OC0AHS
OC0BLS
OC0BHS
OC0CLS
OC0CHS
OC0DLS
OC0DHS
SDA
SCL
XCK0
RXD0
TXD0
SYNC/ASYNC
SYNC
SYNC
OC1A
OC1B
SS
SYNC
MOSI
MISO
SCK
SYNC
SYNC
CLKOUT
EVOUT
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8135I–AVR–10/10
XMEGA D4
Table 27-4. Port D - Alternate functions
PORTD
GND
VCC
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PIN #
INTERRUPT
TCD0
USARTD0
SPID
CLOCKOUT
EVENTOUT
18
19
20
SYNC
SYNC
OC0A
OC0B
OC0C
OC0D
21
XCK0
RXD0
TXD0
22
SYNC/ASYNC
SYNC
23
24
SYNC
SS
25
SYNC
MOSI
MISO
SCK
26
SYNC
27
SYNC
CLKOUT
EVOUT
Table 27-5. Port E - Alternate functions
PORT E
PIN #
INTERRUPT
TCE0
OC0A
OC0B
TWIE
SDA
SCL
PE0
28
SYNC
PE1
29
SYNC
GND
VCC
PE2
30
31
32
SYNC/ASYNC
SYNC
OC0C
OC0D
PE3
33
Table 27-6. Port R - Alternate functions
PORTR
PIN #
XTAL
PDI
TOSC
PDI
34
PDI_DATA
PDI_CLK
RESET
PR0
35
36
XTAL2
XTAL1
TOSC2
TOSC1
PR1
37
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XMEGA D4
28. Peripheral Module Address Map
The address maps show the base address for each peripheral and module in XMEGA D4. For
complete register description and summary for each peripheral module, refer to the XMEGA A
Manual.
Table 28-1. Peripheral Module Address Map
Base Address
Name
Description
0x0000
0x0010
0x0014
0x0018
0x001C
0x0030
0x0040
0x0048
0x0050
0x0060
0x0068
0x0070
0x0078
0x0080
0x0090
0x00A0
0x00B0
0x0180
0x01C0
0x0200
0x0380
0x0400
0x0480
0x04A0
0x0600
0x0620
0x0640
0x0660
0x0680
0x07E0
0x0800
0x0840
0x0880
0x0890
0x08A0
0x08C0
0x08F8
0x0900
0x09A0
0x09C0
0x0A00
GPIO
General Purpose IO Registers
Virtual Port 0
Virtual Port 1
Virtual Port 2
Virtual Port 2
CPU
Clock Control
Sleep Controller
Oscillator Control
DFLL for the 32 MHz Internal RC Oscillator
DFLL for the 2 MHz RC Oscillator
Power Reduction
Reset Controller
Watch-Dog Timer
MCU Control
Programmable MUltilevel Interrupt Controller
Port Configuration
VPORT0
VPORT1
VPORT2
VPORT3
CPU
CLK
SLEEP
OSC
DFLLRC32M
DFLLRC2M
PR
RST
WDT
MCU
PMIC
PORTCFG
EVSYS
NVM
ADCA
ACA
RTC
TWIC
Event System
Non Volatile Memory (NVM) Controller
Analog to Digital Converter on port A
Analog Comparator pair on port A
Real Time Counter
Two Wire Interface on port C
Two Wire Interface on port E
Port A
Port B
Port C
Port D
Port E
TWIE
PORTA
PORTB
PORTC
PORTD
PORTE
PORTR
TCC0
Port R
Timer/Counter 0 on port C
Timer/Counter 1 on port C
Advanced Waveform Extension on port C
High Resolution Extension on port C
USART 0 on port C
Serial Peripheral Interface on port C
Infrared Communication Module
Timer/Counter 0 on port D
USART 0 on port D
TCC1
AWEXC
HIRESC
USARTC0
SPIC
IRCOM
TCD0
USARTD0
SPID
TCE0
Serial Peripheral Interface on port D
Timer/Counter 0 on port E
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XMEGA D4
29. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
Arithmetic and Logic Instructions
ADD
Rd, Rr
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add without Carry
Rd
Rd
Rd
Rd
Rd
Rd
Rd
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
Rd + Rr
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,C,N,V,S
Z,C,N,V,S,H
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
None
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
ADC
Add with Carry
Rd + Rr + C
Rd + 1:Rd + K
Rd - Rr
ADIW
SUB
Add Immediate to Word
Subtract without Carry
Subtract Immediate
Subtract with Carry
Subtract Immediate with Carry
Subtract Immediate from Word
Logical AND
SUBI
SBC
Rd - K
Rd - Rr - C
Rd - K - C
Rd + 1:Rd - K
Rd • Rr
SBCI
SBIW
AND
Rd + 1:Rd
Rd
ANDI
OR
Logical AND with Immediate
Logical OR
Rd
Rd • K
Rd
Rd v Rr
ORI
Logical OR with Immediate
Exclusive OR
Rd
Rd v K
EOR
COM
NEG
SBR
Rd
Rd ⊕ Rr
One’s Complement
Two’s Complement
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Rd
$FF - Rd
Rd
Rd
$00 - Rd
Rd,K
Rd,K
Rd
Rd
Rd v K
CBR
Rd
Rd • ($FFh - K)
Rd + 1
INC
Rd
DEC
Rd
Decrement
Rd
Rd - 1
TST
Rd
Test for Zero or Minus
Clear Register
Rd
Rd • Rd
CLR
Rd
Rd
Rd ⊕ Rd
SER
Rd
Set Register
Rd
$FF
MUL
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
Multiply Unsigned
R1:R0
R1:R0
R1:R0
R1:R0
R1:R0
R1:R0
Rd x Rr (UU)
Rd x Rr (SS)
Rd x Rr (SU)
Rd x Rr<<1 (UU)
Rd x Rr<<1 (SS)
Rd x Rr<<1 (SU)
Z,C
MULS
MULSU
FMUL
FMULS
FMULSU
Multiply Signed
Z,C
Multiply Signed with Unsigned
Fractional Multiply Unsigned
Fractional Multiply Signed
Fractional Multiply Signed with Unsigned
Z,C
Z,C
Z,C
Z,C
Branch Instructions
RJMP
IJMP
k
Relative Jump
PC
←
PC + k + 1
None
None
2
2
Indirect Jump to (Z)
PC(15:0)
PC(21:16)
←
←
Z,
0
EIJMP
Extended Indirect Jump to (Z)
PC(15:0)
PC(21:16)
←
←
Z,
EIND
None
2
JMP
k
k
Jump
PC
PC
←
←
k
None
None
None
3
RCALL
ICALL
Relative Call Subroutine
Indirect Call to (Z)
PC + k + 1
2 / 3(1)
2 / 3(1)
PC(15:0)
PC(21:16)
←
←
Z,
0
EICALL
CALL
Extended Indirect Call to (Z)
call Subroutine
PC(15:0)
PC(21:16)
←
←
Z,
EIND
None
None
3(1)
k
PC
←
k
3 / 4(1)
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XMEGA D4
Mnemonics
RET
Operands
Description
Operation
Flags
None
I
#Clocks
4 / 5(1)
4 / 5(1)
1 / 2 / 3
1
Subroutine Return
PC
PC
←
←
←
STACK
RETI
Interrupt Return
STACK
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC
PC + 2 or 3
None
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Rd,Rr
Rd - Rr
CPC
Rd,Rr
Compare with Carry
Rd - Rr - C
1
CPI
Rd,K
Compare with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd - K
1
SBRC
SBRS
SBIC
Rr, b
if (Rr(b) = 0) PC
if (Rr(b) = 1) PC
if (I/O(A,b) = 0) PC
If (I/O(A,b) =1) PC
if (SREG(s) = 1) then PC
if (SREG(s) = 0) then PC
if (Z = 1) then PC
if (Z = 0) then PC
if (C = 1) then PC
if (C = 0) then PC
if (C = 0) then PC
if (C = 1) then PC
if (N = 1) then PC
if (N = 0) then PC
if (N ⊕ V= 0) then PC
if (N ⊕ V= 1) then PC
if (H = 1) then PC
if (H = 0) then PC
if (T = 1) then PC
if (T = 0) then PC
if (V = 1) then PC
if (V = 0) then PC
if (I = 1) then PC
if (I = 0) then PC
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
1 / 2 / 3
1 / 2 / 3
2 / 3 / 4
2 / 3 / 4
1 / 2
Rr, b
A, b
A, b
s, k
s, k
k
SBIS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
1 / 2
1 / 2
k
Branch if Not Equal
1 / 2
k
Branch if Carry Set
1 / 2
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
1 / 2
k
1 / 2
k
1 / 2
k
Branch if Minus
1 / 2
k
Branch if Plus
1 / 2
k
Branch if Greater or Equal, Signed
Branch if Less Than, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
1 / 2
k
1 / 2
k
1 / 2
k
1 / 2
k
1 / 2
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
1 / 2
k
1 / 2
k
1 / 2
k
1 / 2
BRID
k
1 / 2
Data Transfer Instructions
MOV
MOVW
LDI
Rd, Rr
Rd, Rr
Rd, K
Rd, k
Copy Register
Rd
Rd+1:Rd
Rd
←
←
←
←
←
Rr
None
None
None
None
None
None
1
Copy Register Pair
Load Immediate
Rr+1:Rr
1
K
1
LDS
LD
Load Direct from data space
Load Indirect
Rd
(k)
(X)
2(1)(2)
1(1)(2)
1(1)(2)
Rd, X
Rd, X+
Rd
LD
Load Indirect and Post-Increment
Rd
X
←
←
(X)
X + 1
LD
Rd, -X
Load Indirect and Pre-Decrement
X ← X - 1,
Rd ← (X)
←
←
X - 1
(X)
None
2(1)(2)
LD
LD
Rd, Y
Load Indirect
Rd ← (Y)
←
(Y)
None
None
1(1)(2)
1(1)(2)
Rd, Y+
Load Indirect and Post-Increment
Rd
Y
←
←
(Y)
Y + 1
52
8135I–AVR–10/10
XMEGA D4
Mnemonics
Operands
Description
Operation
Flags
#Clocks
LD
Rd, -Y
Load Indirect and Pre-Decrement
Y
Rd
←
←
Y - 1
(Y)
None
2(1)(2)
LDD
LD
Rd, Y+q
Rd, Z
Load Indirect with Displacement
Load Indirect
Rd
Rd
←
←
(Y + q)
(Z)
None
None
None
2(1)(2)
1(1)(2)
1(1)(2)
LD
Rd, Z+
Load Indirect and Post-Increment
Rd
Z
←
←
(Z),
Z+1
LD
Rd, -Z
Load Indirect and Pre-Decrement
Z
Rd
←
←
Z - 1,
(Z)
None
2(1)(2)
LDD
STS
ST
Rd, Z+q
k, Rr
Load Indirect with Displacement
Store Direct to Data Space
Store Indirect
Rd
(k)
(X)
←
←
←
(Z + q)
Rd
None
None
None
None
2(1)(2)
2(1)
X, Rr
Rr
1(1)
ST
X+, Rr
Store Indirect and Post-Increment
(X)
X
←
←
Rr,
X + 1
1(1)
ST
-X, Rr
Store Indirect and Pre-Decrement
X
(X)
←
←
X - 1,
Rr
None
2(1)
ST
ST
Y, Rr
Store Indirect
(Y)
←
Rr
None
None
1(1)
1(1)
Y+, Rr
Store Indirect and Post-Increment
(Y)
Y
←
←
Rr,
Y + 1
ST
-Y, Rr
Store Indirect and Pre-Decrement
Y
(Y)
←
←
Y - 1,
Rr
None
2(1)
STD
ST
Y+q, Rr
Z, Rr
Store Indirect with Displacement
Store Indirect
(Y + q)
(Z)
←
←
Rr
Rr
None
None
None
2(1)
1(1)
1(1)
ST
Z+, Rr
Store Indirect and Post-Increment
(Z)
Z
←
←
Rr
Z + 1
ST
-Z, Rr
Store Indirect and Pre-Decrement
Store Indirect with Displacement
Load Program Memory
Z
(Z + q)
R0
←
←
←
←
Z - 1
Rr
None
None
None
None
None
2(1)
2(1)
3
STD
LPM
LPM
LPM
Z+q,Rr
(Z)
Rd, Z
Load Program Memory
Rd
(Z)
3
Rd, Z+
Load Program Memory and Post-Increment
Rd
Z
←
←
(Z),
Z + 1
3
ELPM
ELPM
ELPM
Extended Load Program Memory
Extended Load Program Memory
R0
Rd
←
←
(RAMPZ:Z)
(RAMPZ:Z)
None
None
None
3
3
3
Rd, Z
Rd, Z+
Extended Load Program Memory and Post-
Increment
Rd
Z
←
←
(RAMPZ:Z),
Z + 1
SPM
SPM
Store Program Memory
(RAMPZ:Z)
←
R1:R0
None
None
-
-
Z+
Store Program Memory and Post-Increment
by 2
(RAMPZ:Z)
Z
←
←
R1:R0,
Z + 2
IN
Rd, A
A, Rr
Rr
In From I/O Location
Out To I/O Location
Rd
I/O(A)
STACK
Rd
←
←
←
←
I/O(A)
Rr
None
None
None
None
1
OUT
PUSH
POP
1
Push Register on Stack
Pop Register from Stack
Rr
1(1)
2(1)
Rd
STACK
Bit and Bit-test Instructions
LSL
LSR
Rd
Rd
Logical Shift Left
Logical Shift Right
Rd(n+1)
Rd(0)
C
←
←
←
Rd(n),
0,
Rd(7)
Z,C,N,V,H
Z,C,N,V
1
1
Rd(n)
Rd(7)
C
←
←
←
Rd(n+1),
0,
Rd(0)
53
8135I–AVR–10/10
XMEGA D4
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ROL
Rd
Rotate Left Through Carry
Rd(0)
Rd(n+1)
C
←
←
←
C,
Rd(n),
Rd(7)
Z,C,N,V,H
1
ROR
Rd
Rotate Right Through Carry
Rd(7)
Rd(n)
C
←
←
←
C,
Z,C,N,V
1
Rd(n+1),
Rd(0)
ASR
SWAP
BSET
BCLR
SBI
Rd
Arithmetic Shift Right
Swap Nibbles
Rd(n)
←
↔
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
Rd(n+1), n=0..6
Z,C,N,V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rd
Rd(3..0)
Rd(7..4)
None
s
Flag Set
SREG(s)
1
SREG(s)
s
Flag Clear
SREG(s)
0
SREG(s)
A, b
A, b
Rr, b
Rd, b
Set Bit in I/O Register
Clear Bit in I/O Register
Bit Store from Register to T
Bit load from T to Register
Set Carry
I/O(A, b)
1
None
CBI
I/O(A, b)
0
None
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
T
Rr(b)
T
1
T
Rd(b)
C
C
N
N
Z
None
C
C
N
N
Z
Clear Carry
0
Set Negative Flag
1
Clear Negative Flag
Set Zero Flag
0
1
Clear Zero Flag
Z
0
Z
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Two’s Complement Overflow
Clear Two’s Complement Overflow
Set T in SREG
I
1
I
CLI
I
0
I
SES
CLS
SEV
CLV
SET
CLT
S
1
S
S
V
V
T
S
0
V
1
V
0
T
1
Clear T in SREG
T
0
T
SEH
CLH
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H
H
1
H
H
0
MCU Control Instructions
BREAK
NOP
Break
(See specific descr. for BREAK)
None
None
None
None
1
1
1
1
No Operation
Sleep
SLEEP
WDR
(see specific descr. for Sleep)
Watchdog Reset
(see specific descr. for WDR)
Notes: 1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid
for accesses via the external RAM interface.
2. One extra cycle must be added when accessing Internal SRAM.
54
8135I–AVR–10/10
XMEGA D4
30. Packaging information
30.1 44A
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0˚~7˚
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
11.75
9.90
11.75
9.90
0.30
0.09
0.45
0.15
1.00
12.00
10.00
12.00
10.00
–
1.05
12.25
D1
E
10.10 Note 2
12.25
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
E1
B
10.10 Note 2
0.45
C
–
0.20
3. Lead coplanarity is 0.10 mm maximum.
L
–
0.75
e
0.80 TYP
10/5/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
44A
B
R
55
8135I–AVR–10/10
XMEGA D4
30.2 44M1
D
Marked Pin# 1 ID
E
SEATING PLANE
A1
A3
TOP VIEW
A
K
L
Pin #1 Corner
SIDE VIEW
D2
Pin #1
Triangle
Option A
COMMON DIMENSIONS
(Unit of Measure = mm)
1
2
3
MIN
0.80
–
MAX
1.00
0.05
NOM
0.90
NOTE
SYMBOL
A
E2
Option B
Option C
A1
A3
b
0.02
Pin #1
Chamfer
(C 0.30)
0.20 REF
0.23
0.18
6.90
5.00
6.90
0.30
7.10
5.40
7.10
D
7.00
D2
E
5.20
K
Pin #1
Notch
(0.20 R)
e
b
7.00
E2
e
5.00
5.20
0.50 BSC
0.64
5.40
BOTTOM VIEW
L
0.59
0.20
0.69
0.41
Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3.
K
0.26
9/26/08
GPC
ZWS
DRAWING NO.
TITLE
REV.
44M1, 44-pad, 7 x 7 x 1.0 mm Body, Lead
Pitch 0.50 mm, 5.20 mm Exposed Pad,Thermally
Enhanced Plastic Very Thin Quad Flat No
Lead Package (VQFN)
Package Drawing Contact:
packagedrawings@atmel.com
44M1
H
56
8135I–AVR–10/10
XMEGA D4
30.3 49C2
E
A1 BALL ID
0.10
D
A1
A2
TOP VIEW
A
SIDE VIEW
E1
G
F
e
E
D
C
B
A
D1
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.00
–
NOM
–
NOTE
SYMBOL
A
1
2
3
4
5
6
7
A1
A2
D
0.20
0.65
4.90
–
A1 BALL CORNER
49 - Ø0.35 0.05
b
e
–
–
5.00
5.10
BOTTOM VIEW
D1
E
3.90 BSC
5.00
4.90
0.30
5.10
0.40
E1
b
3.90 BSC
0.35
e
0.65 BSC
3/14/08
GPC
CBD
DRAWING NO.
TITLE
REV.
49C2, 49-ball (7 x 7 Array), 0.65 mm Pitch,
5.0 x 5.0 x 1.0 mm, Very Thin, Fine-Pitch
Ball Grid Array Package (VFBGA)
Package Drawing Contact:
packagedrawings@atmel.com
49C2
A
57
8135I–AVR–10/10
XMEGA D4
31. Electrical Characteristics
31.1 Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Operating Temperature.................................. -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on any Pin with respect to Ground..-0.5V to VCC+0.5V
Maximum Operating Voltage ............................................ 3.6V
DC Current per I/O Pin ............................................... 20.0 mA
DC Current VCC and GND Pins................................ 200.0 mA
31.2 DC Characteristics
Table 31-1. Current Consumption
Symbol Parameter
Condition
32 kHz, Ext. Clk
Min.
Typ.
30
Max.
Units
V
CC = 1.8V
CC = 3.0V
CC = 1.8V
CC = 3.0V
CC = 1.8V
V
V
V
V
75
260
570
510
1.1
µA
1 MHz, Ext. Clk
Active
690
1.49
13
2 MHz, Ext. Clk
32 MHz, Ext. Clk
32 kHz, Ext. Clk
VCC = 3.0V
VCC = 3.0V
mA
11.4
2.8
Power Supply Current(1)
V
CC = 1.8V
VCC = 3.0V
CC = 1.8V
VCC = 3.0V
4.8
V
80
1 MHz, Ext. Clk
µA
Idle
150
160
295
4.8
V
CC = 1.8V
CC = 3.0V
225
390
6
ICC
2 MHz, Ext. Clk
32 MHz, Ext. Clk
V
VCC = 3.0V
VCC = 3.0V
VCC = 3.0V
mA
All Functions Disabled
0.1
All Functions Disabled, T = 85°C
1.5
5
Power-down mode
Power-save mode
V
CC = 1.8V
VCC = 3.0V
CC = 3.0V
VCC = 1.8V
CC = 3.0V
1.1
ULP, WDT, Sampled BOD
1.1
ULP, WDT, Sampled BOD, T=85°C
V
2.6
10
µA
0.52
0.61
1.16
RTC 1 kHz from Low Power 32 kHz
TOSC
V
RTC from Low Power 32 kHz TOSC
without Reset pull-up resistor current
VCC = 3.0V
VCC = 3.0V
Reset Current
Consumption
505
58
8135I–AVR–10/10
XMEGA D4
Table 31-1. Current Consumption (Continued)
Symbol Parameter
Module current consumption(2)
RC32M
Condition
Min.
Typ.
Max.
Units
470
600
112
145
30
RC32M w/DFLL
RC2M
Internal 32.768 kHz oscillator as DFLL source
Internal 32.768 kHz oscillator as DFLL source
Multiplication factor = 10x
RC2M w/DFLL
RC32K
PLL
225
0.9
120
1
Watchdog normal mode
BOD Continuous mode
BOD Sampled mode
µA
ICC
Internal 1.00 V ref
80
Temperature reference
80
RTC with int. 32 kHz RC
as source
No prescaling
No prescaling
30
RTC with ULP as source
0.9
110
5.3
19
AC
USART
Rx and Tx enabled, 9600 BAUD
Prescaler DIV1
Vcc = 2V
Timer/Counter
13
25
Flash/EEPROM
Programming
mA
Vcc = 3V
18
Notes: 1. All Power Reduction Registers set. T = 25°C if not specified.
2. All parameters measured as the difference in current consumption between module enabled and disabled. All data at
VCC = 3.0V, ClkSYS = 1 MHz External clock with no prescaling, T = 25°C.
59
8135I–AVR–10/10
XMEGA D4
31.3 Speed
Table 31-2. Operating voltage and frequency
Symbol
Parameter
Condition
VCC = 1.6V
CC = 1.8V
VCC = 2.7V
CC = 3.6V
Min
0
Typ
Max
12
Units
V
0
12
ClkCPU
CPU clock frequency
MHz
0
32
V
0
32
The maximum CPU clock frequency of the XMEGA D4 devices is depending on VCC. As shown
in Figure 31-1 on page 60 the Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V.
Figure 31-1. Operating Frequency vs.Vcc
MHz
32
Safe Operating Area
12
V
1.6
1.8
2.7
3.6
60
8135I–AVR–10/10
XMEGA D4
31.4 Flash and EEPROM Memory Characteristics
Table 31-3. Endurance and Data Retention
Symbol Parameter
Condition
Min
10K
10K
100
25
Typ
Max
Units
25°C
85°C
25°C
55°C
25°C
85°C
25°C
55°C
Write/Erase cycles
Cycle
Flash
Data retention
Year
Cycle
Year
80K
30K
100
25
Write/Erase cycles
Data retention
EEPROM
Table 31-4. Programming time
Symbol Parameter
Chip Erase
Condition
Min
Typ(1)
40
6
Max
Units
Flash, EEPROM(2) and SRAM Erase
Page Erase
Flash
Page Write
6
Page WriteAutomatic Page Erase and Write
Page Erase
12
6
ms
EEPROM
Page Write
6
Page WriteAutomatic Page Erase and Write
12
Notes: 1. Programming is timed from the internal 2 MHz oscillator.
2. EEPROM is not erased if the EESAVE fuse is programmed.
61
8135I–AVR–10/10
XMEGA D4
31.5 ADC Characteristics
Table 31-5. ADC Characteristics
Symbol
RES
Parameter
Condition
Programmable: 8/12
100 ksps
Min
Typ
12
Max
Units
Resolution
8
12
Bits
INL
Integral Non-Linearity
Differential Non-Linearity
Gain Error
2
LSB
mV
DNL
100 ksps
< 1
< 10
< 2
Offset Error
ADCclk
ADC Clock frequency
Conversion rate
Max is 1/4 of Peripheral Clock
(RES+2)/2+GAIN
1400
200
kHz
ksps
Conversion time
ADCclk
cycles
5
7
10
RES = 8 or 12, GAIN = 0, 1, 2
or 3
(propagation delay)
Sampling Time
1/2 ADCclk cycle
0.36
0
uS
V
Conversion range
VREF
Vcc+0.3
Vcc-0.6V
AVCC
VREF
Analog Supply Voltage
Reference voltage
Vcc-0.3
1.0
Input bandwidth
kHz
V
INT1V
INTVCC
SCALEDVCC
RAREF
Internal 1.00V reference
Internal VCC/1.6
1.00
VCC/1.6
VCC/10
> 10
Scaled internal VCC/10 input
Reference input resistance
MΩ
ADCclk
cycles
Start-up time
12
24
Temp. sensor, VCC/10, Bandgap
Internal input sampling speed
100
ksps
Table 31-6. ADC Gain Stage Characteristics
Symbol
Parameter
Gain error
Offset error
Condition
Min
Typ
Max
Units
1 to 64 gain
< 1
< 1
0.12
0.06
%
VREF = Int. 1V
VREF = Ext. 2V
mV
Vrms
Noise level at input
Clock rate
64x gain
Same as ADC
200
kHz
62
8135I–AVR–10/10
XMEGA D4
31.6 Analog Comparator Characteristics
Table 31-7. Analog Comparator Characteristics
Symbol Parameter
Condition
Min
Typ
< 10
< 1000
0
Max
Units
mV
Voff
Ilk
Input Offset Voltage
VCC = 1.6 - 3.6V
VCC = 1.6 - 3.6V
VCC = 1.6 - 3.6V
VCC = 1.6 - 3.6V
VCC = 1.6 - 3.6V
VCC = 1.6 - 3.6V
Input Leakage Current
Hysteresis, No
pA
Vhys1
Vhys2
Vhys3
tdelay
Hysteresis, Small
Hysteresis, Large
Propagation delay
20
mV
ns
40
175
31.7 Bandgap Characteristics
Table 31-8. Bandgap Voltage Characteristics
Symbol Parameter
Condition
Min
Typ
Max
Units
As reference for ADC
As input to AC or ADC
1 Clk_PER + 2.5µs
Bandgap Startup Time
Bandgap voltage
µs
1.5
1.1
T= 85°C, After calibration
0.99
1
1
1.01
V
ADC ref
Variation over voltage and temperature
VCC = 1.6 - 3.6V, TA = -40°C to 85°C
5
%
31.8 Brownout Detection Characteristics
Table 31-9. Brownout Detection Characteristics(1)
Symbol Parameter
Condition
Min
Typ
1.62
1.9
Max
Units
BOD level 0 falling Vcc
BOD level 1 falling Vcc
BOD level 2 falling Vcc
2.17
2.43
2.68
2.96
3.22
3.49
1
BOD level 3 falling Vcc
V
BOD level 4 falling Vcc
BOD level 5 falling Vcc
BOD level 6 falling Vcc
BOD level 7 falling Vcc
Hysteresis
BOD level 0-5
%
Note:
1. BOD is calibrated to BOD level 0 at 85°C, and BOD level 0 is the default level.
63
8135I–AVR–10/10
XMEGA D4
31.9 PAD Characteristics
Table 31-10. PAD Characteristics
Symbol Parameter
Condition
CC = 2.4 - 3.6V
Min
0.7*VCC
0.8*VCC
-0.5
Typ
Max
VCC+0.5
VCC+0.5
0.3*VCC
0.2*VCC
0.76
Units
V
V
V
VIH
VIL
Input High Voltage
Input Low Voltage
CC = 1.6 - 2.4V
CC = 2.4 - 3.6V
VCC = 1.6 - 2.4V
OH = 8 mA, VCC = 3.3V
-0.5
I
0.4
0.3
V
VOL
Output Low Voltage GPIO
Output High Voltage GPIO
IOH = 5 mA, VCC = 3.0V
IOH = 3 mA, VCC = 1.8V
0.64
0.2
0.46
I
OH = -4 mA, VCC = 3.3V
2.6
2.1
1.4
3.0
VOH
IOH = -3 mA, VCC = 3.0V
IOH = -1 mA, VCC = 1.8V
2.7
1.6
IIL
IIH
Input Leakage Current I/O pin
Input Leakage Current I/O pin
<0.001
<0.001
20
1
1
µA
RP
I/O pin Pull/Buss keeper Resistor T= -40°C to 85°C
kΩ
RRST
Reset pin Pull-up Resistor
Input hysteresis
T= -40°C to 85°C
20
VCC = 1.6 V - 3.6 V, T= -40°C to 85°C
0.5
V
31.10 POR Characteristics
Table 31-11. Power-on Reset Characteristics
Symbol Parameter
Condition
Min
Typ
1
Max
Units
VPOT-
POR threshold voltage falling Vcc
POR threshold voltage rising Vcc
V
VPOT+
1.3
31.11 Reset Characteristics
Table 31-12. Reset Characteristics
Symbol Parameter
Condition
Min
Typ
90
Max
Units
Minimum reset pulse width
ns
V
CC = 2.7 - 3.6V
0.45*VCC
0.42*VCC
Reset threshold voltage
V
VCC = 1.6 - 2.7V
64
8135I–AVR–10/10
XMEGA D4
31.12 Oscillator Characteristics
Table 31-13. Internal 32.768 kHz Oscillator Characteristics
Symbol Parameter
Condition
Min
Typ
Max
Units
T = 85°C, VCC = 3V,
After production calibration
Accuracy
-0.5
0.5
%
Table 31-14. Internal 2 MHz Oscillator Characteristics
Symbol Parameter
Condition
Min
Typ
Max
Units
T = 85°C, VCC = 3V,
After production calibration
Accuracy
-1.5
1.5
%
DFLL Calibration step size
T = 25°C, VCC = 3V
0.15
Table 31-15. Internal 32 MHz Oscillator Characteristics
Symbol Parameter
Condition
Min
Typ
Max
Units
T = 85°C, VCC = 3V,
After production calibration
Accuracy
-1.5
1.5
%
DFLL Calibration stepsize
T = 25°C, VCC = 3V
0.2
Table 31-16. Internal 32 kHz, ULP Oscillator Characteristics
Symbol Parameter Condition
Output frequency 32 kHz ULP OSC T = 85°C, VCC = 3.0V
Min
Typ
Max
Units
26
kHz
Table 31-17. Maximum load capacitance (CL) and ESR recommendation for 32.768 kHz Crystal
Crystal CL [pF]
Max ESR [kΩ]
6.5
9
60
35
65
8135I–AVR–10/10
XMEGA D4
Table 31-18. Device wake-up time from sleep
Symbol Parameter
Condition(1)
Int. 32.768 kHz RC
Int. 2 MHz RC
Min
Typ()
130
2
Max
Units
Idle Sleep, Standby and Extended
Standby sleep mode
Ext. 2 MHz Clock
Int. 32 MHz RC
Int. 32.768 kHz RC
Int. 2 MHz RC
2
0.17
320
10.3
4.5
5.8
µS
Power-save and Power-down Sleep
mode
Ext. 2 MHz Clock
Int. 32 MHz RC
Notes: 1. Non-prescaled System Clock source.
Time from pin change on external interrupt pin to first available clock cycle. Additional interrupt response
time is minimum 5 system clock source cycles.
66
8135I–AVR–10/10
XMEGA D4
32. Typical Characteristics
32.1 Active Supply Current
Figure 32-1. Active Supply Current vs. Frequency
fSYS = 0 - 1.0 MHz External clock, T = 25°C.
700
600
500
400
300
200
100
0
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency [MHz]
Figure 32-2. Active Supply Current vs. Frequency
fSYS = 1 - 32 MHz External clock, T = 25°C.
14
12
10
8
3.3 V
3.0 V
2.7 V
6
2.2 V
4
1.8 V
2
0
0
4
8
12
16
20
24
28
32
Frequency [MHz]
67
8135I–AVR–10/10
XMEGA D4
Figure 32-3. Active Supply Current vs. Vcc
fSYS = 1.0 MHz External Clock.
800
700
600
500
400
300
200
100
0
85 °C
25 °C
-40 °C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
Figure 32-4. Active Supply Current vs. VCC
fSYS = 32.768 kHz internal RC.
160
140
120
100
80
-40 °C
85 °C
25 °C
60
40
20
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
68
8135I–AVR–10/10
XMEGA D4
Figure 32-5. Active Supply Current vs. Vcc
fSYS = 2.0 MHz internal RC.
1600
1400
1200
1000
800
600
400
200
0
85 °C
25 °C
-40 °C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
Figure 32-6. Active Supply Current vs. Vcc
fSYS = 32 MHz internal RC prescaled to 8 MHz.
7
6
5
4
3
2
1
0
-40 °C
25 °C
85 °C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
69
8135I–AVR–10/10
XMEGA D4
Figure 32-7. Active Supply Current vs. Vcc
fSYS = 32 MHz internal RC.
16
14
12
10
8
-40 °C
25 °C
85 °C
6
4
2
0
2.7
2.8
2.9
3
3.1
3.2
CC [V]
3.3
3.4
3.5
3.6
V
32.2 Idle Supply Current
Figure 32-8. Idle Supply Current vs. Frequency
fSYS = 0 - 1.0 MHz, T = 25°C.
180
160
140
120
100
80
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
60
40
20
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency [MHz]
70
8135I–AVR–10/10
XMEGA D4
Figure 32-9. Idle Supply Current vs. Frequency
fSYS = 1 - 32 MHz, T = 25°C.
6
5
4
3
2
3.3 V
3.0 V
2.7 V
2.2 V
1
1.8 V
0
0
4
8
12
16
20
24
28
32
Frequency [MHz]
Figure 32-10. Idle Supply Current vs. Vcc
fSYS = 1.0 MHz External Clock.
200
160
120
80
85 °C
25 °C
-40 °C
40
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
71
8135I–AVR–10/10
XMEGA D4
Figure 32-11. Idle Supply Current vs. Vcc
fSYS = 32.768 kHz internal RC.
40
35
30
25
20
15
10
5
85 °C
-40 °C
25 °C
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
Figure 32-12. : Idle Supply Current vs. Vcc
fSYS = 2.0 MHz internal RC.
500
400
300
200
100
0
-40 °C
25 °C
85 °C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
72
8135I–AVR–10/10
XMEGA D4
Figure 32-13. Idle Supply Current vs. Vcc
fSYS = 32 MHz internal RC prescaled to 8 MHz.
3000
2500
2000
1500
1000
500
-40 °C
25 °C
85 °C
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
Figure 32-14. : Idle Supply Current vs. Vcc
fSYS = 32 MHz internal RC.
7
6
5
4
3
2
1
0
-40 °C
25 °C
85 °C
2.7
2.8
2.9
3
3.1
3.2
CC [V]
3.3
3.4
3.5
3.6
V
73
8135I–AVR–10/10
XMEGA D4
32.3 Power-down Supply Current
Figure 32-15. Power-down Supply Current vs. Temperature
1.8
1.6
1.4
1.2
1
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
0.8
0.6
0.4
0.2
0
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90
Temperature [°C]
Figure 32-16. Power-down Supply Current vs. Temperature
With WDT and sampled BOD enabled.
3
2.5
2
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
1.5
1
0.5
0
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90
Temperature [°C]
74
8135I–AVR–10/10
XMEGA D4
32.4 Power-save Supply Current
Figure 32-17. Power-save Supply Current vs. Temperature
With WDT, sampled BOD and RTC from ULP enabled.
3
2.5
2
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
1.5
1
0.5
0
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90
Temperature [°C]
32.5 Pin Pull-up
Figure 32-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 1.8V.
100
80
60
40
20
0
-40 °C
25 °C
85 °C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
V
RESET [V]
75
8135I–AVR–10/10
XMEGA D4
Figure 32-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.0V.
160
140
120
100
80
60
40
-40 °C
25 °C
85 °C
20
0
0
0.5
1
1.5
2
2.5
3
V
RESET [V]
Figure 32-20. Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.3V.
180
160
140
120
100
80
60
40
-40 °C
25 °C
85 °C
20
0
0
0.5
1
1.5
2
2.5
3
VRESET [V]
76
8135I–AVR–10/10
XMEGA D4
32.6 Pin Output Voltage vs. Sink/Source Current
Figure 32-21. I/O Pin Output Voltage vs. Source Current
Vcc = 1.8V.
2
1.8
1.6
1.4
1.2
1
-40 °C
25 °C
85 °C
0.8
0.6
0.4
0.2
0
-6
-5
-4
-3
-2
-1
0
I
PIN [mA]
Figure 32-22. I/O Pin Output Voltage vs. Source Current
Vcc = 3.0V.
3.5
3
-40 °C
25 °C
85 °C
2.5
2
1.5
1
0.5
0
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
IPIN [mA]
77
8135I–AVR–10/10
XMEGA D4
Figure 32-23. I/O Pin Output Voltage vs. Source Current
Vcc = 3.3V.
3.5
3
-40 °C
25 °C
85 °C
2.5
2
1.5
1
0.5
0
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
IPIN [mA]
Figure 32-24. I/O Pin Output Voltage vs. Sink Current
Vcc = 1.8V.
85°C 25°C
1.8
1.6
1.4
1.2
1
-40 °C
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
6
7
8
9
10
IPIN [mA]
78
8135I–AVR–10/10
XMEGA D4
Figure 32-25. I/O Pin Output Voltage vs. Sink Current
Vcc = 3.0V.
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
85 °C
25 °C
-40 °C
0
1
2
3
4
5
6
7
8
9
10
IPIN [mA]
Figure 32-26. I/O Pin Output Voltage vs. Sink Current
Vcc = 3.3V.
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
85 °C
25 °C
-40 °C
0
1
2
3
4
5
6
7
8
9
10
IPIN [mA]
79
8135I–AVR–10/10
XMEGA D4
32.7 Pin Thresholds and Hysteresis
Figure 32-27. I/O Pin Input Threshold Voltage vs. VCC
VIH - I/O Pin Read as “1”.
2.5
2
-40 °C
25 °C
85 °C
1.5
1
0.5
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
Figure 32-28. I/O Pin Input Threshold Voltage vs. VCC
VIL - I/O Pin Read as “0”.
1.8
1.6
1.4
1.2
1
85 °C
25 °C
-40 °C
0.8
0.6
0.4
0.2
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
80
8135I–AVR–10/10
XMEGA D4
Figure 32-29. I/O Pin Input Hysteresis vs. VCC.
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
85 °C
25 °C
-40 °C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
Figure 32-30. Reset Input Threshold Voltage vs. VCC
VIH - I/O Pin Read as “1”.
1.8
1.6
1.4
1.2
1
-40 °C
25 °C
85 °C
0.8
0.6
0.4
0.2
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
81
8135I–AVR–10/10
XMEGA D4
Figure 32-31. Reset Input Threshold Voltage vs. VCC
VIL - I/O Pin Read as “0”.
1.8
1.6
1.4
1.2
1
-40 °C
25 °C
85 °C
0.8
0.6
0.4
0.2
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
32.8 Bod Thresholds
Figure 32-32. BOD Thresholds vs. Temperature
BOD Level = 1.6V.
1.645
1.64
1.635
1.63
Rising Vcc
1.625
1.62
Falling Vcc
1.615
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90
Temperature [°C]
82
8135I–AVR–10/10
XMEGA D4
Figure 32-33. BOD Thresholds vs. Temperature
BOD Level = 2.9V.
3.03
3.02
3.01
Rising Vcc
3
2.99
2.98
2.97
2.96
2.95
Falling Vcc
2.94
2.93
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90
Temperature [°C]
32.9 Analog Comparator
Figure 32-34. Analog Comparator Hysteresis vs. VCC
High-speed, Small hysteresis.
20
16
12
8
85 °C
25 °C
-40 °C
4
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
83
8135I–AVR–10/10
XMEGA D4
Figure 32-35. Analog Comparator Hysteresis vs. VCC
High-speed, Large hysteresis.
60
50
40
30
20
10
0
85 °C
25 °C
-40 °C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
Figure 32-36. Analog Comparator Propagation Delay vs. VCC
High-speed.
180
162
144
126
108
90
85 °C
25 °C
-40 °C
72
54
36
18
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
84
8135I–AVR–10/10
XMEGA D4
32.10 Oscillators and Wake-up Time
32.10.1 Internal 32.768 kHz Oscillator
Figure 32-37. Internal 32.768 kHz Oscillator Calibration Step Size
T = -40 to 85°C, VCC = 3V.
0.80 %
0.65 %
0.50 %
0.35 %
0.20 %
0.05 %
0
32
64
96
128
160
192
224
256
RC32KCAL[7..0]
32.10.2 Internal 2 MHz Oscillator
Figure 32-38. Internal 2 MHz Oscillator CALA Calibration Step Size
T = -40 to 85°C, VCC = 3V.
0.50 %
0.40 %
0.30 %
0.20 %
0.10 %
0.00 %
-0.10 %
-0.20 %
-0.30 %
0
16
32
48
64
80
96
112
128
DFLLRC2MCALA
85
8135I–AVR–10/10
XMEGA D4
Figure 32-39. Internal 2 MHz Oscillator CALB Calibration Step Size
T = -40 to 85°C, VCC = 3V.
3.00 %
2.50 %
2.00 %
1.50 %
1.00 %
0.50 %
0.00 %
0
8
16
24
32
40
48
56
64
DFLLRC2MCALB
32.10.3 Internal 32 MHZ Oscillator
Figure 32-40. Internal 32 MHz Oscillator CALA Calibration Step Size
T = -40 to 85°C, VCC = 3V.
0.60 %
0.50 %
0.40 %
0.30 %
0.20 %
0.10 %
0.00 %
-0.10 %
-0.20 %
0
16
32
48
64
80
96
112
128
DFLLRC32MCALA
86
8135I–AVR–10/10
XMEGA D4
Figure 32-41. Internal 32 MHz Oscillator CALB Calibration Step Size
T = -40 to 85°C, VCC = 3V.
3.00 %
2.50 %
2.00 %
1.50 %
1.00 %
0.50 %
0.00 %
0
8
16
24
32
40
48
56
64
DFLLRC32MCALB
32.11 Module current consumption
Figure 32-42. AC current consumption vs. Vcc
Low-power Mode.
140
120
100
80
85 °C
25 °C
-40 °C
60
40
20
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
87
8135I–AVR–10/10
XMEGA D4
Figure 32-43. Power-up current consumption vs. Vcc
25 °C
600
85 °C
-40 °C
500
400
300
200
100
0
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
V
CC [V]
32.12 Reset Pulsewidth
Figure 32-44. Minimum Reset Pulse Width vs. Vcc
100
80
60
40
20
0
85 °C
25 °C
-40 °C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
88
8135I–AVR–10/10
XMEGA D4
32.13 PDI Speed
Figure 32-45. PDI Speed vs. Vcc
35
25 °C
30
25
20
15
10
5
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
89
8135I–AVR–10/10
XMEGA D4
33. Errata
33.1 ATxmega16D4, ATxmega32D4
33.1.1
rev. B
• Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously
• VCC voltage scaler for AC is non-linear
• ADC has increased INL error for some operating conditions
• ADC gain stage output range is limited to 2.4 V
• ADC Event on compare match non-functional
• Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
• Accuracy lost on first three samples after switching input to ADC gain stage
• Configuration of PGM and CWCM not as described in XMEGA A Manual
• PWM is not restarted properly after a fault in cycle-by-cycle mode
• BOD: BOD will be enabled at any reset
• Sampled BOD in Active mode will cause noise when bandgap is used as reference
• DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V
• DAC has increased INL or noise for some operating conditions
• EEPROM page buffer always written when NVM DATA0 is written
• Pending full asynchronous pin change interrupts will not wake the device
• Pin configuration does not affect Analog Comparator Output
• NMI Flag for Crystal Oscillator Failure automatically cleared
• Flash Power Reduction Mode can not be enabled when entering sleep
• Crystal start-up time required after power-save even if crystal is source for RTC
• RTC Counter value not correctly read after sleep
• Pending asynchronous RTC-interrupts will not wake up device
• TWI Transmit collision flag not cleared on repeated start
• Clearing TWI Stop Interrupt Flag may lock the bus
• TWI START condition at bus timeout will cause transaction to be dropped
• TWI Data Interrupt Flag (DIF) erroneously read as set
• WDR instruction inside closed window will not issue reset
1. Bandgap voltage input for the ACs cannot be changed when used for both ACs
simultaneously
If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then
selected/deselected as input for another AC, the first comparator will be affected for up to
1 µs and could potentially give a wrong comparison result.
Problem fix/Workaround
If the Bandgap is required for both ACs simultaneously, configure the input selection for both
ACs before enabling any of them.
2. VCC voltage scaler for AC is non-linear
The 6-bit VCC voltage scaler in the Analog Comparators is non-linear.
90
8135I–AVR–10/10
XMEGA D4
Figure 33-1. Analog Comparator Voltage Scaler vs. Scalefac
T = 25°C
3.5
3
3.3 V
2.7 V
2.5
2
1.8 V
1.5
1
0.5
0
0
5
10
15
20
25
30
35
40
45
50
55
60
65
SCALEFAC
Problem fix/Workaround
Use external voltage input for the analog comparator if accurate voltage levels are needed
3. ADC has increased INL error for some operating conditions
Some ADC configurations or operating condition will result in increased INL error.
In signed mode INL is increased to:
– 6 LSB for sample rates above 1 Msps, and up to 8 LSB for 2 Msps sample rate.
– 6 LSB for reference voltage below 1.1V when VCC is above 3.0V.
– 20 LSB for ambient temperature below 0 degree C and reference voltage below 1.3V.
In unsigned mode, the INL is increased up to a factor of 3 for the conditions above.
Problem fix/Workaround
None, avoid using the ADC in the above configurations in order to prevent increased INL
error.
4. ADC gain stage output range is limited to 2.4 V
The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential
input will only give correct output when below 2.4 V/gain. For the available gain settings, this
gives a differential input range of:
–
–
–
–
–
–
–
1x gain:
2x gain:
4x gain:
8x gain:
16x gain:
32x gain:
64x gain:
2.4
1.2
0.6
V
V
V
300 mV
150 mV
75 mV
38 mV
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XMEGA D4
Problem fix/Workaround
Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a cor-
rect result, or keep ADC voltage reference below 2.4 V.
5. ADC Event on compare match non-functional
ADC signalling event will be given at every conversion complete even if Interrupt mode (INT-
MODE) is set to BELOW or ABOVE.
Problem fix/Workaround
Enable and use interrupt on compare match when using the compare function.
6. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
The ADC can not be used to do bandgap measurements when VCC is below 2.7V.
Problem fix/Workaround
None.
7. Accuracy lost on first three samples after switching input to ADC gain stage
Due to memory effect in the ADC gain stage, the first three samples after changing input
channel must be disregarded to achieve 12-bit accuracy.
Problem fix/Workaround
Run three ADC conversions and discard these results after changing input channels to ADC
gain stage.
8. Configuration of PGM and CWCM not as described in XMEGA A Manual
Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM),
but not Common Waveform Channel Mode.
Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode
(CWCM) will enable both Pattern Generation Mode and Common Waveform Channel Mode.
Problem fix/Workaround
Table 33-1. Configure PWM and CWCM according to this table:
PGM
CWCM
Description
0
0
1
1
0
1
0
1
PGM and CWCM disabled
PGM enabled
PGM and CWCM enabled
PGM enabled
9. PWM is not restarted properly after a fault in cycle-by-cycle mode
When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not
return to normal operation at first update after fault condition is no longer present.
Problem fix/Workaround
Do a write to any AWeX I/O register to re-enable the output.
10. BOD will be enabled after any reset
If any reset source goes active, the BOD will be enabled and keep the device in reset if the
VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be
released until VCC is above the programmed BOD level even if the BOD is disabled.
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Problem fix/Workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
11. Sampled BOD in Active mode will cause noise when bandgap is used as reference
Using the BOD in sampled mode when the device is running in Active or Idle mode will add
noise on the bandgap reference for ADC, DAC and Analog Comparator.
Problem fix/Workaround
If the bandgap is used as reference for either the ADC, DAC or the Analog Comparator, the
BOD must not be set in sampled mode.
12. DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V
Using the DAC with a reference voltage above 2.4V or VCC - 0.6V will give inaccurate out-
put when converting codes that give below 0.75V output:
– 10 LSB for continuous mode
– 200 LSB for Sample and Hold mode
Problem fix/Workaround
None.
13. DAC has increased INL or noise for some operating conditions
Some DAC configurations or operating condition will result in increased output error.
– Continous mode: 5 LSB
– Sample and hold mode: 15 LSB
– Sample and hold mode for reference above 2.0v: up to 100 LSB
Problem fix/Workaround
None.
14. EEPROM page buffer always written when NVM DATA0 is written
If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM
page buffer.
Problem fix/Workaround
Before writing to NVM DATA0, for example when doing software CRC or flash page buffer
write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM
DATA0 when EELOAD is set.
15. Pending full asynchronous pin change interrupts will not wake the device
Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the
sleep instruction is executed, will be ignored until the device is woken from another source
or the source triggers again. This applies when entering all sleep modes where the System
Clock is stopped.
Problem fix/Workaround
None.
16. Pin configuration does not affect Analog Comparator output
The Output/Pull and inverted pin configuration does not affect the Analog Comparator
output.
Problem fix/Workaround
None for Output/Pull configuration.
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For inverted I/O, configure the Analog Comparator to give an inverted result (i.e. connect
positive input to the negative AC input and vice versa), or use and external inverter to
change polarity of Analog Comparator output.
17. NMI Flag for Crystal Oscillator Failure automatically cleared
NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when exe-
cuting the NMI interrupt handler.
Problem fix/Workaround
This device revision has only one NMI interrupt source, so checking the interrupt source in
software is not required.
18. Flash Power Reduction Mode can not be enabled when entering sleep
If Flash Power Reduction Mode is enabled when entering Power-save or Extended Standby
sleep mode, the device will only wake up on every fourth wake-up request. If Flash Power
Reduction Mode is enabled when entering Idle sleep mode, the wake-up time will vary with
up to 16 CPU clock cycles.
Problem fix/Workaround
Disable Flash Power Reduction mode before entering sleep mode.
19. Crystal start-up time required after power-save even if crystal is source for RTC
Even if 32.768 kHz crystal is used for RTC during sleep, the clock from the crystal will not be
ready for the system before the specified start-up time. See "XOSCSEL[3:0]: Crystal Oscilla-
tor Selection" in XMEGA A Manual. If BOD is used in active mode, the BOD will be on during
this period (0.5s).
Problem fix/Workaround
If faster start-up is required, go to sleep with internal oscillator as system clock.
20. RTC Counter value not correctly read after sleep
If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to
bit 0 of RTC PER as the device is entering sleep, the value in the RTC count register can not
be read correctly within the first prescaled RTC clock cycle after wakeup. The value read will
be the same as the value in the register when entering sleep.
The same applies if RTC Compare Match is used as wake-up source.
Problem fix/Workaround
Wait at least one prescaled RTC clock cycle before reading the RTC CNT value.
21. Pending asynchronous RTC-interrupts will not wake up device
Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep
instruction is executed, will be ignored until the device is woken from another source or the
source triggers again.
Problem fix/Workaround
None.
22. TWI Transmit collision flag not cleared on repeated start
The TWI transmit collision flag should be automatically cleared on start and repeated start,
but is only cleared on start.
Problem fix/Workaround
Clear the flag in software after address interrupt.
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23. Clearing TWI Stop Interrupt Flag may lock the bus
If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the
hardware sets this flag due to a new address received, CLKHOLD is not cleared and the
SCL line is not released. This will lock the bus.
Problem fix/Workaround
Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is
not IDLE, wait for the SCL pin to be low before clearing APIF.
Code:
/* Only clear the interrupt flag if within a "safe zone". */
while ( /* Bus not IDLE: */
((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) !=
TWI_MASTER_BUSSTATE_IDLE_gc)) &&
/* SCL not held by slave: */
!(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm)
)
{
/* Ensure that the SCL line is low */
if ( !(COMMS_PORT.IN & PIN1_bm) )
if ( !(COMMS_PORT.IN & PIN1_bm) )
break;
}
/* Check for an pending address match interrupt */
if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) )
{
/* Safely clear interrupt flag */
COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm;
}
24. TWI START condition at bus timeout will cause transaction to be dropped
If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a
START is detected, the transaction will be dropped.
Problem fix/Workaround
None.
25. TWI Data Interrupt Flag erroneously read as set
When issuing the TWI slave response command CMD=0b11, it takes 1 Peripheral Clock
cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command
will show the DIF still set.
Problem fix/Workaround
Add one NOP instruction before checking DIF.
26. WDR instruction inside closed window will not issue reset
When a WDR instruction is execute within one ULP clock cycle after updating the window
control register, the counter can be cleared without giving a system reset.
Problem fix/Workaround
Wait at least one ULP clock cycle before executing a WDR instruction.
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33.1.2
rev. A
• Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously
• VCC voltage scaler for AC is non-linear
• ADC has increased INL error for some operating conditions
• ADC gain stage output range is limited to 2.4 V
• ADC Event on compare match non-functional
• Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
• Accuracy lost on first three samples after switching input to ADC gain stage
• Configuration of PGM and CWCM not as described in XMEGA A Manual
• PWM is not restarted properly after a fault in cycle-by-cycle mode
• BOD: BOD will be enabled at any reset
• Sampled BOD in Active mode will cause noise when bandgap is used as reference
• DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V
• DAC has increased INL or noise for some operating conditions
• EEPROM page buffer always written when NVM DATA0 is written
• Pending full asynchronous pin change interrupts will not wake the device
• Pin configuration does not affect Analog Comparator Output
• NMI Flag for Crystal Oscillator Failure automatically cleared
• Flash Power Reduction Mode can not be enabled when entering sleep
• Crystal start-up time required after power-save even if crystal is source for RTC
• RTC Counter value not correctly read after sleep
• Pending asynchronous RTC-interrupts will not wake up device
• TWI Transmit collision flag not cleared on repeated start
• Clearing TWI Stop Interrupt Flag may lock the bus
• TWI START condition at bus timeout will cause transaction to be dropped
• TWI Data Interrupt Flag (DIF) erroneously read as set
• WDR instruction inside closed window will not issue reset
1. Bandgap voltage input for the ACs cannot be changed when used for both ACs
simultaneously
If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then
selected/deselected as input for another AC, the first comparator will be affected for up to
1 µs and could potentially give a wrong comparison result.
Problem fix/Workaround
If the Bandgap is required for both ACs simultaneously, configure the input selection for both
ACs before enabling any of them.
2. VCC voltage scaler for AC is non-linear
The 6-bit VCC voltage scaler in the Analog Comparators is non-linear.
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Figure 33-2. Analog Comparator Voltage Scaler vs. Scalefac
T = 25°C
3.5
3
3.3 V
2.7 V
2.5
2
1.8 V
1.5
1
0.5
0
0
5
10
15
20
25
30
35
40
45
50
55
60
65
SCALEFAC
Problem fix/Workaround
Use external voltage input for the analog comparator if accurate voltage levels are needed
3. ADC has increased INL error for some operating conditions
Some ADC configurations or operating condition will result in increased INL error.
In signed mode INL is increased to:
– 6 LSB for sample rates above 1 Msps, and up to 8 LSB for 2 Msps sample rate.
– 6 LSB for reference voltage below 1.1V when VCC is above 3.0V.
– 20 LSB for ambient temperature below 0 degree C and reference voltage below 1.3V.
In unsigned mode, the INL is increased up to a factor of 3 for the conditions above.
Problem fix/Workaround
None, avoid using the ADC in the above configurations in order to prevent increased INL
error.
4. ADC gain stage output range is limited to 2.4 V
The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential
input will only give correct output when below 2.4 V/gain. For the available gain settings, this
gives a differential input range of:
–
–
–
–
–
–
–
1x gain:
2x gain:
4x gain:
8x gain:
16x gain:
32x gain:
64x gain:
2.4
1.2
0.6
V
V
V
300 mV
150 mV
75 mV
38 mV
97
8135I–AVR–10/10
XMEGA D4
Problem fix/Workaround
Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a cor-
rect result, or keep ADC voltage reference below 2.4 V.
5. ADC Event on compare match non-functional
ADC signalling event will be given at every conversion complete even if Interrupt mode (INT-
MODE) is set to BELOW or ABOVE.
Problem fix/Workaround
Enable and use interrupt on compare match when using the compare function.
6. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
The ADC can not be used to do bandgap measurements when VCC is below 2.7V.
Problem fix/Workaround
None.
7. Accuracy lost on first three samples after switching input to ADC gain stage
Due to memory effect in the ADC gain stage, the first three samples after changing input
channel must be disregarded to achieve 12-bit accuracy.
Problem fix/Workaround
Run three ADC conversions and discard these results after changing input channels to ADC
gain stage.
8. Configuration of PGM and CWCM not as described in XMEGA A Manual
Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM),
but not Common Waveform Channel Mode.
Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode
(CWCM) will enable both Pattern Generation Mode and Common Waveform Channel Mode.
Problem fix/Workaround
Table 33-2. Configure PWM and CWCM according to this table:
PGM
CWCM
Description
0
0
1
1
0
1
0
1
PGM and CWCM disabled
PGM enabled
PGM and CWCM enabled
PGM enabled
9. PWM is not restarted properly after a fault in cycle-by-cycle mode
When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not
return to normal operation at first update after fault condition is no longer present.
Problem fix/Workaround
Do a write to any AWeX I/O register to re-enable the output.
10. BOD will be enabled after any reset
If any reset source goes active, the BOD will be enabled and keep the device in reset if the
VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be
released until VCC is above the programmed BOD level even if the BOD is disabled.
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Problem fix/Workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
11. Sampled BOD in Active mode will cause noise when bandgap is used as reference
Using the BOD in sampled mode when the device is running in Active or Idle mode will add
noise on the bandgap reference for ADC, DAC and Analog Comparator.
Problem fix/Workaround
If the bandgap is used as reference for either the ADC, DAC or the Analog Comparator, the
BOD must not be set in sampled mode.
12. DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V
Using the DAC with a reference voltage above 2.4V or VCC - 0.6V will give inaccurate out-
put when converting codes that give below 0.75V output:
– 10 LSB for continuous mode
– 200 LSB for Sample and Hold mode
Problem fix/Workaround
None.
13. DAC has increased INL or noise for some operating conditions
Some DAC configurations or operating condition will result in increased output error.
– Continous mode: 5 LSB
– Sample and hold mode: 15 LSB
– Sample and hold mode for reference above 2.0v: up to 100 LSB
Problem fix/Workaround
None.
14. EEPROM page buffer always written when NVM DATA0 is written
If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM
page buffer.
Problem fix/Workaround
Before writing to NVM DATA0, for example when doing software CRC or flash page buffer
write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM
DATA0 when EELOAD is set.
15. Pending full asynchronous pin change interrupts will not wake the device
Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the
sleep instruction is executed, will be ignored until the device is woken from another source
or the source triggers again. This applies when entering all sleep modes where the System
Clock is stopped.
Problem fix/Workaround
None.
16. Pin configuration does not affect Analog Comparator output
The Output/Pull and inverted pin configuration does not affect the Analog Comparator
output.
Problem fix/Workaround
None for Output/Pull configuration.
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For inverted I/O, configure the Analog Comparator to give an inverted result (i.e. connect
positive input to the negative AC input and vice versa), or use and external inverter to
change polarity of Analog Comparator output.
17. NMI Flag for Crystal Oscillator Failure automatically cleared
NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when exe-
cuting the NMI interrupt handler.
Problem fix/Workaround
This device revision has only one NMI interrupt source, so checking the interrupt source in
software is not required.
18. Flash Power Reduction Mode can not be enabled when entering sleep
If Flash Power Reduction Mode is enabled when entering Power-save or Extended Standby
sleep mode, the device will only wake up on every fourth wake-up request. If Flash Power
Reduction Mode is enabled when entering Idle sleep mode, the wake-up time will vary with
up to 16 CPU clock cycles.
Problem fix/Workaround
Disable Flash Power Reduction mode before entering sleep mode.
19. Crystal start-up time required after power-save even if crystal is source for RTC
Even if 32.768 kHz crystal is used for RTC during sleep, the clock from the crystal will not be
ready for the system before the specified start-up time. See "XOSCSEL[3:0]: Crystal Oscilla-
tor Selection" in XMEGA A Manual. If BOD is used in active mode, the BOD will be on during
this period (0.5s).
Problem fix/Workaround
If faster start-up is required, go to sleep with internal oscillator as system clock.
20. RTC Counter value not correctly read after sleep
If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to
bit 0 of RTC PER as the device is entering sleep, the value in the RTC count register can not
be read correctly within the first prescaled RTC clock cycle after wakeup. The value read will
be the same as the value in the register when entering sleep.
The same applies if RTC Compare Match is used as wake-up source.
Problem fix/Workaround
Wait at least one prescaled RTC clock cycle before reading the RTC CNT value.
21. Pending asynchronous RTC-interrupts will not wake up device
Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep
instruction is executed, will be ignored until the device is woken from another source or the
source triggers again.
Problem fix/Workaround
None.
22. TWI Transmit collision flag not cleared on repeated start
The TWI transmit collision flag should be automatically cleared on start and repeated start,
but is only cleared on start.
Problem fix/Workaround
Clear the flag in software after address interrupt.
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23. Clearing TWI Stop Interrupt Flag may lock the bus
If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the
hardware sets this flag due to a new address received, CLKHOLD is not cleared and the
SCL line is not released. This will lock the bus.
Problem fix/Workaround
Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is
not IDLE, wait for the SCL pin to be low before clearing APIF.
Code:
/* Only clear the interrupt flag if within a "safe zone". */
while ( /* Bus not IDLE: */
((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) !=
TWI_MASTER_BUSSTATE_IDLE_gc)) &&
/* SCL not held by slave: */
!(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm)
)
{
/* Ensure that the SCL line is low */
if ( !(COMMS_PORT.IN & PIN1_bm) )
if ( !(COMMS_PORT.IN & PIN1_bm) )
break;
}
/* Check for an pending address match interrupt */
if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) )
{
/* Safely clear interrupt flag */
COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm;
}
24. TWI START condition at bus timeout will cause transaction to be dropped
If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a
START is detected, the transaction will be dropped.
Problem fix/Workaround
None.
25. TWI Data Interrupt Flag erroneously read as set
When issuing the TWI slave response command CMD=0b11, it takes 1 Peripheral Clock
cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command
will show the DIF still set.
Problem fix/Workaround
Add one NOP instruction before checking DIF.
26. WDR instruction inside closed window will not issue reset
When a WDR instruction is execute within one ULP clock cycle after updating the window
control register, the counter can be cleared without giving a system reset.
Problem fix/Workaround
Wait at least one ULP clock cycle before executing a WDR instruction.
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34. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The
referring revisions in this section are referring to the document revision.
34.1 8135I – 10/10
1.
Updated Table 31-1 on page 58.
34.2 8135H – 09/10
34.3 8135G – 08/10
1.
Updated ”Errata” on page 90.
1.
2.
3.
4.
5.
6.
7.
Updated the Footnote 3 of ”Ordering Information” on page 2.
All references to CRC removed. Updated Figure 3-1 on page 6.
Updated ”Features” on page 26. Event Channel 0 output on port pin 7.
Updated ”DC Characteristics” on page 58 by adding Icc for Flash/EEPROM Programming.
Added AVCC in ”ADC Characteristics” on page 62.
Updated Start up time in ”ADC Characteristics” on page 62.
Updated and fixed typo in “Errata” section.
34.4 8135F – 02/10
34.5 8135E – 02/10
1.
Added ”PDI Speed” on page 89.
1.
2.
3.
4.
5.
6.
Updated the device pin-out Figure 2-1 on page 3. PDI_CLK and PDI_DATA renamed only PDI.
Updated Table 7-3 on page 14. No of Pages for ATxmega32D4: 32
Updated ”Alternate Port Functions” on page 29.
Updated ”ADC - 12-bit Analog to Digital Converter” on page 39.
Updated Figure 23-1 on page 40.
Updated ”Alternate Pin Functions” on page 48.
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7.
Updated ”Timer/Counter and AWEX functions” on page 46.
Added Table 31-17 on page 65.
8.
9.
Added Table 31-18 on page 66.
10.
11.
Changed Internal Oscillator Speed to ”Oscillators and Wake-up Time” on page 85.
Updated ”Errata” on page 90.
34.6 8135D – 12/09
1.
2.
3.
4.
5.
Added ATxmega128D4 device and updated the datasheet accordingly.
Updated ”Electrical Characteristics” on page 58 with Max/Min numbers.
Added ”Flash and EEPROM Memory Characteristics” on page 61.
Updated Table 31-10 on page 64, Input hysteresis is in V and not in mV.
Added ”Errata” on page 90.
34.7 8135C – 10/09
1.
2.
3.
4.
5.
6.
7.
8.
Updated ”Features” on page 1 with Two Two-Wire Interfaces.
Updated ”Bock Diagram and TQFP/QFN pinout” on page 3.
Updated ”Overview” on page 5.
Updated ”XMEGA D4 Block Diagram” on page 6.
Updated Table 13-1 on page 24.
Updated ”Overview” on page 35.
Updated Table 27-5 on page 49.
Updated ”Peripheral Module Address Map” on page 50.
34.8 8135B – 09/09
34.9 8135A – 03/09
1.
2.
Added ”Electrical Characteristics” on page 58.
Added ”Typical Characteristics” on page 67.
1.
Initial revision.
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Table of Contents
Features..................................................................................................... 1
Typical Applications ................................................................................ 1
Ordering Information ............................................................................... 2
Pinout/Block Diagram .............................................................................. 3
Overview ................................................................................................... 5
1
2
3
3.1
Block Diagram ...................................................................................................6
4
Resources ................................................................................................. 7
4.1
Recommended reading .....................................................................................7
5
6
Disclaimer ................................................................................................. 7
AVR CPU ................................................................................................... 8
6.1
6.2
6.3
6.4
6.5
Features ............................................................................................................8
Overview ............................................................................................................8
Register File ......................................................................................................9
ALU - Arithmetic Logic Unit ...............................................................................9
Program Flow ....................................................................................................9
7
Memories ................................................................................................ 10
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Features ..........................................................................................................10
Overview ..........................................................................................................10
In-System Programmable Flash Program Memory .........................................11
Data Memory ...................................................................................................12
Production Signature Row ...............................................................................13
User Signature Row ........................................................................................13
Flash and EEPROM Page Size .......................................................................13
8
9
Event System ......................................................................................... 15
8.1
8.2
Features ..........................................................................................................15
Overview ..........................................................................................................15
System Clock and Clock options ......................................................... 17
9.1
9.2
9.3
Features ..........................................................................................................17
Overview ..........................................................................................................17
Clock Options ..................................................................................................18
10 Power Management and Sleep Modes ................................................. 20
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10.1
10.2
10.3
Features ..........................................................................................................20
Overview ..........................................................................................................20
Sleep Modes ....................................................................................................20
11 System Control and Reset .................................................................... 22
11.1
11.2
11.3
Features ..........................................................................................................22
Resetting the AVR ...........................................................................................22
Reset Sources .................................................................................................22
12 WDT - Watchdog Timer ......................................................................... 23
12.1
12.2
Features ..........................................................................................................23
Overview ..........................................................................................................23
13 PMIC - Programmable Multi-level Interrupt Controller ....................... 24
13.1
13.2
13.3
Features ..........................................................................................................24
Overview ..........................................................................................................24
Interrupt vectors ...............................................................................................24
14 I/O Ports .................................................................................................. 26
14.1
14.2
14.3
14.4
14.5
14.6
Features ..........................................................................................................26
Overview ..........................................................................................................26
I/O configuration ..............................................................................................26
Input sensing ...................................................................................................29
Port Interrupt ....................................................................................................29
Alternate Port Functions ..................................................................................29
15 T/C - 16-bit Timer/Counter ..................................................................... 30
15.1
15.2
Features ..........................................................................................................30
Overview ..........................................................................................................30
16 AWEX - Advanced Waveform Extension ............................................. 32
16.1
16.2
Features ..........................................................................................................32
Overview ..........................................................................................................32
17 Hi-Res - High Resolution Extension ..................................................... 33
17.1
17.2
Features ..........................................................................................................33
Overview ..........................................................................................................33
18 RTC - 16-bit Real-Time Counter ............................................................ 34
18.1
18.2
Features ..........................................................................................................34
Overview ..........................................................................................................34
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19 TWI - Two-Wire Interface ....................................................................... 35
19.1
19.2
Features ..........................................................................................................35
Overview ..........................................................................................................35
20 SPI - Serial Peripheral Interface ............................................................ 36
20.1
20.2
Features ..........................................................................................................36
Overview ..........................................................................................................36
21 USART ..................................................................................................... 37
21.1
21.2
Features ..........................................................................................................37
Overview ..........................................................................................................37
22 IRCOM - IR Communication Module .................................................... 38
22.1
22.2
Features ..........................................................................................................38
Overview ..........................................................................................................38
23 ADC - 12-bit Analog to Digital Converter ............................................. 39
23.1
23.2
Features ..........................................................................................................39
Overview ..........................................................................................................39
24 AC - Analog Comparator ....................................................................... 41
24.1
24.2
24.3
24.4
Features ..........................................................................................................41
Overview ..........................................................................................................41
Input Selection .................................................................................................43
Window Function .............................................................................................43
25 OCD - On-chip Debug ............................................................................ 44
25.1
25.2
Features ..........................................................................................................44
Overview ..........................................................................................................44
26 PDI - Program and Debug Interface ..................................................... 45
26.1
26.2
26.3
Features ..........................................................................................................45
Overview ..........................................................................................................45
PDI - Program and Debug Interface ................................................................45
27 Pinout and Pin Functions ...................................................................... 46
27.1
27.2
Alternate Pin Functions Description ................................................................46
Alternate Pin Functions ...................................................................................48
28 Peripheral Module Address Map .......................................................... 50
29 Instruction Set Summary ...................................................................... 51
iii
8135I–AVR–10/10
XMEGA D4
30 Packaging information .......................................................................... 55
30.1
30.2
30.3
44A ..................................................................................................................55
44M1 ................................................................................................................56
49C2 ................................................................................................................57
31 Electrical Characteristics ...................................................................... 58
31.1
31.2
31.3
31.4
31.5
31.6
31.7
31.8
31.9
Absolute Maximum Ratings* ...........................................................................58
DC Characteristics ..........................................................................................58
Speed ..............................................................................................................60
Flash and EEPROM Memory Characteristics .................................................61
ADC Characteristics ........................................................................................62
Analog Comparator Characteristics .................................................................63
Bandgap Characteristics .................................................................................63
Brownout Detection Characteristics ................................................................63
PAD Characteristics ........................................................................................64
31.10 POR Characteristics ........................................................................................64
31.11 Reset Characteristics ......................................................................................64
31.12 Oscillator Characteristics .................................................................................65
32 Typical Characteristics .......................................................................... 67
32.1
32.2
32.3
32.4
32.5
32.6
32.7
32.8
32.9
Active Supply Current ......................................................................................67
Idle Supply Current ..........................................................................................70
Power-down Supply Current ............................................................................74
Power-save Supply Current .............................................................................75
Pin Pull-up .......................................................................................................75
Pin Output Voltage vs. Sink/Source Current ...................................................77
Pin Thresholds and Hysteresis ........................................................................80
Bod Thresholds ...............................................................................................82
Analog Comparator .........................................................................................83
32.10 Oscillators and Wake-up Time ........................................................................85
32.11 Module current consumption ...........................................................................87
32.12 Reset Pulsewidth .............................................................................................88
32.13 PDI Speed .......................................................................................................89
33 Errata ....................................................................................................... 90
33.1
ATxmega16D4, ATxmega32D4 .......................................................................90
34 Datasheet Revision History ................................................................ 102
34.1
8135I – 10/10 .................................................................................................102
iv
8135I–AVR–10/10
34.2
34.3
34.4
34.5
34.6
34.7
34.8
34.9
8135H – 09/10 ...............................................................................................102
8135G – 08/10 ...............................................................................................102
8135F – 02/10 ...............................................................................................102
8135E – 02/10 ...............................................................................................102
8135D – 12/09 ...............................................................................................103
8135C – 10/09 ...............................................................................................103
8135B – 09/09 ...............................................................................................103
8135A – 03/09 ...............................................................................................103
Table of Contents....................................................................................... i
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