ATXMEGA8E5_14 [ATMEL]
8/16-bit Atmel AVR XMEGA Microcontrollers;型号: | ATXMEGA8E5_14 |
厂家: | ATMEL |
描述: | 8/16-bit Atmel AVR XMEGA Microcontrollers 微控制器 |
文件: | 总147页 (文件大小:2657K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
8/16-bit Atmel AVR XMEGA Microcontrollers
ATxmega32E5 / ATxmega16E5 / ATxmega8E5
DATASHEET
Features
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High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller
Nonvolatile program and data memories
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8K –32KBytes of in-system self-programmable flash
2K – 4KBytes boot section
512Bytes – 1KBytes EEPROM
1K – 4KBytes internal SRAM
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Peripheral features
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Four-channel enhanced DMA controller with 8/16-bit address match
Eight-channel event system
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Asynchronous and synchronous signal routing
Quadrature encoder with rotary filter
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Three 16-bit timer/counters
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One timer/counter with 4 output compare or input capture channels
Two timer/counter with 2 output compare or input capture channels
High resolution extension enabling down to 4ns PWM resolution
Waveform extension for control of motor, LED, lighting, H-bridge, high drives and more
Fault extension for safe and deterministic handling and/or shut-down of external driver
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CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3) generator
XMEGA Custom Logic (XCL) module with timer, counter and logic functions
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Two 8-bit timer/counters with capture/compare and 16-bit cascade mode
Connected to one USART to support custom data frame length
Connected to I/O pins and event system to do programmable logic functions
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MUX, AND, NAND, OR, NOR, XOR, XNOR, NOT, D-Flip-Flop, D Latch, RS Latch
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Two USARTs with full-duplex and single wire half-duplex configuration
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Master SPI mode
Support custom protocols with configurable data frame length up to 256-bit
System wake-up from deep sleep modes when used with internal 8MHz oscillator
One two-wire interface with dual address match (I2C and SMBus compatible)
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Bridge configuration for simultaneous master and slave operation
Up to 1MHz bus speed support
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One serial peripheral interface (SPI)
16-bit real time counter with separate oscillator and digital correction
One sixteen-channel, 12-bit, 300ksps Analog to Digital Converter with:
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Offset and gain correction
Averaging
Over-sampling and decimation
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One two-channel, 12-bit, 1Msps Digital to Analog Converter
Two Analog Comparators with window compare function and current sources
External interrupts on all general purpose I/O pins
Programmable watchdog timer with separate on-chip ultra low power oscillator
QTouch® library support
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Capacitive touch buttons, sliders and wheels
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Special microcontroller features
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Power-on reset and programmable brown-out detection
Internal and external clock options with PLL
Programmable multilevel interrupt controller
Five sleep modes
Programming and debug interface
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PDI (Program and Debug Interface)
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I/O and Packages
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26 programmable I/O pins
7x7mm 32-lead TQFP
5x5mm 32-lead VQFN
4x4mm 32-lead UQFN
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Operating Voltage
1.6 – 3.6V
Operating frequency
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0 – 12MHz from 1.6V
0 – 32MHz from 2.7V
Atmel 8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014
1.
Ordering Information
Flash
(Bytes)
EEPROM
(Bytes)
SRAM
(Bytes)
Speed
(MHz)
Ordering Code
ATxmega8E5-AU
Package(1)(2)(3)
Power supply
Temp.
32A
(7x7mm TQFP)
ATxmega8E5-AUR(4)
ATxmega8E5-MU
32Z
8K + 2K
16K + 4K
32K + 4K
8K + 2K
512B
512B
1K
1K
2K
4K
1K
2K
32
32
32
32
32
1.6 – 3.6V
-40°C – 85°C
(5x5mm VQFN)
ATxmega8E5-MUR(4)
ATxmega8E5-M4U
ATxmega8E5-M4UR(4)
ATxmega16E5-AU
32MA
(4x4mm UQFN)
32A
(7x7mm TQFP)
ATxmega16E5-AUR(4)
ATxmega16E5-MU
ATxmega16E5-MUR(4)
ATxmega16E5-M4U
ATxmega16E5-M4UR(4)
ATxmega32E5-AU
32Z
1.6 – 3.6V
1.6 – 3.6V
1.6 – 3.6V
1.6 – 3.6V
-40°C – 85°C
-40°C – 85°C
-40°C – 105°C
-40°C – 105°C
(5x5mm VQFN)
32MA
(4x4mm UQFN)
32A
(7x7mm TQFP)
ATxmega32E5AUR(4)
ATxmega32E5-MU
ATxmega32E5-MUR(4)
ATxmega32E5-M4U
ATxmega32E5-M4UR(4)
ATxmega8E5-AN
32Z
(5x5mm VQFN)
32MA
(4x4mm UQFN)
32A
(7x7mm TQFP)
ATxmega8E5-ANR(4)
ATxmega8E5-MN
32Z
512B
(5x5mm VQFN)
ATxmega8E5-MNR(4)
ATxmega8E5-M4N
ATxmega8E5-M4NR(4)
ATxmega16E5-AN
32MA
(4x4mm UQFN)
32A
(7x7mm TQFP)
ATxmega16E5-ANR(4)
ATxmega16E5-MN
ATxmega16E5-MNR(4)
ATxmega16E5-M4N
ATxmega16E5-M4NR(4)
32Z
16K + 4K
512B
(5x5mm VQFN)
32MA
(4x4mm UQFN)
XMEGA E5 [DATASHEET]
Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014
2
Flash
(Bytes)
EEPROM
(Bytes)
SRAM
(Bytes)
Speed
(MHz)
Ordering Code
Package(1)(2)(3)
Power supply
Temp.
ATxmega32E5-AN
ATxmega32E5ANR(4)
ATxmega32E5-MN
ATxmega32E5-MNR(4)
ATxmega32E5-M4N
ATxmega32E5-M4NR(4)
32A
(7x7mm TQFP)
32Z
32K + 4K
1K
4K
32
1.6 – 3.6V
-40°C – 105°C
(5x5mm VQFN)
32MA
(4x4mm UQFN)
Notes:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
3. For packaging information, see “Packaging information” on page 69.
4. Tape and Reel
Package Type
32-lead, 7x7mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (TQFP)
32-lead, 0.5mm pitch, 5x5mm Very Thin quad Flat No Lead Package (VQFN) Sawn
32-lead, 0.4mm pitch, 4x4x0.60mm Ultra Thin Quad No Lead (UQFN) Package
32A
32Z
32MA
2.
Typical Applications
Board controller
Sensor control
Industrial control
Battery charger
Motor control
User interface
Ballast control, Inverters
Utility metering
Communication bridges
Appliances
XMEGA E5 [DATASHEET]
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3.
Pinout and Block Diagram
Power
Programming, debug, test
Ground
External clock / Crystal pins
General Purpose I/O
Digital function
Analog function / Oscillators
Port D
GND
PA4
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PD4
PD5
PD6
PD7
PR0
PR1
GND
VCC
EVENT ROUTING NETWORK
DATA BUS
Power
Watchdog
Reset
TEMPREF
VREF
Supervision
Oscillator
Controller
PA3
AREF
ADC
Real Time
Counter
Sleep
Controller
OSC/CLK
Control
PA2
Event System
Controller
Interrupt
Controller
Prog/Debug
Interface
DAC
OCD
AC0:1
Watchdog
Timer
EDMA
Controller
PA1
BUS
Controller
CPU
CRC
PA0
EEPROM
FLASH
SRAM
DATA BUS
PDI
PDI / RESET
Port C
Notes: 1. For full details on pinout and alternate pin functions refer to “Pinout and Pin Functions” on page 58.
XMEGA E5 [DATASHEET]
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4.
Overview
The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based
on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA devices
achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system
designer to optimize power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly
connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction,
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times
faster than conventional single-accumulator or CISC based microcontrollers.
The AVR XMEGA E5 devices provide the following features: in-system programmable flash with read-while-write
capabilities; internal EEPROM and SRAM; four-channel enhanced DMA (EDMA) controller; eight-channel event system
with asynchronous event support; programmable multilevel interrupt controller; 26 general purpose I/O lines; CRC-16
(CRC-CCITT) and CRC-32 (IEEE 802.3) generators; one XMEGA Custom Logic module with timer, counter and logic
functions (XCL); 16-bit real-time counter (RTC) with digital correction; three flexible, 16-bit timer/counters with compare
and PWM channels; two USARTs; one two-wire serial interface (TWI) allowing simultaneous master and slave; one
serial peripheral interface (SPI); one sixteen-channel, 12-bit ADC with programmable gain, offset and gain correction,
averaging, over-sampling and decimation; one 2-channel 12-bit DAC; two analog comparators (ACs) with window mode
and current sources; programmable watchdog timer with separate internal oscillator; accurate internal oscillators with
PLL and prescaler; and programmable brown-out detection.
The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available.
The AVR XMEGA E5 devices have five software selectable power saving modes. The idle mode stops the CPU while
allowing the SRAM, EDMA controller, event system, interrupt controller, and all peripherals to continue functioning. The
power-down mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the
next TWI, or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to run,
allowing the application to maintain a timer base while the rest of the device is sleeping. In standby mode, the external
crystal oscillator keeps running while the rest of the device is sleeping. This allows very fast startup from the external
crystal, combined with low power consumption. In extended standby mode, both the main oscillator and the
asynchronous timer continue to run. In each power save, standby or extended standby mode, the low power mode of the
internal 8MHz oscillator allows very fast startup time combined with very low power consumption.
To further reduce power consumption, the peripheral clock to each individual peripheral can optionally be stopped in
active mode and idle sleep mode and low power mode of the internal 8MHz oscillator can be enabled.
Atmel offers a free QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR
microcontrollers. The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program
flash memory can be reprogrammed in-system through the PDI. A boot loader running in the device can use any
interface to download the application program to the flash memory. The boot loader software in the boot flash section can
continue to run. By combining an 8/16-bit RISC CPU with in-system, self-programmable flash, the AVR XMEGA is a
powerful microcontroller family that provides a highly flexible and cost effective solution for many embedded applications.
All Atmel AVR XMEGA devices are supported with a full suite of program and system development tools, including C
compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.
XMEGA E5 [DATASHEET]
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5.
Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
http://www.atmel.com/avr.
5.1
Recommended reading
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XMEGA® E Manual
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XMEGA Application Notes
This device data sheet only contains part specific information with a short description of each peripheral and module. The
XMEGA E Manual describes the modules and peripherals in depth. The XMEGA application notes contain example code
and show applied use of the modules and peripherals.
All documentations are available from www.atmel.com/avr.
6.
Capacitive touch sensing
The Atmel® QTouch® library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR®
microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced
reporting of touch keys and includes Adjacent key suppression® (AKS®) technology for unambiguous detection of key
events. The QTouch library includes support for the QTouch and QMatrix acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch library for the AVR
Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the
touch sensing API’s to retrieve the channel information and determine the touch sensor states.
The Atmel QTouch library is FREE and downloadable from the Atmel website at the following location:
http://www.atmel.com/tools/QTOUCHLIBRARY.aspx. For implementation details and other information, refer to the
Atmel QTouch library user guide - also available for download from the Atmel website.
XMEGA E5 [DATASHEET]
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7.
CPU
7.1
Features
z 8/16-bit, high-performance Atmel AVR RISC CPU
z 142 instructions
z Hardware multiplier
z 32x8-bit registers directly connected to the ALU
z Stack in RAM
z Stack pointer accessible in I/O memory space
z Direct addressing of up to 16MB of program memory and 16MB of data memory
z True 16/24-bit access to 16/24-bit I/O registers
z Efficient support for 8-, 16-, and 32-bit arithmetic
z Configuration change protection of system-critical features
7.2
7.3
Overview
All AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and perform all
calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the program in
the flash memory. Interrupt handling is described in a separate section, refer to “Interrupts and Programmable Multilevel
Interrupt Controller” on page 28.
Architectural Overview
In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories
and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to
be executed on every clock cycle. For details of all AVR instructions, refer to http://www.atmel.com/avr.
XMEGA E5 [DATASHEET]
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Figure 7-1. Block Diagram of the AVR CPU architecture.
The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a
register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is
updated to reflect information about the result of the operation.
The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purpose working registers all have
single clock cycle access time allowing single-cycle arithmetic logic unit (ALU) operation between registers or between a
register and an immediate. Six of the 32 registers can be used as three 16-bit address pointers for program and data
space addressing, enabling efficient address calculations.
The memory spaces are linear. The data memory space and the program memory space are two different memory
spaces.
The data memory space is divided into I/O registers, SRAM, and memory mapped EEPROM.
All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the I/O
memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3F.
The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be accessed as
data space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions.
The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five different
addressing modes supported in the AVR architecture. The first SRAM address is 0x2000.
Data addresses 0x1000 to 0x1FFF are reserved for EEPROM.
The program memory is divided in two sections, the application program section and the boot program section. Both
sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for self-
programming of the application flash memory must reside in the boot program section. The application section contains
an application table section with separate lock bits for write and read/write protection. The application table section can
be used for save storing of nonvolatile data in the program memory.
XMEGA E5 [DATASHEET]
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7.4
ALU - Arithmetic Logic Unit
The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a
register. Single-register operations can also be executed. The ALU operates in direct connection with all 32 general
purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register
and an immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the
status register is updated to reflect information about the result of the operation.
ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit
arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit arithmetic. The hardware
multiplier supports signed and unsigned multiplication and fractional format.
7.4.1 Hardware Multiplier
The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different
variations of signed and unsigned integer and fractional numbers:
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Multiplication of unsigned integers
Multiplication of signed integers
Multiplication of a signed integer with an unsigned integer
Multiplication of unsigned fractional numbers
Multiplication of signed fractional numbers
Multiplication of a signed fractional number with an unsigned one
A multiplication takes two CPU clock cycles.
7.5
Program Flow
After reset, the CPU starts to execute instructions from the lowest address in the flash program memory ‘0.’ The program
counter (PC) addresses the next instruction to be fetched.
Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole
address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general
data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After
reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the
I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be
accessed through the five different addressing modes supported in the AVR CPU.
7.6
Status Register
The status register (SREG) contains information about the result of the most recently executed arithmetic or logic
instruction. This information can be used for altering program flow in order to perform conditional operations. Note that
the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many
cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
The status register is not automatically stored when entering an interrupt routine nor restored when returning from an
interrupt. This must be handled by software.
The status register is accessible in the I/O memory space.
7.7
Stack and Stack Pointer
The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing
temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit
registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and
POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing
data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded
XMEGA E5 [DATASHEET]
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after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point
above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled.
During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be
two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program
memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices
with more than 128KB of program memory, the return address is three bytes, and hence the SP is
decremented/incremented by three. The return address is popped off the stack when returning from interrupts using the
RETI instruction, and from subroutine calls using the RET instruction.
The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one
when data is popped off the stack using the POP instruction.
To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts
for up to four instructions or until the next I/O memory write.
7.8
Register File
The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The register
file supports the following input/output schemes:
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One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient
address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash
program memory.
XMEGA E5 [DATASHEET]
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8.
Memories
8.1
Features
z Flash program memory
z One linear address space
z In-system programmable
z Self-programming and boot loader support
z Application section for application code
z Application table section for application code or data storage
z Boot section for application code or bootloader code
z Separate read/write protection lock bits for all sections
z Built in fast CRC check of a selectable flash program memory section
z Data memory
z One linear address space
z Single-cycle access from CPU
z SRAM
z EEPROM
z
Byte and page accessible
z
Memory mapped for direct load and store
z I/O memory
z
Configuration and status registers for all peripherals and modules
4 bit-accessible general purpose registers for global variables or flags
z
z Bus arbitration
z
Deterministic handling of priority between CPU, EDMA controller, and other bus masters
z Separate buses for SRAM, EEPROM and I/O memory
z
Simultaneous bus access for CPU and EDMA controller
z Production signature row memory for factory programmed data
z ID for each microcontroller device type
z Serial number for each device
z Calibration bytes for factory calibrated peripherals
z User signature row
z One flash page in size
z Can be read and written from software
z Content is kept after chip erase
8.2
Overview
The Atmel AVR architecture has two main memory spaces, the program memory and the data memory. Executable code
can reside only in the program memory, while data can be stored in the program memory and the data memory. The data
memory includes the internal SRAM, and EEPROM for nonvolatile data storage. All memory spaces are linear and
require no memory bank switching. Nonvolatile memory (NVM) spaces can be locked for further write and read/write
operations. This prevents unrestricted access to the application software.
A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can
only be written by an external programmer.
The available memory size configurations are shown in “Ordering Information” on page 2”. In addition, each device has a
Flash memory signature row for calibration data, device identification, serial number etc.
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8.3
Flash Program Memory
The Atmel® AVR® XMEGA® devices contain on-chip, in-system reprogrammable flash memory for program storage. The
flash memory can be accessed for read and write from an external programmer through the PDI or from application
software running in the device.
All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized
in two main sections, the application section and the boot loader section. The sizes of the different sections are fixed, but
device-dependent. These two sections have separate lock bits, and can have different levels of protection. The store
program memory (SPM) instruction, which is used to write to the flash from the application software, will only operate
when executed from the boot loader section.
The application section contains an application table section with separate lock settings. This enables safe storage of
nonvolatile data in the program memory.
Figure 8-1. Flash Program Memory (Hexadecimal address).
Word Address
ATxmega32E5
0
ATxmega16E5
0
ATxmega8E5
0
Application Section
(32K/16K/8K)
...
37FF
3800
3FFF
4000
47FF
/
/
/
/
/
17FF
1800
1FFF
2000
27FF
/
/
/
/
/
BFF
C00
Application Table Section
(4K/4K/2K)
FFF
1000
13FF
Boot Section
(4K/4K/2K)
8.3.1 Application Section
The Application section is the section of the flash that is used for storing the executable application code. The protection
level for the application section can be selected by the boot lock bits for this section. The application section can not store
any boot loader code since the SPM instruction cannot be executed from the application section.
8.3.2 Application Table Section
The application table section is a part of the application section of the flash memory that can be used for storing data.
The size is identical to the boot loader section. The protection level for the application table section can be selected by
the boot lock bits for this section. The possibilities for different protection levels on the application section and the
application table section enable safe parameter storage in the program memory. If this section is not used for data,
application code can reside here.
8.3.3 Boot Loader Section
While the application section is used for storing the application code, the boot loader software must be located in the boot
loader section because the SPM instruction can only initiate programming when executing from this section. When
programming, the CPU is halted, waiting for the flash operation to complete. The SPM instruction can access the entire
flash, including the boot loader section itself. The protection level for the boot loader section can be selected by the boot
loader lock bits. If this section is not used for boot loader software, application code can be stored here.
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8.3.4 Production Signature Row
The production signature row is a separate memory section for factory programmed data. It contains calibration data for
functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the
corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to
the corresponding peripheral registers from software. For details on calibration conditions, refer to “Electrical
Characteristics” on page 72.
The production signature row also contains an ID that identifies each microcontroller device type and a serial number for
each manufactured device. The serial number consists of the production lot number, wafer number, and wafer
coordinates for the device. The device ID for the available devices is shown in Table 8-1.
The production signature row cannot be written or erased, but it can be read from application software and external
programmers.
Table 8-1. Device ID bytes for Atmel AVR XMEGA E5 devices.
Device
Device ID bytes
Byte 1
Byte 2
4C
Byte 0
1E
ATxmega32E5
ATxmega16E5
ATxmega8E5
95
94
93
45
1E
41
1E
8.3.5 User Signature Row
The user signature row is a separate memory section that is fully accessible (read and write) from application software
and external programmers. It is one flash page in size, and is meant for static user parameter storage, such as calibration
data, custom serial number, identification numbers, random number seeds, etc. This section is not erased by chip erase
commands that erase the flash, and requires a dedicated erase command. This ensures parameter storage during
multiple program/erase operations and on-chip debug sessions.
8.4
Fuses and Lock bits
The fuses are used to configure important system functions, and can only be written from an external programmer. The
application software can read the fuses. The fuses are used to configure reset sources such as brownout detector and
watchdog, startup configuration, etc.
The lock bits are used to set protection levels for the different flash sections (i.e., if read and/or write access should be
blocked). Lock bits can be written by external programmers and application software, but only to stricter protection levels.
Chip erase is the only way to erase the lock bits. To ensure that flash contents are protected even during chip erase, the
lock bits are erased after the rest of the flash memory has been erased.
An un-programmed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value zero.
Both fuses and lock bits are reprogrammable like the flash program memory.
8.5
Data Memory
The data memory contains the I/O memory, internal SRAM and EEPROM. The data memory is organized as one
continuous memory section, see Table 8-2 on page 15. To simplify development, I/O Memory, EEPROM and SRAM will
always have the same start addresses for all XMEGA devices.
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Figure 8-2. Data Memory Map (Hexadecimal Value)
Byte Address
ATxmega32E5
Byte Address
ATxmega16E5
Byte Address
ATxmega8E5
0
0
0
I/O Registers (4K)
I/O Registers (4K)
I/O Registers (4K)
FFF
1000
13FF
FFF
1000
11FF
FFF
1000
11FF
EEPROM (1K)
RESERVED
EEPROM (512B)
RESERVED
EEPROM (512B)
RESERVED
2000
2FFF
2000
27FF
2000
27FF
Internal SRAM (4K)
Internal SRAM (2K)
Internal SRAM (2K)
8.6
8.7
EEPROM
Atmel AVR XMEGA E5 devices have EEPROM for nonvolatile data storage. It is memory mapped and accessed in
normal data space. The EEPROM supports both byte and page access. EEPROM allows highly efficient EEPROM
reading and EEPROM buffer loading. When doing this, EEPROM is accessible using load and store instructions.
EEPROM will always start at hexadecimal address 0x1000.
I/O Memory
The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O
memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions,
which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT
instructions can address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 - 0x1F,
single-cycle instructions for manipulation and checking of individual bits are available.
The I/O memory address for all peripherals and modules in XMEGA E5 is shown in the “Peripheral Module Address Map”
on page 62.
8.7.1 General Purpose I/O Registers
The lowest 4 I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for
storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
8.8
8.9
Data Memory and Bus Arbitration
Since the data memory is organized as three separate sets of memories, the different bus masters (CPU, EDMA
controller read and EDMA controller write, etc.) can access different memory sections at the same time.
Memory Timing
Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from
SRAM takes two cycles. For burst read (EDMA), new data are available every cycle. EEPROM page load (write) takes
one cycle, and three cycles are required for read. For burst read, new data are available every second cycle. Refer to the
instruction summary for more details on instructions and instruction timing.
8.10 Device ID and Revision
Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A
separate register contains the revision number of the device.
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8.11 I/O Memory Protection
Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the
I/O register related to the clock system, the event system, and the waveform extensions. As long as the lock is enabled,
all related I/O registers are locked and they cannot be written from the application software. The lock registers
themselves are protected by the configuration change protection mechanism.
8.12 Flash and EEPROM Page Size
The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the
flash and byte accessible for the EEPROM.
Table 8-2 shows the Flash Program Memory organization and Program Counter (PC) size. Flash write and erase
operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash access the
Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) give the page number and the
least significant address bits (FWORD) give the word in the page.
Table 8-2. Number of words and pages in the flash.
Devices
PC size
Flash size
Page Size
FWORD
FPAGE
Application
Boot
No of
No of
pages
bits
bytes
words
Size
Size
pages
256
128
64
ATxmega32E5
ATxmega16E5
ATxmega8E5
15
14
13
32K+4K
16K+4K
8K+2K
64
64
64
Z[6:0]
Z[6:0]
Z[6:0]
Z[14:7]
Z[13:7]
Z[12:7]
32K
16K
8K
4K
4K
2K
32
32
16
Table 8-3 shows EEPROM memory organization for the Atmel AVR XMEGA E5 devices. EEPROM write and erase
operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at a time. For
EEPROM access the NVM address register (ADDR[m:n]) is used for addressing. The most significant bits in the address
(E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the page.
Table 8-3. Number of words and pages in the EEPROM.
Devices
EEPROM
Page Size
E2BYTE
E2PAGE
No of Pages
Size
1K
bytes
32
ATxmega32E5
ATxmega16E5
ATxmega8E5
ADDR[4:0]
ADDR[10:5]
ADDR[10:5]
ADDR[10:5]
32
16
16
512Bytes
512Bytes
32
ADDR[4:0]
ADDR[4:0]
32
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9.
EDMA – Enhanced DMA Controller
9.1
Features
z The EDMA Controller allows data transfers with minimal CPU intervention
z from data memory to data memory
z from data memory to peripheral
z from peripheral to data memory
z from peripheral to peripheral
z Four peripheral EDMA channels with separate:
z transfer triggers
z interrupt vectors
z addressing modes
z data matching
z Two peripheral channels can be combined to one standard channel with separate:
z transfer triggers
z interrupt vectors
z addressing modes
z data search
z Programmable channel priority
z From 1byte to 128KB of data in a single transaction
z Up to 64K block transfer with repeat
z 1 or 2 bytes burst transfers
z Multiple addressing modes
z Static
z Increment
z Optional reload of source and destination address at the end of each
z Burst
z Block
z Transaction
z Optional Interrupt on end of transaction
z Optional connection to CRC Generator module for CRC on EDMA data
9.2
Overview
The four-channel enhanced direct memory access (EDMA) controller can transfer data between memories and
peripherals, and thus offload these tasks from the CPU. It enables high data transfer rates with minimum CPU
intervention, and frees up CPU time. The four EDMA channels enable up to four independent and parallel transfers.
The EDMA controller can move data between SRAM and peripherals, between SRAM locations and directly between
peripheral registers. With access to all peripherals, the EDMA controller can handle automatic transfer of data to/from
communication modules. The EDMA controller can also read from EEPROM memory.
Data transfers are done in continuous bursts of 1 or 2 bytes. They build block transfers of configurable size from 1 byte to
64KB. Repeat option can be used to repeat once each block transfer for single transactions up to 128KB. Source and
destination addressing can be static or incremental. Automatic reload of source and/or destination addresses can be
done after each burst or block transfer, or when a transaction is complete. Application software, peripherals, and events
can trigger EDMA transfers.
The four EDMA channels have individual configuration and control settings. This includes source, destination, transfer
triggers, and transaction sizes. They have individual interrupt settings. Interrupt requests can be generated when a
transaction is complete or when the EDMA controller detects an error on an EDMA channel.
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To enable flexibility in transfers, channels can be interlinked so that the second takes over the transfer when the first is
finished.
The EDMA controller supports extended features such as double buffering, data match for peripherals and data search
for SRAM or EEPROM.
The EDMA controller supports two types of channel. Each channel type can be selected individually.
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10. Event System
10.1 Features
z System for direct peripheral-to-peripheral communication and signaling
z Peripherals can directly send, receive, and react to peripheral events
z CPU and EDMA controller independent operation
z 100% predictable signal timing
z Short and guaranteed response time
z Synchronous and asynchronous event routing
z Eight event channels for up to eight different and parallel signal routing and configurations
z Events can be sent and/or used by most peripherals, clock system, and software
z Additional functions include
z Quadrature decoder with rotary filtering
z Digital filtering of I/O pin state with configurable filter
z Simultaneous synchronous and asynchronous events provided to peripheral
z Works in all sleep modes
10.2 Overview
The event system enables direct peripheral-to-peripheral communication and signaling. It allows a change in one
peripheral’s state to automatically trigger actions in other peripherals. It is designed to provide a predictable system for
short and predictable response times between peripherals. It allows for autonomous peripheral control and interaction
without the use of interrupts, CPU, or EDMA controller resources, and is thus a powerful tool for reducing the complexity,
size and execution time of application code. It allows for synchronized timing of actions in several peripheral modules.
The event system enables also asynchronous event routing for instant actions in peripherals.
A change in a peripheral’s state is referred to as an event, and usually corresponds to the peripheral’s interrupt
conditions. Events can be directly passed to other peripherals using a dedicated routing network called the event routing
network. How events are routed and used by the peripherals is configured in software.
Figure 10-1 shows a basic diagram of all connected peripherals. The event system can directly connect together analog
and digital converters, analog comparators, I/O port pins, the real-time counter, timer/counters, IR communication
module (IRCOM) and XMEGA Custom Logic (programmable logic) block (XCL). It can also be used to trigger EDMA
transactions (EDMA controller). Events can also be generated from software and peripheral clock.
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Figure 10-1. Event system overview and connected peripherals.
CPU /
Software
EDMA
Controller
Event Routing Network
clkPER
Prescaler
ADC
AC
Real Time
Counter
Event
System
Controller
Timer /
Counters
DAC
XMEGA
Custom Logic
IRCOM
Port Pins
The event routing network consists of eight software-configurable multiplexers that control how events are routed and
used. These are called event channels, and allow up to eight parallel event configurations and routing. The maximum
routing latency of an external event is two peripheral clock cycles due to re-synchronization, but several peripherals can
directly use the asynchronous event without any clock delay. The event system works in all power sleep modes, but only
asynchronous events can be routed in sleep modes where the system clock is not available.
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11. System Clock and Clock options
11.1 Features
z Fast start-up time
z Safe run-time clock switching
z Internal Oscillators:
z 32MHz run-time calibrated and tuneable oscillator
z 8MHz calibrated oscillator with 2MHz output option and fast start-up
z 32.768kHz calibrated oscillator
z 32kHz Ultra Low Power (ULP) oscillator with 1kHz output
z External clock options
z 0.4 - 16MHz Crystal Oscillator
z 32kHz crystal oscillator with digital correction
z External clock input in selectable pin location
z PLL with 20 - 128MHz output frequency
z Internal and external clock options and 1 to 31x multiplication
z Lock detector
z Clock Prescalers with 1x to 2048x division
z Fast peripheral clocks running at 2 and 4 times the CPU clock frequency
z Automatic Run-Time Calibration of the 32MHz internal oscillator
z External oscillator and PLL lock failure detection with optional non maskable interrupt
11.2 Overview
Atmel AVR XMEGA E5 devices have a flexible clock system supporting a large number of clock sources. It incorporates
both accurate internal oscillators and external crystal oscillator and resonator support. A high-frequency phase locked
loop (PLL) and clock prescalers can be used to generate a wide range of clock frequencies. A calibration feature (DFLL)
is available, and can be used for automatic run-time calibration of the 32MHz internal oscillator to remove frequency drift
over voltage and temperature. An oscillator failure monitor can be enabled to issue a nonmaskable interrupt and switch
to the internal oscillator if the external oscillator or PLL fails.
When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device
will always start up running from the 2MHz output of the 8MHz internal oscillator. During normal operation, the system
clock source and prescalers can be changed from software at any time.
Figure 11-1 presents the principal clock system in the XMEGA E5 family of devices. Not all of the clocks need to be
active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and power reduction
registers, as described in “Power Management and Sleep Modes” on page 23.
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Figure 11-1. The clock system, clock sources and clock distribution.
Real Time
Peripherals
Counter
Non-Volatile
Memory
RAM
AVR CPU
clkPER
clkCPU
clkPER2
clkPER4
clkRTC
System Clock Prescalers
clkSYS
Brown-out
Detector
Watchdog
Timer
System Clock Multiplexer
(SCLKSEL)
RTCSRC
PLL
PLLSRC
XOSCSEL
32 kHz
Int. ULP
32.768 kHz
Int. OSC
32.768 kHz
TOSC
0.4 – 16 MHz
XTAL
32 MHz
Int. Osc
8 MHz
Int. Osc
11.3 Clock Sources
The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the clock
sources can be directly enabled and disabled from software, while others are automatically enabled or disabled,
depending on peripheral settings. After reset, the device starts up running from the 2MHz output of the 8MHz internal
oscillator. The other clock sources, DFLL and PLL, are turned off by default.
The internal oscillators do not require any external components to run. For details on characteristics and accuracy of the
internal oscillators, refer to the device datasheet.
11.3.1 32kHz Ultra Low Power Internal Oscillator
This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low
power clock source, and it is not designed for high accuracy. The oscillator employs a built-in prescaler that provides a
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1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device.
This oscillator can be selected as the clock source for the RTC.
11.3.2 32.768kHz Calibrated Internal Oscillator
This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency
close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the
oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz
output.
11.3.3 32.768kHz Crystal Oscillator
A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low
frequency oscillator input circuit. A low power mode with reduced voltage swing on TOSC2 is available. This oscillator
can be used as a clock source for the system clock and RTC, and as the DFLL reference clock.
11.3.4 0.4 - 16MHz Crystal Oscillator
This oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4 - 16MHz.
11.3.5 8MHz Calibrated Internal Oscillator
The 8MHz calibrated internal oscillator is the default system clock source after reset. It is calibrated during production to
provide a default frequency close to its nominal frequency. The calibration register can also be written from software for
run-time calibration of the oscillator frequency. The oscillator employs a built-in prescaler, with 2MHz output. The default
output frequency at start-up and after reset is 2MHz. A low power mode option can be used to enable fast system wake-
up from power-save mode. In all other modes, the low power mode can be enabled to significantly reduce the power
consumption of the internal oscillator.
11.3.6 32MHz Run-time Calibrated Internal Oscillator
The 32MHz run-time calibrated internal oscillator is a high-frequency oscillator. It is calibrated during production to
provide a default frequency close to its nominal frequency. A digital frequency looked loop (DFLL) can be enabled for
automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator
accuracy. This oscillator can also be adjusted and calibrated to any frequency between 30MHz and 55MHz.
11.3.7 External Clock Sources
The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator.
XTAL1 or pin 4 of port C (PC4) can be used as input for an external clock signal. The TOSC1 and TOSC2 pins are
dedicated to driving a 32.768kHz crystal oscillator.
11.3.8 PLL with 1x-31x Multiplication Factor
The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a user-
selectable multiplication factor of from 1 to 31. In combination with the prescalers, this gives a wide range of output
frequencies from all clock sources.
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12. Power Management and Sleep Modes
12.1 Features
z Power management for adjusting power consumption and functions
z Five sleep modes
z Idle
z Power down
z Power save
z Standby
z Extended standby
z Power reduction register to disable clock and turn off unused peripherals in active and idle modes
12.2 Overview
Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.
This enables the Atmel AVR XMEGA microcontroller to stop unused modules to save power.
All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing application
code. When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the
device again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals
and all enabled reset sources can restore the microcontroller from sleep to active mode.
In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. When
this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. This
reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power
management than sleep modes alone.
12.3 Sleep Modes
Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. XMEGA
microcontrollers have five different sleep modes tuned to match the typical functional stages during application
execution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to wake the
device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. When an
enabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normal
program execution from the first instruction after the SLEEP instruction. If other, higher priority interrupts are pending
when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt
service routine for the wake-up interrupt is executed. After wake-up, the CPU is halted for four cycles before execution
starts.
The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device will
reset, start up, and execute from the reset vector.
12.3.1 Idle Mode
In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed), but
all peripherals, including the interrupt controller, event system and EDMA controller are kept running. Any enabled
interrupt will wake the device.
12.3.2 Power-down Mode
In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of
asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the two-
wire interface address match interrupt and asynchronous port interrupts.
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12.3.3 Power-save Mode
Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep
running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt. Low
power mode option of 8MHz internal oscillator enables instant oscillator wake-up time. This reduces the MCU wake-up
time or enables the MCU wake-up from UART bus.
12.3.4 Standby Mode
Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running
while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time. The low power option of 8MHz
internal oscillator can be enabled to further reduce the power consumption.
12.3.5 Extended Standby Mode
Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are
kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time. The low power option of
8MHz internal oscillator can be enabled to further reduce the power consumption.
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13. System Control and Reset
13.1 Features
z Reset the microcontroller and set it to initial state when a reset source goes active
z Multiple reset sources that cover different situations
z Power-on reset
z External reset
z Watchdog reset
z Brownout reset
z PDI reset
z Software reset
z Asynchronous operation
z No running system clock in the device is required for reset
z Reset status register for reading the reset source from the application code
13.2 Overview
The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where
operation should not start or continue, such as when the microcontroller operates below its power supply rating. If a reset
source goes active, the device enters and is kept in reset until all reset sources have released their reset. The I/O pins
are immediately tri-stated. The program counter is set to the reset vector location, and all I/O registers are set to their
initial values. The SRAM content is kept. However, if the device accesses the SRAM when a reset occurs, the content of
the accessed location can not be guaranteed.
After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts
running from the reset vector address. By default, this is the lowest program memory address, 0, but it is possible to
move the reset vector to the lowest address in the boot section.
The reset functionality is asynchronous, and so no running system clock is required to reset the device. The software
reset feature makes it possible to issue a controlled system reset from the user software.
The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and shows
which sources have issued a reset since the last power-on.
13.3 Reset Sequence
A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is
active. When all reset requests are released, the device will go through three stages before the device starts running
again:
z
z
z
Reset counter delay
Oscillator startup
Oscillator calibration
If another reset requests occurs during this process, the reset sequence will start over again.
13.4 Reset Sources
13.4.1 Power-on Reset
A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the VCC rises and
reaches the POR threshold voltage (VPOT), and this will start the reset sequence.
The POR is also activated to power down the device properly when the VCC falls and drops below the VPOT level. The
VPOT level is higher for falling VCC than for rising VCC. Consult the datasheet for POR characteristics data.
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13.4.2 Brownout Detection
The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed,
programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip
erase and when the PDI is enabled.
13.4.3 External Reset
The external reset circuit is connected to the external RESET pin. The external reset will trigger when the RESET pin is
driven below the RESET pin threshold voltage, VRST, for longer than the minimum pulse period, tEXT. The reset will be
held as long as the pin is kept low. The RESET pin includes an internal pull-up resistor.
13.4.4 Watchdog Reset
The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from
the software within a programmable timeout period, a watchdog reset will be given. The watchdog reset is active for one
to two clock cycles of the 2MHz internal oscillator. For more details see “WDT – Watchdog Timer” on page 27.
13.4.5 Software Reset
The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset
control register. The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to execute any
instruction from when a software reset is requested until it is issued.
13.4.6 Program and Debug Interface Reset
The program and debug interface reset contains a separate reset source that is used to reset the device during external
programming and debugging. This reset source is accessible only from external debuggers and programmers.
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14. WDT – Watchdog Timer
14.1 Features
z Issues a device reset if the timer is not reset before its timeout period
z Asynchronous operation from dedicated oscillator
z 1kHz output of the 32kHz ultra low power oscillator
z 11 selectable timeout periods, from 8ms to 8s
z Two operation modes:
z Normal mode
z Window mode
z Configuration lock to prevent unwanted changes
14.2 Overview
The watchdog timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover
from error situations such as runaway or deadlocked code. The WDT is a timer, configured to a predefined timeout
period, and is constantly running when enabled. If the WDT is not reset within the timeout period, it will issue a
microcontroller reset. The WDT is reset by executing the WDR (watchdog timer reset) instruction from the application
code.
The window mode makes it possible to define a time slot or window inside the total timeout period during which WDT
must be reset. If the WDT is reset outside this window, either too early or too late, a system reset will be issued.
Compared to the normal mode, this can also catch situations where a code error causes constant WDR execution.
The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a CPU-independent clock
source, and will continue to operate to issue a system reset even if the main clocks fail.
The configuration change protection mechanism ensures that the WDT settings cannot be changed by accident. For
increased safety, a fuse for locking the WDT settings is also available.
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15. Interrupts and Programmable Multilevel Interrupt Controller
15.1 Features
z Short and predictable interrupt response time
z Separate interrupt configuration and vector address for each interrupt
z Programmable multilevel interrupt controller
z Interrupt prioritizing according to level and vector address
z Three selectable interrupt levels for all interrupts: low, medium and high
z Selectable, round-robin priority scheme within low-level interrupts
z Non-maskable interrupts for critical functions
z Interrupt vectors optionally placed in the application section or the boot loader section
15.2 Overview
Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have
one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it
will generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt
controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged
by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed.
All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are
prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level
interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the
interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest
interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are
serviced within a certain amount of time.
Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions.
15.3 Interrupt vectors
The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts in
each peripheral. The base addresses for the Atmel AVR XMEGA E5 devices are shown in Table 15-1. Offset addresses
for each interrupt available in the peripheral are described for each peripheral in the XMEGA AU manual. For peripherals
or modules that have only one interrupt, the interrupt vector is shown in Table 15-1. The program address is the word
address.
Table 15-1. Peripheral module address map
Program address
(base address)
0x0000
Source
Interrupt Description
RESET
0x0002
OSCF_INT_vect
PORTR_INT_vect
EDMA_INT_base
RTC_INT_base
PORTC_INT_vect
TWIC_INT_base
Crystal oscillator failure and PLL lock failure interrupt vector (NMI)
Port R Interrupt vector
0x0004
0x0006
EDMA Controller Interrupt base
0x000E
Real time counter interrupt base
0x0012
Port C interrupt vector
0x0014
Two-wire interface on Port C interrupt base
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Program address
(base address)
Source
Interrupt Description
0x0018
0x0024
0x002C
0x002E
0x0034
0x0038
0x003C
0x003E
0x0044
0x0046
0x0048
0x0050
TCC4_INT_base
TCC5_INT_base
SPIC_INT_vect
USARTC0_INT_base
NVM_INT_base
XCL_INT_base
PORTA_INT_vect
ACA_INT_base
ADCA_INT_base
PORTD_INT_vect
TCD5_INT_base
USARTD0_INT_base
Timer/counter 4 on port C interrupt base
Timer/counter 5 on port C interrupt base
SPI on port C interrupt vector
USART 0 on port C interrupt base
Non-Volatile Memory interrupt base
XCL (programmable logic) module interrupt base
Port A interrupt vector
Analog comparator on Port A interrupt base
Analog to digital converter on Port A interrupt base
Port D interrupt vector
Timer/counter 5 on port D interrupt base
USART 0 on port D interrupt base
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16. I/O Ports
16.1 Features
z 26 general purpose input and output pins with individual configuration
z Output driver with configurable driver and pull settings:
z Totem-pole
z Wired-AND
z Wired-OR
z Bus-keeper
z Inverted I/O
z Input with asynchronous sensing with interrupts and events
z Sense both edges
z Sense rising edges
z Sense falling edges
z Sense low level
z Optional pull-up and pull-down resistor on input and Wired-OR/AND configurations
z Optional slew rate control per I/O port
z Asynchronous pin change sensing that can wake the device from all sleep modes
z One port interrupt with pin masking per I/O port
z Efficient and safe access to port pins
z Hardware read-modify-write through dedicated toggle/clear/set registers
z Configuration of multiple pins in a single operation
z Mapping of port registers into bit-accessible I/O memory space
z Peripheral clocks output on port pin
z Real-time counter clock output to port pin
z Event channels can be output on port pin
z Remapping of digital peripheral pin functions
z Selectable USART and timer/counters input/output pin locations
z Selectable Analog Comparator output pin locations
16.2 Overview
One port consists of up to 8 pins ranging from pin 0 to 7. Each port pin can be configured as input or output with
configurable driver and pull settings. They also implement asynchronous input sensing with interrupt and events for
selectable pin change conditions.
Asynchronous pin-change sensing means that a pin change can wake the device from all sleep modes, including the
modes where no clocks are running.
All functions are individual and configurable per pin, but several pins can be configured in a single operation. The pins
have hardware read-modify-write (RMW) functionality for safe and correct change of drive value and/or pull resistor
configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other
pin.
The port pin configuration also controls input and output selection of other device functions. It is possible to have both the
peripheral clock and the real-time clock output to a port pin, and available for external use. The same applies to events
from the event system that can be used to synchronize and control external functions. Other digital peripherals, such as
USART, timer/counters, and analog comparator output can be remapped to selectable pin locations in order to optimize
pin-out versus application needs.
The notations of the ports are PORTA, PORTC, PORTD, and PORTR.
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16.3 Output Driver
All port pins (Pxn) have programmable output configuration. The port pins also have configurable slew rate limitation to
reduce electromagnetic emission.
16.3.1 Push-pull
Figure 16-1. I/O configuration - Totem-pole.
DIRxn
OUTxn
INxn
Pxn
16.3.2 Pull-down
Figure 16-2. I/O configuration - Totem-pole with pull-down (on input).
DIRxn
OUTxn
INxn
Pxn
16.3.3 Pull-up
Figure 16-3. I/O configuration - Totem-pole with pull-up (on input).
DIRxn
OUTxn
INxn
Pxn
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16.3.4 Bus-keeper
The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level
was ‘1’, and pull-down if the last level was ‘0’.
Figure 16-4. I/O configuration - Totem-pole with bus-keeper.
DIRxn
OUTxn
INxn
Pxn
16.3.5 Others
Figure 16-5. Output configuration - Wired-OR with optional pull-down.
OUTxn
Pxn
INxn
Figure 16-6. I/O configuration - Wired-AND with optional pull-up.
INxn
Pxn
OUTxn
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16.4 Input sensing
Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is
shown in Figure 16-7.
Figure 16-7. Input sensing system overview.
Asynchronous sensing
EDGE
DETECT
Interrupt
Control
IRQ
Synchronous sensing
Pxn
Synchronizer
INn
EDGE
DETECT
Synchronous
Events
D
Q
D
Q
R
R
INVERTED I/O
Asynchronous
Events
When a pin is configured with inverted I/O, the pin value is inverted before the input sensing.
16.5 Alternate Port Functions
Most port pins have alternate pin functions in addition to being a general purpose I/O pin. When an alternate function is
enabled, it might override the normal port pin function or pin value. This happens when other peripherals that require pins
are enabled or configured to use pins. If and how a peripheral will override and use pins is described in the section for
that peripheral. “Pinout and Pin Functions” on page 58 shows which modules on peripherals that enable alternate
functions on a pin, and which alternate functions that are available on a pin.
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17. Timer Counter type 4 and 5
17.1 Features
z Three 16-bit timer/counter
z One timer/counter of type 4
z Two timer/counter of type 5
z 32-bit timer/counter support by cascading two timer/counters
z Up to four compare or capture (CC) channels
z Four CC channels for timer/counters of type 4
z Two CC channels for timer/counters of type 5
z Double buffered timer period setting
z Double buffered CC channels
z Waveform generation modes:
z Frequency generation
z Single-slope pulse width modulation
z Dual-slope pulse width modulation
z Input capture:
z Input capture with noise cancelling
z Frequency capture
z Pulse width capture
z 32-bit input capture
z Timer overflow and error interrupts/events
z One compare match or input capture interrupt/event per CC channel
z Can be used with event system for:
z Quadrature decoding
z Count and direction control
z Input capture
z Can be used with EDMA and to trigger EDMA transactions
z High-resolution extension
z Increases frequency and waveform resolution by 4x (2-bit) or 8x (3-bit)
z Waveform extension
z Low- and high-side output with programmable dead-time insertion (DTI)
z Fault extention
z Event controlled fault protection for safe disabling of drivers
17.2 Overview
Atmel AVR XMEGA devices have a set of flexible, 16-bit timer/counters (TC). Their capabilities include accurate program
execution timing, frequency and waveform generation, and input capture with time and frequency measurement of digital
signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit input capture.
A timer/counter consists of a base counter and a set of compare or capture (CC) channels. The base counter can be
used to count clock cycles or events. It has direction control and period setting that can be used for timing. The CC
channels can be used together with the base counter to do compare match control, frequency generation, and pulse
width modulation (PWM) generation, as well as various input capture operations. A timer/counter can be configured for
either capture, compare, or capture and compare function.
A timer/counter can be clocked and timed from the peripheral clock with optional prescaling, or from the event system.
The event system can also be used for direction control, input capture trigger or to synchronize operations.
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There are two differences between timer/counter type 4 and type 5. Timer/counter 4 has four CC channels, and
timer/counter 5 has two CC channels. Both timer/counter 4 and 5 can be set in 8-bit mode, allowing the application to
double the number of compare and capture channels that then get 8-bit resolution.
Some timer/counters have extensions that enable more specialized waveform generation. The waveform extension
(WeX) is intended for motor control, ballast, LED, H-bridge, power converters, and other types of power control
applications. It enables more customized waveform output distribution, and low- and high-side channel output with
optional dead-time insertion. It can also generate a synchronized bit pattern across the port pins. The high-resolution (hi-
res) extension can increase the waveform resolution by four or eight times by using an internal clock source four times
faster than the peripheral clock. The fault extension (FAULT) enables fault protection for safe and deterministic handling,
disabling and/or shut down of external drivers.
A block diagram of the 16-bit timer/counter with extensions and closely related peripheral modules (in grey) is shown in
Figure 17-1.
Figure 17-1. 16-bit timer/counter and closely related peripherals.
Timer/Counter
Base Counter
Prescaler
clkPER
Timer Period
Counter
Control Logic
Event
System
clkPER4
Compare/Capture Channel D
Compare/Capture Channel C
Compare/Capture Channel B
Compare/Capture Channel A
WeX
Capture
Comparator
Control
Waveform
Generation
Buffer
PORTC has one timer/counter 4 and one timer/counter 5. PORTD has one timer/counter 5. Notation of these are TCC4
(timer/counter C4), TCC5 and TCD5 respectively.
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18. WeX – Waveform Extension
18.1 Features
z Module for more customized and advanced waveform generation
z Optimized for various type of motor, ballast, and power stage control
z Output matrix for timer/counter waveform output distribution
z Configurable distribution of compare channel output across port pins
z Redistribution of dead-time insertion resource between TC4 and TC5.
z Four dead-time insertion (DTI) units, each with
z Complementary high and low side with non overlapping outputs
z Separate dead-time setting for high and low side
z 8-bit resolution
z Four swap (SWAP) units
z Separate port pair or low high side drivers swap
z Double buffered swap feature
z Pattern generation creating synchronized bit pattern across the port pins
z Double buffered pattern generation
18.2 Overview
The waveform extension (WEX) provides extra functions to the timer/counter in waveform generation (WG) modes. It is
primarily intended for motor control, ballast, LED, H-bridge, power converters, and other types of power control
applications. The WEX consist of five independent and successive units, as shown in Figure 18-1.
Figure 18-1. Waveform extension and closely related peripherals.
WEX
Px0
DTI1
DTI1
DTI1
DTI1
SWAP1
SWAP1
SWAP1
SWAP1
Px1
Px2
Px3
Px4
Px5
Px6
Px7
Fault
Unit 4
T/C4
T/C5
Fault
Unit 5
The output matrix (OTMX) can distribute and route out the waveform outputs from timer/counter 4 and 5 across the port
pins in different configurations, each optimized for different application types. The dead time insertion (DTI) unit splits the
four lower OTMX outputs into a two non-overlapping signals, the non-inverted low side (LS) and inverted high side (HS)
of the waveform output with optional dead-time insertion between LS and HS switching.
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The swap (SWAP) unit can swap the LS and HS pin position. This can be used for fast decay motor control. The pattern
generation unit generates synchronized output waveform with constant logic level. This can be used for easy stepper
motor and full bridge control.
The output override disable unit can disable the waveform output on selectable port pins to optimize the pins usage. This
is to free the pins for other functional use, when the application does not need the waveform output spread across all the
port pins as they can be selected by the OTMX configurations.
The waveform extension is available for TCC4 and TCC5. The notation of this is WEXC.
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19. Hi-Res – High Resolution Extension
19.1 Features
z Increases waveform generator resolution up to 8x (three bits)
z Supports frequency, single-slope PWM, and dual-slope PWM generation
z Supports the WeX when this is used for the same timer/counter
19.2 Overview
The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a
timer/counter by four or eight. It can be used for a timer/counter doing frequency, single-slope PWM, or dual-slope PWM
generation. It can also be used with the WeX if this is used for the same timer/counter.
The hi-res extension uses the peripheral 4x clock (ClkPER4). The system clock prescalers must be configured so the
peripheral 4x clock frequency is four times higher than the peripheral and CPU clock frequency when the hi-res extension
is enabled.
There is one hi-res extension that can be enabled for timer/counters pair on PORTC. The notation of this is HIRESC.
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20. Fault Extension
20.1 Features
z Connected to timer/counter output and waveform extension input
z Event controlled fault protection for instant and predictable fault triggering
z Fast, synchronous and asynchronous fault triggering
z Flexible configuration with multiple fault sources
z Recoverable fault modes
z Restart or halt the timer/counter on fault condition
z Timer/counter input capture on fault condition
z Waveform output active time reduction on fault condition
z Non-recoverable faults
z Waveform output is forced to a pre-configured safe state on fault condition
z Optional fuse output value configuration defining the output state during system reset
z Flexible fault filter selections
z Digital filter to prevent false triggers from I/O pin glitches
z Fault blanking to prevent false triggers during commutation
z Fault input qualification to filter the fault input during the inactive output compare states
20.2 Overview
The fault extension enables event controlled fault protection by acting directly on the generated waveforms from
timer/counter compare outputs. It can be used to trigger two types of faults with the following actions:
z
Recoverable faults: the timer/counter can be restarted or halted as long as the fault condition is preset. The
compare output pulse active time can be reduced as long as the fault condition is preset. This is typically used for
current sensing regulation, zero crossing re-triggering, demagnetization re-triggering, and so on.
z
Non-recoverable faults: the compare outputs are forced to a safe and pre-configured values that are safe for the
application. This is typically used for instant and predictable shut down and to disable the high current or voltage
drivers.
Events are used to trigger a fault condition. One or several simultaneous events are supported, both synchronously or
asynchronously. By default, the fault extension supports asynchronous event operation, ensuring predictable and instant
fault reaction, including system power modes where the system clock is stopped.
By using the input blanking, the fault input qualification or digital filter option in event system, the fault sources can be
filtered to avoid false faults detection.
There are two fault extensions, one for each of the timer/counter 4 and timer/counter 5 on PORTC. The notation of these
are FAULTC4 and FAULTC5, respectively.
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21. RTC – 16-bit Real-Time Counter
21.1 Features
z 16-bit resolution
z Selectable clock source
z 32.768kHz external crystal
z External clock
z 32.768kHz internal oscillator
z 32kHz internal ULP oscillator
z Programmable 10-bit clock prescaling
z One compare register
z One period register
z Clear counter on period overflow
z Optional interrupt/event on overflow and compare match
z Correction for external crystal oscillator frequency error down to ±0.5 ppm accuracy
21.2 Overview
The 16-bit real-time counter (RTC) is a counter that typically runs continuously, including in low power sleep modes, to
keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular intervals.
The reference clock is typically the 1.024kHz output from a high-accuracy crystal of 32.768kHz, and this is the
configuration most optimized for low power consumption. The faster 32.768kHz output can be selected if the RTC needs
a resolution higher than 1ms. The RTC can also be clocked from an external clock signal, the 32.768kHz internal
oscillator or the 32kHz internal ULP oscillator.
The RTC includes a 10-bit programmable prescaler that can scale down the reference clock before it reaches the
counter. A wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock source, the
maximum resolution is 30.5μs, and time-out periods can range up to 2000 seconds. With a resolution of 1s, the
maximum timeout period is more than 18 hours (65536 seconds). The RTC can give a compare interrupt and/or event
when the counter equals the compare register value, and an overflow interrupt and/or event when it equals the period
register value.
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Figure 21-1. Real-time counter overview.
External Clock
TOSC1
32.768 kHz Crystal
Osc
TOSC2
32.768 kHz Int. Osc
32 kHz int ULP
(DIV32)
RTCSRC
CALIB
PER
CNT
clkRTC
TOP/
=
=
Overflow
Hold Count
Correction
Counter
10-bit
prescaler
”match”/
Compare
COMP
The RTC also supports correction when operated using external 32.768 kHz crystal oscillator. An externally calibrated
value will be used for correction. The calibration can be done by measuring the default RTC frequency relative to a more
accurate clock input to the device as system clock. The RTC can be calibrated to an accuracy of ±0.5 PPM. The RTC
correction operation will either speed up (by skipping count) or slow down (adding extra cycles) the prescaler to account
for the crystal oscillator error.
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22. TWI – Two Wire Interface
22.1 Features
z One two-wire interface
z Phillips I2C compatible
z System Management Bus (SMBus) compatible
z Bus master and slave operation supported
z Slave operation
z Single bus master operation
z Bus master in multi-master bus environment
z Multi-master arbitration
z Bridge mode with independent and simultaneous master and slave operation
z Flexible slave address match functions
z 7-bit and general call address recognition in hardware
z 10-bit addressing supported
z Address mask register for dual address match or address range masking
z Optional software address recognition for unlimited number of addresses
z Slave can operate in all sleep modes, including power-down
z Slave address match can wake device from all sleep modes
z 100kHz, 400kHz and 1MHz bus frequency support
z Slew-rate limited output drivers
z Input filter for bus noise and spike suppression
z Support arbitration between start/repeated start and data bit (SMBus)
z Slave arbitration allows support for address resolve protocol (ARP) (SMBus)
z Supports SMBUS Layer 1 timeouts
z Configurable timeout values
z Independent timeout counters in master and slave (Bridge mode support)
22.2 Overview
The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I2C and System Management Bus
(SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each bus line.
A device connected to the bus must act as a master or a slave. One bus can have many slaves and one or several
masters that can take control of the bus.
The TWI module supports master and slave functionality. The master and slave functionality are separated from each
other, and can be enabled and operate simultaneously and separately. The master module supports multi-master bus
operation and arbitration. It contains the baud rate generator. Quick command and smart mode can be enabled to auto-
trigger operations and reduce software complexity. The master can support 100kHz, 400kHz and 1MHz bus frequency.
The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is
also supported. A dedicated address mask register can act as a second address match register or as a register for
address range masking. The slave continues to operate in all sleep modes, including power-down mode. This enables
the slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the address
matching to let this be handled in software instead. By using the bridge option, the slave can be mapped to different pin
locations. The master and slave can support 100kHz, 400kHz and 1MHz bus frequency.
The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors, collision,
and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave
modes.
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It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external
TWI bus driver. This can be used for applications where the device operates from a different VCC voltage than used by
the TWI bus.
It is also possible to enable the bridge mode. In this mode, the slave I/O pins are selected from an alternative port,
enabling independent and simultaneous master and slave operation.
PORTC has one TWI. Notation of this peripheral is TWIC. Alternative TWI Slave location in bridge mode is on PORTD.
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23. SPI – Serial Peripheral Interface
23.1 Features
z One SPI peripheral
z Full-duplex, three-wire synchronous data transfer
z Master or slave operation
z Lsb first or msb first data transfer
z Eight programmable bit rates
z Interrupt flag at the end of transmission
z Write collision flag to indicate data collision
z Wake up from idle sleep mode
z Double speed master mode
23.2 Overview
The Serial Peripheral Interface (SPI) is a high-speed, full duplex, synchronous data transfer interface using three or four
pins. It allows fast communication between an AVR XMEGA device and peripheral devices or between several
microcontrollers.
A device connected to the bus must act as a master or slave. The master initiates and controls all data transactions. The
interconnection between master and slave devices with SPI is shown in Figure 23-1. The system consists of two shift
registers and a clock generator. The SPI master initiates the communication by pulling the slave select (SS) signal low
for the desired slave. Master and slave prepare the data to be sent in their respective shift registers, and the master
generates the required clock pulses on the SCK line to interchange data. Data are always shifted from master to slave on
the master output, slave input (MOSI) line, and from slave to master on the master input, slave output (MISO) line. After
each data packet, the master can synchronize the slave by pulling the SS line high.
Figure 23-1. SPI master-slave interconnection
MASTER
SLAVE
Transmit Data Register
Transmit Data Register
(DATA)
(DATA)
msb
lsb
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
8-bit Shift Register
lsb
msb
8-bit Shift Register
SPI CLOCK
GENERATOR
Receive Buffer Register
Receive Buffer Register
Receive Data Register
(DATA)
Receive Data Register
(DATA)
By default, the SPI module is single buffered and transmit direction and double buffered in the receive direction. A byte
written to the transmit data register will be copied to the shift register when a full character has been received. When
receiving data, a received character must be read from the transmit data register before the third character has been
completely shifted in to avoid losing data. Optionally, buffer modes can be enabled. When used, one buffer is available
for transmitter and a double buffer for reception.
PORTC has one SPI. Notation of this is SPIC
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24. USART
24.1 Features
z Two identical USART peripherals
z Full-duplex or one-wire half-duplex operation
z Asynchronous or synchronous operation
z Synchronous clock rates up to 1/2 of the device clock frequency
z Asynchronous clock rates up to 1/8 of the device clock frequency
z Supports serial frames with:
z 5, 6, 7, 8, or 9 data bits
z Optionally even and odd parity bits
z 1 or 2 stop bits
z Fractional baud rate generator
z Can generate desired baud rate from any system clock frequency
z No need for external oscillator with certain frequencies
z Built-in error detection and correction schemes
z Odd or even parity generation and parity check
z Data overrun and framing error detection
z Noise filtering includes false start bit detection and digital low-pass filter
z Separate interrupts for
z Transmit complete
z Transmit data register empty
z Receive complete
z Multiprocessor communication mode
z Addressing scheme to address a specific devices on a multidevice bus
z Enable unaddressed devices to automatically ignore all frames
z System wake-up from Start bit
z Master SPI mode
z Double buffered operation
z Configurable data order
z Operation up to 1/2 of the peripheral clock frequency
z IRCOM module for IrDA compliant pulse modulation/demodulation
z One USART is connected to XMEGA Custom Logic (XCL) module:
z Extend serial frame length up to 256 bit by using the peripheral counter
z Modulate/demodulate data within the frame by using the glue logic outputs
24.2 Overview
The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible serial
communication module. The USART supports full-duplex with asynchronous and synchronous operation and single wire
half-duplex communication with asynchronous operation. The USART can be configured to operate in SPI master mode
and used for SPI communication.
Communication is frame based, and the frame format can be customized to support a wide range of standards. The
USART is buffered in both directions, enabling continued data transmission without any delay between frames. Separate
interrupts for receive and transmit complete enable fully interrupt driven communication. Frame error and buffer overflow
are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can
also be enabled.
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In one-wire configuration, the TxD pin is connected to the RxD pin internally, limiting the IO pins usage. If the receiver is
enabled when transmitting, it will receive what the transmitter is sending. This mode can be used for bit error detection.
The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART baud rates
from any system clock frequencies. This removes the need to use an external crystal oscillator with a specific frequency
to achieve a required baud rate. It also supports external clock input in synchronous slave operation.
An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and
demodulation for baud rates up to 115.2Kbps.
One USART can be connected to the XMEGA Custom Logic module (XCL). When used with the XCL, the data length
within an USART/SPI frame can be controlled by the peripheral counter (PEC) within the XCL. This enables configurable
frame length up to 256 bits. In addition, the TxD/RxD data can be encoded/decoded before the signal is fed into the
USART receiver, or after the signal is output from transmitter when the USART is connected to XCL LUT outputs.
When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and receive
buffers, shift registers, and baud rate generator enabled. The registers are used in both modes, but their functionality
differs for some control settings. Pin control and interrupt generation are identical in both modes.
PORTC and PORTD each has one USART. Notation of these peripherals are USARTC0 and USARTD0, respectively.
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25. IRCOM – IR Communication Module
25.1 Features
z Pulse modulation/demodulation for infrared communication
z IrDA compatible for baud rates up to 115.2Kbps
z Selectable pulse modulation scheme
z 3/16 of the baud rate period
z Fixed pulse period, 8-bit programmable
z Pulse modulation disabled
z Built-in filtering
z Can be connected to and used by any USART
25.2 Overview
Atmel AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates
up to 115.2Kbps. It can be connected to any USART to enable infrared pulse encoding/decoding for that USART.
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26. XCL – XMEGA Custom Logic Module
26.1 Features
z Two independent 8-bit timer/counter with:
z Period and compare channel for each timer/counter
z Input Capture for each timer
z Serial peripheral data length control for each timer
z Timeout support for each timer
z Timer underflow interrupt/event
z Compare match or input capture interrupt/event for each timer
z One 16-bit timer/counter by cascading two 8-bit timer/counters with:
z Period and compare channel
z Input capture
z Timeout support
z Timer underflow interrupt/event
z Compare match or input capture interrupt/event
z Programmable lookup table supporting multiple configurations:
z Two 2-input units
z One 3-input unit
z RS configuration
z Duplicate input with selectable delay on one input or output
z Connection to external I/O pins, event system or one selectable USART
z Combinatorial Logic Functions using programmable truth table:
z AND, NAND, OR, NOR, XOR, XNOR, NOT, MUX
z Sequential Logic Functions:
z D-Flip-Flop, D Latch, RS Latch
z Input sources:
z From external pins or the event system
z One input source includes selectable delay or synchronizing option
z Can be shared with selectable USART pin locations
z Outputs:
z Available on external pins or event system
z Includes selectable delay or synchronizing option
z Can override selectable USART pin locations
z Operates in active mode and all sleep modes
26.2 Overview
The XMEGA Custom Logic module (XCL) consists of two sub-units, each including 8-bit timer/counter with flexible
settings, peripheral counter working with one software selectable USART module, delay elements, glue logic with
programmable truth table and a global logic interconnect array.
The timer/counter configuration allows for two 8-bits timer/counters. Each timer/counter supports normal, compare and
input capture operation, with common flexible clock selections and event channels for each timer. By cascading the two
8-bit timer/counters, the XCL can be used as a 16-bit timer/counter.
The peripheral counter (PEC) configuration, the XCL is connected to one software selectable USART. This USART
controls the counter operation, and the PEC can optionally control the data length within the USART frame.
The glue logic configuration, the XCL implements two programmable lookup tables (LUTs). Each defines the truth table
corresponding to the logical condition between two inputs. Any combinatorial function logic is possible. The LUT inputs
can be connected to I/O pins or event system channels. If the LUT is connected to the USART0 pin locations, the data
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lines (TXD/RXD) data encoding/decoding will be possible. Connecting together the LUT units, RS Latch or any
combinatorial logic between two operands or three inputs can be enabled.
The LUT works in all sleep modes. Combined with event system and one I/O pin, the LUT can wake-up the system if, and
only if, condition on up to 3 input pins is true.
A block diagram of the programmable logic unit with extensions and closely related peripheral modules (in grey) is shown
in Figure 26-1.
Figure 26-1. XMEGA custom logic module and closely related peripherals.
Event
Port
Pins
USART
System
Interrupts
Periph.Counter
One Shot
PWM
Truth
Table
LUT0
Capture
Q
D
Normal
BTC0
BTC1
D
G
Q
Normal
Capture
PWM
LUT1
One Shot
Truth
Table
Periph.Counter
Timer/Counter
Glue Logic
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27. CRC – Cyclic Redundancy Check Generator
27.1 Features
z Cyclic redundancy check (CRC) generation and checking for
z Communication data
z Program or data in flash memory
z Data in SRAM and I/O memory space
z Integrated with flash memory, EDMA controller and CPU
z Continuous CRC on data going through an EDMA channel
z Automatic CRC of the complete or a selectable range of the flash memory
z CPU can load data to the CRC generator through the I/O interface
z CRC polynomial software selectable to
z CRC-16 (CRC-CCITT)
z CRC-32 (IEEE 802.3)
z Zero remainder detection
27.2 Overview
A cyclic redundancy check (CRC) is an error detection technique test algorithm used to find accidental errors in data, and
it is commonly used to determine the correctness of a data transmission, and data present in the data and program
memories. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be
appended to the data and used as a checksum. When the same data are later received or read, the device or application
repeats the calculation. If the new CRC result does not match the one calculated earlier, the block contains a data error.
The application will then detect this and may take a corrective action, such as requesting the data to be sent again or
simply not using the incorrect data.
Typically, an n-bit CRC applied to a data block of arbitrary length will detect any single error burst not longer than n bits
(any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2-n of all longer error
bursts. The CRC module in XMEGA devices supports two commonly used CRC polynomials; CRC-16 (CRC-CCITT) and
CRC-32 (IEEE 802.3).
z
CRC-16:
z
z
Polynomial: x16 + x12 + x5 + 1
Hex Value: 0x1021
z
CRC-32:
z
z
Polynomial: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
Hex Value: 0x04C11DB7
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28. ADC – 12-bit Analog to Digital Converter
28.1 Features
z 12-bit resolution
z Up to 300 thousand samples per second
z Down to 2.3μs conversion time with 8-bit resolution
z Down to 3.35μs conversion time with 12-bit resolution
z Differential and single-ended input
z Up to 16 single-ended inputs
z 16x8 differential inputs with optional gain
z Built-in differential gain stage
z 1/2x, 1x, 2x, 4x, 8x, 16x, 32x, and 64x gain options
z Single, continuous and scan conversion options
z Four internal inputs
z Internal temperature sensor
z DAC output
z AVCC voltage divided by 10
z 1.1V bandgap voltage
z Internal and external reference options
z Compare function for accurate monitoring of user defined thresholds
z Offset and gain correction
z Averaging
z Over-sampling and decimation
z Optional event triggered conversion for accurate timing
z Optional interrupt/event on compare result
z Optional EDMA transfer of conversion results
28.2 Overview
The ADC converts analog signals to digital values. The ADC has 12-bit resolution and is capable of converting up to 300
thousand samples per second (ksps). The input selection is flexible, and both single-ended and differential
measurements can be done. For differential measurements, an optional gain stage is available to increase the dynamic
range. In addition, several internal signal inputs are available. The ADC can provide both signed and unsigned results.
The ADC measurements can either be started by application software or an incoming event from another peripheral in
the device. The ADC measurements can be started with predictable timing, and without software intervention. It is
possible to use EDMA to move ADC results directly to memory or peripherals when conversions are done.
Both internal and external reference voltages can be used. An integrated temperature sensor is available for use with the
ADC. The output from the DAC, AVCC/10 and the bandgap voltage can also be measured by the ADC.
The ADC has a compare function for accurate monitoring of user defined thresholds with minimum software intervention
required.
When operation in noisy conditions, the average feature can be enabled to increase the ADC resolution. Up to 1024
samples can be averaged, enabling up to 16-bit resolution results. In the same way, using the over-sampling and
decimation mode, the ADC resolution is increased up to 16-bits, which results in up to 4-bit extra LSB resolution. The
ADC includes various calibration options. In addition to standard production calibration, the user can enable the offset
and gain correction to improve the absolute ADC accuracy.
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Figure 28-1. ADC overview.
VIN
VOUT
2x
S&H
Σ
ADC
DAC
ADC0
ADC1
2 bits
Stage
•
•
•
CMP
RES
ADC14
ADC15
Stage
VINP
<
>
Threshold
(Int. Req.)
1
2
2
2
Gain & Offset
Error
Correction
clkADC
Internal
Signals
½x-64x
Digital Correction Logic
ADC0
Averaging
•
•
•
VINN
ADC
ADC7
Internal 1.00V
Internal AVCC/1.6
Internal AVCC/2
AREFA
Reference
Voltage
AREFD
The ADC may be configured for 8- or 12-bit result, reducing the propagation delay from 3.35µs for 12-bit to 2.3µs for 8-bit
result. ADC conversion results are provided left- or right adjusted with eases calculation when the result is represented
as a signed.
PORTA has one ADC. Notation of this peripheral is ADCA.
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29. DAC – Digital to Analog Converter
29.1 Features
z One Digital to Analog Converter (DAC)
z 12-bit resolution
z Two independent, continuous-drive output channels
z Up to 1 million samples per second conversion rate per DAC channel
z Built-in calibration that removes:
z Offset error
z Gain error
z Multiple conversion trigger sources
z On new available data
z Events from the event system
z Drive capabilities and support for
z Resistive loads
z Capacitive loads
z Combined resistive and capacitive loads
z Internal and external reference options
z DAC output available as input to analog comparator and ADC
z Low-power mode, with reduced drive strength
z Optional EDMA transfer of data
29.2 Overview
The digital-to-analog converter (DAC) converts digital values to voltages. The DAC has two channels, each with 12-bit
resolution, and is capable of converting up to one million samples per second (Msps) on each channel. The built-in
calibration system can remove offset and gain error when loaded with calibration values from software.
Figure 29-1. DAC overview.
EDMA req
(Data Empty)
D
A
T
12
Output
Driver
CH0DATA
DAC0
A
To
AC/ADC
Int.
driver
Trigger
Select
Enable
CTRLA
Enable
AVCC
Reference
selection
Internal 1.00V
AREFA
CTRLB
Internal Output
enable
AREFD
Trigger
Select
D
A
T
12
Output
Driver
CH1DATA
DAC1
A
EDMA req
(Data Empty)
A DAC conversion is automatically started when new data to be converted are available. Events from the event system
can also be used to trigger a conversion, and this enables synchronized and timed conversions between the DAC and
other peripherals, such as a timer/counter. The EDMA controller can be used to transfer data to the DAC.
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The DAC is capable of driving both resistive and capacitive loads aswell as loads which combine both. A low-power
mode is available, which will reduce the drive strength of the output. Internal and external voltage references can be
used. The DAC output is also internally available for use as input to the analog comparator or ADC.
PORTA has one DAC. Notation of this peripheral is DACA.
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30. AC – Analog Comparator
30.1 Features
z Two Analog Comparators
z Selectable propagation delay
z Selectable hysteresis
z No
z Small
z Large
z Analog Comparator output available on pin
z Flexible Input Selection
z All pins on the port
z Output from the DAC
z Bandgap reference voltage.
z A 64-level programmable voltage scaler of the internal AVCC voltage
z Interrupt and event generation on
z Rising edge
z Falling edge
z Toggle
z Window function interrupt and event generation on
z Signal above window
z Signal inside window
z Signal below window
z Constant current source with configurable output pin selection
z Source of asynchronous event
30.2 Overview
The Analog Comparator (AC) compares the voltage level on two inputs and gives a digital output based on this
comparison. The Analog Comparator may be configured to give interrupt requests and/or synchronous/asynchronous
events upon several different combinations of input change.
One important property of the Analog Comparator when it comes to the dynamic behavior, is the hysteresis. This
parameter may be adjusted in order to find the optimal operation for each application.
The input section includes analog port pins, several internal signals and a 64-level programmable voltage scaler. The
analog comparator output state can also be directly available on a pin for use by external devices. Using as pair they can
also be set in Window mode to monitor a signal compared to a voltage window instead of a voltage level.
A constant current source can be enabled and output on a selectable pin. This can be used to replace, for example,
external resistors used to charge capacitors in capacitive touch sensing applications.
The analog comparators are always grouped in pairs on each port. These are called analog comparator 0 (AC0) and
analog comparator 1 (AC1). They have identical behavior, but separate control registers. Used as pair, they can be set in
window mode to compare a signal to a voltage range instead of a voltage level.
PORTA has one AC pair. Notation is ACA.
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Figure 30-1. Analog comparator overview.
Pin Input
AC0OUT
Pin Input
Hysteresis
DAC
Enable
Interrupt
Interrupts
Events
Sensititivity
Control
&
Interrupt
Mode
Voltage
Scaler
ACnMUXCTRL
ACnCTRL
WINCTRL
Window
Function
Enable
Bandgap
Hysteresis
Pin Input
Pin Input
AC1OUT
The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in
Figure 30-2.
Figure 30-2. Analog comparator window function.
+
AC0
Upper limit of window
-
Interrupts
Interrupt
Input signal
sensitivity
Events
control
+
AC1
Lower limit of window
-
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31. Programming and Debugging
31.1 Features
z Programming
z External programming through PDI interface
z
Minimal protocol overhead for fast operation
z
Built-in error detection and handling for reliable operation
z Boot loader support for programming through any communication interface
z Debugging
z Nonintrusive, real-time, on-chip debug system
z No software or hardware resources required from device except pin connection
z Program flow control
z Go, Stop, Reset, Step Into, Step Over, Step Out, Run-to-Cursor
z Unlimited number of user program breakpoints
z Unlimited number of user data breakpoints, break on:
z Data location read, write, or both read and write
z Data location content equal or not equal to a value
z Data location content is greater or smaller than a value
z Data location content is within or outside a range
z No limitation on device clock frequency
z Program and Debug Interface (PDI)
z Two-pin interface for external programming and debugging
z Uses the Reset pin and a dedicated pin
z No I/O pins required during programming or debugging
31.2 Overview
The Program and Debug Interface (PDI) is an Atmel proprietary interface for external programming and on-chip
debugging of a device. The PDI supports fast programming of nonvolatile memory (NVM) spaces; flash, EEPOM, fuses,
lock bits, and the user signature row.
Debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. It does not require any
software or hardware resources except for the device pin connection. Using the Atmel tool chain, it offers complete
program flow control and support for an unlimited number of program and complex data breakpoints. Application debug
can be done from a C or other high-level language source code level, as well as from an assembler and disassemble
level.
Programming and debugging can be done through the PDI physical layer. This is a two-pin interface that uses the Reset
pin for the clock input (PDI_CLK) and one other dedicated pin for data input and output (PDI_DATA). Any external
programmer or on-chip debugger/emulator can be directly connected to this interface.
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32. Pinout and Pin Functions
The device pinout is shown in Pinout and Block Diagram on page 3. In addition to general purpose I/O functionality, each
pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin.
Only one of the pin functions can be used at time.
32.1 Alternate Pin Function Description
The tables below show the notation for all pin functions available and describe its function.
32.1.1 Operation/Power Supply
VCC
Digital supply voltage
Analog supply voltage
Ground
AVCC
GND
32.1.2 Port Interrupt functions
SYNC
Port pin with full synchronous and limited asynchronous interrupt function
ASYNC
Port pin with full synchronous and full asynchronous interrupt function
32.1.3 Analog functions
ACn
Analog Comparator input pin n
Analog Comparator n Output
ACnOUT
ADCn
DACn
AREF
Analog to Digital Converter input pin n
Digital to Analog Converter output pin n
Analog Reference input pin
32.1.4 Timer/Counter and WEX functions
OCnx
Output Compare channel x for timer/counter n
OCnxLS
OCnxHS
Output Compare Channel x Low Side for Timer/Counter n
Output Compare Channel x High Side for Timer/Counter n
32.1.5 Communication functions
SCL
Serial Clock for TWI
SDA
Serial Data for TWI
SCLIN
SCLOUT
Serial Clock In for TWI when external driver interface is enabled
Serial Clock Out for TWI when external driver interface is enabled
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SDAIN
SDAOUT
XCKn
RXDn
TXDn
SS
Serial Data In for TWI when external driver interface is enabled
Serial Data Out for TWI when external driver interface is enabled
Transfer Clock for USART n
Receiver Data for USART n
Transmitter Data for USART n
Slave Select for SPI
MOSI
MISO
SCK
Master Out Slave In for SPI
Master In Slave Out for SPI
Serial Clock for SPI
32.1.6 Oscillators, Clock and Event
TOSCn
XTALn
Timer Oscillator pin n
Input/Output for Oscillator pin n
Peripheral Clock Output
Event Channel Output
CLKOUT
EVOUT
RTCOUT
RTC Clock Source Output
32.1.7 Debug/System functions
RESET
Reset pin
PDI_CLK
PDI_DATA
Program and Debug Interface Clock pin
Program and Debug Interface Data pin
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32.2 Alternate Pin Functions
The tables below show the primary/default function for each pin on a port in the first column, the pin number in the
second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that
enable and use the alternate pin functions.
For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under the
first table where this apply.
Table 32-1. PORT A – Alternate Functions.
ADCA POS/
GAINPOS
ADCA NEG/
GAINNEG
ACA
POS
ACA
NEG
ACA
OUT
PORT A
PA0
Pin#
6
DACA
REFA
ADC 0
ADC 1
ADC 2
ADC 3
ADC 4
ADC 5
ADC 6
ADC 7
ADC 0
ADC 1
ADC 2
ADC 3
ADC 4
ADC 5
ADC 6
ADC 7
AC0
AC1
AC2
AC3
AC4
AC5
AC6
AC0
AC1
AREF
PA1
5
PA2
4
DAC0
DAC1
PA3
3
AC3
AC5
AC7
PA4
2
PA5
31
30
29
PA6
AC1OUT
AC0OUT
PA7
Table 32-2. PORT C – Alternate Functions.
XCL
PORT C
PC0
Pin #
16
15
14
13
12
11
TCC4
OC4A
OC4B
OC4C
OC4D
OC4A
OC4B
OC4C
OC4D
WEXC
TCC5
USARTC0
SPIC
TWI
SDA
SCL
(LUT)
EXTCLK
AC OUT
OC4ALS
OC4AHS
OC4BLS
OC4BHS
OC4CLS
OC4CHS
OC4DLS
OC4DHS
IN1/OUT0
IN2
PC1
XCK0
RXD0
TXD0
PC2
IN0
PC3
IN3
PC4
OC5A
OC5B
SS
IN1/OUT0
IN2
EXTCLK
PC5
XCK0
RXD0
TXD0
SCK
PC6
10
9
MISO
MOSI
IN0
AC1OUT
AC0OUT
PC7
IN3
Table 32-3. Debug – Program and Debug Functions.
DEBUG
RESET
PDI
Pin #
PROG
8
7
PDI CLOCK
PDI DATA
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Table 32-4. PORT R – Alternate Functions.
PORT R
PR0
Pin #
20
XTAL
XTAL2
XTAL1
TOSC
TOSC2
TOSC1
EXTCLK
CLOCKOUT
EVENTOUT
RTCOUT
AC OUT
AC1 OUT
AC0 OUT
CLKOUT
EVOUT
RTCOUT
PR1
19
EXTCLK
Table 32-5. PORT D – Alternate Functions.
TWID
ADCAPOS
GAINPOS
USART
D0
XCL
(LUT)
XCL
(TC)
CLOCK
OUT
EVENT
OUT
PORT D
Pin #
TCD5
(Bridge)
RTCOUT
ACOUT
REFD
AREF
IN1/
OUT0
28
ADC8
SDA
SCL
PD0
PD1
PD2
PD3
27
26
25
ADC9
ADC10
ADC11
XCK0
RXD0
TXD0
IN2
IN0
IN3
OC0
OC1
IN1/
OUT0
24
ADC12
OC5A
OC5B
CLKOUT
CLKOUT
EVOUT
EVOUT
PD4
PD5
PD6
PD7
23
22
21
ADC13
ADC14
ADC15
XCK0
RXD0
TXD0
IN2
IN0
IN3
RTCOUT
AC1OUT
AC0OUT
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33. Peripheral Module Address Map
The address maps show the base address for each peripheral and module in XMEGA E5. For complete register
description and summary for each peripheral module, refer to the XMEGA E Manual.
Table 33-1. Peripheral module address map.
Base Address
0x0000
0x0010
0x0014
0x0018
0x001C
0x0030
0x0040
0x0048
0x0050
0x0060
0x0070
0x0078
0x0080
0x0090
0x00A0
0x00B0
0x00D0
0x0100
0x0180
0x01C0
0x0200
0x0300
0x0380
0x0400
0x0460
0x0480
0x0600
0x0640
Name
GPIO
Description
General Purpose IO Registers
Virtual Port A
VPORT0
VPORT1
VPORT2
VPORT3
CPU
Virtual Port C
Virtual Port D
Virtual Port R
CPU
CLK
Clock Control
SLEEP
OSC
Sleep Controller
Oscillator Control
DFLLRC32M
PR
DFLL for the 32MHz Internal Oscillator
Power Reduction
RST
Reset Controller
WDT
Watch-Dog Timer
MCU
MCU Control
PMIC
Programmable Multilevel Interrupt Controller
Port Configuration
PORTCFG
CRC
CRC Module
EDMA
EVSYS
NVM
Enhanced DMA Controller
Event System
Non Volatile Memory (NVM) Controller
Analog to Digital Converter on port A
Digital to Analog Converter on port A
Analog Comparator pair on port A
Real Time Counter
ADCA
DACA
ACA
RTC
XCL
XMEGA Custom Logic Module
Two-Wire Interface on port C
Port A
TWIC
PORTA
PORTC
Port C
XMEGA E5 [DATASHEET]
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Base Address
0x0660
0x07E0
0x0800
0x0840
0x0880
0x0890
0x08A0
0x08B0
0x08C0
0x08E0
0x08F8
0x0940
0x09C0
Name
Description
PORTD
PORTR
TCC4
Port D
Port R
Timer/Counter 4 on port C
Timer/Counter 5 on port C
Fault Extension on TCC4
Fault Extensionon TCC5
Waveform Extension on port C
High Resolution Extension on port C
USART 0 on port C
TCC5
FAULTC4
FAULTC5
WEXC
HIRESC
USARTC0
SPIC
Serial Peripheral Interface on port C
Infrared Communication Module
Timer/Counter 5 on port D
USART 0 on port D
IRCOM
TCD5
USARTD0
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34. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
Arithmetic and Logic Instructions
ADD
ADC
ADIW
SUB
Rd, Rr
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add without Carry
Rd
Rd
Rd
Rd
Rd
Rd
Rd
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
Rd + Rr
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,C,N,V,S
Z,C,N,V,S,H
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
None
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
1/2
Add with Carry
Rd + Rr + C
Rd + 1:Rd + K
Rd - Rr
Add Immediate to Word
Subtract without Carry
Subtract Immediate
Subtract with Carry
Subtract Immediate with Carry
Subtract Immediate from Word
Logical AND
SUBI
SBC
Rd - K
Rd - Rr - C
Rd - K - C
Rd + 1:Rd - K
Rd • Rr
SBCI
SBIW
AND
ANDI
OR
Rd + 1:Rd
Rd
Logical AND with Immediate
Logical OR
Rd
Rd • K
Rd
Rd v Rr
ORI
Logical OR with Immediate
Exclusive OR
Rd
Rd v K
EOR
COM
NEG
SBR
Rd
Rd ⊕ Rr
One’s Complement
Two’s Complement
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Rd
$FF - Rd
Rd
Rd
$00 - Rd
Rd,K
Rd,K
Rd
Rd
Rd v K
CBR
INC
Rd
Rd • ($FFh - K)
Rd + 1
Rd
DEC
TST
Rd
Decrement
Rd
Rd - 1
Rd
Test for Zero or Minus
Clear Register
Rd
Rd • Rd
CLR
Rd
Rd
Rd ⊕ Rd
SER
Rd
Set Register
Rd
$FF
MUL
MULS
MULSU
FMUL
FMULS
FMULSU
DES
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
K
Multiply Unsigned
R1:R0
R1:R0
R1:R0
R1:R0
R1:R0
R1:R0
Rd x Rr (UU)
Rd x Rr (SS)
Rd x Rr (SU)
Rd x Rr<<1 (UU)
Rd x Rr<<1 (SS)
Rd x Rr<<1 (SU)
Z,C
Multiply Signed
Z,C
Multiply Signed with Unsigned
Fractional Multiply Unsigned
Fractional Multiply Signed
Fractional Multiply Signed with Unsigned
Data Encryption
Z,C
Z,C
Z,C
Z,C
if (H = 0) then R15:R0
else if (H = 1) then R15:R0
←
←
Encrypt(R15:R0, K)
Decrypt(R15:R0, K)
Branch instructions
RJMP
IJMP
k
Relative Jump
PC
←
PC + k + 1
None
None
2
2
Indirect Jump to (Z)
PC(15:0)
PC(21:16)
←
←
Z,
0
EIJMP
Extended Indirect Jump to (Z)
PC(15:0)
PC(21:16)
←
←
Z,
EIND
None
2
JMP
k
k
Jump
PC
PC
←
←
k
None
None
3
RCALL
Relative Call Subroutine
PC + k + 1
2 / 3(1)
XMEGA E5 [DATASHEET]
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Mnemonics
Operands
Description
Operation
Flags
#Clocks
ICALL
Indirect Call to (Z)
PC(15:0)
PC(21:16)
←
←
Z,
0
None
2 / 3(1)
EICALL
Extended Indirect Call to (Z)
PC(15:0)
PC(21:16)
←
←
Z,
EIND
None
3(1)
CALL
RET
k
call Subroutine
PC
PC
←
←
←
←
k
None
None
I
3 / 4(1)
4 / 5(1)
4 / 5(1)
1 / 2 / 3
1
Subroutine Return
STACK
STACK
PC + 2 or 3
RETI
Interrupt Return
PC
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC
None
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Rd,Rr
Rd - Rr
CPC
Rd,Rr
Compare with Carry
Rd - Rr - C
1
CPI
Rd,K
Compare with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd - K
1
SBRC
SBRS
SBIC
SBIS
Rr, b
if (Rr(b) = 0) PC
if (Rr(b) = 1) PC
if (I/O(A,b) = 0) PC
If (I/O(A,b) =1) PC
if (SREG(s) = 1) then PC
if (SREG(s) = 0) then PC
if (Z = 1) then PC
if (Z = 0) then PC
if (C = 1) then PC
if (C = 0) then PC
if (C = 0) then PC
if (C = 1) then PC
if (N = 1) then PC
if (N = 0) then PC
if (N ⊕ V= 0) then PC
if (N ⊕ V= 1) then PC
if (H = 1) then PC
if (H = 0) then PC
if (T = 1) then PC
if (T = 0) then PC
if (V = 1) then PC
if (V = 0) then PC
if (I = 1) then PC
if (I = 0) then PC
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
1 / 2 / 3
1 / 2 / 3
2 / 3 / 4
2 / 3 / 4
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
Rr, b
A, b
A, b
s, k
s, k
k
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
BRID
k
Branch if Not Equal
k
Branch if Carry Set
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
k
k
k
Branch if Minus
k
Branch if Plus
k
Branch if Greater or Equal, Signed
Branch if Less Than, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
k
k
k
k
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
k
k
k
k
Data transfer instructions
MOV
MOVW
LDI
Rd, Rr
Rd, Rr
Rd, K
Copy Register
Rd
Rd+1:Rd
Rd
←
←
←
Rr
None
None
None
1
1
1
Copy Register Pair
Load Immediate
Rr+1:Rr
K
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Mnemonics
Operands
Rd, k
Description
Operation
Flags
None
None
None
#Clocks
2(1)(2)
LDS
LD
Load Direct from data space
Load Indirect
Rd
Rd
←
←
(k)
Rd, X
(X)
1(1)(2)
LD
Rd, X+
Load Indirect and Post-Increment
Rd
X
←
←
(X)
X + 1
1(1)(2)
LD
Rd, -X
Load Indirect and Pre-Decrement
X ← X - 1,
Rd ← (X)
←
←
X - 1
(X)
None
2(1)(2)
LD
LD
Rd, Y
Load Indirect
Rd ← (Y)
←
(Y)
None
None
1(1)(2)
1(1)(2)
Rd, Y+
Load Indirect and Post-Increment
Rd
Y
←
←
(Y)
Y + 1
LD
Rd, -Y
Load Indirect and Pre-Decrement
Y
Rd
←
←
Y - 1
(Y)
None
2(1)(2)
LDD
LD
Rd, Y+q
Rd, Z
Load Indirect with Displacement
Load Indirect
Rd
Rd
←
←
(Y + q)
(Z)
None
None
None
2(1)(2)
1(1)(2)
1(1)(2)
LD
Rd, Z+
Load Indirect and Post-Increment
Rd
Z
←
←
(Z),
Z+1
LD
Rd, -Z
Load Indirect and Pre-Decrement
Z
Rd
←
←
Z - 1,
(Z)
None
2(1)(2)
LDD
STS
ST
Rd, Z+q
k, Rr
Load Indirect with Displacement
Store Direct to Data Space
Store Indirect
Rd
(k)
(X)
←
←
←
(Z + q)
Rd
None
None
None
None
2(1)(2)
2(1)
X, Rr
Rr
1(1)
ST
X+, Rr
Store Indirect and Post-Increment
(X)
X
←
←
Rr,
X + 1
1(1)
ST
-X, Rr
Store Indirect and Pre-Decrement
X
(X)
←
←
X - 1,
Rr
None
2(1)
ST
ST
Y, Rr
Store Indirect
(Y)
←
Rr
None
None
1(1)
1(1)
Y+, Rr
Store Indirect and Post-Increment
(Y)
Y
←
←
Rr,
Y + 1
ST
-Y, Rr
Store Indirect and Pre-Decrement
Y
(Y)
←
←
Y - 1,
Rr
None
2(1)
STD
ST
Y+q, Rr
Z, Rr
Store Indirect with Displacement
Store Indirect
(Y + q)
(Z)
←
←
Rr
Rr
None
None
None
2(1)
1(1)
1(1)
ST
Z+, Rr
Store Indirect and Post-Increment
(Z)
Z
←
←
Rr
Z + 1
ST
-Z, Rr
Store Indirect and Pre-Decrement
Store Indirect with Displacement
Load Program Memory
Z
(Z + q)
R0
←
←
←
←
Z - 1
Rr
None
None
None
None
None
2(1)
2(1)
3
STD
LPM
LPM
LPM
Z+q,Rr
(Z)
Rd, Z
Load Program Memory
Rd
(Z)
3
Rd, Z+
Load Program Memory and Post-Increment
Rd
Z
←
←
(Z),
Z + 1
3
ELPM
ELPM
ELPM
Extended Load Program Memory
Extended Load Program Memory
R0
Rd
←
←
(RAMPZ:Z)
(RAMPZ:Z)
None
None
None
3
3
3
Rd, Z
Rd, Z+
Extended Load Program Memory and Post-
Increment
Rd
Z
←
←
(RAMPZ:Z),
Z + 1
SPM
SPM
Store Program Memory
(RAMPZ:Z)
←
R1:R0
None
None
-
-
Z+
Store Program Memory and Post-Increment
by 2
(RAMPZ:Z)
Z
←
←
R1:R0,
Z + 2
XMEGA E5 [DATASHEET]
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Mnemonics
IN
Operands
Rd, A
A, Rr
Rr
Description
Operation
Flags
None
None
None
None
None
#Clocks
In From I/O Location
Out To I/O Location
Push Register on Stack
Pop Register from Stack
Exchange RAM location
Rd
I/O(A)
STACK
Rd
←
←
←
←
I/O(A)
Rr
1
1
OUT
PUSH
POP
Rr
1(1)
2(1)
2
Rd
STACK
XCH
Z, Rd
Temp
Rd
(Z)
←
←
←
Rd,
(Z),
Temp
LAS
LAC
LAT
Z, Rd
Z, Rd
Z, Rd
Load and Set RAM location
Load and Clear RAM location
Load and Toggle RAM location
Temp
Rd
(Z)
←
←
←
Rd,
(Z),
Temp v (Z)
None
None
None
2
2
2
Temp
Rd
(Z)
←
←
←
Rd,
(Z),
($FFh – Rd) z (Z)
Temp
Rd
(Z)
←
←
←
Rd,
(Z),
Temp ⊕ (Z)
Bit and bit-test instructions
LSL
Rd
Rd
Rd
Rd
Logical Shift Left
Rd(n+1)
Rd(0)
C
←
←
←
Rd(n),
0,
Rd(7)
Z,C,N,V,H
Z,C,N,V
1
1
1
1
LSR
ROL
ROR
Logical Shift Right
Rd(n)
Rd(7)
C
←
←
←
Rd(n+1),
0,
Rd(0)
Rotate Left Through Carry
Rotate Right Through Carry
Rd(0)
Rd(n+1)
C
←
←
←
C,
Rd(n),
Rd(7)
Z,C,N,V,H
Z,C,N,V
Rd(7)
Rd(n)
C
←
←
←
C,
Rd(n+1),
Rd(0)
ASR
SWAP
BSET
BCLR
SBI
Rd
Arithmetic Shift Right
Swap Nibbles
Rd(n)
←
↔
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
Rd(n+1), n=0..6
Z,C,N,V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rd
Rd(3..0)
Rd(7..4)
None
s
Flag Set
SREG(s)
1
SREG(s)
s
Flag Clear
SREG(s)
0
SREG(s)
A, b
A, b
Rr, b
Rd, b
Set Bit in I/O Register
Clear Bit in I/O Register
Bit Store from Register to T
Bit load from T to Register
Set Carry
I/O(A, b)
1
None
CBI
I/O(A, b)
0
None
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
T
Rr(b)
T
1
T
Rd(b)
None
C
C
N
N
Z
Z
I
C
C
N
N
Z
Z
I
Clear Carry
0
Set Negative Flag
Clear Negative Flag
Set Zero Flag
1
0
1
Clear Zero Flag
0
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
1
CLI
I
0
I
SES
CLS
S
S
1
S
S
0
XMEGA E5 [DATASHEET]
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Mnemonics
SEV
Operands
Description
Operation
Flags
#Clocks
Set Two’s Complement Overflow
Clear Two’s Complement Overflow
Set T in SREG
V
V
T
←
←
←
←
←
←
1
0
1
0
1
0
V
V
T
T
H
H
1
1
1
1
1
1
CLV
SET
CLT
Clear T in SREG
T
SEH
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H
H
CLH
MCU control instructions
BREAK
NOP
Break
(See specific descr. for BREAK)
None
None
None
None
1
1
1
1
No Operation
Sleep
SLEEP
WDR
(see specific descr. for Sleep)
(see specific descr. for WDR)
Watchdog Reset
Notes:
1. Cycle times for data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface.
2. One extra cycle must be added when accessing internal SRAM.
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35. Packaging information
35.1 32A
XMEGA E5 [DATASHEET]
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35.2 32Z
XMEGA E5 [DATASHEET]
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35.3 32MA
XMEGA E5 [DATASHEET]
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36. Electrical Characteristics
All typical values are measured at T = 25°C unless other temperature condition is given. All minimum and maximum
values are valid across operating temperature and voltage unless other conditions are given.
36.1 Absolute Maximum Ratings
Symbol
VCC
IVCC
IGND
VPIN
IPIN
Parameter
Min.
Typ.
Max.
4
Units
V
Power supply voltage
Current into a VCC pin
Current out of a Gnd pin
Pin voltage with respect to Gnd and VCC
I/O pin sink/source current
Storage temperature
-0.3
200
mA
mA
V
200
-0.5
-25
-65
VCC+0.5
25
mA
°C
TA
150
Tj
Junction temperature
150
°C
36.2 General Operating Ratings
The device must operate within the ratings listed in Table 36-1 in order for all other electrical characteristics and typical
characteristics of the device to be valid.
Table 36-1. General operating conditions.
Symbol
VCC
Parameter
Min.
1.6
Typ.
Max.
3.6
Units
V
Power supply voltage
Analog supply voltage
Temperature range
Junction temperature
AVCC
TA
1.6
3.6
V
-40
-40
85
°C
°C
Tj
105
Table 36-2. Operating voltage and frequency.
Symbol
Parameter
Condition
VCC = 1.6V
VCC = 1.8V
VCC = 2.7V
VCC = 3.6V
Min.
Typ.
Max.
12
Units
0
0
0
0
12
ClkCPU
CPU clock frequency
MHz
32
32
The maximum CPU clock frequency depends on VCC. As shown in Figure 36-1 the Frequency vs. VCC curve is linear
between 1.8V < VCC < 2.7V.
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Figure 36-1. Maximum Frequency vs. VCC
.
MHz
32
Safe Operating Area
12
V
1.6
1.8
2.7
3.6
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36.3 Current Consumption
Table 36-3. Current consumption for Active mode and Sleep modes
Symbol Parameter
Condition
Min.
Typ.
20
Max.
Units
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
VCC = 3.0V
32kHz, Ext. Clk
35
155
290
300
0.6
7
µA
1MHz, Ext. Clk
Active power
consumption (1)
400
1.2
10
2MHz, Ext. Clk
32MHz, Ext. Clk
32kHz, Ext. Clk
mA
7
12
55
1MHz, Ext. Clk
2MHz, Ext. Clk
µA
Idle power
105
110
200
3.5
0.1
1
consumption (1)
250
350
5
32MHz, Ext. Clk
mA
All disabled, T = 25°C
All disabled, T = 85°C
All disabled, T = 105°C
0.9
3
VCC = 3.0V
ICC
2
5
WDT and sampled BOD enabled,
T = 25°C
Power-down power
consumption
0.5
1.2
2.5
µA
WDT and sampled BOD enabled,
T = 85°C
VCC = 3.0V
3.5
6
WDT and sampled BOD enabled,
T = 105°C
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
0.4
0.6
0.5
RTC from ULP clock, WDT and
sampled BOD enabled, T = 25°C
RTC from ULP clock, WDT,
sampled BOD enabled and 8MHz
internal oscillator in low power
mode, T = 25°C
VCC = 3.0V
0.6
Power-save power
consumption
µA
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
0.8
0.9
0.9
1.0
RTC on 1kHz low power 32.768kHz
TOSC, T = 25°C
RTC from low power 32.768kHz
TOSC, T = 25°C
Current through RESET pin
substracted, T = 25°C
Reset power consumption
VCC = 3.0V
110
µA
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Notes:
1. All Power Reduction Registers set.
Table 36-4. Current consumption for modules and peripherals.
Symbol
Parameter
Condition(1)
Min.
Typ.
100
27
Max.
Units
nA
Internal ULP oscillator
32.768kHz int. oscillator
µA
Normal power mode
Low power mode
65
8MHz int. oscillator
32MHz int. oscillator
µA
µA
45
275
400
DFLL enabled with 32.768kHz int. osc. as reference
20x multiplication factor,
PLL
230
µA
µA
32MHz int. osc. DIV4 as reference
Watchdog timer
0.3
245
0.4
200
100
1.5
1.4
1.3
1.2
1.7
3.1
1.9
Continuous mode
Sampled mode
BOD
µA
Internal 1.0V reference
µA
µA
Internal temperature sensor
ICC
CURRLIMIT = LOW
CURRLIMIT = MEDIUM
CURRLIMIT = HIGH
CURRLIMIT = LOW
16ksps
VREF = Ext ref
ADC
mA
75ksps, VREF = Ext ref
300ksps, VREF = Ext ref
250ksps
Normal mode
DAC
VREF = Ext ref
No load
mA
Low Power mode
1.1
AC
200
200
25
8
µA
µA
µA
µA
µA
mA
EDMA
Timer/counter
USART
XCL
Rx and Tx enabled, 9600 BAUD
16-bit timer/counter
6
Flash memory and EEPROM programming
4
Note:
1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external clock
without prescaling, T = 25°C unless other conditions are given.
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36.4 Wake-up Time from Sleep Modes
Table 36-5. Device wake-up time from sleep modes with various system clock sources.
Symbol
Parameter
Condition
Min.
Typ.(1)
0.2
Max.
Units
External 2MHz clock
32kHz internal oscillator
8MHz internal oscillator
32MHz internal oscillator
External 2MHz clock
32kHz internal oscillator
Wake-up time from
idle, standby, and
extended standby
mode
120
0.5
0.2
4.5
320
4.5
Wake-up time from
power save mode
twakeup
Normal mode
µs
8MHz internal oscillator
Low power mode
0.5
32MHz internal oscillator
External 2MHz clock
5.0
4.5
32kHz internal oscillator
8MHz internal oscillator
32MHz internal oscillator
320
4.5
Wake-up time from
power down mode
5.0
Note:
1.
The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 36-2. All peripherals and
modules start execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.
Figure 36-2. Wake-up time definition.
Wakeup time
Wakeup request
Clock output
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36.5 I/O Pin Characteristics
The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output
voltage limits reflect or exceed this specification.
Table 36-6. I/O pin characteristics.
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
(1)
IOH
/
I/O pin source/sink current
-15
15
mA
(2)
IOL
VCC = 2.4 - 3.6V
0.7*VCC
0.8*VCC
-0.5
VCC+0.5
VCC+0.5
0.3*VCC
0.2*VCC
High level input voltage,
except XTAL1 and RESET pin
VIH
V
V
VCC = 1.6 - 2.4V
VCC = 2.4- 3.6V
VCC = 1.6 - 2.4V
VCC = 3.3V
Low level input voltage,
except XTAL1 and RESET pin
VIL
-0.5
IOH = -4mA
IOH = -3mA
IOH = -1mA
IOL = 8mA
IOL = 5mA
IOL = 3mA
2.6
3.1
2.7
VOH
High level output voltage
Low level output voltage
VCC = 3.0V
2.1
V
V
VCC = 1.8V
1.4
1.7
VCC = 3.3V
0.20
0.15
0.10
<0.01
27
0.76
0.64
0.46
1.0
VOL
VCC = 3.0V
VCC = 1.8V
IIN
Input leakage current
T = 25°C
µA
RP
Pull/buss keeper resistor
kΩ
Notes:
1. The sum of all IOH for PA[7:5] on PORTA must not exceed 100mA.
The sum of all IOH for PA[4:0] on PORTA must not exceed 200mA.
The sum of all IOH for PORTD and PORTR must not exceed 100mA.
The sum of all IOH for PORTC and PDI must not exceed 100mA.
2. The sum of all IOL for PA[7:5] on PORTA must not exceed 100mA.
The sum of all IOL for PA[4:0] on PORTA must not exceed 100mA.
The sum of all IOL for PORTD and PORTR must not exceed 100mA.
The sum of all IOL for PORTC PDI must not exceed 100mA.
36.6 ADC Characteristics
Table 36-7. Power supply, reference and input range.
Symbol
AVCC
VREF
Rin
Parameter
Condition
Min.
VCC- 0.3
1
Typ.
Max.
VCC+ 0.3
AVCC- 0.6
4.5
Units
V
Analog supply voltage
Reference voltage
Input resistance
V
Switched
kΩ
pF
Cin
Input capacitance
Reference input resistance
Switched
5
RAREF
CAREF
(leakage only)
>10
7
MΩ
pF
Reference input capacitance Static load
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Symbol
Vin
Parameter
Condition
Min.
0
Typ.
Max.
VREF
Units
Input range
V
V
V
Vin
Conversion range
Conversion range
Differential mode, Vinp - Vinn
-0.95*VREF
-0.05*VREF
0.95*VREF
0.95*VREF
Vin
Single ended unsigned mode, Vinp
Table 36-8. Clock and timing.
Symbol
ClkADC
fClkADC
Parameter
Condition
Min.
Typ.
Max.
Units
kHz
Maximum is 1/4 of Peripheral clock
frequency
100
1800
ADC Clock frequency
Sample rate
Measuring internal signals
125
16
16
300
300
250
150
50
ksps
Current limitation (CURRLIMIT) off
CURRLIMIT = LOW
fADC
Sample rate
ksps
µs
CURRLIMIT = MEDIUM
CURRLIMIT = HIGH
Sampling Time
1/2 ClkADC cycle
0.25
6
5
(RES+2)/2+(GAIN !=0)
RES (Resolution) = 8 or 12
ClkADC
cycles
Conversion time (latency)
10
24
ClkADC
cycles
Start-up time
ADC clock cycles
12
7
ClkADC
cycles
ADC settling time
After changing reference or input mode
7
Table 36-9. Accuracy characteristics.
Symbol
Parameter
Condition(2)
Min.
Typ.
12
11
12
1
Max.
12
Units
Differential
8
7
RES
Resolution
12-bit resolution
Single ended signed
11
Bits
Single ended unsigned
16kSPS, VREF = 3V
16kSPS, VREF = 1V
300kSPS, VREF = 3V
300kSPS, VREF = 1V
16kSPS, VREF = 3.0V
16kSPS, VREF = 1.0V
8
12
2
Differential mode
1
INL(1)
Integral non-linearity
lsb
2
1
1.5
3
Single ended
unsigned mode
2
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Symbol
Parameter
Condition(2)
16kSPS, VREF = 3V
Min.
Typ.
1
Max.
Units
16kSPS, VREF = 1V
300kSPS, VREF = 3V
300kSPS, VREF = 1V
16kSPS, VREF = 3.0V
16kSPS, VREF = 1.0V
2
Differential mode
1
DNL(1)
Differential non-linearity
lsb
2
1
1.5
3
Single ended
unsigned mode
2
8
mV
Offset Error
Differential mode
Temperature drift
Operating voltage drift
External reference
AVCC/1.6
0.01
0.25
-5
mV/K
mV/V
-5
mV
AVCC/2.0
-6
Gain Error
Differential mode
Bandgap
±10
0.02
2
Temperature drift
Operating voltage drift
External reference
AVCC/1.6
mV/K
mV/V
-8
-8
mV
AVCC/2.0
-8
Single ended
unsigned mode
Gain Error
Bandgap
±10
0.03
2
Temperature drift
Operating voltage drift
mV/K
mV/V
Notes:
1. Maximum numbers are based on characterisation and not tested in production, and valid for 10% to 90% input voltage range.
2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used.
Table 36-10. Gain stage characteristics.
Symbol
Rin
Csample
Parameter
Condition
Min.
Typ.
4.0
Max.
Units
kΩ
pF
Input resistance
Input capacitance
Signal range
Switched
Switched
4.4
Gain stage output
0
AVCC- 0.6
3
V
ClkADC
cycles
Propagation delay
Clock rate
ADC conversion rate
Same as ADC
1/2
100
1
1800
kHz
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Symbol
Parameter
Condition
Min.
Typ.
-1
Max.
Units
0.5x gain
1x gain
-1
Gain error
%
8x gain
-1
64x gain
0.5x gain
1x gain
-1.5
10
5
Offset error,
mV
input referred
8x gain
5
64x gain
5
36.7 DAC Characteristics
Table 36-11. Power supply, reference and output range.
Symbol
AVCC
Parameter
Condition
Min.
Typ.
Max.
VCC+ 0.3
VCC- 0.6
50
Units
Analog supply voltage
VCC- 0.3
1.0
AVREF
External reference voltage
DC output impedance
V
Ω
Rchannel
Linear output voltage range
Reference input resistance
Reference input capacitance Static load
Minimum Resistance load
0.15
VREF-0.15
V
RAREF
>10
7
MΩ
pF
kΩ
pF
nF
CAREF
1
100
Maximum capacitance load
1000Ω serial resistance
Operating within accuracy specification
Safe operation
1
AVCC/1000
10
Output sink/source
mA
Table 36-12. Clock and timing.
Symbol
Parameter
Condition
Min.
Typ.
Max.
1000
500
Units
Normal mode
0
0
fDAC
Conversion rate
Cload=100pF, maximum step size
ksps
Low power mode
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Table 36-13. Accuracy characteristics.
Symbol
Parameter
Condition
Min.
Typ.
Max.
12
Units
RES
Input Resolution
Bits
VCC = 1.6V
VCC = 3.6V
VCC = 1.6V
VCC = 3.6V
VCC = 1.6V
VCC = 3.6V
VCC = 1.6V
VCC = 3.6V
VCC = 1.6V
VCC = 3.6V
VCC = 1.6V
VCC = 3.6V
±2.0
±1.5
±2.0
±1.5
±5.0
±5.0
±1.5
±0.6
±1.0
±0.6
±4.5
±4.5
<4
±3
VREF= Ext 1.0V
VREF=AVCC
±2.5
±4
INL (1)
Integral non-linearity
lsb
±4
VREF=INT1V
VREF=Ext 1.0V
VREF=AVCC
3
1.5
3.5
1.5
DNL (1)
Differential non-linearity
lsb
VREF=INT1V
Gain error
After calibration
lsb
lsb
Gain calibration step size
Gain calibration drift
Offset error
4
VREF= Ext 1.0V
After calibration
<0.2
<1
mV/K
lsb
Offset calibration step size
1
Note:
1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% output voltage range.
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36.8 Analog Comparator Characteristics
Table 36-14. Analog comparator characteristics.
Symbol Parameter
Condition
Min.
Typ.
10
Max.
Units
mV
nA
Voff
Ilk
Input offset voltage
Input leakage current
Input voltage range
AC startup time
<10
50
-0.1
AVCC
V
50
0
µs
Vhys1
Vhys2
Vhys3
Hysteresis, none
Hysteresis, small
Hysteresis, large
VCC = 1.6V - 3.6V
mV
mV
mV
VCC = 1.6V - 3.6V
VCC = 1.6V - 3.6V
VCC = 3.0V, T= 85°C
VCC = 1.6V - 3.6V
12
28
22
21
30
40
tdelay
Propagation delay
ns
64-Level Voltage Scaler Integral non-
linearity (INL)
0.3
5
0.5
lsb
Current source accuracy after calibration
Current source calibration range
Current source calibration range
%
Single mode
Double mode
4
8
6
µA
µA
12
36.9 Bandgap and Internal 1.0V Reference Characteristics
Table 36-15. Bandgap and Internal 1.0V reference characteristics.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
As reference for ADC
As input voltage to ADC and AC
1 ClkPER + 2.5μs
Startup time
µs
1.5
1.1
BANDGAP
INT1V
Bandgap voltage
V
V
Internal 1.00V reference for ADC and DAC
Variation over voltage and temperature
T= 25°C, after calibration
Calibrated at T= 25°C
0.99
1.0
±3
1.01
%
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36.9.1 Brownout Detection Characteristics
Symbol
Parameter
Condition
Min.
Typ.
1.65
1.8
2.0
2.2
2.4
2.6
2.8
3.0
0.4
1.0
Max.
Units
BOD level 0 falling VCC
BOD level 1 falling VCC
BOD level 2 falling VCC
BOD level 3 falling VCC
BOD level 4 falling VCC
BOD level 5 falling VCC
BOD level 6 falling VCC
BOD level 7 falling VCC
1.50
1.75
VBOT
V
Continuous mode
Sampled mode
µs
TBOD
Detection time
Hysteresis
ms
BOD level 0 - 7. Min
value measured at
BOD level 0
VHYST
1.0
%
36.10 External Reset Characteristics
Table 36-16. External reset characteristics
Symbol
Parameter
Condition
Min.
90
Typ.
Max.
Units
tEXT
Minimum reset pulse width
1000
ns
VCC = 2.7 - 3.6V
VCC = 1.6 - 2.7V
VCC = 2.7 - 3.6V
VCC = 1.6 - 2.7V
0.6*VCC
0.6*VCC
Reset threshold voltage (VIH)
VRST
V
0.5*VCC
0.4*VCC
Reset threshold voltage (VIL)
Reset pin Pull-up Resistor
RRST
25
kΩ
36.11 Power-on Reset Characteristics
Table 36-17. Power-on reset characteristics.
Symbol
Parameter
Condition
Min.
0.4
Typ.
Max.
Units
VCC falls faster than 1V/ms
VCC falls at 1 V/ms or slower
1.0
1.3
1.3
(1)
VPOT-
POR threshold voltage falling VCC
V
V
0.8
VPOT+
POR threshold voltage raising VCC
1.59
Note:
1.
VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+.
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36.12 Flash and EEPROM Characteristics
Table 36-18. Endurance and data retention.
Parameter
Condition
Min.
10K
10K
2K
Typ.
Max.
Units
25°C
85°C
105°C
25°C
85°C
105°C
25°C
85°C
105°C
25°C
85°C
105°C
Write/Erase cycles
Cycle
Flash
100
25
Data retention
Year
Cycle
Year
10
100K
100K
30K
100
25
Write/Erase cycles
Data retention
EEPROM
10
Table 36-19. Programming time.
Parameter
Condition
Min.
Typ.(1)
Max.
Units
32KB Flash, EEPROM(2)
16KB Flash, EEPROM(2)
8KB Flash, EEPROM(2)
Page erase
50
45
42
4
Chip Erase
ms
ms
ms
Flash
Page write
4
Atomic page erase and write
Page erase
8
4
EEPROM
Page write
4
Atomic page erase and write
8
Notes:
1. Programming is timed from the 2MHz output of 8MHz internal oscillator.
2. EEPROM is not erased if the EESAVE fuse is programmed.
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36.13 Clock and Oscillator Characteristics
36.13.1 Calibrated 32.768kHz Internal Oscillator Characteristics
Table 36-20. 32.768kHz internal oscillator characteristics.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
kHz
%
Frequency
32.768
Factory calibration accuracy
User calibration accuracy
T = 25°C, VCC = 3.0V
-0.5
-0.5
0.5
0.5
%
36.13.2 Calibrated 8MHz Internal Oscillator Characteristics
Table 36-21. 8MHz internal oscillator characteristics.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
MHz
MHz
%
Frequency range
4.4
9.4
Factory calibrated frequency
Factory calibration accuracy
User calibration accuracy
8
T = 25°C, VCC = 3.0V
-0.5
-0.5
0.5
0.5
%
36.13.3 Calibrated and tunable 32MHz Internal Oscillator Characteristics
Table 36-22. 32MHz internal oscillator characteristics.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
DFLL can tune to this frequency over
voltage and temperature
Frequency range
30
55
MHz
Factory calibrated frequency
Factory calibration accuracy
User calibration accuracy
DFLL calibration step size
32
MHz
%
T = 25°C, VCC = 3.0V
-1.5
-0.2
1.5
0.2
%
0.23
%
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36.13.4 32 kHz Internal ULP Oscillator Characteristics
Table 36-23. 32 kHz internal ULP oscillator characteristics.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
kHz
%
Output frequency
Accuracy
32
-30
30
36.13.5 Internal Phase Locked Loop (PLL) Characteristics
Table 36-24. Internal PLL characteristics.
Symbol
Parameter
Condition
Output frequency must be within fOUT
VCC= 1.6 - 1.8V
Min.
0.4
20
Typ.
Max.
Units
fIN
Input frequency
64
48
MHz
fOUT
Output frequency (1)
MHz
VCC= 2.7 - 3.6V
20
128
Start-up time
Re-lock time
25
25
µs
µs
Note:
1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
36.13.6 External Clock Characteristics
Figure 36-3. External clock drive waveform.
tCH
tCH
tCR
tCF
VIH1
VIL1
tCL
tCK
Table 36-25. External clock used as system clock without prescaling.
Symbol
Parameter
Condition
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
Min.
0
Typ.
Max.
12
Units
1/tCK
Clock Frequency (1)
MHz
0
32
83.3
31.5
30.0
12.5
tCK
Clock Period
ns
ns
tCH
Clock High Time
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Symbol
Parameter
Condition
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
Min.
30.0
12.5
Typ.
Max.
Units
tCL
Clock Low Time
ns
10
3
tCR
Rise Time (for maximum frequency)
ns
10
3
tCF
Fall Time (for maximum frequency)
ns
%
ΔtCK
Change in period from one clock cycle to the next
10
Note:
1. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
Table 36-26. External clock with prescaler (1)for system clock.
Symbol Parameter
Condition
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
Min.
0
Typ.
Max.
90
Units
1/tCK
Clock Frequency (2)
Clock Period
MHz
0
142
11
tCK
ns
ns
ns
ns
7
4.5
2.4
4.5
2.4
tCH
Clock High Time
tCL
Clock Low Time
1.5
1.0
1.5
1.0
10
tCR
Rise Time (for maximum frequency)
tCF
Fall Time (for maximum frequency)
ns
%
ΔtCK
Change in period from one clock cycle to the next
Notes:
1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
2. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
36.13.7 External 16MHz Crystal Oscillator and XOSC Characteristics
Table 36-27. External 16MHz crystal oscillator and XOSC characteristics.
Symbol Parameter
Condition
Min.
Typ.
<10
<1
Max.
Units
FRQRANGE=0
XOSCPWR=0
XOSCPWR=1
Cycle to cycle jitter
FRQRANGE=1, 2, or 3
ns
<1
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Symbol Parameter
Condition
Min.
Typ.
<6
Max.
Units
FRQRANGE=0
XOSCPWR=0
XOSCPWR=1
Long term jitter
FRQRANGE=1, 2, or 3
<0.5
<0.5
<0.1
<0.05
<0.005
<0.005
40
ns
FRQRANGE=0
FRQRANGE=1
FRQRANGE=2 or 3
XOSCPWR=0
XOSCPWR=1
XOSCPWR=0
XOSCPWR=1
Frequency error
%
%
FRQRANGE=0
FRQRANGE=1
FRQRANGE=2 or 3
42
Duty cycle
45
48
0.4MHz resonator,
CL=100pF
XOSCPWR=0,
FRQRANGE=0
1MHz crystal, CL=20pF
2MHz crystal, CL=20pF
2MHz crystal
XOSCPWR=0,
FRQRANGE=1,
CL=20pF
8MHz crystal
9MHz crystal
8MHz crystal
XOSCPWR=0,
FRQRANGE=2,
CL=20pF
9MHz crystal
12MHz crystal
9MHz crystal
XOSCPWR=0,
FRQRANGE=3,
CL=20pF
12MHz crystal
16MHz crystal
9MHz crystal
Negative impedance (1)
Ω
RQ
XOSCPWR=1,
FRQRANGE=0,
CL=20pF
12MHz crystal
16MHz crystal
9MHz crystal
XOSCPWR=1,
FRQRANGE=1,
CL=20pF
12MHz crystal
16MHz crystal
12MHz crystal
XOSCPWR=1,
FRQRANGE=2,
CL=20pF
16MHz crystal
12MHz crystal
16MHz crystal
XOSCPWR=1,
FRQRANGE=3,
CL=20pF
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Symbol Parameter
Condition
Min.
Typ.
Max.
Units
ESR
SF=Safety factor
min(RΩ)SF
kΩ
Parasitic capacitance
XTAL1 pin
CXTAL1
CXTAL2
CLOAD
5.4
7.1
Parasitic capacitance
XTAL2 pin
pF
Parasitic capacitance
load
3.07
Note:
1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization.
36.13.8 External 32.768kHz Crystal Oscillator and TOSC Characteristics
Table 36-28. External 32.768kHz crystal oscillator and TOSC characteristics.
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
Crystal load capacitance 6.5pF
Crystal load capacitance 9.0pF
60
35
Recommended crystal equivalent
series resistance (ESR)
ESR/R1
kΩ
CTOSC1
CTOSC2
Parasitic capacitance TOSC1 pin
Parasitic capacitance TOSC2 pin
5.3
7.4
pF
pF
capacitance load matched to
crystal specification
Recommended safety factor
3.0
Note:
1. See Figure 36-4 for definition.
Figure 36-4. TOSC input capacitance.
CL1
CL2
Device internal
External
TOSC1
TOSC2
32.768kHz crystal
The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating without
external capacitors.
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36.14 SPI Characteristics
Figure 36-5. SPI timing requirements in master mode.
SS
tMOS
tSCKR
tSCKF
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS
tMIH
MSB
tSCK
MISO
(Data Input)
LSB
tMOH
tMOH
MOSI
(Data Output)
MSB
LSB
Figure 36-6. SPI timing requirements in slave mode.
SS
tSSS
tSCKR
tSCKF
tSSH
SCK
(CPOL = 0)
tSSCKW
SCK
(CPOL = 1)
tSSCKW
tSIS
tSIH
MSB
tSSCK
LSB
MOSI
(Data Input)
tSOSSS
tSOS
tSOSSH
MISO
(Data Output)
MSB
LSB
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Table 36-29. SPI timing characteristics and requirements.
Symbol Parameter Condition
Min.
Typ.
Max.
Units
tSCK
tSCKW
tSCKR
tSCKF
tMIS
SCK period
Master
Master
Master
Master
Master
Master
Master
Master
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
SCK high/low width
SCK rise time
0.5×SCK
2.7
SCK fall time
2.7
MISO setup to SCK
MISO hold after SCK
MOSI setup SCK
MOSI hold after SCK
Slave SCK Period
SCK high/low width
SCK rise time
10
tMIH
10
tMOS
tMOH
tSSCK
tSSCKW
tSSCKR
tSSCKF
tSIS
0.5×SCK
1.0
4×t ClkPER
2×t ClkPER
ns
1600
1600
SCK fall time
MOSI setup to SCK
MOSI hold after SCK
SS setup to SCK
SS hold after SCK
MISO setup SCK
MISO hold after SCK
MISO setup after SS low
MISO hold after SS high
3.0
t ClkPER
21
tSIH
tSSS
tSSH
20
tSOS
8.0
13
tSOH
tSOSS
tSOSH
11
8.0
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36.15 Two-Wire Interface Characteristics
Table 36-6 on page 77 describes the requirements for devices connected to the two-wire interface (TWI) Bus. The Atmel
AVR XMEGA TWI meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 36-
7.
Figure 36-7. Two-wire interface bus timing
tof
tHIGH
tLOW
tr
SCL
SDA
tHD;DAT
tSU;STA
tSU;STO
tSU;DAT
tHD;STA
tBUF
Table 36-30. Two-wire interface characteristics.
Symbol
VIH
Parameter
Condition
Min.
0.7VCC
-0.5
Typ.
Max.
VCC+0.5
0.3VCC
Units
Input high voltage
V
V
V
V
VIL
Input low voltage
(1)
Vhys
VOL
Hysteresis of Schmitt trigger inputs
Output low voltage
0.05VCC
3mA, sink current
fSCL ≤ 400kHz
fSCL ≤ 1MHz
0
3
0.4
IOL
Low level output current
VOL = 0.4V
mA
ns
20
(1)(2)
(1)(2)
fSCL ≤ 400kHz
fSCL ≤ 1MHz
20+0.1Cb
300
120
tr
Rise time for both SDA and SCL
Output fall time from VIHmin to VILmax
fSCL ≤ 400kHz
fSCL ≤ 1MHz
20+0.1Cb
250
10pF< Cb
<400pF(2)
tof
ns
120
tSP
II
Spikes suppressed by Input filter
Input current for each I/O Pin
Capacitance for each I/O Pin
SCL clock frequency
0
50
ns
µA
0.1 VCC <VI <0.9 VCC
-10
10
CI
10
pF
fSCL
fPER(3) > max(10fSCL,250kHz)
fSCL ≤ 100kHz
0
1
MHz
100ns/Cb
300ns/Cb
550ns/Cb
(VCC-0.4V)
/IOL
RP
Value of pull-up resistor
fSCL ≤ 400kHz
Ω
fSCL ≤ 1MHz
fSCL ≤ 100kHz
4
Hold time (repeated) START
condition
tHD;STA
fSCL ≤ 400kHz
0.6
0.26
µs
fSCL ≤ 1MHz
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Symbol
Parameter
Condition
Min.
4.7
1.3
0.5
4
Typ.
Max.
Units
fSCL ≤ 100kHz
fSCL ≤ 400kHz
fSCL ≤ 1MHz
fSCL ≤ 100kHz
fSCL ≤ 400kHz
fSCL ≤ 1MHz
fSCL ≤ 100kHz
fSCL ≤ 400kHz
fSCL ≤ 1MHz
fSCL ≤ 100kHz
fSCL ≤ 400kHz
fSCL ≤ 1MHz
fSCL ≤ 100kHz
fSCL ≤ 400kHz
fSCL ≤ 1MHz
fSCL ≤ 100kHz
fSCL ≤ 400kHz
fSCL ≤ 1MHz
fSCL ≤ 100kHz
fSCL ≤ 400kHz
fSCL ≤ 1MHz
tLOW
Low period of SCL Clock
µs
tHIGH
High period of SCL Clock
0.6
0.26
4.7
0.6
0.26
0
µs
µs
µs
ns
µs
µs
Set-up time for a repeated START
condition
tSU;STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
3.45
0.9
Data hold time
0
0
0.45
250
100
50
Data setup time
4
Setup time for STOP condition
0.6
0.26
4.7
1.3
0.5
Bus free time between a STOP and
START condition
Notes:
1.
2.
3.
Required only for fSCL > 100kHz.
Cb = Capacitance of one bus line in pF.
fPER = Peripheral clock frequency.
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37. Typical Characteristics
37.1 Current consumption
37.1.1 Active Mode Supply Current
Figure 37-1. Active mode supply current vs. frequency.
fSYS = 0 – 1MHz external clock, T = 25°C
V_CC_
1.6
1.8
2.2
2.7
3
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
3.6
0.0
0.2
0.4
0.6
0.8
1.0
Frequency [MHz]
Figure 37-2. Active mode supply current vs. frequency.
fSYS = 0 – 32MHz external clock, T = 25°C
V_CC_
1.6
1.8
2.2
2.7
3
9
8
7
6
5
4
3
2
1
0
3.6
0
4
8
12
16
20
24
28
32
Frequency [MHz]
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Figure 37-3. Active mode supply current vs. VCC
.
fSYS = 32.768kHz internal oscillator
Temperature
-40
25
38.0
37.0
36.0
35.0
34.0
33.0
32.0
31.0
30.0
29.0
28.0
27.0
85
105
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
Figure 37-4. Active mode supply current vs. VCC
.
fSYS = 1MHz external clock
Temperature
-40
25
0.35
0.30
0.25
0.20
0.15
0.10
85
105
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
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Figure 37-5. Active mode supply current vs. VCC
.
fSYS = 8MHz internal oscillator prescaled to 2MHz
Temperature
-40
25
0.8
0.7
0.6
0.5
0.4
0.3
0.2
85
105
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
Figure 37-6. Active mode supply current vs. VCC
.
fSYS = 8MHz internal oscillator
Temperature
-40
25
2.5
2.0
1.5
1.0
0.5
85
105
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
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Figure 37-7. Active mode supply current vs. VCC
.
fSYS = 32MHz internal oscillator prescaled to 8MHz
Temperature
-40
25
3.0
2.5
2.0
1.5
1.0
85
105
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
Figure 37-8. Active mode supply current vs. VCC
.
fSYS = 32MHz internal oscillator
Temperature
-40
25
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
85
105
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
Vcc [V]
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37.1.2 Idle Mode Supply Current
Figure 37-9. Idle mode supply current vs. frequency.
fSYS = 0 - 1MHz external clock, T = 25°C.
V_CC_
1.600
1.800
2.200
2.700
3.000
3.600
150
125
100
75
50
25
0
0.0
0.2
0.4
0.6
0.8
1.0
Frequency [MHz]
Figure 37-10.Idle mode supply current vs. frequency.
fSYS = 1 - 32MHz external clock, T = 25°C.
V_CC_
1.6
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.8
2.2
2.7
3
3.6
0
4
8
12
16
20
24
28
32
Frequency [MHz]
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Figure 37-11.Idle mode supply current vs. VCC
.
fSYS = 32.768kHz internal oscillator
Temperature
-40
25
32
31
30
29
28
27
26
25
85
105
1.6
1.8
2.0
2.2
2.4
2.6
Vcc [V]
2.8
3.0
3.2
3.4
3.6
Figure 37-12.Idle mode supply current vs. VCC
.
fSYS = 1MHz external clock
Temperature
-40
25
55.5
54.0
52.5
51.0
49.5
48.0
46.5
45.0
85
105
1.6
1.8
1.700
2.2
2.4
2.6
Vcc [V]
2.8
1.800
3.2
3.4
3.6
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Figure 37-13.Idle mode supply current vs. VCC
.
fSYS = 8MHz internal oscillator prescaled to 2MHz
Temperature
-40
25
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
85
105
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
Figure 37-14.Idle mode supply current vs. VCC
.
fSYS = 8MHz internal oscillator.
Temperature
-40
25
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
85
105
1.6
1.8
2.0
2.2
2.4
2.6
Vcc [V]
2.8
3.0
3.2
3.4
3.6
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Figure 37-15.Idle mode supply current vs. VCC
.
fSYS = 32MHz internal oscillator prescaled to 8MHz.
Temperature
-40
25
1.8
1.6
1.4
1.2
1.0
0.8
0.6
85
105
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
Figure 37-16.Idle mode supply current vs. VCC
.
fSYS = 32MHz internal oscillator.
Temperature
-40
25
4.5
4.0
3.5
3.0
2.5
85
105
2.6
2.7
2.8
2.9
3.0
3.1
Vcc [V]
3.2
3.3
3.4
3.5
3.6
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37.1.3 Power-down Mode Supply Current
Figure 37-17.Power-down mode supply current vs. temperature.
All functions disabled.
V_CC_
1.6
1.8
2.2
2.7
3
3.00
2.70
2.40
2.10
1.80
1.50
1.20
0.90
0.60
0.30
0.00
3.6
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
Figure 37-18.Power-down mode supply current vs. VCC
.
All functions disabled.
Temperature
-40
25
3.00
2.70
2.40
2.10
1.80
1.50
1.20
0.90
0.60
0.30
0.00
85
105
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
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Figure 37-19.Power-down mode supply current vs. temperature.
Sampled BOD with Watchdog Timer running on ULP oscillator.
0.760
0.755
0.750
0.745
0.740
0.735
0.730
0.725
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
37.1.4 Power-save Mode Supply Current
Figure 37-20.Power-save mode supply current vs. VCC
.
Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC.
1.100
1.050
1.000
0.950
0.900
0.850
0.800
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
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37.1.5 Standby Mode Supply Current
Figure 37-21.Standby supply current vs. VCC
.
Standby, fSYS = 1MHz.
Temperature
-40
25
10
9
8
7
6
5
4
3
2
1
85
105
1.6
1.8
2.0
2.2
2.4
2.6
Vcc [V]
2.8
3.0
3.2
3.4
3.6
Figure 37-22.Standby supply current vs. VCC
.
25°C, running from different crystal oscillators.
500
Crystals
16.0MHz
450
400
350
300
250
200
150
12.0MHz
8.0MHz
2.0MHz
0.455MHz
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
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37.2 I/O Pin Characteristics
37.2.1 Pull-up
Figure 37-23.I/O pin pull-up resistor current vs. input voltage.
VCC = 1.8V.
Temperature
-40
25
10
0
85
-10
-20
-30
-40
-50
-60
-70
105
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
VPIN [V]
Figure 37-24.I/O pin pull-up resistor current vs. input voltage.
VCC = 3.0V.
Temperature
-40
25
20
0
85
-20
-40
-60
-80
-100
-120
105
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
VPIN [V]
XMEGA E5 [DATASHEET]
Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014
105
Figure 37-25.I/O pin pull-up resistor current vs. input voltage.
VCC = 3.3V.
Temperature
-40
25
0
-50
85
105
-100
-150
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
VPIN [V]
37.2.2 Output Voltage vs. Sink/Source Current
Figure 37-26.I/O pin output voltage vs. source current.
VCC = 1.8V.
Temperature
25
1.80
1.75
1.70
1.65
1.60
1.55
85
105
-40
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
IPIN [mA]
XMEGA E5 [DATASHEET]
Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014
106
Figure 37-27.I/O pin output voltage vs. source current.
VCC = 3.0V.
Temperature
25
85
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
105
-40
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
IPIN [mA]
Figure 37-28.I/O pin output voltage vs. source current.
VCC = 3.3V.
Temperature
25
85
3.3
3.2
3.1
3.0
2.9
2.8
2.7
2.6
105
-40
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
IPIN [mA]
XMEGA E5 [DATASHEET]
Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014
107
Figure 37-29.I/O pin output voltage vs. source current.
V_CC_
1.6
1.8
2.7
3
4.0
3.5
3.0
3.3
3.6
2.5
2.0
1.5
1.0
0.5
-18
-15
-12
-9
-6
-3
0
IPIN [mA]
Figure 37-30.I/O pin output voltage vs. sink current.
VCC = 1.8V.
Temperature
25
85
0.30
0.25
0.20
0.15
0.10
0.05
0.00
105
-40
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
IPIN [mA]
XMEGA E5 [DATASHEET]
Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014
108
Figure 37-31.I/O pin output voltage vs. sink current.
VCC = 3.0V.
Temperature
25
85
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
105
-40
0
2
4
6
8
10
12
14
16
18
20
IPIN [mA]
Figure 37-32.I/O pin output voltage vs. sink current.
VCC = 3.3V.
Temperature
25
85
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
105
-40
0
2
4
6
8
10
12
14
16
18
20
IPIN [mA]
XMEGA E5 [DATASHEET]
Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014
109
Figure 37-33.I/O pin output voltage vs. sink current.
V_CC_
1.6
1.8
2.7
3
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
3.3
3.6
0
2
4
6
8
10
12
14
16
18
20
IPIN [mA]
37.2.3 Thresholds and Hysteresis
Figure 37-34.I/O pin input threshold voltage vs. VCC.
T = 25°C.
Test Info
VIH
VIL
1.65
1.50
1.35
1.20
1.05
0.90
0.75
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
XMEGA E5 [DATASHEET]
Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014
110
Figure 37-35.I/O pin input threshold voltage vs. VCC
.
VIH I/O pin read as “1”
Temperature
-40
25
1.80
1.60
1.40
1.20
1.00
0.80
0.60
85
105
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
Figure 37-36.I/O pin input threshold voltage vs. VCC
.
VIL I/O pin read as “0”
Temperature
-40
25
1.80
1.60
1.40
1.20
1.00
0.80
0.60
85
105
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
XMEGA E5 [DATASHEET]
Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014
111
Figure 37-37.I/O pin input hysteresis vs. VCC
.
Temperature
-40
25
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
85
105
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
37.3 ADC Characteristics
Figure 37-38.ADC INL vs. VREF
.
T = 25°C, VCC = 3.6V, external reference.
Mode
Single-ended unsigned mode
Single-ended signed mode
Differential mode
1.75
1.50
1.25
1.00
0.75
0.50
0.25
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Vref [V]
XMEGA E5 [DATASHEET]
Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014
112
Figure 37-39.ADC INL error vs. VCC
.
T = 25°C, VREF = 1.0V
Mode
Single-ended unsigned mode
Single-ended signed mode
Differential mode
1.80
1.60
1.40
1.20
1.00
0.80
0.60
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
Figure 37-40.ADC DNL error vs. VREF
.
SE Unsigned mode, T=25°C, VCC = 3.6V, external reference.
0.75
0.70
0.65
0.60
0.55
0.50
0.45
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Vref [V]
XMEGA E5 [DATASHEET]
Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014
113
Figure 37-41. ADC gain error vs. VCC
.
T = 25°C, VREF = 1.0V, ADC sample rate = 300ksps.
Mode
Single-ended signed mode
Differential mode
0.0
-1.0
-2.0
-3.0
-4.0
-5.0
Single-ended unsigned mode
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
Figure 37-42. ADC gain error vs. VREF
.
T = 25°C, VCC = 3.6V, ADC sample rate = 300ksps
Mode
Single-ended signed mode
Differential mode
0.0
-2.0
Single-ended unsigned mode
-4.0
-6.0
-8.0
-10.0
-12.0
-14.0
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Vref [V]
XMEGA E5 [DATASHEET]
Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014
114
Figure 37-43. ADC gain error vs. temperature.
VCC = 3.6V, VREF = 1.0V, ADC sample rate = 300ksps
Mode
Single-ended signed mode
Differential mode
0.0
-1.0
-2.0
-3.0
-4.0
-5.0
-6.0
-7.0
Single-ended unsigned mode
-40
-20
0
20
40
60
80
100
Temperature [°C]
Figure 37-44. ADC offset error vs. VCC
.
T = 25°C, VREF = 1.0V, ADC sample rate = 300ksps
Mode
Single-ended unsigned mode
Single-ended signed mode
Differential mode
25.0
20.0
15.0
10.0
5.0
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
XMEGA E5 [DATASHEET]
Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014
115
Figure 37-45. ADC offset error vs. VREF
.
T = 25°C, VCC = 3.6V, ADC sample rate = 300ksps
Mode
Single-ended unsigned mode
Single-ended signed mode
Differential mode
30.0
25.0
20.0
15.0
10.0
5.0
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Vref [V]
Figure 37-46.ADC gain error vs. temperature.
VCC = 3.6V, VREF = external 1.0V, sample rate = 300ksps
Mode
Single-ended signed mode
Differential mode
0.0
-1.0
-2.0
-3.0
-4.0
-5.0
-6.0
-7.0
Single-ended unsigned mode
-40
-20
0
20
40
60
80
100
Temperature [°C]
XMEGA E5 [DATASHEET]
Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014
116
37.4 DAC Characteristics
Figure 37-47.DAC INL error vs. external VREF
.
T = 25°C, VCC = 3.6V
2.2
2.1
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Vref [V]
Figure 37-48.DNL error vs. VREF
.
T = 25°C, VCC = 3.6V
Mode
Single-ended unsigned mode
Single-ended signed mode
Differential mode
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Vref [V]
XMEGA E5 [DATASHEET]
Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014
117
Figure 37-49.DNL error vs. VCC
.
T = 25°C, VREF = 1.0V
Mode
Single-ended unsigned mode
Single-ended signed mode
Differential mode
0.80
0.70
0.60
0.50
0.40
0.30
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
37.5 AC Characteristics
Figure 37-50.Analog comparator hysteresis vs. VCC
.
Small hysteresis
16
14
12
10
8
Temperature (°C)
85
25
-40
6
4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
XMEGA E5 [DATASHEET]
Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014
118
Figure 37-51.Analog comparator hysteresis vs. VCC
.
Large hysteresis
34
32
30
28
26
24
22
20
18
16
14
Temperature (°C)
85
25
-40
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
Figure 37-52.Analog comparator propagation delay vs. VCC
.
26
24
22
20
18
16
14
12
10
Temperature (°C)
85
25
-40
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Vcc [V]
Figure 37-53.Analog comparator propagation delay vs. temperature.
26
24
22
20
18
16
14
12
10
Vcc (V)
1.6
2
2.7
3
3.3
3.6
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature [°C]
XMEGA E5 [DATASHEET]
Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014
119
Figure 37-54.Analog comparator current consumption vs. VCC
.
Temperature
-40
25
240
230
220
210
200
190
180
170
160
150
85
105
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
Figure 37-55.Analog comparator voltage scaler vs. SCALEFAC.
T = 25°C, VCC = 3.0V
0.050
0.025
0
-0.025
-0.050
-0.075
-0.100
-0.125
-0.150
25°C
0
10
20
30
40
50
60
70
SCALEFAC
XMEGA E5 [DATASHEET]
Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014
120
Figure 37-56.Analog comparator offset voltage vs. common mode voltage.
35
Temperature (°C)
-40
25
85
30
25
20
15
10
5
0
0
0.4
0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
Vcm [V]
Figure 37-57.Analog comparator source vs. calibration value.
VCC = 3.0V
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
Temperature (°C)
-40
25
85
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CALIB [3..0]
Figure 37-58.Analog comparator source vs. calibration value.
T = 25°C
8.0
7.0
6.0
5.0
4.0
3.0
2.0
Vcc [V]
3.6
3
2.2
1.8
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CALIB [3..0]
XMEGA E5 [DATASHEET]
Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014
121
37.6 Internal 1.0V Reference Characteristics
Figure 37-59.ADC/DAC internal 1.0V reference vs. temperature.
Vcc
1.6
1.8
2.2
2.7
3
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.980
3.3
3.6
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100 110
Temperature [°C]
37.7 BOD Characteristics
Figure 37-60.BOD thresholds vs. temperature.
BOD level = 1.6V
Test Info
fall
1.70
1.69
1.68
1.67
1.66
1.65
1.64
1.63
1.62
1.61
rise
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
XMEGA E5 [DATASHEET]
Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014
122
Figure 37-61.BOD thresholds vs. temperature.
BOD level = 3.0V
Test Info
fall
rise
3.10
3.05
3.00
2.95
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
37.8 External Reset Characteristics
Figure 37-62.Minimum reset pin pulse width vs. VCC
.
T [°C]
-40
25
140
130
120
110
100
90
85
105
80
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
XMEGA E5 [DATASHEET]
Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014
123
Figure 37-63.Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 1.8V
Temperature
-40
25
10
0
85
-10
-20
-30
-40
-50
-60
-70
-80
105
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
VRESET [V]
Figure 37-64.Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 3.0V
Temperature
-40
25
25
0
85
105
-25
-50
-75
-100
-125
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
VRESET [V]
XMEGA E5 [DATASHEET]
Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014
124
Figure 37-65.Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 3.3V
Temperature
-40
25
0
-25
85
105
-50
-75
-100
-125
-150
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
VRESET [V]
Figure 37-66.Reset pin input threshold voltage vs. VCC.
VIH - Reset pin read as “1”
T [°C]
-40
25
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
85
105
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
XMEGA E5 [DATASHEET]
Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014
125
Figure 37-67.Reset pin input threshold voltage vs. VCC.
VIL - Reset pin read as “0”
T [°C]
-40
25
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
85
105
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
37.9 Power-on Reset Characteristics
Figure 37-68.Power-on reset current consumption vs. VCC
.
BOD level = 3.0V, enabled in continuous mode
T [°C]
-40
25
700
600
500
400
300
200
100
0
85
105
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
V_CC_ [V]
XMEGA E5 [DATASHEET]
Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014
126
Figure 37-69.Power-on reset current consumption vs. VCC
.
BOD level = 3.0V, enabled in sampled mode
T [°C]
-40
25
650
585
520
455
390
325
260
195
130
65
85
105
0
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
V_CC_ [V]
XMEGA E5 [DATASHEET]
Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014
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37.10 Oscillator Characteristics
37.10.1 Ultra Low-Power Internal Oscillator
Figure 37-70. Ultra Low-Power internal oscillator frequency vs. temperature.
V_CC_
1.6
1.8
2.2
2.7
3
37
36
35
34
33
32
31
30
29
28
3.6
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
37.10.2 32.768KHz Internal Oscillator
Figure 37-71. 32.768kHz internal oscillator frequency vs. temperature.
V_CC_
1.6
1.8
2.2
2.7
3
33.00
32.90
32.80
32.70
32.60
3.6
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
XMEGA E5 [DATASHEET]
Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014
128
Figure 37-72. 32.768kHz internal oscillator frequency vs. calibration value.
VCC = 3.0V
Temperature
-40
25
50.00
45.00
40.00
35.00
30.00
25.00
20.00
85
105
0
24
48
72
96
120
144
168
192
216
240
264
CAL
Figure 37-73. 32.768kHz internal oscillator calibration step size.
VCC = 3.0V, T = 25°C to 105°C
Temperature
-40
25
1.00
0.00
85
105
-1.00
-2.00
-3.00
-4.00
-5.00
0
32
64
96
128
160
192
224
256
CAL
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37.10.3 8MHz Internal Oscillator
Figure 37-74. 8MHz internal oscillator frequency vs. temperature.
Normal mode
V_CC_[V]
1.6
1.8
2.2
2.7
3
8.160
8.140
8.120
8.100
8.080
8.060
8.040
8.020
8.000
7.980
7.960
3.6
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
Figure 37-75. 8MHz internal oscillator frequency vs. temperature.
Low power mode
V_CC_
1.6
8.160
8.140
8.120
8.100
8.080
8.060
8.040
8.020
8.000
7.980
1.8
2.2
2.7
3
3.6
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
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Figure 37-76. 8MHz internal oscillator CAL calibration step size.
VCC = 3.0V
Temperature
-40
25
1.50
1.25
1.00
0.75
0.50
0.25
0.00
85
105
0
32
64
96
128
160
192
224
256
CAL
Figure 37-77. 8MHz internal oscillator frequency vs. calibration.
VCC = 3.0V, Normal mode
Temperature
-40
25
16.000
14.000
12.000
10.000
8.000
85
105
6.000
4.000
2.000
0
32
64
96
128
160
192
224
256
CAL
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37.10.4 32MHz Internal Oscillator
Figure 37-78. 32MHz internal oscillator frequency vs. temperature.
DFLL disabled
V_CC_[V]
1.6
1.8
2.2
2.7
3
34.00
33.50
33.00
32.50
32.00
31.50
31.00
30.50
30.00
3.6
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100 110
Figure 37-79. 32MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator
V_CC_ [V]
1.6
1.8
2.2
2.7
3
32.10
32.08
32.06
32.04
32.02
32.00
31.98
31.96
31.94
31.92
31.90
31.88
3.6
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
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Figure 37-80. 32MHz internal oscillator CALA calibration step size.
VCC = 3.0V
Temperature
-40
25
0.25
0.24
0.23
0.22
0.21
0.20
0.19
0.18
0.17
0.16
0.15
85
105
0
16
32
48
64
80
96
112
128
CALA
Figure 37-81. 32MHz internal oscillator frequency vs. CALA calibration value.
VCC = 3.0V
Temperature
-40
25
54
52
50
48
46
44
42
40
38
85
105
0
16
32
48
64
80
96
112
128
CALA
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Figure 37-82. 32MHz internal oscillator frequency vs. CALB calibration value.
VCC = 3.0V
Temperature
-40
25
70.00
60.00
50.00
40.00
30.00
20.00
85
105
0
8
16
24
32
40
48
56
64
CALB
37.11 Two-wire Interface Characteristics
Figure 37-83. SDA fall time vs. temperature.
80
70
60
50
40
30
20
10
Mode
STD
FAST
FAST +
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
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Figure 37-84. SDA fall time vs. VCC
.
70
60
50
40
30
20
10
Mode
STD
FAST
FAST +
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Vcc [V]
37.12 PDI Characteristics
Figure 37-85. Maximum PDI frequency vs. VCC
.
T [°C]
-40
25
24
21
18
15
12
9
85
105
6
1.6
1.8
2.0
2.2
2.4
2.6
Vcc [V]
2.8
3.0
3.2
3.4
3.6
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38. Errata – ATxmega32E5 / ATxmega16E5 / ATxmega8E5
38.1 Rev. B
z
z
z
z
z
z
z
z
DAC: AREF on PD0 is not available for the DAC
ADC: Offset correction fails in unsigned mode
EEPROM write and Flash write operations fails under 2.0V
TWI Master or slave remembering data
TWI SM bus level one Master or slave remembering data
Temperature Sensor not calibrated
Automatic port override on PORT C
Sext timer is not implemented in slave mode
Issue:
DAC: AREF on PD0 is not available for the DAC
The AREF external reference input on pin PD0 is not available for the DAC.
Workaround:
No workaround. Only AREF on pin PA0 can be used as external reference input for the DAC.
Issue:
ADC: Offset correction fails in unsigned mode
In single ended, unsigned mode, a problem appears in low saturation (zero) when the offset correction is acti-
vated. The offset is removed from result and when a negative result appears, the result is not correct.
Workaround:
No workaround, but avoid using this correction method to cancel ΔV effect.
Issue:
EEPROM write and Flash write operations fails under 2.0V
EEPROM write and Flash write operations are limited from 2.0V to 3.6V. Other functionalities operates from 1.6V
to 3.6V.
Workaround:
None.
Issue:
TWI master or slave remembering data
If a write is made to Data register, prior to Address register, the TWI design sends the data as soon as the write to
Address register is made. But the send data will be always 0x00.
Workaround:
None.
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Issue:
TWI SM bus level one Master or slave remembering data
If a write is made to Data register, prior to Address register, the TWI design sends the data as soon as the write to
Address register is made. But the send data will be always 0x00.
Workaround:
Since single interrupt line is shared by both timeout interrupt and other TWI interrupt sources, there is a possibility
in software that data register will be written after timeout is detected but before timeout interrupt routine is exe-
cuted. To avoid this, in software, before writing data register, always ensure that timeout status flag is not set.
Issue:
Temperature Sensor not calibrated
Temperature sensor factory calibration is not implemented on devices before date code 1324.
Workaround:
None.
Issue:
Automatic port override on PORT C
When Waveform generation is enabled on PORT C Timers, Automatic port override of peripherals other than Tc
may not work even though the pin is not used as waveform output pin.
Workaround:
No workaround.
Issue:
Sext timer is not implemented in slave mode
In slave mode, only Ttout timer is implemented. Sext timer is needed in slave mode to release the SCL line
and to allow the master to send a STOP condition. If only master implements Sext timer, slave continues to stretch
the SCL line (up to the Ttout timeout in the worse case). Sext = Slave cumulative timeout
Workaround:
No workaround.
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38.2 Rev. A
z
z
z
z
z
z
z
z
z
z
z
z
z
z
DAC: AREF on PD0 is not available for the DAC
EDMA: Channel transfer never stops when double buffering is enabled on sub-sequent channels
ADC: Offset correction fails in unsigned mode
ADC: Averaging is failing when channel scan is enabled
ADC: Averaging in single conversion requires multiple conversion triggers
ADC accumulator sign extends the result in unsigned mode averaging
ADC: Free running average mode issue
ADC: Event triggered conversion in averaging mode
AC: Flag can not be cleared if the module is not enabled
USART: Receiver not functional when variable data length and start frame detector are enabled
T/C: Counter does not start when CLKSEL is written
EEPROM write and Flash write operations fails under 2.0V
TWI master or slave remembering data
Temperature Sensor not calibrated
Issue:
DAC: AREF on PD0 is not available for the DAC
The AREF external reference input on pin PD0 is not available for the DAC.
Workaround:
No workaround. Only AREF on pin PA0 can be used as external reference input for the DAC.
Issue:
EDMA: Channel transfer never stops when double buffering is enabled on sub-sequent
channels
When the double buffering is enabled on two channels, the channels which are not set in double buffering mode
are never disabled at the end of the transfer. A new transfer can start if the channel is not disabled by software.
Workaround:
z
CHMODE = 00
Enable double buffering on all channels or do not use channels which are not set the double buffering mode.
CHMODE = 01 or 10
z
Do not use the channel which is not supporting the double buffering mode.
Issue:
ADC: Offset correction fails in unsigned mode
In single ended, unsigned mode, a problem appears in low saturation (zero) when the offset correction is acti-
vated. The offset is removed from result and when a negative result appears, the result is not correct.
Workaround:
No workaround, but avoid using this correction method to cancel ΔV effect.
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Issue:
ADC: Averaging is failing when channel scan is enabled
For a correct operation, the averaging must complete on the on-going channel before incrementing the input off-
set. In the current implementation, the input offset is incremented after the ADC sampling is done.
Workaround:
None.
Issue:
ADC: Averaging in single conversion requires multiple conversion triggers
For a normal operation, an unique start of conversion trigger starts a complete average operation. Then, for N-
samples average operation, we should have:
z
z
z
One start of conversion
N conversions + average
Optional interrupt when the Nth conversion/last average is completed
On silicon we need:
z
N start of conversion
The two additional steps are well done.
Workaround:
Set averaging configuration
z
z
z
N starts of conversion by polling the reset of START bit
Wait for interrupt flag (end of averaging)
Issue:
ADC accumulator sign extends the result in unsigned mode averaging
In unsigned mode averaging, when the MSB is going high(1), measurements are considered as negative when
right shift is used. This sets the unused most significant bits once the shift is done.
Workaround:
Mask to zero the unused most significant bits once shift is done.
Issue:
ADC: Free running average mode issue
In free running mode the ADC stops the ongoing averaging as soon as free running bit is disabled. This creates
the need to flush the ADC before starting the next conversion since one or two conversions might have taken
place in the internal accumulator.
Workaround:
Disable and re-enable the ADC before the start of next conversion in free running average mode.
Issue:
ADC: Event triggered conversion in averaging mode
If the ADC is configured as event triggered in averaging mode, then a single event does not complete the entire
averaging as it should be.
Workaround:
In the current revision, N events are needed for completing averaging on N samples.
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Issue:
AC: Flag can not be cleared if the module is not enabled
It is not possible to clear the AC interrupt flags without enabling either of the analog comparators.
Workaround:
Clear the interrupt flags before disabling the module.
Issue:
USART: Receiver not functional when variable data length and start frame detector are
enabled
When using USART in variable frame length with XCL PEC01 configuration and start frame detection activated,
the USART receiver is not functional.
Workaround:
Use XCL BTC0PCE2 configuration instead of PEC01.
Issue:
T/C: Counter does not start when CLKSEL is written
When STOP bit is cleared (CTRLGCLR.STOP) before the timer/counter is enabled (CTRLA.CLKSEL != OFF), the
T/C doesn't start operation.
Workaround:
Do not write CTRLGCLR.STOP bit before writing CTRLA.CLKSEL bits.
Issue:
EEPROM write and Flash write operations fails under 2.0V
EEPROM write and Flash write operations are limited from 2.0V to 3.6V. Other functionalities operates from 1.6V
to 3.6V.
Workaround:
None.
Issue:
TWI master or Slave remembering data
If a write is made to Data register, prior to Address register, the TWI design sends the data as soon as the write to
Address register is made. But the send data will be always 0x00.
Workaround:
None.
Issue:
Temperature Sensor not calibrated
Temperature sensor factory calibration is not implemented.
Workaround:
None.
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39. Revision History
Please note that referring page numbers in this section are referred to this document. The referring revision in this
document section are referring to the document revision.
39.1 8153I – 08/2014
1.
2.
3.
Removed preliminary from the front page
Updated with ESR info in Table 36-27 on page 87.
Added errata on Automatic port override on PORT C in Section 38. “Errata – ATxmega32E5 / ATxmega16E5 /
ATxmega8E5” on page 136.
4.
Added errata on Sext timer not implemented in slave mode in Section 38. “Errata – ATxmega32E5 /
ATxmega16E5 / ATxmega8E5” on page 136.
39.2 8153H – 07/2014
1.
2.
“Ordering Information” on page 2: Added ordering codes for XMEGA E5 devices @105°C.
Electrical characteristics updates:
“Current Consumption” : Added power-down numbers for 105°C and updated values in Table 36-3 on page 74.
“ Flash and EEPROM Characteristics” : Added Flash and EEPROM write/erase cycles and data retention for
105°C in Table 36-18 on page 84.
3.
Changed Vcc to AVcc in Section 28. “ADC – 12-bit Analog to Digital Converter” on page 51 and in Section 30.1
“Features” on page 55.
4.
5.
32.768 KHz changed to 32 kHz in the heading in Section 36.13.4 on page 86 and in Table 36-23 on page 86.
Changed back page according to datasheet template 2014-0502
39.3 8153G – 10/2013
1.
Updated wake-up time from power-save mode for 32MHz internal oscillator from 0.2µs to 5.0µs in Table 36-5 on
page 76.
39.4 8153F – 08/2013
1.
TWI characteristics: Units of Data setup time (tSU;DAT) changed from µs to ns in Table 36-30 on page 92.
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39.5 8153E – 06/2013
1.
Errata “Rev. B” : Updated date code from 1318 to 1324 in “Temperature Sensor not calibrated” on page 137.
39.6 8153D – 06/2013
1.
Analog Comparator Characteristics: Updated minimum and maximum values of Input Voltage Range, Table 36-14
on page 82.
39.7 8153C – 05/2013
1.
2.
Electrical Characteristics, Table 36.3 on page 74: Updated typical value from 7mA to 6mA for Active Current
Consumption, 32MHz, VCC=3.0V.
Errata “Rev. A” and “Rev. B” : Added DAC errata: AREF on PORT C0.
39.8 8153B – 04/2013
1.
“Rev. B” on page 136: Removed the “EDMA: Channel transfer never stops when double buffering is enabled on
sub-sequent channels” errata.
39.9 8153A – 04/2013
1.
Initial revision.
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Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Pinout and Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5. Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5.1
Recommended reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6. Capacitive touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
7. CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ALU - Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Program Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Stack and Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
8. Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash Program Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Fuses and Lock bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
I/O Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Data Memory and Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.10 Device ID and Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.11 I/O Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.12 Flash and EEPROM Page Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9. EDMA – Enhanced DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10. Event System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
11. System Clock and Clock options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11.3 Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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12. Power Management and Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
12.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
12.3 Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
13. System Control and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
13.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
13.3 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
13.4 Reset Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
14. WDT – Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
14.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
15. Interrupts and Programmable Multilevel Interrupt Controller . . . . . . . . . . . . . . . . 28
15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
15.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
15.3 Interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
16. I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
16.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
16.3 Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
16.4 Input sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
16.5 Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
17. Timer Counter type 4 and 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
17.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
18. WeX – Waveform Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
18.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
19. Hi-Res – High Resolution Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
19.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
20. Fault Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
20.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
21. RTC – 16-bit Real-Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
21.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
21.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
22. TWI – Two Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
22.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
22.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
23. SPI – Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
23.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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23.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
24. USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
24.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
24.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
25. IRCOM – IR Communication Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
25.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
25.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
26. XCL – XMEGA Custom Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
26.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
26.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
27. CRC – Cyclic Redundancy Check Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
27.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
27.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
28. ADC – 12-bit Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
28.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
28.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
29. DAC – Digital to Analog Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
29.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
29.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
30. AC – Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
30.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
30.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
31. Programming and Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
31.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
31.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
32. Pinout and Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
32.1 Alternate Pin Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
32.2 Alternate Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
33. Peripheral Module Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
34. Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
35. Packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
35.1 32A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
35.2 32Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
35.3 32MA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
36. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
36.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
36.2 General Operating Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
36.3 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
36.4 Wake-up Time from Sleep Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
36.5 I/O Pin Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
36.6 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
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36.7 DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
36.8 Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
36.9 Bandgap and Internal 1.0V Reference Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
36.10 External Reset Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
36.11 Power-on Reset Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
36.12 Flash and EEPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
36.13 Clock and Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
36.14 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
36.15 Two-Wire Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
37. Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
37.1 Current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
37.2 I/O Pin Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
37.3 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
37.4 DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
37.5 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
37.6 Internal 1.0V Reference Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
37.7 BOD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
37.8 External Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
37.9 Power-on Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
37.10 Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
37.11 Two-wire Interface Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
37.12 PDI Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
38. Errata – ATxmega32E5 / ATxmega16E5 / ATxmega8E5 . . . . . . . . . . . . . . . . . . . . 136
38.1 Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
38.2 Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
39. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
39.1 8153I – 08/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
39.2 8153H – 07/2014. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
39.3 8153G – 10/2013. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
39.4 8153F – 08/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
39.5 8153E – 06/2013. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
39.6 8153D – 06/2013. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
39.7 8153C – 05/2013. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
39.8 8153B – 04/2013. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
39.9 8153A – 04/2013. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [PRELIMINARY DATASHEET]
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