PC7410M16VG450L_技术文档

Features

• PC7410 RISC Microprocessor

• Dedicated 2 MB SSRAM L2 Cache, Configured as 256Kx72

• 21 mm x 25 mm, 255 Ceramic Ball Grid Array

• Maximum Core Frequency = 400 MHz

• Maximum L2 Cache Frequency = 200 MHz

• Maximum 60x Bus Frequency = 100 MHz

Description

RISC

The PC7410M16 multichip package is targeted for high performance, space sensitive,

low power systems and supports the following power management features: doze,

nap, sleep and dynamic power management.

Microprocessor

Multichip

Package

Preliminary

Specification

α-site

The PC7410M16 is offered in industrial and military temperature ranges and is well

suited for embedded applications.

Screening

•

CBGA Upscreening Based on Atmel Standards

•

Full Military Temperature Range (T_j= -55°C, +125°C),

Industrial Temperature Range (T_j= -40°C, +110°C)

PC7410M16

SSRAM

PC7410

SSRAM

Rev. 2183A–HIREL–12/02

1

Block Diagram

Figure 1. PC7410M16 Microprocessor Block Diagram

2

PC7410M16

2183A–HIREL–12/02

PC7410M16

Features

This section summarizes features of the PC7410M16’s implementation of the PowerPC

architecture. Major features of the PC7410M16 are as follows:

•

Branch Processing Unit

–

Four instructions fetched per clock

One branch processed per cycle (plus resolving two speculations)

Up to one speculative stream in execution, one additional speculative stream

in fetch

–

512-entry branch history table (BHT) for dynamic prediction

64-entry, 4-way set associative branch target instruction cache (BTIC) for

eliminating branch delay slots

•

Dispatch Unit

–

Full hardware detection of dependencies (resolved in the execution units)

Dispatch two instructions to eight independent units (system, branch,

load/store, fixed-point unit 1, fixed-point unit 2, floating-point, AltiVec

permute, AltiVec ALU)

–

Serialization control (predispatch, postdispatch, execution serialization)

•

Decode

–

Register file access

Forwarding control

Partial instruction decode

Completion

–

8-entry completion buffer

Instruction tracking and peak completion of two instructions per cycle

Completion of instructions in program order while supporting out-of-order

instruction execution, completion serialization and all instruction flow

changes

•

Fixed-point Units (FXUs) that Share 32 GPRs for Integer Operands

–

Fixed-point unit 1 (FXU1) — multiply, divide, shift, rotate, arithmetic, logical

Fixed-point unit 2 (FXU2) – shift, rotate, arithmetic, logical

Single-cycle arithmetic, shifts, rotates, logical

Multiply and divide support (multi-cycle)

Early out multiply

Three-stage Floating-point Unit and a 32-entry FPR File

–

Support for IEEE-754 standard single- and double-precision floating-point

arithmetic

–

Three-cycle latency, one-cycle throughput (single or double precision)

Hardware support for divide

Hardware support for denormalized numbers

Time deterministic non-IEEE mode

•

System Unit

–

Executes CR logical instructions and miscellaneous system instructions

Special register transfer instructions

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2183A–HIREL–12/02

•

AltiVec Unit

–

Full 128-bit data paths

Two dispatchable units: vector permute unit and vector ALU unit

Contains its own 32-entry 128-bit vector register file (VRF) with six renames

The vector ALU unit is further sub-divided into the vector simple integer unit

(VSIU), the vector complex integer unit (VCIU) and the vector floating-point

unit (VFPU).

–

Fully pipelined

•

Load/Store Unit

–

One-cycle load or store cache access (byte, half-word, word, double-word)

Two-cycle load latency with one-cycle throughput

Effective address generation

Hits under misses (multiple outstanding misses)

Single-cycle unaligned access within double-word boundary

Alignment, zero padding, sign extend for integer register file

Floating-point internal format conversion (alignment, normalization)

Sequencing for load/store multiples and string operations

Store gathering

Executes the cache and TLB instructions

Big- and little-endian byte addressing supported

Misaligned little-endian supported

Supports FXU, FPU, and AltiVec load/store traffic

Complete support for all four architecture AltiVec DST streams

•

Level 1 (L1) Cache Structure

–

32K 32-byte line, 8-way set associative instruction cache (iL1)

32K 32-byte line, 8-way set associative data cache (dL1)

Single-cycle cache access

Pseudo least-recently-used (LRU) replacement

Data cache supports AltiVec LRU and transient instructions algorithm

Copy-back or write-through data cache (on a page-per-page basis)

Supports all PowerPC memory coherency modes

Non-blocking instruction and data cache

Separate copy of data cache tags for efficient snooping

No snooping of instruction cache except for ICBI instruction

•

Memory Management Unit

–

128 entry, 2-way set associative instruction TLB

128 entry, 2-way set associative data TLB

Hardware reload for TLBs

Four instruction BATs and four data BATs

Virtual memory support for up to four petabytes (2⁵²) of virtual memory

Real memory support for up to four gigabytes (2³²) of physical memory

Snooped and invalidated for TLBI instructions

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PC7410M16

2183A–HIREL–12/02

PC7410M16

•

Efficient Data Flow

–

All data buses between VRF, load/store unit, dL1, iL1, L2 and the bus are

128 bits wide

–

dL1 is fully pipelined to provide 128 bits per cycle to/from the VRF

L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L1s

Up to eight outstanding out-of-order cache misses between dL1 and L2/bus

Up to seven outstanding out-of-order transactions on the bus

Load folding to fold new dL1 misses into older outstanding load and store

misses to the same line

–

Store miss merging for multiple store misses to the same line. Only

coherency action taken (i.e., address only) for store misses merged to all 32

bytes of a cache line (no data tenure needed).

–

Two-entry finished store queue and four-entry completed store queue

between load/store unit and dL1

Separate additional queues for efficient buffering of outbound data (castouts,

write throughs, etc.) from dL1 and L2

•

Bus Interface

–

MPX bus extension to 60X processor interface

Mode-compatible with 60x processor interface

32-bit address bus

64-bit data bus

Bus-to-core frequency multipliers of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x,

6.5x, 7x, 7.5x, 8x, 9x supported

–

Selectable interface voltages of 1.8V, 2.5V and 3.3V

•

Power Management

–

Low-power design with thermal requirements very similar to PC740 and

PC750

–

Low voltage 1.8V processor core

Selectable interface voltages of 1.8V can reduce power in output buffers

Three static power saving modes: doze, nap, and sleep

Dynamic power management

•

Testability

–

LSSD scan design

IEEE 1149.1 JTAG interface

Array built-in self test (ABIST) – factory test only

Redundancy on L1 data arrays and L2 tag arrays

Reliability and Serviceability

Parity checking on 60x and L2 cache buses

–

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Signal Description

Figure 2. PC7410M16 Microprocessor Signal Groups

SSRAM 1

L2V

DD

U1

L2pin_DATA

L2DP0-3

DQa

DQb

DQc

FT

SBd

SBc

SBb

SBa

SW

DQd

DP0-3

ADSP

ADV

SE2

L2 CLK_OUT A

L2WE

K

SGW

SE1

L2CE

ADSC

SE3

LBO

G

SA^0-17

ZZ

A

0-17

SSRAM 2

PC7410

L2V

DD

U2

SA0-17

FT

SBd

SBc

SBb

SBa

SW

ADSP

ADV

SGW

SE1

K

L2CLK_OUT B

L2pin_DATA

L2DP4-7

DQa

DQb

DQc

DQd

SE2

ADSC

SE3

LBO

G

DP0-3

ZZ

L2ZZ

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PC7410M16

2183A–HIREL–12/02

PC7410M16

L2OV_DD

GND

L2AV_DD

L2ADDR[0:18]

L2DATA[0:63]

L2DP[0:7]

BR

BG

1

19

64

8

13

49

1

L2 Cache

Address/Data

Address

Arbitration

ABB/AMON[0]

TS

1

Address

Start

L2CE

L2WE

1

A[0:31]

AP[0:3]

TT[0:4]

TBST

1

32

4

L2CLKOUTA,

L2CLKOUTB

Address

Bus

L2 Cache

Clock/Control

2

L2SYNC_OUT

L2SYNC_IN

L2ZZ

1

5

1

INT

TSIZ[0:2]

GBL

3

SMI

Transfer

Attribute

MCP

1

SRESET

HRESET

CKSTP_IN

CKSTP_OUT

HIT

WT

1

Interrupts

Reset

CI

PCX7410

1

CHK

1

AACK

1

Address

Termination

SHDO, SHD1

RSRV

2

1

4

1

5

3

ARTRY

DBG

1

TBEN

1

Processor

Status

Control

EMODE

QREQ

Data

Arbitration

DBWO, DTI(0)

DBB, DMON(0)

D[0:63]

DP[0:7]

DTI(2)

TA

1

QACK

1

DRDY

64

8

SYSCLK

PLL_CFG[0:3]

CLK_OUT

JTAG:COP

Factory Test

Data

Transfer

Clock

Control

1

Test Interface

LSSD_MODE

1

Data

Termination

DTI1

L1_TSTCLK,

L2_TSTCLK

1

BVSEL

TEA

I/O Voltage

Selection

1

L2VSEL

12

20

1

OV_DD

V_DD

AV_DD

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2183A–HIREL–12/02

Detailed Specification

Scope

This drawing describes the specific requirements for the microprocessor PC7410M16 in

compliance with Atmel standard screening.

Applicable

Documents

1. MIL-STD-883: Test methods and procedures for electronics

2. MIL-PRF-38535: Appendix A: General specifications for microcircuits

Requirements

General

The microcircuits are in accordance with the applicable documents and as specified

herein.

Design and Construction

Terminal Connections

Depending on the package, the terminal connections are as shown in Table 10, Table 3

and Figure 2.

Absolute Maximum

Ratings

Table 1. Absolute Maximum Ratings⁽¹⁾

Symbol

V_DD

Characteristic

Value

Unit Notes

(4)

Core supply voltage

PLL supply voltage

L2 DLL supply voltage

60x bus supply voltage

L2 bus supply voltage

L2 supply voltage

Input supply

-0.3 to 2.1

V

(4)

AV_DD

L2AV_DD

OV_DD

L2OV_DD

L2V_DD

V_IN

-0.3 to 2.1

V

(4)

-0.3 to 2.1

V

(3)

-0.3 to 3.465

-0.3 to 2.6

V

(3)

V

(5)

-0.3 to 4.6

V

(2)

Processor Bus

L2 bus

-0.3 to OV_DD+ 0,2

-0.3 to L2OV_DD+ 0,2

-0.3 to OV_DD+ 0,2

-55 to 150

V

(2)

V_IN

V

(2)

V_IN

JTAG Signals

V

T_STG

Storage temperature range

°C

Notes: 1. Functional and tested operating conditions are given in Operating Conditions table.

Absolute maximum ratings are stress ratings only, and functional operation at the

maximums is not guaranteed. Stresses beyond those listed may affect device reliabil-

ity or cause permanent damage to the device.

2. Caution: Vin must not exceed OV_DDby more than 0.2V at any time including during

power-on reset.

3. Caution: OV_DD/L2OV_DDmust not exceed V_DD/AV_DD/L2AV_DDby more than 2.0V at any

time including during power-on reset.

4. Caution: V_DD/AV_DDD/L2AV_DDmust not exceed L2OV_DD/OV_DDby more than 0.4V at

any time including during power-on reset.

5. L2OV_DDshould never exceed L2V_DD

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PC7410M16

2183A–HIREL–12/02

PC7410M16

Figure 3. Overshoot/Undershoot Voltage

(L2)OV_DD+ 20%

(L2)OV_DD+ 5%

(L2)OV_DD

V_IH

V_IL

GND

GND - 0.3V

GND - 0.7V

Not to exceed

10% of t_SYSCLK

The PC7410M16 provides several I/O voltages to support both compatibility with exist-

ing systems and migration to future systems. The PC7410M16 “core” voltage must

always be provided at nominal voltage (see Table 3 for actual recommended core volt-

age). Voltage to the L2 I/Os and processor interface I/Os are provided through separate

sets of supply pins and may be provided at the voltages shown in Table 2. The input

voltage threshold for each bus is selected by sampling the state of the voltage select

pins at the negation of the signal HRESET. The output voltage will swing from GND to

the maximum voltage applied to the OV_DDor L2OV_DDpower pins.

Table 2. Input Threshold Voltage Setting

Processor Bus Input

BVSEL Signal Threshold is Relative to:

L2 Bus Input Threshold

is Relative to:

L2VSEL Signal

0⁽¹⁾

1.8V

2.5V

3.3V

0

1.8

HRESET^{(1) (2)}

1⁽¹⁾⁽³⁾

HRESET

1

2.5

HRESET

Not supported

Notes: 1. Caution: The input threshold selection must agree with the OV_DD/L2OV_DDvoltages

supplied.

2. To select the 2.5V threshold option, L2VSEL/BVSEL should be tied to HRESET so

that the two signals change state together. This is the preferred method for selecting

this mode operation.

3. Default voltage setting if left unconnected (internal pull-up). To overcome the internal

pull up resistance, a pull down resistance less than 250Ω should be used.

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2183A–HIREL–12/02

Recommended

Operating Conditions

Table 3. Recommended Operating Conditions⁽¹⁾

Recommended

Value

Unit

Symbol

V_DD

Characteristic

Core supply voltage

PLL supply voltage

1.8 100 mV

2.5 100 mV

3.3 165 mV

2.5 100 mV

3.3V 165mV

GND to OV_DD

V

AV_DD

L2AV_DD

OV_DD

L2OV_DD

L2V_DD

V_IN

L2 DLL supply voltage

Processor bus supply voltage

BVSEL = 0

BVSEL = HRESET

BVSEL = 1 or = HRESET

L2VSEL = 1 or L2VSEL = HRESET

L2 bus supply voltage

Memory core supply voltage

Input voltage

Processor bus and JTAG Signals

Note:

1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not

guaranteed.

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PC7410M16

2183A–HIREL–12/02

PC7410M16

L2 Cache Control

Register (L2CR)

The L2 cache control register, shown in Figure 4, is a supervisor-level, implementation-

specific SPR used to configure and operate the L2 cache. It is cleared by hard reset or

power-on reset.

Figure 4. L2 Cache Control Register (L2CR)

L2WT

L2DF L2FA

L2HWF L2IO

L2SL L2BYP

L2CLKSTP

L2PE

L2IP

L2DO L2CTL L2TS

L2DRO

L2E

0

L2SIZ

2

L2CLK L2RAM

L2I

L2OH

0000000

31

1

4

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

The L2CR bits are described in Table 4.

Table 4. L2CR Bit Settings

Bit

Name

Function

0

L2E

L2 enable. Enables L2 cache operation (including snooping) starting with the next transaction the L2 cache

unit receives. Before enabling the L2 cache, the L2 clock must be configured through L2CR[2CLK], and the

L2 DLL must stabilize. All other L2CR bits must be set appropriately. The L2 cache may need to be

invalidated globally.

1

L2PE

L2 data parity checking enable. Enables parity generation and checking for the L2 data RAM interface. When

disabled, generated parity is always zeros. L2 Parity is supported by PC7410M16, but is dependent on

application.

2-3

4-6

L2SIZ

L2 size — Should be set according to the size of the private memory setting. Total SRAM space is 2M bytes

(256Kx72). See L2 cache/private memory configurations table in Motorola^®User's Manual.

L2CLK

L2 clock ratio (core-to-L2 frequency divider). Specifies the clock divider ratio based from the core clock

frequency that the L2 data RAM interface is to operate at. When these bits are cleared, the L2 clock is

stopped and the on-chip DLL for the L2 interface is disabled. For nonzero values, the processor generates

the L2 clock and the on-chip DLL is enabled. After the L2 clock ratio is chosen, the DLL must stabilize before

the L2 interface can be enabled. The resulting L2 clock frequency cannot be slower than the clock frequency

of the 60x bus interface.

000 L2 clock and DLL disabled

001 ÷ 1

010 ÷ 1.5

011 ÷ 3.5

100 ÷ 2

101 ÷ 2.5

110 ÷ 3

111 ÷ 4

7-8

L2RAM

L2 RAM type – Configures the L2 RAM interface for the type of synchronous SRAMs used:

• Pipelined (register-register) synchronous burst SRAMs that clock addresses in and clock data out

The 7410 does not burst data into the L2 cache, it generates an address for each access.

10 Pipelined (register-register) synchronous burst SRAM - Setting for PC7410M16

9

L2DO

L2I

L2 data only. Setting this bit enables Údata-only operation in the L2 cache. When this bit is set, only

transactions from the L1 data cache can be cached in the L2 cache. L1 instruction cache operations will be

serviced for instruction addresses already in the L2 cache; however, the L2 cache will not be reloaded for L1

instruction cache misses. Note that setting both L2DO and L2IO effectively locks the L2 cache.

10

L2 global invalidate. Setting L2I invalidates the L2 cache globally by clearing the L2 status bits. This bit must

not be set while the L2 cache is enabled. See Motorola's User manual for L2 Invalidation procedure.

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2183A–HIREL–12/02

Table 4. L2CR Bit Settings (Continued)

Bit

Name

Function

11

L2CTL

L2 RAM control (ZZ enable). Setting L2CTL enables the automatic operation of the L2ZZ (low-power mode)

signal for cache RAMs. Sleep mode is supported by the PC7410M16. While L2CTL is asserted, L2ZZ

asserts automatically when the device enters nap or sleep mode and negates automatically when the device

exits nap or sleep mode. This bit should not be set when the device is in nap mode and snooping is to be

performed through deassertion of QACK.

12

13

L2WT

L2TS

L2 write-through. Setting L2WT selects write-through mode (rather than the default write-back mode) so all

writes to the L2 cache also write through to the system bus. For these writes, the L2 cache entry is always

marked as clean (value unmodified) rather than dirty (value modified). This bit must never be asserted after

the L2 cache has been enabled as previously-modified lines can get remarked as clean (value unmodified)

during normal operation.

L2 test support. Setting L2TS causes cache block pushes from the L1 data cache that result from dcbf and

dcbst instructions to be written only into the L2 cache and marked valid, rather than being written only to the

system bus and marked invalid in the L2 cache in case of hit. This bit allows a dcbz/dcbf instruction

sequence to be used with the L1 cache enabled to easily initialize the L2 cache with any address and data

information. This bit also keeps dcbz instructions from being broadcast on the system and single-beat

cacheable store misses in the L2 from being written to the system bus.

14-15

16

L2OH

L2SL

L2 output hold. These bits configure output hold time for address, data, and control signals driven to the L2

data RAMs.

01: 0.8 ms Hold Time - Setting for PC7410M16

L2 DLL slow. Setting L2SL increases the delay of each tap of the DLL delay line. It is intended to increase the

delay through the DLL to accommodate slower L2 RAM bus frequencies.

0: Setting for PC7410M16 because L2 RAM interface is operated above 100 MHz.

17

18

19

L2DF

L2BYP

L2FA

L2 differential clock. This mode supports the differential clock requirements of late-write SRAMs.

0: Setting for PC7410M16 because late-write SRAMs are not used.

L2 DLL bypass is reserved.

0: Setting for PC7410M16

L2 flush assist (for software flush). When this bit is negated, all lines castout from the dL1 which have a state

of CDMRSV=01xxx1 (i.e. C-bit negated), will not allocate in the L2 if they miss. Asserting this bit forces every

castout from the dL1 to allocate an entry in the L2 if that castout misses in the L2 regardless of the state of

the C-bit. The L2FA bit must be set and the L2IO bit must be cleared in order to use the software flush

algorithm.

20

L2HWF

L2 hardware flush. When the processor detects the value of L2HWF set to 1, the L2 will begin a hardware

flush. The flush will be done by starting with low cache indices and increment these indices for way 0 of the

cache, one index at a time until the maximum index value is obtained. Then, the index will be cleared to zero

and the same process is repeated for way 1 of the cache. For each index and way of the cache, the processor

will generate a castout operation to the system bus for all modified 32-byte sectors. At the end of the

hardware flush, all lines in the L2 tag will be invalidated. During the flush, all memory activity from the icache

and dcache are blocked from accessing the L2 until the flush is complete. Snoops, however, are fully

serviced by the L2 during the flush. When the L2 tags have been fully flushed of all valid entries, this bit will

be reset to b'0" by hardware. When this bit is cleared, it does not necessarily guarantee that all lines from the

L2 have been written completely to the system interface. L2 copybacks can still be queued in the bus

interface unit. Below is the code which must be run to use L2 Hardware Flush. When the final sync

completes, all modified lines in the L2 will have been written to the system address bus.

Disable interrupts

dssall

sync

set L2HWF

sync

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PC7410M16

2183A–HIREL–12/02

PC7410M16

Table 4. L2CR Bit Settings (Continued)

Bit

Name

Function

21

L2IO

L2 Instruction-Only. Setting this bit enables instruction-only operation in the L2 cache. For this operation, only

transactions from the L1 instruction cache are allowed to be reloaded in the L2 cache. Data addresses

already in the cache will still hit for the L1 data cache. When both L2DO and L2IO are asserted, the L2 cache

is effectively locked.

22

23

L2CLKSTP

L2DRO

L2 Clock Stop. Setting this bit enables the automatic stopping of the L2CLK_OUT signals for cache rams that

support this function. While L2CLKSTP is set, the L2CLK_OUT signals will automatically be stopped when

PC7410M16 enters nap or sleep mode, and automatically restarted when PC7410M16 exits nap or sleep.

L2 DLL rollover. Setting this bit enables a potential rollover (or actual rollover) condition of the DLL to cause a

checkstop for the processor. A potential rollover condition occurs when the DLL is selecting the last tap of the

delay line, and thus may risk rolling over to the first tap with one adjustment while in the process of keeping

synchronized. Such a condition is improper operation for the DLL, and, while this condition is not expected, it

allows detection for added security. This bit can be set when the DLL is first enabled (set with the L2CLK bits)

to detect rollover during initial synchronization. It could also be set when the L2 cache is enabled (with L2E

bit) after the DLL has achieved its initial lock.

24-30

31

–

Reserved

L2IP

L2 global invalidate in progress (read only) – See the Motorola user's manual for L2 Invalidation procedure.

Power Consideration

Power Management

The PC7410M16 provides four power modes, selectable by setting the appropriate con-

trol bits in the MSR and HIDO registers. The four power modes are:

•

Full-power: This is the default power state of the PC7410M16. The PC7410M16 is

fully powered and the internal functional units are operating at the full processor

clock speed. If the dynamic power management mode is enabled, functional units

that are idle will automatically enter a low-power state without affecting

performance, software execution or external hardware.

•

Doze: All the functional units of the PC7410M16 are disabled except for the time

base/decrementer registers and the bus snooping logic. When the processor is in

doze mode, an external asynchronous interrupt, a system management interrupt, a

decrementer exception, a hard or soft reset or machine check brings the

PC7410M16 into the full-power state. The PC7410M16 in doze mode maintains the

PLL in a fully powered state and locked to the system external clock input (SYSCLK)

so a transition to the full-power state takes only a few processor clock cycles.

•

Nap: The nap mode further reduces power consumption by disabling bus snooping,

leaving only the time base register and the PLL in a powered state. The

PC7410M16 returns to the full-power state upon receipt of an external

asynchronous interrupt, a system management interrupt, a decrementer exception,

a hard or soft reset or a machine check input (MCP). A return to full-power state

from a nap state takes only a few processor clock cycles. When the processor is in

nap mode, if QACK is negated, the processor is put in doze mode to support

snooping.

Sleep: Sleep mode minimizes power consumption by disabling all internal functional

units, after which external system logic may disable the PLL and SYSCLK.

Returning the PC7410M16 to the full-power state requires the enabling of the PLL

and SYSCLK, followed by the assertion of an external asynchronous interrupt, a

system management interrupt, a hard or soft reset or a machine check input (MCP)

signal after the time required to relock the PLL.

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2183A–HIREL–12/02

Power Dissipation

Table 5. Power Consumption

V_DD= AV_DD= 1.8 0.1V V_DC, L2V_DD= 3.3V 5% V_DC, GND = 0 V_DC, 0 ≤ TJ < 125°C

Processor (CPU) Frequency/L2 Frenquency

400 MHz/200 MHz

Unit

W

Notes

(1)(3)

Full-on Mode

Typical

5.7

13.5

5.3

(1)(2)

Maximum

W

Doze Mode Maximum

Nap Mode Maximum

Sleep Mode

W

2.25

2.20

2.0

W

Sleep Mode–PLL and DLL Disabled

W

Notes: 1. These values apply for all valid system bus and L2 bus ratios. The values do not include OV_DD; AV_DDand L2AV_DDsuppling

power. OV_DDpower is system dependent, but is typically < 10% of V_DDpower. Worst case power consumption, for AV_DD= 15

mW and L2AV_DD= 15 mW.

2. Maximum power is measured at V_DD= 1.9V while running an entirely cache-resident, contrived sequence of instructions

which keep the execution units maximally busy.

3. Typical power is an average value measured at V_DD= AV_DD= L2AV_DD= 1.8V, OV_DD= L2OV_DD= 2.5V in a system, executing

typical applications and benchmark sequences.

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PC7410M16

2183A–HIREL–12/02

PC7410M16

Electrical

Characteristics

Static Characteristics

Table 6. DC Electrical Specifications (see Table 3 for Recommended Operating Conditions)

NominalBus

Symbol

V_IH

Characteristic

Voltage⁽¹⁾

1.8

Min

Max

Unit

V

Input high voltage

0.65 x (L2)OV_DD

(L2)OV_DD+ 0.2

(L2)OV_DD+ 0.3

0.35 x OV_DD

0.2 x (L2)OV_DD

0.8

(all inputs except SYSCLK)⁽²⁾⁽³⁾

V_IH

2.5

1.7

2.0

V

V_IH

3.3

V

V_IL

Input low voltage

(all inputs except SYSCLK)

1.8

-0.3

1.5

V

V_IL

2.5

V

V_IL

3.3

V

CV_IH

CV_IL

I_IN

SYSCLK input high voltage⁽²⁾

SYSCLK input low voltage

Input leakage current,

1.8

OV_DD+ 0.2

OV_DD+ 0.3

0.2

V

2.5

2.0

V

3.3

2.4

V

1.8

-0.3

V

2.5

0.4

V

3.3

0.4

V

10

µA

(2)(3)

V_IN= L2OV_DD/OV_DD

I_TSI

High-Z (off-state) leakage current,

10

µA

(2)(3)(5)

V_IN= L2OV_DD/OV_DD

V_OH

V_OL

C_IN

Output high voltage,

I_OH= -6 mA

1.8

2.5

3.3

1.8

2.5

3.3

(L2)OV_DD- 0.45

V

1.7

2.4

V

Output low voltage,

0.45

0.4

V

I

_OL= 6 mA

V

0.4

V

Capacitance, V_IN= 0V,

f = 1 MHz⁽³⁾⁽⁴⁾

7.5

pF

Notes: 1. Nominal voltages; see Table 3 for Recommended Operating Conditions.

2. For processor bus signals, the reference is OV_DDwhile L2OV_DDis the reference for the L2 bus signals.

3. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK) and IEEE 1149.1 boundary scan (JTAG) signals.

4. Capacitance is periodically sampled rather than 100% tested.

5. The leakage is measured for nominal OV_DDand V_DD, or both OV_DDand V_DDmust vary in the same direction (for example,

both OV_DDand V_DDvary by either +5% or -5%).

15

2183A–HIREL–12/02

Dynamic Characteristics After fabrication, parts are sorted by maximum processor core frequency as shown in

“Clock AC Specifications” and tested for conformance to the AC specifications for that

frequency. These specifications are for valid processor core frequencies. The processor

core frequency is determined by the bus (SYSCLK) frequency and the settings of the

PLL_CFG[0:3] signals. Parts are sold by maximum processor core frequency.

Clock AC Specifications

Table 7 provides the clock AC timing specifications as defined in Figure 5.

Table 7. Clock AC Timing Specifications (See Table 3 for Recommended Operating Conditions)

Maximum Processor Core Frequency

400 MHz

Max

450 MHz

Max

Symbol

Characteristic

Min

350

450

33

Min

350

450

33

Unit

MHz

ns

(1)

f_CORE

Processor frequency

VCO frequency

400

800

133

30

450

900

133

30

(1)

f_VCO

(1)

f_SYSCLK

t_SYSCLK

SYSCLK frequency

SYSCLK cycle time

SYSCLK rise and fall time

7.5

(2)

(3)

t

_KR& t_KF

1.0

0.5

60

1.0

0.5

60

ns

(4)

t_KHKL/t_SYSCLK

SYSCLK duty cycle measured at OV_DD/2

SYSCLK jitter⁽⁵⁾

40

%

150

100

150

100

ps

Internal PLL relock time⁽⁶⁾

µs

Notes: 1. Caution: The SYSCLK frequency and PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK (bus) fre-

quency, CPU (core) frequency and PLL (VCO) frequency do not exceed their respective maximum or minimum operating

frequencies. Refer to the PLL_CFG[0:3] signal description in “Clock Selection” on page 26 for valid PLL_CFG[0:3] settings

2. Rise and fall times for the SYSCLK input measured from 0.4V to 2.4V when OV_DD= 3.3V nominal.

3. Rise and fall times for the SYSCLK input measured from 0.2V to 1.2V when OV_DD= 1.8V or 2.5V nominal.

4. Timing is guaranteed by design and characterization.

5. This represents total input jitter, short-term and long-term combined, and is guaranteed by design.

6. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for

PLL lock after a stable V_DDand SYSCLK are reached during the power-on reset sequence. This specification also applies

when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held

asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.

Figure 5. SYSCLK Input Timing Diagram

t_KR

t_KF

t_SYSCLK

t_KHKL

CVIH

CVIL

SYSCLK

VM

Note:

VM = Midpoint Voltage (OV_DD/2)

16

PC7410M16

2183A–HIREL–12/02

PC7410M16

Processor Bus AC

Specifications

Table 8 provides the processor AC timing specifications for the PC7410M16 as defined

in Figure 7 and Figure 8.

Table 8. Processor Bus AC Timing Specifications⁽¹⁾at V_DD= AV_DD= 1.8V 100 mV;

-55°C ≤ T_j≤ 125°C, OV_DD= 1.8V 100 mV

400, 450 MHz

Min Max

Symbol⁽²⁾

Parameter

Unit

t_SYSCLK

ns

(3)(4)(5)(6)

t_MVRH

t_MXRH

t_IVKH

Mode select input setup to HRESET

HRESET to mode select input hold

Input Setup

8

0

(2)(3)(5)

1.0

0

ns

t_IXKH

Input Hold

ns

Output Valid Times:⁽⁷⁾⁽⁸⁾

TS

ns

t_KHTSV

t_KHARV

t_KHOV

3.0

2.3

3.0

ARTRY/SHD0/SHD1

All Other Outputs

Output Hold Times:^(7)(12)

TS

ns

t_KHTSX

t_KHARX

t_KHOX

0.5

ARTRY/SHD0/SHD1

All Other Outputs

(11)

t_KHOE

t_KHOZ

SYSCLK to Output Enable

0.5

ns

SYSCLK to Output High Impedance (all except ABB/AMON[0], ARTRY/SHD,

DBB/DMON[0]), SHD0, SHD1)

3.5

(5)(9)(11)

t_KHABPZ

SYSCLK to ABB/AMON[0], DBB/DMON[0] High Impedance after precharge

Maximum Delay to ARTRY/SHD0/SHD1 Precharge

1.0

1

t_SYSCLK

(5)(10)(11)

t_KHARP

t_KHARPZ

SYSCLK to ARTRY/SHD0/SHD1 High Impedance After Precharge

2

Notes: 1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input

SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the sig-

nal in question. All output timings assume a purely resistive 50Ω load (see Figure 7). Input and output timings are measured

at the pin; time-of-flight delays must be added for trace lengths, vias and connectors in the system.

2. The symbology used for timing specifications herein follows the pattern of

t_{(signal)(state)(reference)(state)}for inputs and t_{(reference)(state)(signal)(state)}for outputs. For example, t_IVKHsymbolizes the time input signals

(I) reach the valid state (V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And t_KHOV

symbolizes the time from SYSCLK (K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can

be read as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH) - note the position of

the reference and its state for inputs -and output hold time can be read as the time from the rising edge (KH) until the output

went invalid (OX).

3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 8).

4. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of

255 bus clocks after the PLL re-lock time during the power-on reset sequence.

5. t_SYSCLKis the period of the external clock (SYSCLK) in nanoseconds(ns). The numbers given in the table must be multiplied

by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question.

6. Mode select signals are BVSEL, EMODE, L2VSEL, PLL_CFG[0:3].

7. All other output signals are composed of the following - A[0:31], AP[0:3], TT[0:4], TBST, TSIZ[0:2], GBL, WT, CI, DH[0:31],

DL[0:31], DP[0:7], BR, CKSTP_OUT, DRDY, HIT, QREQ, RSRV.

8. Output valid time is measured from 2.4V to 0.8V which may be longer than the time required to discharge from V_DDto 0.8V.

17

2183A–HIREL–12/02

9. According to the 60x bus protocol, ABB and DBB are driven only by the currently active bus master. They are asserted low

then precharged high before returning to high-Z as shown in Figure 6. The nominal precharge width for ABB or DBB is 0.5 x

t

_SYSCLK, i.e., less than the minimum t_SYSCLKperiod, to ensure that another master asserting ABB, or DBB on the following

clock will not contend with the precharge. Output valid and output hold timing is tested for the signal asserted. Output valid

time is tested for precharge. The high-Z behavior is guaranteed by design.

10. According to the 60x bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately fol-

lowing AACK. Bus contention is not an issue since any master asserting ARTRY will be driving it low. Any master asserting

it low in the first clock following AACK will then go to high-Z for one clock before precharging it high during the second cycle

after the assertion of AACK. The nominal precharge width for ARTRY is 1.0 t_SYSCLK; i.e., it should be high-Z as shown in Fig-

ure 6 before the first opportunity for another master to assert ARTRY. Output valid and output hold timing are tested for the

signal asserted. Output valid time is tested for precharge. The high-Z behavior is guaranteed by design.

11. Guaranteed by design and not tested.

12. Output hold time characteristics can be altered by the use of the L2_TSTCK pin during system reset, similar to L2 output

hold being altered by the use of bits [14-15] in the L2CR register. Information on the operation of the L2_TSTCLK will be

included in future revisions of this specification.

Figure 6. Input/Output Timing Diagram

VM

SYSCLK

t_IVKH

t_IXKH

All Inputs

t_KHOX

t_KHOV

All Outputs

(except TS, ABB,

ARTRY, DBB)

t_KHOE

t_KHOZ

All Outputs

(except TS, ABB,

ARTRY, DBB)

t_KHABPZ

t_KHTSV

t_KHTSX

TS,

t_KHTSV

ABB/AMON[0],

DBB/DMON[0]

t_KHARPZ

t_KHARP

t_KHARX

t_KHARV

ARTRY,

SHD0,

SHD1

t_KHARV

VM = Midpont Voltage (OVDD/2)

18

PC7410M16

2183A–HIREL–12/02

PC7410M16

Figure 7. AC Test Load for the 60x Interface

Output

Z0 = 50 Ohms

OV_DD/2

RL = 50 Ohms

Figure 8. Mode Input Timing Diagram

VM

HRESET

t_MVRH

t_MXRH

MODE SIGNALS

where VM = Midpoint Voltage (OV_DD/2)

IEEE 1149.1 AC Timing

Specifications

Table 9 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure

9, Figure 10, Figure 11 and Figure 12.

Table 9. JTAG AC Timing Specifications (Independent of SYSCLK)⁽¹⁾at Recommended

Operating Conditions (see Table 3)

Symbol

f_TCLK

Parameter

Min

0

Max

Unit

MHz

ns

TCK frequency of operation

TCK cycle time

33.3

t _TCLK

t_JHJL

30

15

0

TCK clock pulse width measured at OV_DD/2

TCK rise and fall times

TRST assert time

ns

t

_JR& t_JF

2

ns

(2)

t_TRST

25

ns

Input Setup Times:

Boundary-scan data

TMS, TDI

ns

(3)

t_DVJH

t_IVJH

4

0

Input Hold Times:

Boundary-scan data

TMS, TDI

ns

t_DXJH

t_IXJH

20

25

Valid Times:

Boundary-scan data

TDO

(4)

t_JLDV

t_JLOV

4

20

25

TCK to output high impedance:

Boundary-scan data

TDO

(4)(5)

(5)

t_JLDZ

t_JLOZ

3

19

9

Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK

to the midpoint of the signal in question. The output timings are measured at the pins.

All output timings assume a purely resistive 50Ω load (see Figure 9). Time-of-flight

delays must be added for trace lengths, vias and connectors in the system.

2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes

only.

3. Non-JTAG signal input timing with respect to TCK.

4. Non-JTAG signal output timing with respect to TCK.

5. Guaranteed by design and characterization

19

2183A–HIREL–12/02

Figure 9. Alternate AC Test Load for the JTAG Interface

Output

Z0 = 50 Ohms

OV_DD/2

RL = 50 Ohms

Figure 10. JTAG Clock Input Timing Diagram

t_JR

t_JF

VM

TCLK

t_JHJL

t_TCLK

Note:

VM = Midpoint Voltage (OV_DD/2)

Figure 11. TRST Timing Diagram

t_TRST

VM

TRST

Note:

VM = Midpoint Voltage (OV_DD/2)

Figure 12. Boundary-scan Timing Diagram

TCK

VM

t_DVJH

Boundary

t_DXJH

Data Inputs

Input Data

Valid

t_JLDV

t_JLDX

Boundary

Data Outputs

Output Data Valid

t_JLDZ

Output Data Valid

Boundary

Data Outputs

Note:

VM = Midpoint Voltage (OV_DD/2)

20

PC7410M16

2183A–HIREL–12/02

PC7410M16

Figure 13. Test Access Port Timing Diagram

VM

TCK

t_IVJH

t_IXJH

TDI, TMS

Input Data

Valid

t_JLOV

t_JLOX

Output Data Valid

TDO

t_JLOZ

TDO

Output Data Valid

Note:

VM = Midpoint Voltage (OV_DD/2)

Preparation for

Delivery

Handling

MOS devices must be handled with certain precautions to avoid damage due to accu-

mulation of static charge. Input protection devices have been designed in the chip to

minimize the effect of static buildup. However, the following handling practices are

recommended:

•

Devices should be handled on benches with conductive and grounded surfaces.

Ground test equipment, tools and operator.

Do not handle devices by the leads.

Store devices in conductive foam or carriers.

Avoid use of plastic, rubber or silk in MOS areas.

Maintain relative humidity above 50% if practical.

For CI-CGA packages, use specific tray to take care of the highest height of the

package compared with the normal CBGA.

21

2183A–HIREL–12/02

Figure 14. Pin Assignments

Ball assignments of the 255 CBGA package as viewed from the top surface

Side profile of the CBGA package to indicate the direction of the top surface view

View

Substrate Assembly

Underfill Encapsulant

Die

22

PC7410M16

2183A–HIREL–12/02

PC7410M16

Table 10. Package Pinout Listing

Signal Name

Pin Number

Active

I/O

1.8V⁽⁷⁾

2.5V⁽⁷⁾

3.3V⁽⁷⁾

A[0-31]

C16, E4, D13, F2, D14, G1, D15, E2, D16, D4, E13, G2,

E15, H1, E16, H2, F13, J1, F14, J2, F15, H3, F16, F4, G13,

K1, G15, K2, H16, M1, J15, P1

High

I/O

AACK

L2

Low

High

Low

–

Input

Output

I/O

ABB/AMONO⁽⁸⁾

K4

AP[0-3]

C1, B4, B3, B2

ARTRY

J4

I/O

AV_DD

A10

L1

–

1.8V

GND

1.8V

BG

Low

High

Low

–

Input

Output

Input

Output

Input

Output

Input

I/O

BR

B6

B1

C6

E1

D8

A6

D7

J14

N1

G4

BVSEL⁽⁴⁾⁽⁶⁾

CHK^(5)(6)(13)

CI

HRESET

OV_DD

CKSTP_IN

CKSTP_OUT

CLK_OUT

DBB/DMONO⁽⁸⁾

DBG

Low

High

DBWO/DTIO

DH[0-31]

P14, T16, R15, T15, R13, R12, P11, N11, R11, T12, T11,

R10, P9, N9, T10, R9, T9, P8, N8, R8, T8, N7, R7, T7, P6,

N6, R6, T6, R5, N5, T5, T4

DL[0-31]

K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16,

N15, N13, N14, P16, P15, R16, R14, T14, N10, P13, N12,

T13, P3, N3, N4, R3, T1, T2, P4, T3, R4

High

I/O

DP[0-7]

M2, L3, N2, L4, R1, P2, M4, R2

High

Low

–

I/O

Output

Input

I/O

DRDY^(5)(9)(12)

DTI 1-2^(9)(11)

EMODE^(10)(11)

GBL

D5

G16, H15

C4

F1

GND

C5, C12, E3, E6, E8, E9, E11, E14, F3, F5, F7, F10, F12,

G6, G8, G9, G11, H5, H7, H10, H12, J5, J7, J10, J12, K6,

K8, K9, K11, L5, L7, L10, L12, M3, M6, M8, M9, M11, M14,

P5, P12

–

GND

HIT^(5)(12)

HRESET

INT

A3

Low

High

Output

Input

A7

B15

D11

L1_TSTCLK⁽¹⁾

23

2183A–HIREL–12/02

Table 10. Package Pinout Listing (Continued)

Signal Name

L2_TSTCLK⁽¹⁾

L2AV_DD

Pin Number

Active

High

–

I/O

Input

–

1.8V⁽⁷⁾

2.5V⁽⁷⁾

3.3V⁽⁷⁾

D12

L11

1.8V

3.3V

1.8V

3.3V

1.8V

3.3V

N/A

(5)(7)

L2V_DD

A2, B8, C3, D6, J16

–

L2OV_DD

E10, E12, M12, G12, G14, K12, K14

–

2.5V

(15)

L2VSEL⁽³⁾⁽⁶⁾

LSSD_MODE⁽¹⁾

MCP

B5

High

Low

–

Input

–

HRESET

3.3V

N/A

B10

C13

B7, C8

NC (No-

connect)

(2)

OV_DD

C7, E5, G3, G5, K3, K5, P7, P10, E07, M05, M07, M10

–

PLL_CFG[0-3]

QACK

QREQ

RSRV

A8, B9, A9, D9

High

Low

–

Input

Output

I/O

D3

J3

D1

SHDO-1^(5)(14)

A4, A5

SMI

A16

Input

I/O

SRESET

SYSCLK

TA

B14

C9

H14

Low

High

Low

High

Low

High

Low

High

–

TBEN

C2

TBST

A14

TCK

C11

Input

Output

Input

I/O

TDI⁽⁶⁾

A11

TDO

A12

TEA

H13

TMS⁽⁶⁾

TRST⁽⁶⁾

TS

B11

C10

J13

TSIZ[0-2]

TT[0-4]

A13, D10, B12

B13, A15, B16, C14, C15

Output

I/O

(2)

V_DD

F6, F8, F9, F11, G7, G10, H4, H6, H8, H9, H11, J6, J8, J9,

J11, K7, K10, L6, L8, L9

–

1.8V

WT

D2

Low

Output

Notes: 1. These are test signals for factory use only and must be pulled up to OV_DDfor normal machine operation.

2. OV_DDinputs supply power to the I/O drivers and V_DDinputs supply power to the processor core.

3. To allow future L2 cache I/O interface voltage changes.

4. To allow processor bus I/0 voltage changes, provide the option to connect BVSEL to HRESET (Selects 2.5V Interface) or to

GND (Selects 1.8V Interface) or to OV_DD(Selects 3.3V Interface).

5. Uses one of 9 existing no-connects in PC755BM8.

24

PC7410M16

2183A–HIREL–12/02

PC7410M16

6. Internal pull up on die.

7. OV_DDsupplies power to the processor bus, JTAG, and all control signals except the L2 cache controls (L2CE, L2WE, and

L2ZZ); L2OV_DDsupplies power to the L2 cache I/O interface (L2ADDR (0-18], L2DATA (0-63), L2DP{0-7] and L2SYNC-OUT)

and the L2 control signals; L2AV_DDsupplies power to the SSRAM core memory; and V_DDsupplies power to the processor

core and the PLL and DLL (after filtering to become AV_DDand L2AV_DDrespectively). These columns serve as a reference for

the nominal voltage supported on a given signal as selected by the BVSEL pin configuration and the voltage supplied. For

actual recommended value of Vin or supply voltages see Recommended Operating Conditions.

8. Output only for 7410, was I/O for 750/755.

9. Enhanced mode only.

10. Deasserted (pulled high) at HRESET for 60x bus mode.

11. Reuses 750/755 DRTRY, DBIS, and TLBISYNC pins (DTI1, DTI2, and EMODE respectively).

12. Unused output in 60x bus mode.

13. Connect to HRESET to trigger post power-on-reset (por) internal memory test.

14. Ignored in 60x bus mode.

15. Not supported on this version.

Table 11. Package Description

Package Outline

Interconnects

Pitch

21 x 25 mm

255 (16 x 16 ball array less one)

1.27 mm

3.90 mm

0.8 mm

Maximum module height

Ball diameter

Figure 15. Package Dimensions 255 Ball Grid Array

25.25 (0.994)

MAX

A1 Corner

21.21 (0.835)

MAX

0.80 (0.032)

BSC

∅

1

2 3 4 5 6 7 8 9 10 11 1213 14 15 16

A

B

C

D

E

F

G

H

J

K

L

19.05 (0.750)

BSC

M

N

P

R

T

1.27 (0.050)

BSC

2.20 (0.087)

MAX

19.05 (0.750)

BSC

25

2183A–HIREL–12/02

Clock Selection

The PC7410M16’s PLL is configured by the PLL_CFG[0:3] signals. For a given

SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO

frequency of operation. The PLL configuration for the PC7410M16 is shown in Table 12

for example frequencies.

Table 12. PC7410M16 Microprocessor PLL Configuration

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

Bus-to-

Core

Core-to-

VCO

PLL_C

Bus

FG[0:3]

Multiplier

33.3 MHz

50 MHz

66.6 MHz

75 MHz

83.3 MHz

100 MHz

133 MHz

0100

0110

1000

1110

1010

0111

1011

1001

1101

0101

0010

0001

1100

0000

0011

1111

2x

2.5x

3x

2x

400 (800)

3.5x

4x

350 (700)

400 (800)

450 (900)

4.5x

5x

375 (750)

416 (833)

375 (750)

412 (825)

450 (900)

5.5x

6x

366 (733)

400 (800)

433 (866)

350 (700)

375 (750)

6.5x

7x

7.5x

8x

400 (800)

450 (900)

9x

PLL off/bypass

PLL off

Notes: 1. PLL_CFG[0:3] settings not listed are reserved.

PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied

PLL off, no core clocking occurs

2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO

frequencies which are not useful, not supported, or not tested for by the PC7410M16; see “Clock AC Specifications” on

page 16 for valid SYSCLK, core, and VCO frequencies.

3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode

is set for 1:1 mode operation. This mode is intended for factory use only.

Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.

4. In PLL-off mode, no clocking occurs inside the PC7410M16 regardless of the SYSCLK input.

26

PC7410M16

2183A–HIREL–12/02

PC7410M16

System Design

Information

PLL Power Supply

Filtering

The AV_DDand L2AV_DDpower signals are provided on the PC7410M16 to provide power

to the clock generation phase-locked loop and L2 cache delay-locked loop, respectively.

To ensure stability of the internal clock, the power supplied to the AV_DDinput signal

should be filtered of any noise in the 500 kHz to 10 MHz resonant frequency range of

the PLL. A circuit similar to the one shown in Figure 16 using surface mount capacitors

with minimum effective series inductance (ESL) is recommended.

The circuit should be placed as close as possible to the AV_DDpin to minimize noise cou-

pled from nearby circuits. An identical but separate circuit should be placed as close as

possible to the L2AV_DDpin. It is often possible to route directly from the capacitors to the

AV_DDpin, which is on the periphery of the 360-ball CBGA footprint without the induc-

tance of vias. The L2AV_DDpin may be more difficult to route but is proportionately less

critical.

Figure 16. PLL Power Supply Filter Circuit

Low ESL surface mount capacitor

10Ω

V_DD

AV_DD(or L2AV_DD)

2.2 µF

GND

Power Supply Voltage

Sequency

The notes in Table 1 contain cautions about the sequencing of the external bus voltages

and core voltage of the PC7410M16 (when they are different). These cautions are nec-

essary for the long term reliability of the part. If they are violated, the electrostatic

discharge (ESD) protection diodes will be forward-biased and excessive current can

flow through these diodes. If the system power supply design does not control the volt-

age sequencing, one or both of the circuits of Figure 17 can be added to meet these

requirements. The MUR420 Schottky diodes of Figure 17 control the maximum potential

difference between the external bus and core power supplies on power-up and the

1N5820 diodes regulate the maximum potential difference on power-down.

Figure 17. Example Voltage Sequencing Circuits

2.5V

1.8V

MUR420

1N5820

27

2183A–HIREL–12/02

Decoupling

Recommendations

Due to the PC7410M16’s dynamic power management feature, large address and data

buses and high operating frequencies, the PC7410M16 can generate transient power

surges and high frequency noise in its power supply, especially while driving large

capacitive loads. This noise must be prevented from reaching other components in the

PC7410M16 system and the PC7410M16 itself requires a clean, tightly regulated

source of power. Therefore, it is recommended that the system designer place at least

one decoupling capacitor at each V_DD, OV_DD, and L2OV_DDpin of the PC7410M16. It is

also recommended that these decoupling capacitors receive their power from separate

V_DD, (L2)OV_DD, and GND power planes in the PCB, utilizing short traces to minimize

inductance.

These capacitors should have a value of 0.01 µF or 0.1 µF. Only ceramic SMT (surface

mount technology) capacitors should be used to minimize lead inductance, preferably

0508 or 0603 orientations where connections are made along the length of the part.

Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital

Design: A Handbook of Black Magic (Prentice Hall, 1993) and contrary to previous rec-

ommendations for decoupling PowerPC microprocessors, multiple small capacitors of

equal value are recommended over using multiple values of capacitance.

In addition, it is recommended that there be several bulk storage capacitors distributed

around the PCB, feeding the V_DD, L2OV_DD, and OV_DDplanes to enable quick recharging

of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent

series resistance) rating to ensure the quick response time necessary. They should also

be connected to the power and ground planes through two vias to minimize inductance.

Suggested bulk capacitors are 100 - 330 µF (AVX TPS tantalum or Sanyo OSCON).

Connection

Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an

appropriate signal level. Unused active low inputs should be tied to OV_DD. Unused

active high inputs should be connected to GND. All NC (no-connect) signals must

remain unconnected.

Power and ground connections must be made to all external V_DD, OV_DD, L2OV_DD, and

GND pins of the PC7410M16.

See “IEEE 1149.1 AC Timing Specifications” on page 19 for a discussion of the

L2SYNC_OUT and L2SYNC_IN signals.

Output Buffer DC

Impedance

The PC7410M16 60x and L2 I/O drivers are characterized over process, voltage and

temperature. To measure Z₀, an external resistor is connected from the chip pad to

OV_DDor GND. Then the value of each resistor is varied until the pad voltage is OV_DD/2

(see Figure 18).

The output impedance is the average of two components, the resistances of the pull-up

and pull-down devices. When data is held low, SW2 is closed (SW1 is open), and R_Nis

trimmed until the voltage at the pad equals OV_DD/2. R_Nthen becomes the resistance of

the pull-down devices. When data is held high, SW1 is closed (SW2 is open), and R_Pis

trimmed until the voltage at the pad equals OV_DD/2. R_Pthen becomes the resistance of

the pull-up devices. R_Pand R_Nare designed to be close to each other in value.

Then Z₀= (R_P+ R_N)/2.

28

PC7410M16

2183A–HIREL–12/02

PC7410M16

Figure 18. Driver Impedance Measurement

OV_DD

RN

SW2

SW1

Pad

RP

Data

OGND

Table 13 summarizes the signal impedance results. The impedance increases with junc-

tion temperature and is relatively unaffected by bus voltage.

Table 13. Impedance Characteristics with V_DD= 1.8V, OV_DD= 1.8V or 2.5V,

T_j= -55°C to 125°C

Impedance

Processor bus

41.5 - 54.3

L2 Bus

42.7 - 54.1

39.3 - 50

Symbol

Unit

R_N

R_P

Z₀

Ohms

37.3 - 55.3

Pull-up Resistor

Requirements

The PC7410M16 requires high-resistive (weak: 10 kΩ) pull-up resistors on several con-

trol pins of the bus interface to maintain the control signals in the negated state after

they have been actively negated and released by the PC7410M16 or other bus masters.

These pins are TS, ARTRY, SHDO and SHD1.

In addition, the PC7410M16 has one open-drain style output that requires a pull-up

resistor (weak or stronger: 4.7 kΩ – 10 kΩ) if it is used by the system. This pin is

CKSTP_OUT.

During inactive periods on the bus, the address and transfer attributes may not be

driven by any master and may therefore float in the high-impedance state for relatively

long periods of time. Since the PC7410M16 must continually monitor these signals for

snooping, this float condition may cause excessive power draw by the input receivers on

the PC7410M16 or by other receivers in the system. It is recommended that these sig-

nals be pulled up through weak (10 kΩ) pull-up resistors by the system, or that they may

be otherwise driven by the system during inactive periods of the bus. The snooped

address and transfer attribute inputs are A[0:31], AP[0:3], TT[0:4], and GBL.

In systems where GBL is not connected and another device may be asserting TS for a

snoopable transaction while not driving GBL to the processor, we recommend that a

strong (1 kΩ) pull-up resistor be used on GBL.

29

2183A–HIREL–12/02

The data bus input receivers are normally turned off when no read operation is in

progress and therefore do not require pull-up resistors on the bus. Other data bus

receivers in the system, however, may require pull-ups, or that those signals be other-

wise driven by the system during inactive periods by the system. The data bus signals

are D[0:63], DP[0:7].

If address or data parity is not used by the system, and the respective parity checking is

disabled through HID0, the input receivers for those pins are disabled, and those pins

do not require pull-up resistors and should be left unconnected by the system. If all par-

ity generation is disabled through HID0, then all parity checking should also be disabled

through HID0, and all parity pins may be left unconnected by the system.

The L2 interface does not normally require pull-up resistors.

JTAG Configuration

Signals

Figure 19. Suggested TRST Connection

PC7410

HRESET

From Target

Board Sources

QACK

TRST

2 kΩ

COP Header

Figure 20. COP Connector Diagram

15

16

13

11

12

9

7

8

5

6

3

4

1

2

Top View

10

KEY

No pin

Note:

Pins 10, 12 and 14 are no connects. Pin 14 is not physically present.

30

PC7410M16

2183A–HIREL–12/02

PC7410M16

Table 14. COP Pin Definitions

Pins

Signal

TDO

Connection

TDO

Special Notes

1

2

3

4

QACK

TDI

QACK

TDI

Add 2K pull-down to ground. Must be merged with on-board QACK, if any.

TRST

Add 2K pull-down to ground. Must be merged with on-board TRST if any.

See Figure 19.

5

6

7

8

RUN/STOP

VDD_SENSE

TCK

No Connect

VDD

Used on 604e; leave no-connect for all other processors.

Add 2K pull-up to OV_DD(for short circuit limiting protection only).

TCK

CKSTP_IN

Optional. Add 10K pull-up to OV_DD. Used on several emulator products. Useful for

checkstopping the processor from a logic analyzer of other external trigger.

9

TMS

10

11

12

13

14

15

16

N/A

SRESET

N/A

SRESET

HRESET

Merge with on-board SRESET, if any.

HRESET

N/A

Merge with on-board HRESET.

Key location; pin should be removed.

CKSTP_OUT

Ground

CKSTP_OUT

Digital Ground

Add 10K pull-up to OV_DD.

Boundary scan testing is enabled through the JTAG interface signals. (BSDL descrip-

tions of the PC7410M16 are available on the Internet at:

www.mot.com/PowerPC/teksupport.).

The TRST signal is optional in the IEEE 1149.1 specification but is provided on all Pow-

erPC implementations. While it is possible to force the TAP controller to the reset state

using only the TCK and TMS signals, more reliable power-on reset performance will be

obtained if the TRST signal is asserted during power-on reset. Since the JTAG interface

is also used for accessing the common on-chip processor (COP) function of PowerPC

processors, simply tying TRST to HRESET is not practical.

The common on-chip processor (COP) function of PowerPC processors allows a remote

computer system (typically a PC with dedicated hardware and debugging software) to

access and control the internal operations of the processor. The COP interface con-

nects primarily through the JTAG port of the processor with some additional status

monitoring signals. The COP port requires the ability to independently assert HRESET

or TRST in order to fully control the processor. If the target system has independent

reset sources, such as voltage monitors, watchdog timers, power supply failures or

push-button switches, then the COP reset signals must be merged into these signals

with logic.

The arrangement shown in Figure 19 allows the COP to independently assert HRESET

or TRST, while ensuring that the target can drive HRESET as well. The pull-down resis-

tor on TRST ensures that the JTAG scan chain is initialized during power-on if a JTAG

interface cable is not attached; if it is attached, it is responsible for driving TRST when

needed.

31

2183A–HIREL–12/02

The COP header shown in Figure 19 adds many benefits – breakpoints, watchpoints,

register and memory examination/modification and other standard debugger features

are possible through this interface – and can be as inexpensive as an unpopulated foot-

print for a header to be added when needed.

The COP interface has a standard header for connection to the target system, based on

the 0.025” square-post 0.100” centered header assembly (often called a “Berg” header).

The connector typically has pin 14 removed as a connector key, as shown in Figure 20.

32

PC7410M16

2183A–HIREL–12/02

PC7410M16

Definitions

Datasheet Status

Description

Table 15. Datasheet Status

Datasheet Status

Validity

Objective specification

This datasheet contains target and goal

specifications for discussion with customer and

application validation.

Before design phase

Target specification

This datasheet contains target or goal

specifications for product development.

Valid during the design phase

Preliminary specification

α-site

This datasheet contains preliminary data.

Additional data may be published later; could

include simulation results.

Valid before characterization phase

Preliminary specification β-site

Product specification

Limiting Values

This datasheet also contains characterization

results.

Valid before the industrialization phase

Valid for production purposes

This datasheet contains final product

specification.

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the

limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at

any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for

extended periods may affect device reliability.

Application Information

Where application information is given, it is advisory and does not form part of the specification.

Life Support

Applications

These products are not designed for use in life support appliances, devices or systems

where malfunction of these products can reasonably be expected to result in personal

injury. Atmel customers using or selling these products for use in such applications do

so at their own risk and agree to fully indemnify Atmel for any damages resulting from

such improper use or sale.

33

2183A–HIREL–12/02

Ordering Information

16

PC (X) 7410

M

V

G

400

L

x

(1)

Revision Level

Rev. E

Prefix

Prototype

(1)

Application modifier

L: 1.8V 100 mV

Type

(1)

Max Internal Processor Speed

400 MHz

Multichip Package

450 MHz (TBC)

L2 cache densik,:

16 Mbits: 256K x 72 SSRAM

(1)

Temperature Range: T

V: -40°C, +110°C

j

M: -55°C, +125°C

(1)

Package

G: CBGA

GH: HITCE (TBC)

Note:

1. For availability of the different versions, contact your local Atmel sales office.

34

PC7410M16

2183A–HIREL–12/02

Atmel Headquarters

Atmel Operations

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 487-2600

Memory

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74025 Heilbronn, Germany

TEL (49) 71-31-67-0

FAX (49) 71-31-67-2340

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TEL 1(408) 441-0311

FAX 1(408) 436-4314

Europe

Atmel Sarl

Route des Arsenaux 41

Case Postale 80

CH-1705 Fribourg

Switzerland

Microcontrollers

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TEL 1(408) 441-0311

FAX 1(408) 436-4314

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TEL 1(719) 576-3300

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TEL (33) 4-42-53-60-00

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TEL (44) 1355-803-000

FAX (44) 1355-242-743

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty

which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors

which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does

not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted

by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical

components in life support devices or systems.

ATMEL^®is the registered trademark of Atmel.

The PowerPC names and the PowerPC logotype are trademarks of International Business Machines Corpora-

tion, used under license therform.

Motorola^®is the registered trademark of Motorola, Inc.

AltiVec^™is a trademark of Motorola, Inc.

Printed on recycled paper.

Other terms and product names may be the trademarks of others.

2183A–HIREL–12/02

0M


型号：	PC7410M16VG450L
厂家：	ATMEL
描述：	Microprocessor
文件：	总35页 (文件大小：357K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PC7410M16VG450L [ATMEL]

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