PC7410MGH500LE [ATMEL]

RISC Microprocessor, 32-Bit, 500MHz, CMOS, CBGA360, 25 X 25 MM, 3.24 MM HEIGHT, 1.27 MM PITCH, HITCE, CERAMIC, BGA-360;
PC7410MGH500LE
型号: PC7410MGH500LE
厂家: ATMEL    ATMEL
描述:

RISC Microprocessor, 32-Bit, 500MHz, CMOS, CBGA360, 25 X 25 MM, 3.24 MM HEIGHT, 1.27 MM PITCH, HITCE, CERAMIC, BGA-360

文件: 总57页 (文件大小:1023K)
中文:  中文翻译
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PC7410  
PowerPC 7410 RISC Microprocessor  
Datasheet  
Features  
22.8 SPECint95 (estimated), 17SPECfp95 at 500 MHz (estimated)  
917MIPS at 500 MHz  
Selectable Bus Clock (14 CPU Bus Dividers Up To 9x)  
Seven Selectable Core-to-L2 Frequency Divisors  
Selectable 603 Interface Voltage Below 3.3V (1.8V, 2.5V)  
Selectable L2 interface of 1.8V or 2.5V  
PD Typical 5.3W at 500 MHz, Full Operating Conditions  
Nap, Doze and Sleep Modes for Power Saving  
Superscalar (Four Instructions fetched per Clock Cycle)  
4 GB Direct Addressing Range  
Virtual Memory: 4 hexabytes (252)  
64-bit Data and 32-bit Address Bus Interface  
32 KB Instruction and Data Cache  
Eight Independent Execution Units and Three Register Files  
Write-back and Write-through Operations  
fINT Max = 450 MHz 500 MHz  
fBUS Max = 133 MHz  
Description  
The PC7410 is the second microprocessor that uses the fourth (G4) full implementation of the PowerPC Reduced Instruc-  
tion Set Computer (RISC) architecture. It is fully JTAG-compliant.  
The PC7410 maintains some of the characteristics of G3 microprocessors:  
The design is superscalar, capable of issuing three instructions per clock cycle into eight independent execution units  
The microprocessor provides four software controllable power-saving modes and a thermal assist unit management  
The microprocessor has separate 32-Kbyte, physically-addressed instruction and data caches with dedicated L2 cache  
interface with on-chip L2 tags  
In addition, the PC7410 integrates full hardware-based multiprocessing capability, including a 5-state cache coherency pro-  
tocol (4 MESI states plus a fifth state for shared intervention) and an implementation of the new AltiVec® technology  
instruction set.  
New features have been developed to make latency equal for double-precision and single-precision floating-point opera-  
tions involving multiplication. Additionally, in memory subsystem (MSS) bandwidth, the PC7410 offers an optional, high-  
bandwidth MPX bus interface.  
Unlike the PC7400, the PC7410 does not support the 3.3V I/O on the L2 cache interface.  
Visit our website: www.e2v.com  
for the latest version of the datasheet  
e2v semiconductors SAS 2007  
PC7410  
Screening  
CBGA Upscreenings Based on e2v Standards  
Full Military Temperature Range (TJ = -55° C, +125° C),  
Industrial Temperature Range (TJ = -40°C, +110°C)  
CI-CGA Package Version, HiTCE Package Version  
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128 bits  
(4 instructions)  
Instruction MMU  
Instruction Unit  
Branch Processing Unit  
SRs  
32-Kbyte  
iCache  
Tags  
Fetcher  
(Shadow)  
IBAT  
Additional features  
Time Base  
Counter/Decrementer  
Clock Multiplier  
JTAG/COP Interface  
Thermal/Power Management  
Performance Monitor  
Array  
128-entry  
ITLB  
64-entry BTIC/512-entry BHT  
LR/CTR  
Instruction  
Queue  
6-word  
Data MMU  
Dispatch Unit  
EA  
PA  
SRs  
(Original)  
32-Kbyte  
DCache  
Tags  
DBAT  
Array  
2 Instructions  
128-entry  
DTLB  
64-bit  
(2 Instructions)  
Reservation  
Station  
2-entry  
Reservation  
Station  
Reservation  
Station  
Reservation  
Station  
Reservation  
Station  
Reservation  
Station  
Reservation  
Station  
FPR File  
GPR File  
VR File  
6 Rename  
Buffers  
6 Rename  
Buffers  
6 Rename  
Buffers  
Load/Store  
Unit  
- Add -  
32-bit  
EA Calculation  
Finished Stores  
Completed  
Stores  
Integer  
Unit 1  
Integer  
Unit 2  
Floating  
Point Unit  
System  
Register  
Unit  
Vector  
Permute  
Unit  
Vector  
ALU  
64-bit  
64-bit  
Add-Multiply-  
divide  
- Add -  
Add-Multiply-  
divide  
VSIU VCIU VFPU  
FPSCR  
VSCR  
32-bit  
32-bit  
128-bit  
128-bit  
128 bits  
Completion Unit  
L2 Controller  
Memory Subsystem  
Data Reload Data Reload  
Table  
Bus Interface Unit  
8-entry  
Reorder Buffer  
L2 Data  
Transaction  
Queue  
L2 Tags  
L2 Miss  
Data  
Buffer  
Transaction  
Queue  
L2CR  
L2PMCR  
L2 Castout  
19-bit L2 Address Bus  
64- or 32-bit L2 Data Bus  
32-bit Address Bus  
Instruction  
Reload Buffer  
Instruction  
Reload Table  
64-bit Data Bus  
PC7410  
2. General Parameters  
Table 2-1 provides a summary of the general parameters of the PC7410.  
Table 2-1.  
Parameter  
Technology  
Die size  
Device Parameters  
Description  
0.18 µm CMOS, six-layer metal  
6.32 mm × 8.26 mm (52 mm2)  
10.5 million  
Transistor count  
Logic design  
Fully-static  
Surface-mount 360 Ceramic Ball Grid Array (CBGA)  
Surface mount 360 high coefficient of thermal expansion  
ceramic ball grid array (HiTCE)  
Packages  
Surface mount 360-column Ci-CGA Package  
1.8V ± 100 mV dc or 1.5V ± 50 mV dc (nominal; see Table 6-3 on page 11 for  
Recommended Operating Conditions)  
Core power supply  
I/O power supply  
1.8V ± 100 mV dc or  
2.5V ± 100 mV  
3.3V ± 165 mV (603 bus only)(1)  
(input thresholds are configuration pin selectable)  
Note:  
1. 3.3V I/O bus not supported for 1.5V core power supply processor version.  
3. Overview  
This section summarizes features of the PC7410’s implementation of the PowerPC architecture. Major  
features of the PC7410 are as follows:  
• Branch Processing Unit  
– Four instructions fetched per clock  
– One branch processed per cycle (plus resolving two speculations)  
– Up to one speculative stream in execution, one additional speculative stream in fetch  
– 512-entry Branch History Table (BHT) for dynamic prediction  
– 64-entry, 4-way set associative Branch Target Instruction Cache (BTIC) for eliminating  
branch delay slots  
• Dispatch Unit  
– Full hardware detection of dependencies (resolved in the execution units)  
– Dispatch two instructions to eight independent units (system, branch, load/store, fixed-point  
unit 1, fixed-point unit 2, floating-point, AltiVec permute, AltiVec ALU)  
– Serialization control (predispatch, postdispatch, execution serialization)  
• Decode  
– Register file access  
– Forwarding control  
– Partial instruction decode  
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• Completion  
– 8-entry completion buffer  
– Instruction tracking and peak completion of two instructions per cycle  
– Completion of instructions in program order while supporting out-of-order instruction  
execution, completion serialization and all instruction flow changes  
• Fixed-point Units (FXUs) that Share 32 GPRs for Integer Operands  
– Fixed-point Unit 1 (FXU1): multiply, divide, shift, rotate, arithmetic, logical  
– Fixed-point Unit 2 (FXU2)—shift, rotate, arithmetic, logical  
– Single-cycle arithmetic, shifts, rotates, logical  
– Multiply and divide support (multi-cycle)  
– Early out multiply  
• Three-stage Floating-point Unit and a 32-entry FPR File  
– Support for IEEE-754 standard single- and double-precision floating-point arithmetic  
– Three-cycle latency, one-cycle throughput (single or double precision)  
– Hardware support for divide  
– Hardware support for denormalized numbers  
– Time deterministic non-IEEE mode  
• System Unit  
– Executes CR logical instructions and miscellaneous system instructions  
– Special register transfer instructions  
• AltiVec Unit  
– Full 128-bit data paths  
Two dispatchable units: vector permute unit and vector ALU unit  
– Contains its own 32-entry 128-bit Vector Register File (VRF) with six renames  
– The vector ALU unit is further sub-divided into the Vector Simple Integer Unit (VSIU), the  
Vector Complex Integer Unit (VCIU) and the Vector Floating-point Unit (VFPU)  
– Fully pipelined  
• Load/Store Unit  
– One-cycle load or store cache access (byte, half-word, word, double-word)  
Two-cycle load latency with one-cycle throughput  
– Effective address generation  
– Hits under misses (multiple outstanding misses)  
– Single-cycle unaligned access within double-word boundary  
– Alignment, zero padding, sign extend for integer register file  
– Floating-point internal format conversion (alignment, normalization)  
– Sequencing for load/store multiples and string operations  
– Store gathering  
– Executes the cache and TLB instructions  
– Big- and little-endian byte addressing supported  
– Misaligned little-endian supported  
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– Supports FXU, FPU, and AltiVec load/store traffic  
– Complete support for all four architecture AltiVec DST streams  
• Level 1 (L1) Cache Structure  
– 32K 32-byte line, 8-way set associative instruction cache (iL1)  
– 32K 32-byte line, 8-way set associative data cache (dL1)  
– Single-cycle cache access  
– Pseudo Least-recently-used (LRU) replacement  
– Data cache supports AltiVec LRU and transient instructions algorithm  
– Copy-back or write-through data cache (on a page-per-page basis)  
– Supports all PowerPC memory coherency modes  
– Non-blocking instruction and data cache  
– Separate copy of data cache tags for efficient snooping  
– No snooping of instruction cache except for ICBI instruction  
• Level 2 (L2) Cache Interface  
– Internal L2 cache controller and tags; external data SRAMs  
– 512K, 1M and 2-Mbyte 2-way set associative L2 cache support  
– Copyback or write-through data cache (on a page basis or for all L2)  
– 32-byte (512K), 64-byte (1M), or 128-byte (2M) sectored line size  
– Supports pipelined (register-register) synchronous burst SRAMs and pipelined (register-  
register) late-write synchronous burst SRAMs  
– Supports direct mapped mode for 256K, 512K, 1M or 2 Mbytes of SRAM (either all, half or  
none of L2 SRAM must be configured as direct mapped  
– Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, ÷3, ÷3.5, and ÷4 supported  
– 64-bit data bus which also support 32-bits bus mode  
– Selectable interface voltages of 1.8V and 2.5V  
• Memory Management Unit  
– 128 entry, 2-way set associative instruction TLB  
– 128 entry, 2-way set associative data TLB  
– Hardware reload for TLBs  
– Four instruction BATs and four data BATs  
– Virtual memory support for up to four petabytes (252) of virtual memory  
– Real memory support for up to four gigabytes (232) of physical memory  
– Snooped and invalidated for TLBI instructions  
• Efficient Data Flow  
– All data buses between VRF, load/store unit, dL1, iL1, L2 and the bus are 128 bits wide  
– dL1 is fully pipelined to provide 128 bits per cycle to/from the VRF  
– L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L1s  
– Up to eight outstanding out-of-order cache misses between dL1 and L2/bus  
– Up to seven outstanding out-of-order transactions on the bus  
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– Load folding to fold new dL1 misses into older outstanding load and store misses to the  
same line  
– Store miss merging for multiple store misses to the same line. Only coherency action taken  
(i.e., address only) for store misses merged to all 32 bytes of a cache line (no data tenure  
needed)  
Two-entry finished store queue and four-entry completed store queue between load/store  
unit and dL1  
– Separate additional queues for efficient buffering of outbound data (castouts, write throughs,  
etc.) from dL1 and L2  
• Bus Interface  
– MPX bus extension to 60X processor interface  
– Mode-compatible with 60x processor interface  
– 32-bit address bus  
– 64-bit data bus  
– Bus-to-core frequency multipliers of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x,  
8x, 9x supported  
– Selectable interface voltages of 1.8V, 2.5V and 3.3V  
• Power Management  
– Low-power design with thermal requirements very similar to PC740 and PC750  
– Low voltage 1.8V or 1.5V processor core  
– Selectable interface voltages of 1.8V can reduce power in output buffers  
– Three static power saving modes: doze, nap, and sleep  
– Dynamic power management  
Testability  
– LSSD scan design  
– IEEE 1149.1 JTAG interface  
– Array Built-in Self Test (ABIST) – factory test only  
– Redundancy on L1 data arrays and L2 tag arrays  
• Reliability and Serviceability  
– Parity checking on 60x and L2 cache buses  
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4. Signal Description  
Figure 4-1. PC7410 Microprocessor Signal Groups  
L2OVDD  
GND  
L2AVDD  
L2ADDR[0:18]  
L2DATA[0:63]  
L2DP[0:7]  
BR  
BG  
1
1
19  
64  
8
13  
49  
1
L2 Cache  
Address/Data  
Address  
Arbitration  
ABB/AMON[0]  
TS  
1
1
Address  
Start  
L2CE  
L2WE  
1
1
A[0:31]  
AP[0:3]  
TT[0:4]  
TBST  
1
32  
4
L2CLKOUTA,  
L2CLKOUTB  
Address  
Bus  
L2 Cache  
Clock/Control  
2
L2SYNC_OUT  
L2SYNC_IN  
L2ZZ  
1
1
1
1
1
1
1
1
1
1
1
5
1
INT  
TSIZ[0:2]  
GBL  
3
SMI  
Transfer  
Attribute  
MCP  
1
SRESET  
HRESET  
CKSTP_IN  
CKSTP_OUT  
HIT  
WT  
1
Interrupts  
Reset  
CI  
PCX7410  
1
CHK  
1
AACK  
1
Address  
Termination  
SHDO, SHD1  
RSRV  
2
1
1
1
1
1
1
1
4
1
5
3
ARTRY  
DBG  
1
TBEN  
1
Processor  
Status  
Control  
EMODE  
QREQ  
Data  
Arbitration  
DBWO, DTI(0)  
DBB, DMON(0)  
D[0:63]  
DP[0:7]  
DTI(2)  
TA  
1
QACK  
1
DRDY  
64  
8
SYSCLK  
PLL_CFG[0:3]  
CLK_OUT  
JTAG:COP  
Factory Test  
Data  
Transfer  
Clock  
Control  
1
Test Interface  
LSSD_MODE  
1
Data  
Termination  
DTI1  
L1_TSTCLK,  
L2_TSTCLK  
1
BVSEL  
TEA  
I/O Voltage  
Selection  
1
1
1
L2VSEL  
12  
20  
1
OVDD  
VDD  
AVDD  
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5. Detailed Specification  
This specification describes the specific requirements for the microprocessor PC7410 in compliance with  
e2v standard screening.  
6. Applicable Documents  
1. MIL-STD-883: Test methods and procedures for electronics  
2. MIL-PRF-38535: Appendix A: General specifications for microcircuits  
The microcircuits are in accordance with the applicable documents and as specified herein.  
6.1  
Design and Construction  
6.1.1  
Terminal Connections  
Depending on the package, the terminal connections are as shown in Table 12-1 on page 33, Table 6-3  
on page 11 and Figure 4-1 on page 8.  
6.2  
Absolute Maximum Ratings  
Table 6-1.  
Symbol  
VDD  
Absolute Maximum Ratings(1)  
Characteristic  
Value  
Unit  
V
Core supply voltage  
-0.3 to 2.1(4)  
AVDD  
PLL supply voltage  
-0.3 to 2.1(4)  
V
L2AVDD  
OVDD  
L2OVDD  
VIN  
L2 DLL supply voltage  
60x bus supply voltage  
L2 bus supply voltage  
-0.3 to 2.1(4)  
V
-0.3 to 3.465(3)(6)  
-0.3 to 2.6(3)  
V
V
Processor bus input voltage  
L2 bus input voltage  
-0.3 to OVDD + 0,2V(2)(5)  
-0.3 to L2OVDD + 0,2V(2)(5)  
-0.3 to OVDD + 0,2V  
-55 to 150  
V
VIN  
V
JTAG signal input voltage  
VIN  
V
TSTG  
Storage temperature range  
Rework temperature  
°C  
°C  
260  
Notes: 1. Functional and tested operating conditions are given in Table 6-3 on page 11. Absolute maximum ratings are stress ratings  
only. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.  
2. Caution: VIN must not exceed OVDD or L2OVDD by more than 0.2V at any time including during power-on reset.  
3. Caution: L2OVDD/OVDD must not exceed VDD/AVDD/L2AVDD by more than 2.0V at any time including during power-on reset;  
this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.  
4. Caution: VDD/AVDD/L2AVDD must not exceed L2OVDD/OVDD by more than 0.4V at any time including during power-on reset;  
this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.  
5. VIN may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 6-1 on page 10.  
6. PC7410RXnnnLE (Rev 1.4) and later only. Previous revisions do not support 3.3V OVDD and have a maximum value OVDD of  
-0.3 to 2.6V.  
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Figure 6-1. Overshoot/Undershoot Voltage  
(L2)OVDD + 20%  
(L2)OVDD + 5%  
(L2)OVDD  
VIH  
VIL  
GND  
GND - 0.3V  
GND - 0.7V  
Not to exceed  
10% of tSYSCLK  
The PC7410 provides several I/O voltages to support both compatibility with existing systems and migra-  
tion to future systems. The PC7410 “core” voltage must always be provided at nominal voltage (see  
Table 6-3 on page 11 for actual recommended core voltage). Voltage to the L2 I/Os and processor inter-  
face I/Os are provided through separate sets of supply pins and may be provided at the voltages shown  
in Table 6-2. The input voltage threshold for each bus is selected by sampling the state of the voltage  
select pins at the negation of the signal HRESET. The output voltage will swing from GND to the maxi-  
mum voltage applied to the OVDD or L2OVDD power pins.  
Table 6-2.  
Input Threshold Voltage Setting  
Processor Bus Input  
Threshold is Relative to:  
L2 Bus Input Threshold is  
Relative to:  
BVSEL Signal  
0(1)  
L2VSEL Signal(3)  
1.8V  
0
1.8  
HRESET(1)(2)  
1(1)(4)(5)  
2.5V  
HRESET  
1
2.5  
3.3V(7)  
3.3V(7)  
2.5  
HRESET(6)  
HRESET  
Not supported  
Notes: 1. Caution: The input threshold selection must agree with the OVDD/L2OVDD voltages supplied.  
2. To select the 2.5V threshold option, L2VSEL/BVSEL should be tied to HRESET so that the two signals  
change state together. This is the preferred method for selecting this mode operation.  
3. To overcome the internal pull-up resistance, a pull-down resistance less than 250should be used.  
4. Default voltage setting if left unconnected (internal pulled-up). Parts Rev 1.4 and later only. Previous  
revisions do not support 3.3V OVDD, the default voltage setting if left unconnected is 2.5V.  
5. Parts Rev 1.4 and later only. Previous revisions do not support 3.3V OVDD, having BVSEL = 1 selects  
the 2.5V threshold.  
6. Parts Rev 1.4 and later only. Previous revisions do not support BVSEL = HRESET.  
7. NSpec does not support the default OVDD setting of 3.3V. The BVSEL input must be tie either low or  
HRESET.  
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6.3  
Recommended Operating Conditions  
Table 6-3.  
Recommended Operating Conditions(1)  
Recommended  
Symbol  
Characteristic  
Value  
Unit  
1.8 ± 100 mV  
or 1.5 ± 50 mV  
VDD  
Core supply voltage  
V
1.8 ± 100 mV  
or 1.5 ± 50 mV  
AVDD  
PLL supply voltage  
V
V
1.8 ± 100 mV  
or 1.5 ± 50 mV  
L2AVDD  
L2 DLL supply voltage  
OVDD  
OVDD  
BVSEL = 0  
1.8 ± 100 mV  
2.5 ± 100 mV  
3.3 ± 165 mV  
1.8 ± 100 mV  
2.5 ± 100 mV  
GND to OVDD  
GND to L2OVDD  
GND to OVDD  
-55 to 125  
V
V
Processor bus supply voltage see note (3)  
L2 bus supply voltage  
BVSEL = HRESET  
BVSEL = 1 or = HRESET(4)  
L2VSEL = 0  
(2)(3)  
OVDD  
V
L2OVDD  
L2OVDD  
VIN  
V
L2VSEL = 1(2) or L2VSEL = HRESET  
V
Processor bus  
V
VIN  
Input voltage  
L2 Bus  
V
VIN  
JTAG Signals  
V
TJ  
Die-junction temperature  
°C  
Notes: 1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not  
guaranteed.  
2. PC7410RXnnnLE (Rev 1.4) and later only. Previous revisions do not support 3.3V OVDD and have a recommended OVDD  
value of 2.5V ±100 mV for BVSEL = 1.  
3. PC7410RXnnnLE (Rev 1.4) and later only. Previous revisions do not support BVSEL = HRESET.  
4. Not supported for N spec with VDD = 1.5V  
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7. Thermal Characteristics  
7.1  
Package Characteristics  
Table 7-1.  
Package Thermal Characteristics CBGA  
Value  
Symbol  
RθJA  
Characteristic  
PC7410 CBGA  
Unit  
Junction-to-ambient thermal resistance, natural convection, single-layer (1s) board(1)(2)  
Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board(1)(3)  
Junction-to-ambient thermal resistance, 200 ft/min airflow, single-layer (1s) board(1)(3)  
Junction-to-ambient thermal resistance, 400 ft/min airflow, single-layer (1s) board  
Junction-to-ambient thermal resistance, 200 ft/min airflow, four-layer (2s2p) board(1)(3)  
Junction-to-ambient thermal resistance, 400 ft/min airflow, four-layer (2s2p) board  
Junction-to-board thermal resistance(4)  
24  
17  
° C/W  
° C/W  
° C/W  
° C/W  
° C/W  
° C/W  
° C/W  
° C/W  
RθJMA  
RθJMA  
RθJMA  
RθJMA  
RθJMA  
RθJB  
18  
16  
14  
13  
8
RθJC  
Junction-to-case thermal resistance(5)  
< 0.1  
Notes: 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) tempera-  
ture, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.  
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.  
3. Per JEDEC JESD51-6 with the board horizontal.  
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on  
the top surface of the board near the package.  
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883  
Method 1012.1) with the calculated case temperature. The actual value of RθJC for the part is less than 0.1°C/W.  
See “Thermal Management Information” on page 13 for more details about thermal management.  
The board designer can choose between several commercially available heat sink types to place on the  
PC7410. For exposed-die packaging technology as in Table 7-1, the intrinsic conduction thermal resis-  
tance paths are shown in Figure 7-1 on page 13.  
7.1.1  
Package Thermal Characteristics for HiTCE  
Table 7-2 provides the package thermal characteristics for the PC7410, HiTCE.  
Table 7-2.  
Package Thermal Characteristics for HiTCE Package  
Value  
PC7410 HiTCE  
6.8  
Characteristic  
Symbol  
Unit  
Junction-to-bottom of balls(1)  
RθJ  
RθJMA  
RθJB  
°C/W  
Junction-to-ambient thermal resistance, natural  
convection, four-layer (2s2p) board(1)(2)  
20.7  
11.0  
°C/W  
°C/W  
Junction to board thermal resistance  
Notes: 1. Simulation, no convection air flow.  
2. Per JEDEC JESD51-6 with the board horizontal.  
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7.1.2  
Package Thermal Characteristics for CI-CGA  
Table 7-3.  
Package Thermal Characteristics for CI-CGA  
Value  
PC7410 CI-CGA  
8.42  
Characteristic  
Symbol  
Unit  
Junction to board thermal resistance  
RθJB  
°C/W  
7.2  
Internal Package Conduction Resistance  
Figure 7-1 depicts the primary heat transfer path for a package with an attached heat sink mounted on a  
printed circuit board.  
Heat generated on the active side of the chip is conducted through the silicon, then through the heat sink  
attach material (or thermal interface material) and finally to the heat sink where it is removed by forced-  
air convection.  
Since the silicon thermal resistance is quite small, for a first-order analysis the temperature drop in the  
silicon may be neglected. Thus, the heat sink attach material and the heat sink conduction/convective  
thermal resistances are the dominant terms.  
Figure 7-1. C4 Package with Heat Sink Mounted on a Printed Circuit Board  
External Resistance  
Radiation  
Convection  
Heat Sink  
Thermal Interface Material  
Die Junction  
Die/Package  
Package/Leads  
Internal Resistance  
Printed Circuit Board  
Radiation  
Convection  
External Resistance  
7.3  
Thermal Management Information  
This section provides thermal management information for the ceramic ball grid array (CBGA) package  
for air-cooled applications. Proper thermal control design is primarily dependent upon the system-level  
design – the heat sink, airflow and thermal interface material. To reduce the die-junction temperature,  
heat sinks may be attached to the package by several methods: adhesive, spring clip to holes in the  
printed-circuit board or package and mounting clip and screw assembly; see Figure 7-2 on page 14. This  
spring force should not exceed 5.5 pounds of force. Ultimately, the final selection of an appropriate heat  
sink depends on many factors such as thermal performance at a given air velocity, spatial volume, mass,  
attachment method, assembly and cost.  
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Figure 7-2. CBGA Package Cross-section with Heat Sink Options  
Heat Sink  
Heat Sink Clip  
Adhesive or  
Thermal Interface Material  
Option  
Printed-Circuit Board  
7.3.1  
Adhesives and Thermal Interface Materials  
A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the  
thermal contact resistance. For those applications where the heat sink is attached by spring clip mecha-  
nism, Figure 7-3 on page 15 shows the thermal performance of three thin-sheet thermal-interface  
materials (silicone, graphite/oil, floroether oil), a bare joint and a joint with thermal grease as a function of  
contact pressure. As shown, the performance of these thermal interface materials improves with increas-  
ing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance.  
That is, the bare joint results in a thermal resistance approximately seven times greater than the thermal  
grease joint.  
Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board  
(see Figure 7-2). This spring force should not exceed 5.5 pounds of force. Therefore, synthetic grease  
offers the best thermal performance, considering the low interface pressure.  
The board designer can choose between several types of thermal interface. Heat sink adhesive materi-  
als should be selected based upon high conductivity, yet must have adequate mechanical strength to  
meet equipment shock/vibration requirements.  
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Figure 7-3. Thermal Performance of Different Thermal Interface Materials  
Silicone Sheet (0.006")  
Bare Joint  
2
Floroether Oil Sheet (0.007")  
Graphite/Oil Sheet (0.005")  
Synthetic Grease  
1.5  
1
0.5  
0
0
10  
20  
30  
40  
50  
60  
70  
80  
Contact Pressure (psi)  
7.3.1.1  
Heat Sink Selection Example  
For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:  
T = T + T + + θ + θ ) × P  
d
j
a
r
jc  
int  
sa  
where:  
TJ = die-junction temperature  
Ta = inlet cabinet ambient temperature  
Tr = air temperature rise within the computer cabinet  
θjc = junction-to-case thermal resistance  
θint = adhesive or interface material thermal resistance  
θsa = heat sink base-to-ambient thermal resistance  
Pd = power dissipated by the device  
During operation, the die-junction temperatures (TJ) should be maintained less than the value specified  
in Table 6-3 on page 11. The temperature of the air cooling the component greatly depends upon the  
ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic  
cabinet inlet-air temperature (Ta) may range from 30° C to 40° C. The air temperature rise within a cabi-  
net (Tr) may be in the range of 5° C to 10° C. The thermal resistance of the thermal interface material  
(θint) is typically about 1° C/W. Assuming a Ta of 30° C, a Tr of 5° C, a CBGA package θjc = 0.03, and a  
power consumption (Pd) of 5.0 watts, the following expression for TJ is obtained:  
T = 30° C + 5° C + (0,03° C W + 1,0° C W + θ ) × 5W  
j
sa  
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For a Thermally heat sink #2328B, the heat sink-to-ambient thermal resistance (θsa) versus airflow veloc-  
ity is shown in Figure 7-4.  
Figure 7-4. Thermalloy #2328B Heat Sink-to-ambient Thermal Resistance vs. Airflow Velocity  
8
Thermalloy #2328B Pin-Fin Heat Sink  
(25 x 28 x 15 mm)  
7
6
5
4
3
2
1
0
0.5  
1
1.5  
2
2.5  
3
3.5  
Approach Air Velocity (m/s)  
Assuming an air velocity of 0.5 m/s, the effective Rsa is 7°C/W, thus  
T = 30° C + 5° C + (0,03° C W + 1,0° C W + 7° C W) × 5W ,  
J
resulting in a die-junction temperature of approximately 75° C which is well within the maximum operat-  
ing temperature of the component.  
Other heat sinks offered by Chip Coolers, IERC, Thermalloy, Wakefield Engineering and Aavid Engi-  
neering offer different heat sink-to-ambient thermal resistances and may or may not need air flow.  
Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common fig-  
ure of merit used for comparing the thermal performance of various microelectronic packaging  
technologies, one should exercise caution when only using this metric in determining thermal manage-  
ment because no single parameter can adequately describe three-dimensional heat flow. The final die-  
junction operating temperature is not only a function of the component-level thermal resistance, but of  
the system-level design and its operating conditions. In addition to the component's power consumption,  
a number of factors affect the final operating die-junction temperature – airflow, board population (local  
heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level  
interconnect technology, system air temperature rise, altitude, etc.  
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Due to the complexity and the many variations of system-level boundary conditions for today's micro-  
electronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection and  
conduction) may vary widely. For these reasons, it is recommended to use conjugate heat transfer mod-  
els for the board, as well as system-level designs.  
To expedite system-level thermal analysis, several “compact” thermal-package models are available  
within FLOTHERM®. These are available upon request.  
8. Power Consideration  
8.1  
Power Management  
The PC7410 provides four power modes, selectable by setting the appropriate control bits in the MSR  
and HIDO registers. The four power modes are:  
• Full-power: This is the default power state of the PC7410. The PC7410 is fully powered and the  
internal functional units are operating at the full processor clock speed. If the dynamic power  
management mode is enabled, functional units that are idle will automatically enter a low-power state  
without affecting performance, software execution or external hardware.  
• Doze: All the functional units of the PC7410 are disabled except for the time base/decrementer  
registers and the bus snooping logic. When the processor is in doze mode, an external asynchronous  
interrupt, a system management interrupt, a decrementer exception, a hard or soft reset or machine  
check brings the PC7410 into the full-power state. The PC7410 in doze mode maintains the PLL in a  
fully powered state and locked to the system external clock input (SYSCLK) so a transition to the full-  
power state takes only a few processor clock cycles.  
• Nap: The nap mode further reduces power consumption by disabling bus snooping, leaving only the  
time base register and the PLL in a powered state. The PC7410 returns to the full-power state upon  
receipt of an external asynchronous interrupt, a system management interrupt, a decrementer  
exception, a hard or soft reset or a machine check input (MCP). A return to full-power state from a  
nap state takes only a few processor clock cycles. When the processor is in nap mode, if QACK is  
negated, the processor is put in doze mode to support snooping.  
• Sleep: Sleep mode minimizes power consumption by disabling all internal functional units, after which  
external system logic may disable the PLL and SYSCLK. Returning the PC7410 to the full-power  
state requires the enabling of the PLL and SYSCLK, followed by the assertion of an external  
asynchronous interrupt, a system management interrupt, a hard or soft reset or a machine check  
input (MCP) signal after the time required to relock the PLL.  
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8.2  
Power Dissipation  
Table 8-1.  
Power Consumption for PC7410 (1.8V)  
Processor (CPU) Frequency  
450 MHz  
Power Mode  
400 MHz  
500 MHz  
Core power supply  
1.5V  
1.8V  
1.5V  
1.8V  
1.8 V  
Unit  
Full-On Mode  
Typical(1)(3)  
2.92  
6.6  
4.2  
9.5  
3.29  
7.43  
4.7  
5.3  
W
W
Maximum(1)(2)(4)(5)  
10.7  
11.9  
Doze Mode  
Maximum(1)(2)(5)  
Nap Mode  
3.6  
1.35  
1.3  
4.3  
1.35  
1.3  
4.1  
1.5  
4.8  
1.5  
5.3  
1.65  
1.6  
W
W
W
Maximum(1)(2)(5)  
Sleep Mode  
Maximum(1)(2)(5)  
1.45  
1.45  
Sleep Mode - PLL and DLL Disabled  
Typical(1)(3)  
600  
1.1  
600  
1.1  
600  
1.1  
600  
1.1  
600  
1.1  
mW  
W
Maximum(1)(2)(5)  
Notes: 1. These values apply for all valid processor bus and L2 bus ratios. The values do not include I/O supply  
power (OVDD and L2OVDD) or PLL/DLL supply power (AVDD and L2AVDD). OVDD and L2OVDD power is  
system dependent, but is typically <5% of VDD power. Worst case power consumption for AVDD = 15  
mW and L2AVDD = 15 mW.  
2. Maximum power is measured at 105°C, at VDD = 1.8V or 1.5Vwhile running an entirely cache-resident,  
contrived sequence of instructions which keep the execution units, including AltiVec, maximally busy.  
3. Typical power is an average value measured at 65°C, VDD = 1.8V or 1.5V,  
OVDD = L2OVDD = 2.5V in a system while running a codec application that is AltiVec intensive.  
4. These values include the use of AltiVec. Without AltiVec operation, estimate a 25% decrease.  
5. Power consumption derating at low temperatures to be defined after device characterization.  
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9. Electrical Characteristics  
9.1  
Static Characteristics  
Table 9-1.  
DC Electrical Specifications (see Table 6-3 on page 11 for Recommended Operating Conditions)  
NominalBus  
Voltage(1)  
Symbol  
VIH  
Characteristic  
Min  
Max  
Unit  
1.8  
2.5  
3.3  
1.8  
2.5  
3.3  
1.8  
2.5  
3.3  
1.8  
2.5  
3.3  
1.8  
2.5  
3.3  
1.8  
2.5  
3.3  
1.8  
2.5  
3.3  
1.8  
2.5  
3.3  
0.65 x (L2)OVDD  
(L2)OVDD + 0.2  
Input high voltage  
VIH  
1.7  
(L2)OVDD + 0.2  
V
(all inputs except SYSCLK)(2)(3)(8)  
VIH  
2.0  
OVDD + 0.3  
VIL  
-0.3  
0.35 x (L2)OVDD  
Input low voltage  
VIL  
-0.3  
0.2 x (L2)OVDD  
V
V
(all inputs except SYSCLK)(8)  
VIL  
-0.3  
0.8  
CVIH  
CVIH  
CVIH  
CVIL  
CVIL  
CVIL  
IIN  
1.5  
OVDD + 0.2  
SYSCLK input high voltage(2)(8)  
2.0  
OVDD + 0.2  
2.4  
OVDD + 0.3  
-0.3  
0.2  
0.4  
0.4  
20  
35  
70  
20  
35  
70  
SYSCLK input low voltage(8)  
Input leakage current,  
-0.3  
V
-0.3  
IIN  
µA  
µA  
V
(2)(3)(6)(7)  
VIN = L2OVDD/OVDD  
IIN  
ITSI  
High-Z (off-state) leakage current,  
VIN = L2OVDD/OVDD  
ITSI  
(2)(3)(5)(7)  
ITSI  
VOH  
VOH  
VOH  
VOL  
VOL  
VOL  
CIN  
(L2)OVDD - 0.45  
Output high voltage, IOH = -5 mA(8)  
1.7  
2.4  
0.45  
0.4  
0.4  
6.0  
Output low voltage, IOL = 5 mA(8)  
V
Capacitance, VIN = 0V, f = 1 MHz(3)(4)(7)  
pF  
Note:  
1. Nominal voltages; see Table 6-3 on page 11 for recommended operating conditions.  
2. For processor bus signals, the reference is OVDD while L2OVDD is the reference for the L2 bus signals.  
3. Excludes factory test signals.  
4. Capacitance is periodically sampled rather than 100% tested.  
5. The leakage is measured for nominal OVDD and L2OVDD, or both OVDD and L2OVDD must vary in the same direction (for  
example, both OVDD and L2OVDD vary by either +5% or -5%).  
6. Measured at max OVDD/L2OVDD  
.
7. Excludes IEEE 1149.1 boundary scan (JTAG) signals.  
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8. For JTAG support: all signals controlled by BVSEL and L2VSEL will see VIL/VIH/VOL/VOH/CVIH/CVIL DC limits of 1.8V mode  
while either the EXTEST or CLAMP instruction is loaded into the IEEE 1149.1 instruction register by the UpdateIR TAP state  
until a different instruction is loaded into the instruction register by either another UpdateIR or a Test-Logic-Reset TAP state.  
If only TSRT is asserted to the part, and then a SAMPLE instruction is executed, there is no way to control or predict what  
the DC voltage limits are. If HRESET is asserted before executing a SAMPLE instruction, the DC voltage limits will be con-  
trolled by the BVSEL/L2VSEL settings during HRESET. Anytime HRESET is not asserted (i.e., just asserting TRST), the  
voltage mode is not known until either EXTEST or CLAMP is executed, at which time the voltage level will be at the DC limits  
of 1.8V.  
9.2  
Dynamic Characteristics  
After fabrication, parts are sorted by maximum processor core frequency as shown in “Clock AC Specifi-  
cations” and tested for conformance to the AC specifications for that frequency. These specifications are  
for valid processor core frequencies. The processor core frequency is determined by the bus (SYSCLK)  
frequency and the settings of the PLL_CFG[0:3] signals. Parts are sold by maximum processor core  
frequency.  
9.2.1  
Clock AC Specifications  
Table 9-2 provides the clock AC timing specifications as defined in Figure 9-1 on page 21.  
Table 9-2.  
Clock AC Timing Specifications (See Table 6-3 on page 11 for Recommended Operating Conditions)  
Maximum Processor Core Frequency  
400 MHz  
450 MHz  
500 MHz  
Symbol  
Characteristic  
Min  
Max  
400  
800  
133  
30  
Min  
Max  
450  
900  
133  
30  
Min  
Max  
500  
1000  
133  
30  
Unit  
MHz  
MHz  
MHz  
ns  
(1)  
fCORE  
Processor frequency  
VCO frequency  
350  
700  
33  
350  
700  
33  
350  
700  
33  
(1)  
fVCO  
(1)  
fSYSCLK  
SYSCLK frequency  
SYSCLK cycle time  
tSYSCLK  
7.5  
7.5  
7.5  
(2)  
tKR & tKF  
1.0  
1.0  
1
ns  
SYSCLK rise and fall time  
(3)  
t
KR & tKF  
0.5  
0.5  
0.5  
ns  
(4)  
tKHKL/tSYSCLK  
SYSCLK duty cycle measured at OVDD/2  
SYSCLK jitter(5)  
40  
60  
40  
60  
40  
60  
%
±150  
100  
±150  
100  
±150  
100  
ps  
Internal PLL relock time(6)  
µs  
Note:  
1. Caution: The SYSCLK frequency and PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK (bus) fre-  
quency, CPU (core) frequency and PLL (VCO) frequency do not exceed their respective maximum or minimum operating  
frequencies. Refer to the PLL_CFG[0:3] signal description in “Clock Selection” on page 42 for valid PLL_CFG[0:3] settings.  
2. Rise and fall times for the SYSCLK input measured from 0.4V to 2.4V when OVDD = 3.3V nominal.  
3. Rise and fall times for the SYSCLK input measured from 0.2V to 1.2V when OVDD = 1.8V or 2.5V nominal.  
4. Timing is guaranteed by design and characterization.  
5. This represents total input jitter, short-term and long-term combined, and is guaranteed by design.  
6. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for  
PLL lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies  
when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held  
asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.  
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Figure 9-1. SYSCLK Input Timing Diagram  
tKR  
tKF  
tSYSCLK  
tKHKL  
CVIH  
CVIL  
SYSCLK  
VM  
VM  
VM  
Note:  
VM = Midpoint Voltage (OVDD/2).  
9.2.2  
Processor Bus AC Specifications  
Table 9-3 provides the processor AC timing specifications for the PC7410 as defined in Figure 9-3 on  
page 23 and Figure 9-4 on page 24. Timing specifications for the L2 bus are provided in “L2 Bus AC  
Specifications” on page 26.  
Table 9-3.  
Processor Bus AC Timing Specifications(1) at VDD = AVDD = 1.8V ± 100 mV;  
-55°C TJ 125°C, OVDD = 1.8V ± 100 mV  
400, 450, 500 MHz  
Symbol(2)  
tIVKH  
Parameter  
Input Setup  
Input Hold  
Min  
1.0  
0
Max  
Unit  
ns  
tIXKH  
ns  
Output Valid Times:(7)(8)  
TS  
tKHTSV  
tKHARV  
tKHOV  
3.0  
2.3  
3.0  
ns  
ns  
ARTRY/SHD0/SHD1  
All Other Outputs  
Output Hold Times:(7)(12)  
TS  
tKHTSX  
tKHARX  
tKHOX  
0.5  
0.5  
0.5  
ARTRY/SHD0/SHD1  
All Other Outputs  
(11)  
tKHOE  
SYSCLK to Output Enable  
0.5  
ns  
ns  
SYSCLK to Output High Impedance (all except ABB/AMON[0], ARTRY/SHD,  
DBB/DMON[0]), SHD0, SHD1)  
tKHOZ  
3.5  
(5)(9)(11)  
tKHABPZ  
SYSCLK to ABB/AMON[0], DBB/DMON[0] High Impedance after precharge  
Maximum Delay to ARTRY/SHD0/SHD1 Precharge  
1
1
tSYSCLK  
tSYSCLK  
(5)(10)(11)  
tKHARP  
Note:  
1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input  
SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the sig-  
nal in question. All output timings assume a purely resistive 50load (see Figure 9-3 on page 23). Input and output timings  
are measured at the pin; time-of-flight delays must be added for trace lengths, vias and connectors in the system.  
2. The symbology used for timing specifications herein follows the pattern of  
t(signal)(state)(reference)(state) for inputs and t(reference)(state)(signal)(state) for outputs. For example, tIVKH symbolizes the time input signals  
(I) reach the valid state (V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And tKHOV  
symbolizes the time from SYSCLK (K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can  
be read as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH) - note the position of  
the reference and its state for inputs -and output hold time can be read as the time from the rising edge (KH) until the output  
went invalid (OX).  
3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 9-4 on page 24).  
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4. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of  
255 bus clocks after the PLL re-lock time during the power-on reset sequence.  
5. tSYSCLK is the period of the external clock (SYSCLK) in nanoseconds(ns). The numbers given in the table must be multiplied  
by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question.  
6. Mode select signals are BVSEL, EMODE, L2VSEL, PLL_CFG[0:3].  
7. All other output signals are composed of the following - A[0:31], AP[0:3], TT[0:4], TBST, TSIZ[0:2], GBL, WT, CI, DH[0:31],  
DL[0:31], DP[0:7], BR, CKSTP_OUT, DRDY, HIT, QREQ, RSRV.  
8. Output valid time is measured from 2.4V to 0.8V which may be longer than the time required to discharge from VDD to 0.8V.  
9. According to the 60x bus protocol, ABB and DBB are driven only by the currently active bus master. They are asserted low  
then precharged high before returning to high-Z as shown in Figure 9-2 on page 23. The nominal precharge width for ABB or  
DBB is 0.5 x tSYSCLK, i.e., less than the minimum tSYSCLK period, to ensure that another master asserting ABB, or DBB on the  
following clock will not contend with the precharge. Output valid and output hold timing is tested for the signal asserted. Out-  
put valid time is tested for precharge.The high-Z behavior is guaranteed by design.  
10. According to the 60x bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately fol-  
lowing AACK. Bus contention is not an issue since any master asserting ARTRY will be driving it low. Any master asserting  
it low in the first clock following AACK will then go to high-Z for one clock before precharging it high during the second cycle  
after the assertion of AACK. The nominal precharge width for ARTRY is 1.0 tSYSCLK ; i.e., it should be high-Z as shown in Fig-  
ure 9-2 on page 23 before the first opportunity for another master to assert ARTRY. Output valid and output hold timing are  
tested for the signal asserted. Output valid time is tested for precharge. The high-Z behavior is guaranteed by design.  
11. Guaranteed by design and not tested.  
12. Output hold time characteristics can be altered by the use of the L2_TSTCK pin during system reset, similar to L2 output  
hold being altered by the use of bits [14-15] in the L2CR register. Information on the operation of the L2_TSTCLK will be  
included in future revisions of this specification.  
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Figure 9-2. Input/Output Timing Diagram  
VM  
VM  
VM  
SYSCLK  
tIVKH  
tIXKH  
All Inputs  
tKHOX  
tKHOV  
All Outputs  
(except TS, ABB,  
ARTRY, DBB)  
tKHOE  
tKHOZ  
All Outputs  
(except TS, ABB,  
ARTRY, DBB)  
tKHABPZ  
tKHTSV  
tKHTSX  
TS,  
tKHTSV  
ABB/AMON[0],  
DBB/DMON[0]  
tKHARPZ  
tKHARP  
tKHARX  
tKHARV  
ARTRY,  
tKHARV  
SHD0,  
SHD1  
VM = Midpont Voltage (OVDD/2)  
Figure 9-3. AC Test Load for the 60x Interface  
Output  
Z0 = 50Ω  
OVDD/2  
RL = 50Ω  
Figure 9-4 on page 24 provides the mode select input timing diagram for the PC7410. The mode select  
inputs are sampled twice, once before and once after HRESET negation.  
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Figure 9-4. Mode Input Timing Diagram  
VM  
VM  
SYSCLK  
HRESET  
Mode Signals  
First sample  
Second sample  
where VM = Midpoint Voltage (OVDD/2)  
L2 Clock AC Specifications  
9.2.3  
The L2CLK frequency is programmed by the L2 configuration register (L2CR[4:6]) core-to-L2 divisor  
ratio. See Table 13-2 on page 43 for example core and L2 frequencies at various divisors. Table 9-4 on  
page 25 provides the potential range of L2CLK output AC timing specifications as defined in Figure 9-5  
on page 26.  
The L2SYNC_OUT signal is intended to be routed halfway out to the SRAMs and then returned to the  
L2SYNC_IN input of the PC7410 to synchronize L2CLKOUT at the SRAM with the processor’s internal  
clock. L2CLKOUT at the SRAM can be offset forward or backward in time by shortening or lengthening  
the routing of L2SYNC_OUT to L2SYNC_IN. See FreescaleApplication Note AN179/D "PowerPC  
Backside L2 Timing Analysis for the PCB Design Engineer."  
The minimum L2CLK frequency of Table 9-4 is specified by the maximum delay of the internal DLL. The  
variable-tap DLL introduces up to a full clock period delay in the L2CLKOUTA, L2CLKOUTB and  
L2SYNC_OUT signals so that the returning L2SYNC_IN signal is phase aligned with the next core clock  
(divided by the L2 divisor ratio). Do not choose a core-to-L2 divisor which results in an L2 frequency  
below this minimum, or the L2CLKOUT signals provided for SRAM clocking will not be phase aligned  
with the PC7410 core clock at the SRAMs.  
The maximum L2CLK frequency shown in Table 9-4 is the core frequency divided by one. Very few L2  
SRAM designs will be able to operate in this mode. Most designs will select a greater core-to-L2 divisor  
to provide a longer L2CLK period for read and write access to the L2 SRAMs. The maximum L2CLK fre-  
quency for any application of the PC7410 will be a function of the AC timings of the PC7410, the AC  
timings for the SRAM, bus loading and printed circuit board trace length.  
e2v is similarly limited by system constraints and cannot perform tests of the L2 interface on a socketed  
part on a functional tester at the maximum frequencies of Table 9-4. Therefore, functional operation and  
AC timing information are tested at core-to-L2 divisors of 2 or greater.  
L2 input and output signals are latched or enabled respectively by the internal L2CLK (which is SYSCLK  
multiplied up to the core frequency and divided down to the L2CLK frequency). In other words, the AC  
timings of Table 9-5 on page 26 are entirely independent of L2SYNC_IN. In a closed loop system, where  
L2SYNC_IN is driven through the board trace by L2SYNC_OUT, L2SYNC_IN only controls the output  
phase of L2CLKOUTA and L2CLKOUTB which are used to latch or enable data at the SRAMs. How-  
ever, since in a closed loop system L2SYNC_IN is held in phase alignment with the internal L2CLK, the  
signals of Table 9-5 are referenced to this signal rather than the not-externally-visible internal L2CLK.  
During manufacturing test, these times are actually measured relative to SYSCLK.  
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Table 9-4.  
Symbol  
L2CLK Output AC Timing Specifications at Recommended Operating Conditions (See Table 6-3 on page  
11)  
400 MHz  
Min  
450 MHz  
Min  
500 MHz  
Min  
Parameter  
Max  
400  
7.5  
Max  
400  
7.5  
Max  
400  
7.5  
Unit  
MHz  
ns  
(1)(4)  
fL2CLK  
L2CLK frequency  
L2CLK cycle time  
L2CLK duty cycle  
Internal DLL-relock time(3)  
DLL capture window(5)  
133  
2.5  
133  
2.5  
133  
2.5  
tL2CLK  
(2)  
t
CHCL/tL2CLK  
50  
50  
50  
%
640  
0
640  
0
640  
0
-
L2CLK  
ns  
10  
50  
10  
50  
10  
L2CLKOUT output-to-output  
skew(6)  
tL2CSKW  
-
-
-
-
-
-
50  
ps  
ps  
L2CLKOUT output jitter(6)  
±150  
±150  
±150  
Note:  
1. L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB, and L2SYNC_OUT pins. The L2CLK frequency to core frequency set-  
tings must be chosen such that the resulting L2CLK frequency and core frequency do not exceed their respective maximum  
or minimum operating frequencies. The maximum L2LCK frequency will be system-dependent. L2CLK_OUTA and  
L2CLK_OUTB must have equal loading.  
2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.  
3. The DLL re-lock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of L2CLK to  
compute the actual time duration in nanoseconds. Re-lock timing is guaranteed by design and characterization.  
4. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz. This adds more delay to each tap of the DLL.  
5. Allowable skew between L2SYNC_OUT and L2SYNC_IN.  
6. Guaranteed by design and not tested. This output jitter number represents the maximum delay of one tap forward or one tap  
back from the current DLL tap as the phase comparator seeks to minimize the phase difference between L2SYNC_IN and  
the internal L2CLK. This number must be comprehended in the L2 timing analysis. The input jitter on SYSCLK affects  
L2CLKOUT and the L2 address/data/control signals equally and therefore is already comprehended in the AC timing and  
does not have to be considered in the L2 timing analysis.  
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Figure 9-5.  
L2CLK_OUT Output Timing Diagram  
L2 Single-Ended Clock Mode  
tL2CLK  
tCHCL  
tL2CR  
tL2CF  
L2CLK_OUTA  
VM  
VM  
VM  
VM  
VM  
VM  
VM  
VM  
VM  
L2CLK_OUTB  
L2SYNC_OUT  
tL2CSKW  
VM  
L2 Differential Clock Mode  
tL2CLK  
tCHCL  
L2CLK_OUTB  
L2CLK_OUTA  
VM  
VM  
VM  
VM  
VM  
VM  
L2SYNC_OUT  
Note:  
VM = Midpoint Voltage (L2OVDD/2)  
9.2.4  
L2 Bus AC Specifications  
Table 9-5 provides the L2 bus interface AC timing specifications for the PC7410 as defined in Figure 9-6  
on page 27 and Figure 9-7 on page 28 for the loading conditions described in Figure 9-8 on page 28.  
Table 9-5.  
L2 Bus Interface AC Timing Specifications at VDD = AVDD = L2AVDD = 1.8V ± 100mV or 1.5V ± 50mV ;  
-55°C TJ 125°C, L2OVDD = 2.5V ± 100mV or L2OVDD = 1.8V ± 100mV  
400, 450, 500 MHz  
Symbol  
Parameter  
Min  
Max  
Unit  
(1)  
tL2CR & tL2CF  
L2SYNC_IN rise and fall time  
1.0  
ns  
Setup Times  
ns  
ns  
(2)  
tDVL2CH  
Data and parity  
1.5  
Input Hold Times  
Data and parity  
(2)  
tDXL2CH  
0.0  
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Table 9-5.  
Symbol  
L2 Bus Interface AC Timing Specifications at VDD = AVDD = L2AVDD = 1.8V ± 100mV or 1.5V ± 50mV ;  
-55°C TJ 125°C, L2OVDD = 2.5V ± 100mV or L2OVDD = 1.8V ± 100mV (Continued)  
400, 450, 500 MHz  
Parameter  
Min  
Max  
Unit  
Valid Times  
All outputs when L2CR[14:15] = 00  
All outputs when L2CR[14:15] = 01  
All outputs when L2CR[14:15] = 10  
All outputs when L2CR[14:15] = 11  
2.5  
2.5  
2.9  
3.5  
(3)(4)  
tL2CHOV  
ns  
Output Hold Times  
All outputs when L2CR[14:15] = 00  
All outputs when L2CR[14:15] = 01  
All outputs when L2CR[14:15] = 10  
All outputs when L2CR[14:15] = 11  
0.4  
0.8  
1.2  
1.6  
(3)  
tL2CHOX  
ns  
ns  
L2SYNC_IN to high impedance  
All outputs when L2CR[14:15] = 00  
All outputs when L2CR[14:15] = 01  
All outputs when L2CR[14:15] = 10  
All outputs when L2CR[14:15] = 11  
2.0  
2.5  
3.0  
3.5  
tL2CHOZ  
Note:  
1. Rise and fall times for the L2SYNC_IN input are measured from 20% to 80% of L2OVDD.  
2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of  
the input L2SYNC_IN (see Figure 9-6). Input timings are measured at the pins.  
3. All output specifications are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint of the sig-  
nal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50load (see  
Figure 9-8 on page 28).  
4. The outputs are valid for both single-ended and differential L2CLK modes. For pipelined registered synchronous burst  
RAMs, L2CR[14:15] = 00 is recommended. For pipelined late-write synchronous burst SRAMs, L2CR[14:15] = 10 is  
recommended.  
Figure 9-6. L2 Bus Input Timing Diagram  
tL2CR  
tL2CF  
VM  
L2SYNC_IN  
tDVL2CH  
tDXL2CH  
L2 Data and Data  
Parity Inputs  
Note:  
VM = Midpoint Voltage (L2OVDD/2)  
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Figure 9-7. L2 Bus Output Timing Diagram  
VM  
VM  
L2SYNC_IN  
tL2CHOV  
tL2CHOX  
All Outputs  
tL2CHOZ  
L2DATA BUS  
Note:  
VM = Midpoint Voltage (L2OVDD/2)  
Figure 9-8. AC Test Load for the L2 Interface  
Output  
Z0 = 50Ω  
L2OVDD/2  
RL = 50Ω  
9.2.5  
IEEE 1149.1 AC Timing Specifications  
Table 9-6 provides the IEEE® 1149.1 (JTAG) AC timing specifications as defined in Figure 9-9 on page  
29, Figure 9-10 on page 29, Figure 9-11 on page 29 and Figure 9-12 on page 30.  
Table 9-6.  
JTAG AC Timing Specifications (Independent of SYSCLK) (1)at Recommended Operating  
Conditions (see Table 6-3 on page 11)  
Symbol  
fTCLK  
Parameter  
Min  
0
Max  
Unit  
MHz  
ns  
TCK frequency of operation  
TCK cycle time  
33.3  
t TCLK  
tJHJL  
30  
15  
0
TCK clock pulse width measured at OVDD/2  
TCK rise and fall times  
TRST assert time  
ns  
t
JR & tJF  
2
ns  
(2)  
tTRST  
25  
ns  
Input Setup Times:  
Boundary-scan data  
TMS, TDI  
(3)  
tDVJH  
tIVJH  
4
0
ns  
ns  
ns  
ns  
Input Hold Times:  
Boundary-scan data  
TMS, TDI  
(3)  
tDXJH  
tIXJH  
20  
25  
Valid Times:  
Boundary-scan data  
TDO  
(4)  
tJLDV  
4
4
20  
25  
tJLOV  
TCK to output high impedance:  
Boundary-scan data  
TDO  
(4)(5)  
(5)  
tJLDZ  
tJLOZ  
3
3
19  
9
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Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of  
the signal in question. The output timings are measured at the pins. All output timings assume a purely  
resistive 50 load (see Figure 9-9). Time-of-flight delays must be added for trace lengths, vias and con-  
nectors in the system.  
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.  
3. Non-JTAG signal input timing with respect to TCK.  
4. Non-JTAG signal output timing with respect to TCK.  
5. Guaranteed by design and characterization.  
Figure 9-9. Alternate AC Test Load for the JTAG Interface  
Output  
Z0 = 50Ω  
OVDD/2  
RL = 50Ω  
Figure 9-10. JTAG Clock Input Timing Diagram  
tJR  
tJF  
VM  
VM  
VM  
TCLK  
tJHJL  
tTCLK  
Note:  
VM = Midpoint Voltage (OVDD/2)  
Figure 9-11. TRST Timing Diagram  
tTRST  
VM  
VM  
TRST  
Note:  
VM = Midpoint Voltage (OVDD/2)  
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Figure 9-12. Boundary-scan Timing Diagram  
TCK  
VM  
VM  
tDVJH  
Boundary  
tDXJH  
Data Inputs  
Input Data  
Valid  
tJLDV  
tJLDX  
Boundary  
Data Outputs  
Output Data Valid  
tJLDZ  
Boundary  
Data Outputs  
Output Data Valid  
Note:  
VM = Midpoint Voltage (OVDD/2)  
Figure 9-13. Test Access Port Timing Diagram  
VM  
VM  
TCK  
tIVJH  
tIXJH  
TDI, TMS  
Input Data  
Valid  
tJLOV  
tJLOX  
Output Data Valid  
TDO  
tJLOZ  
TDO  
Output Data Valid  
Note:  
VM = Midpoint Voltage (OVDD/2)  
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10. Preparation for Delivery  
10.1 Handling  
MOS devices must be handled with certain precautions to avoid damage due to accumulation of static  
charge. Input protection devices have been designed in the chip to minimize the effect of static buildup.  
However, the following handling practices are recommended:  
• Devices should be handled on benches with conductive and grounded surfaces  
• Ground test equipment, tools and operator  
• Do not handle devices by the leads  
• Store devices in conductive foam or carriers  
• Avoid use of plastic, rubber or silk in MOS areas  
• Maintain relative humidity above 50% if practical  
• For CI-CGA packages, use specific tray to take care of the highest height of the package compared  
with the normal CBGA  
11. Package Mechanical Data  
11.1 Parameters  
The package parameters are as provided in the following list. The package type is 25x25 mm, 360-lead  
CBGA, HiTCE and CI-CGA.  
Table 11-1. Package Parameters  
Parameter  
Package outline  
25 mm x 25 mm  
Interconnects  
360 (19 x 19 ball array minus one)  
1.27 mm (50 mil)  
Pitch  
Minimum module height  
Maximum module height  
Ball or column diameter  
2.65 mm (CBGA, HiTCE), 3.65 mm (CI-CGA)  
3.20 mm (CBGA), 3.24 mm (HiTCE), 4.20 mm (CI-CGA)  
0.89 mm (35 mil)  
The following remarks apply to Figure 12-7 on page 39 and Figure 12-9 on page 41:  
• Dimensions and tolerancing are as per ASME Y14.5M-1994.  
• All dimensions are in millimeters.  
Top side A1 corner index is a metallized feature with various shapes. Bottom side A1 corner is  
designated with a ball missing from the array.  
• Dimension B is the maximum solder ball diameter measured parallel to datum A.  
• D2 and E2 define the area occupied by the die and underfill. Actual size of this area may be smaller  
than shown. D3 and E3 are the minimum clearance from the package edge to the chip capacitors.  
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12. Pin Assignments  
12.1 BGA360 Package  
Figure 12-1, Figure 12-2, Figure 12-3 on page 33 and Figure 12-4 on page 33 show top views of the  
packages available for the PC7410. Note that these drawings are not to scale.  
Figure 12-1. Top View of 360-Ball CBGA and 360-Pin CI-CGA Packages  
Pin A1 Index  
Figure 12-2. Top View of 360-pin CBGA and CI-CGA Packages  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19  
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
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Figure 12-3. Cross-section of 360-ball CBGA and HiTCE Package  
View  
Substrate Assembly  
Die  
Encapsulant  
Figure 12-4. Cross-section of 360-column CI-CGA Package  
View  
Substrate Assembly  
Die  
Encapsulant  
Table 12-1. Pinout Listing for the PC7410, 360-ball CBGA and CI-CGA packages  
Signal Name  
Pin Number  
Active  
I/O  
I/F Select(1)  
A13, D2, H11, C1, B13, F2, C13, E5, D13, G7, F12, G3, G6,  
H2, E2, L3, G5, L4, G4, J4, H7, E1, G2, F3, J7, M3, H3, J2,  
J6, K3, K2, L2  
A[0:31]  
High  
I/O  
BVSEL  
AACK  
N3  
L7  
Low  
Low  
Input  
BVSEL  
BVSEL  
ABB(12)  
AMON[0](12)  
Output  
AP[0:3]  
C4, C5, C6, C7  
High  
Low  
I/O  
I/O  
BVSEL  
BVSEL  
VDD  
ARTRY  
L6  
AVDD  
A8  
H1  
E7  
W1  
K11  
C2  
B8  
D7  
E3  
BG  
Low  
Low  
High  
Low  
Low  
Low  
Low  
High  
Input  
Output  
Input  
BVSEL  
BVSEL  
N/A  
BR  
BVSEL(1)(3)(8)(9)(14)  
CHK(4)(8)(9)  
CI  
Input  
BVSEL  
BVSEL  
BVSEL  
BVSEL  
BVSEL  
I/O  
CKSTP_IN  
CKSTP_OUT  
CLK_OUT  
Input  
Output  
Output  
DBB(12)  
DMON[0](12)  
K5  
K1  
Low  
Low  
Output  
Input  
BVSEL  
BVSEL  
DBG  
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Table 12-1. Pinout Listing for the PC7410, 360-ball CBGA and CI-CGA packages (Continued)  
Signal Name  
Pin Number  
Active  
I/O  
I/F Select(1)  
W12, W11, V11, T9, W10, U9, U10, M11, M9, P8, W7, P9,  
W9, R10, W6, V7, V6, U8, V9, T7, U7, R7, U6, W5, U5, W4,  
P7, V5, V4, W3, U4, R5  
DH[0:31]  
High  
I/O  
BVSEL  
M6, P3, N4, N5, R3, M7, T2, N6, U2, N7, P11, V13, U12,  
P12, T13, W13, U13, V10, W8, T11, U11, V12, V8, T1, P1,  
V1, U1, N1, R2, V3, U3, W2  
DL[0:31]  
High  
I/O  
BVSEL  
DP[0:7]  
L1, P2, M2, V2, M1, N2, T3, R1  
K9  
High  
Low  
I/O  
BVSEL  
BVSEL  
DRDY(6)(8)(13)  
Output  
DBWO  
DTI[0]  
D1  
Low  
Input  
BVSEL  
DTI[1:2](10)(13)  
EMODE(7)(10)  
GBL  
H6, G1  
A3  
High  
Low  
Low  
Input  
Input  
I/O  
BVSEL  
BVSEL  
BVSEL  
B1  
D10, D14, D16, D4, D6, E12, E8, F4, F6, F10, F14, F16, G9,  
G11, H5, H8, H10, H12, H15, J9, J11, K4, K6, K8, K10, K12,  
K14, K16, L9, L11, M5, M8, M10, M12, M15, N9, N11, P4,  
P6, P10, P14, P16, R8, R12, T4, T6, T10, T14, T16  
GND  
N/A  
HIT(6)(8)  
B5  
Low  
Low  
Low  
High  
Output  
Input  
Input  
Input  
BVSEL  
BVSEL  
BVSEL  
BVSEL  
HRESET  
INT  
B6  
C11  
F8  
L1_TSTCLK(2)  
L17, L18, L19, M19, K18, K17, K15, J19, J18, J17, J16, H18,  
H17, J14, J13, H19, G18  
L2ADDR[0:16]  
High  
High  
Output  
Output  
L2VSEL  
L2ADDR[17:18](8)  
L2AVDD  
K19, W19  
L13  
L2VSEL  
VDD  
L2CE  
P17  
Low  
High  
High  
Output  
Output  
Output  
L2VSEL  
L2VSEL  
L2VSEL  
L2CLKOUTA  
L2CLKOUTB  
N15  
L16  
U14, R13, W14, W15, V15, U15, W16, V16, W17, V17, U17,  
W18, V18, U18, V19, U19, T18, T17, R19, R18, R17, R15,  
P19, P18, P13, N14, N13, N19, N17, M17, M13, M18, H13,  
G19, G16, G15, G14, G13, F19, F18, F13, E19, E18, E17,  
E15, D19, D18, D17, C18, C17, B19, B18, B17, A18, A17,  
A16, B16, C16, A14, A15, C15, B14, C14, E13  
L2DATA[0:63]  
High  
High  
I/O  
I/O  
L2VSEL  
L2DP[0:7]  
V14, U16, T19, N18, H14, F17, C19, B15  
L2VSEL  
N/A  
D15, E14, E16, H16, J15, L15, M16, K13, P15, R14, R16,  
T15, F15  
(11)  
L2OVDD  
L2SYNC_IN  
L14  
M14  
F7  
High  
High  
High  
High  
Input  
Output  
Input  
L2VSEL  
L2VSEL  
BVSEL  
N/A  
L2SYNC_OUT  
L2_TSTCLK(2)  
L2VSEL(1)(3)(8)(9)(14)  
A19  
Input  
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Table 12-1. Pinout Listing for the PC7410, 360-ball CBGA and CI-CGA packages (Continued)  
Signal Name  
L2WE  
Pin Number  
Active  
Low  
I/O  
I/F Select(1)  
L2VSEL  
L2VSEL  
BVSEL  
N16  
G17  
F9  
Output  
Output  
Input  
L2ZZ  
High  
Low  
LSSD_MODE(2)  
MCP  
B11  
Low  
Input  
BVSEL  
D5, D8, D12, E4, E6, E9, E11, F5, H4, J5, L5, M4, P5, R4,  
R6, R9, R11, T5, T8, T12  
OVDD  
N/A  
PLL_CFG[0:3]  
QACK  
QREQ  
RSRV  
SHD0(8)  
SHD1(5)(8)  
SMI  
A4, A5, A6, A7  
High  
Low  
Low  
Low  
Low  
Low  
Low  
Low  
Input  
Input  
Output  
Output  
I/O  
BVSEL  
BVSEL  
BVSEL  
BVSEL  
BVSEL  
BVSEL  
BVSEL  
BVSEL  
BVSEL  
BVSEL  
BVSEL  
BVSEL  
BVSEL  
BVSEL  
BVSEL  
BVSEL  
BVSEL  
BVSEL  
BVSEL  
BVSEL  
BVSEL  
BVSEL  
N/A  
B2  
J3  
D3  
B3  
B4  
I/O  
A12  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Input  
Output  
Input  
Input  
Input  
I/O  
SRESET  
SYSCLK  
TA  
E10  
H9  
F1  
Low  
High  
Low  
High  
High  
High  
Low  
High  
Low  
Low  
High  
High  
Low  
TBEN  
TBST  
A2  
A11  
TCK  
B10  
TDI(9)  
B7  
TDO  
D9  
TEA  
J1  
TMS(9)  
TRST(9)(14)  
TS  
C8  
A10  
K7  
TSIZ[0:2]  
TT[0:4]  
WT  
A9, B9, C9  
Output  
I/O  
C10, D11, B12, C12, F11  
C3  
I/O  
VDD  
G8, G10, G12, J8, J10, J12, L8, L10, L12, N8, N10, N12  
Notes: 1. OVDD supplies power to the processor bus, JTAG and all control signals except the L2 cache controls (L2CE, L2WE, and  
L2ZZ); L2OVDD supplies power to the L2 cache interface (L2ADDR[0:18], L2ASPARE, L2DATA[0:63], L2DP[0:7] and  
L2SYNC_OUT) and the L2 control signals and VDD supplies power to the processor core and the PLL and DLL (after filtering  
to become AVDD and L2AVDD respectively). These columns serve as a reference for the nominal voltage supported on a  
given signal as selected by the BVSEL/L2VSEL pin configurations of Table 6-2 on page 10 and the voltage supplied. For  
actual recommended value of VIN or supply voltages, see Table 6-3 on page 11.  
2. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.  
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PC7410  
3. To allow for future I/O voltage changes, provide the option to connect BVSEL and L2VSEL independently to either OVDD  
(selects 2.5V), GND (selects 1.8V), or to HRESET (selects 2.5V). The PC7410 Both the 60x processor bus and the L2 bus  
only support the 1.8 and 2.5 options (see Table 6-2 on page 10). the default selection if BVSEL and/or L2VSEL is left uncon-  
nected is 2.5V.  
4. Connect to HRESET to trigger post power-on-reset (por) internal memory test.  
5. Ignored in 60x bus mode.  
6. Unused output in 60x bus mode.  
7. Deasserted (pulled high) at HRESET for 60x bus mode.  
8. Uses one of 9 existing no-connects in PC750’s 360-ball BGA package.  
9. Internal pull-up on die.  
10. Reuses PC750’s DRTRY, DBDIS and TLBISYNC pins (DTI1, DTI2 and EMODE respectively).  
11. The VOLTDET pin position on the PC750 360-ball CBGA package is now an L2OVDD pin on the PC7410 packages.  
12. Output only for PC7410, was I/O for PC750.  
13. Enhanced mode only.  
14. To overcome the internal pull-up resistance and ensure this input will recognize a low signal, a pull-down resistance less  
than 250should be used.  
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PC7410  
Figure 12-5. Mechanical Dimensions and Bottom Surface Nomenclature of the 360-ball CBGA Package  
2X  
0.2  
A
D
A1 CORNER  
D2  
D3  
Millimeters  
C
C6-2  
C6-1  
12X  
J2  
DIM  
A
MIN  
2,72  
0,8  
MAX  
3,2  
1
C1-1  
C1-2  
C5-1  
C5-2  
0.15  
0.25  
A
A
A1  
A2  
A3  
A4  
b
1,1  
1,3  
0,6  
0,9  
0,93  
C4-1  
C4-2  
E
E2  
E3  
0.35  
A
0,82  
0,82  
L2 L1  
D
25 BSC  
D2  
D3  
e
10 typ  
6,32  
,27 BSC  
C2-2  
C2-1  
2X  
12X  
J3  
K2  
K1  
12X  
J1  
C3-1  
C3-2  
0.2  
1
E
25 BSC  
12,6 typ  
8,26  
0,89 BSC  
3,2 BSC  
0,68 BSC  
6,56  
B
E2  
E3  
J1  
J2  
J3  
K1  
K2  
L1  
L2  
1
2 3 4 5 6 7 8 9 10 111213141516 171819  
W
V
U
T
R
P
N
M
L
8,13  
8,61  
7,04  
K
J
H
G
F
E
D
C
B
A
A3  
A2  
Package  
Caps  
Value  
µF  
Voltage  
Reference  
A4  
A1  
A
C1-1  
C1-2  
C2-1  
C2-2  
C3-1  
C3-2  
C4-1  
C4-2  
C5-1  
C5-2  
C6-1  
C6-2  
L2OVDD  
GND  
0.01  
0.01  
0.01  
0.01  
0.01  
0.01  
L2OVDD  
GND  
e
0.3 C A  
B
360X  
B
VDD  
C
0.15  
GND  
OVDD  
GND  
OVDD  
GND  
VDD  
GND  
Notes: 1. Dimensioning and tolerancing per ASME Y14.5M, 1994  
2. Dimensions in millimeters  
3. Top side A1 corner index is a metallized feature with various shapes. Bottom side A1 corner is designated with a ball missing  
from the array  
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PC7410  
12.2 Substrate Capacitors for the PC7410  
Figure 12-6 shows the connectivity of the substrate capacitor pads for the PC7410, 360 CBGA package.  
Figure 12-6. Substrate Bypass Capacitors for the PC7410  
A1 CORNER  
Package Caps Value µF Voltage Reference  
C6-2  
C1-1  
C1-2  
C2-1  
C2-2  
C3-1  
C3-2  
C4-1  
C4-2  
C5-1  
C5-2  
C6-1  
C6-2  
L2OV  
GND  
L2OV  
GND  
C6-1  
DD  
0.01  
C1-1  
C1-2  
C5-1  
C5-2  
DD  
0.01  
0.01  
V
C4-1  
C4-2  
DD  
GND  
OV  
L2 L1  
DD  
0.01  
0.01  
0.01  
GND  
OV  
DD  
GND  
C2-2  
C2-1  
V
DD  
C3-1  
C3-2  
GND  
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PC7410  
Figure 12-7. Mechanical Dimensions and Bottom Surface Nomenclature of the 360-ball HiTCE Package  
2X  
0.2  
A
D
A1 CORNER  
D2  
D3  
Millimeters  
C
C6-2  
C6-1  
12X  
J2  
DIM  
A
MIN  
2,72  
0,8  
MAX  
3,2  
1
C1-1  
C1-2  
C5-1  
C5-2  
0.15  
0.25  
A
A
A1  
A2  
A3  
A4  
b
1,1  
1,3  
0,6  
0,9  
0,93  
C4-1  
C4-2  
E
E2  
E3  
0.35  
A
0,82  
0,82  
L2 L1  
D
25 BSC  
D2  
D3  
e
10 typ  
6,32  
,27 BSC  
C2-2  
C2-1  
2X  
12X  
J3  
K2  
K1  
12X  
J1  
C3-1  
C3-2  
0.2  
1
E
25 BSC  
12,6 typ  
8,26  
0,89 BSC  
3,2 BSC  
0,68 BSC  
6,56  
B
E2  
E3  
J1  
J2  
J3  
K1  
K2  
L1  
L2  
1
2 3 4 5 6 7 8 9 10 111213141516 171819  
W
V
U
T
R
P
N
M
L
8,13  
8,61  
7,04  
K
J
H
G
F
E
D
C
B
A
A3  
A2  
Package  
Caps  
Value  
µF  
Voltage  
Reference  
A4  
A1  
A
C1-1  
C1-2  
C2-1  
C2-2  
C3-1  
C3-2  
C4-1  
C4-2  
C5-1  
C5-2  
C6-1  
C6-2  
L2OVDD  
GND  
0.01  
0.01  
0.01  
0.01  
0.01  
0.01  
L2OVDD  
GND  
e
0.3 C A  
B
360X  
B
VDD  
C
0.15  
GND  
OVDD  
GND  
OVDD  
GND  
VDD  
GND  
Notes: 1. Dimensioning and tolerancing per ASME Y14.5M, 1994  
2. Dimensions in millimeters  
3. Top side A1 corner index is a metallized feature with various shapes. Bottom side A1 corner is designated with a ball missing  
from the array  
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PC7410  
12.3 Substrate Capacitors for the PC7410  
Figure 12-8 shows the connectivity of the substrate capacitor pads for the PC7410, 360 HITCE package.  
Figure 12-8. Substrate Bypass Capacitors for the PC7410  
A1 CORNER  
Package Caps Value µF Voltage Reference  
C6-2  
C1-1  
C1-2  
C2-1  
C2-2  
C3-1  
C3-2  
C4-1  
C4-2  
C5-1  
C5-2  
C6-1  
C6-2  
L2OV  
GND  
L2OV  
GND  
C6-1  
DD  
0.01  
C1-1  
C1-2  
C5-1  
C5-2  
DD  
0.01  
0.01  
V
C4-1  
C4-2  
DD  
GND  
OV  
L2 L1  
DD  
0.01  
0.01  
0.01  
GND  
OV  
DD  
GND  
C2-2  
C2-1  
V
DD  
C3-1  
C3-2  
GND  
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PC7410  
Figure 12-9. Mechanical Dimensions and Bottom Surface Nomenclature of the 360-column CI-CGA  
Package  
2X  
0.2  
B
2X  
0.15  
D
PIN A1  
INDEX  
A
360X  
0.15  
A
2
1
C6  
A3  
A4  
C5  
C1  
0.35  
A
1
1
2
2
2
2
1
1
E
E2  
E4  
C4  
C2  
1
2X  
C3  
2
0.2  
D4  
D2  
C
D3  
E3  
TOPVIEW  
D1  
1
2
3
4
5
6
7
8
9 10 111213141516 171819  
W
V
U
T
R
P
N
M
L
A2  
A1  
A
K
J
E1  
H
G
F
K
E
D
C
B
A
GND : C1.2 C2.2 C3.2 C4.2 C5.2 C6.2  
C1.1, C2.1 : L2OVDD  
K
G
0.3 T E F  
B
C3.1, C6.1 : OVDD  
360X  
T
0.15  
C4.1, C5.1 : OVDD  
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PC7410  
13. Clock Selection  
The PC7410’s PLL is configured by the PLL_CFG[0:3] signals. For a given SYSCLK (bus) frequency,  
the PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL configura-  
tion for the PC7410 is shown in Table 13-1 for example frequencies. In this example, shaded cells  
represent settings that, for a given SYSCLK frequency, result in core and/or VCO frequencies that do not  
comply with the minimum and maximum core frequencies listed in Table 9-3 on page 21.  
Table 13-1. PC7410 Microprocessor PLL Configuration(1)(2)(3)(4)(5)  
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)  
Bus-to-  
Core  
Multiplier  
Core-to-  
VCO  
Multiplier  
PLL_CFG  
[0:3]  
Bus  
33.3 MHz  
Bus  
50 MHz  
Bus  
66.6 MHz  
Bus  
75 MHz  
Bus  
83.3 MHz  
Bus  
100 MHz  
Bus  
133 MHz  
0100  
0110  
1000  
1110  
1010  
0111  
1011  
1001  
1101  
0101  
0010  
2x  
2.5x  
3x  
2x  
2x  
2x  
2x  
2x  
2x  
2x  
2x  
2x  
2x  
2x  
400 (800)  
465 (930)  
3.5x  
4x  
350 (700)  
400 (800)  
450 (900)  
500 (1000)  
4.5x  
5x  
375 (750)  
416 (833)  
458 (916)  
500 (1000)  
375 (750)  
412 (825)  
450 (900)  
488 (967)  
5.5x  
6x  
366 (733)  
400 (800)  
433 (866)  
466 (933)  
6.5x  
7x  
350 (700)  
375 (750)  
500  
(1000)  
0001  
7.5x  
2x  
1100  
0000  
0011  
1111  
8x  
9x  
2x  
2x  
400 (800)  
450 (900)  
PLL off/bypass  
PLL off  
PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied  
PLL off, no core clocking occurs  
Notes: 1. PLL_CFG[0:3] settings not listed are reserved.  
2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO  
frequencies which are not useful, not supported, or not tested for by the PC7410; see “Clock AC Specifications” on page 20  
for valid SYSCLK, core, and VCO frequencies.  
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode  
is set for 1:1 mode operation. This mode is intended for factory use and third- party emulator tool development only.  
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.  
4. In PLL-off mode, no clocking occurs inside the PC7410 regardless of the SYSCLK input.  
5. PLL-off mode should not be used during chip power-up sequencing.  
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PC7410  
The PC7410 generates the clock for the external L2 synchronous data SRAMs by dividing the core clock  
frequency of the PC7410. The divided-down clock is then phase-adjusted by an on-chip delay-lock-loop  
(DLL) circuit and should be routed from the PC74107410 to the external RAMs. A separate clock output,  
L2SYNC_OUT is sent out half the distance to the SRAMs and then returned as an input to the DLL on  
pin L2SYNC_IN so that the rising-edge of the clock as seen at the external RAMs can be aligned to the  
clocking of the internal latches in the L2 bus interface.  
The core-to-L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of the L2CR register.  
Generally, the divisor must be chosen according to the frequency supported by the external RAMs, the  
frequency of the PC7410 core, and the phase adjustment range that the L2 DLL supports. Table 13-2  
shows various example L2 clock frequencies that can be obtained for a given set of core frequencies.  
The minimum L2 frequency target is 133 MHz. Sample core-to-L2 frequencies for the PC7410 is shown  
in Table 13-2. In this example, shaded cells represent settings that, for a given core frequency, result in  
L2 frequencies that do not comply with the minimum and maximum L2 frequencies listed in Table 9-6 on  
page 28.  
Table 13-2. Sample Core-to-L2 Frequencies  
Core Frequency in MHz  
÷1  
350  
366  
400  
÷1.5  
233  
244  
266  
288  
300  
311  
333  
÷2  
÷2.5  
140  
147  
160  
173  
180  
186  
200  
÷3  
÷3.5  
÷4  
350  
366  
400  
433  
450  
466  
500  
175  
183  
200  
216  
225  
233  
250  
133  
144  
150  
155  
166  
133  
143  
Note:  
The core and L2 frequencies are for reference only. Some examples may represent core or L2 frequencies  
which are not useful, not supported or not tested for by the PC7410; see “L2 Clock AC Specifications” on  
page 24 for valid L2CLK frequencies. The L2CR[L2SL] bit should be set for L2CLK frequencies less than  
150 MHz.  
14. System Design Information  
14.1 PLL and DLL Power Supply Filtering  
The AVDD and L2AVDD power signals are provided on the PC7410 to supply power to the PLL and DLL,  
respectively. Both AVDD and L2AVDD can be supplied power from the VDD power plane. High frequency  
noise in the 500 kHz to 10 MHz resonant frequency range of the PLL on the VDD power plane could  
affect the stability of the internal clocks.  
On systems that use the PC7410 HCTE device, the AVDD and L2AVDD input signals should both imple-  
ment the circuit shown in Figure 14-1 on page 44.  
On systems that use the PC7410 CBGA device, the L2AVDD input should implement the circuit shown in  
Figure 14-1.  
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PC7410  
When selecting which filter to use on the AVDD input of the PC7410 CBGA device specifically, system  
designers should refer to Erratum No. 18 in the PC7410 RISC Microprocessor Chip Errata  
(MPC7410CE). The AVDD input of the PC7410 CBGA device is sensitive to system noise on both the  
V
DD power plane, as described above, and the OVDD power plane as described in the Erratum No. 18.  
With these AVDD sensitivities to OVDD and VDD noise, care must be taken when selecting the filter circuit  
for the AVDD input of the PC7410 CBGA device. Erratum No. 18 does not apply to the AVDD input of the  
MPC7401 HCTE device, nor does it affect the L2AVDD input of either the HCTE or the CBGA device.  
As described in Erratum No. 18, when there is a high amount of noise on the OVDD power plane due to  
I/O switching rates, it is possible for the OVDD noise to couple into the PLL supply voltage (AVDD) internal  
to the PC7410 CBGA package. It is the recommendation of Freescale, that new designs using the  
PC7410 CBGA package provide the ability to implement either filter shown in Figure 14-1 and Figure 14-  
2 at the AVDD input. Existing designs that implemented Figure 14-1 on AVDD may never experience the  
error described in Erratum No. 18. Both new and existing designs should qualify both AVDD filter solu-  
tions, and the filter providing the most robust margin should be implemented.  
Figure 14-1. PLL Power Supply Filter Circuit No.1  
10Ω  
VDD  
AVDD (or L2AVDD)  
2.2 µF  
2.2 µF  
Low ESL surface mount capacitor  
GND  
Figure 14-2. PLL Power Supply Filter Circuit No.2  
51Ω  
AV  
V
DD  
DD  
Capacitor  
Pad Sites  
GND  
The filter circuit should be placed as close as possible to the AVDD pin to minimize noise coupled from  
nearby circuits. A separate circuit should be placed as close as possible to the L2AVDD pin. It is often  
possible to route directly from the capacitors to the AVDD pin, which is on the periphery of the 360 CBGA  
footprint, without the inductance of vias. The L2AVDD pin may be more difficult to route, but is proportion-  
ately less critical.  
It is the recommendation of Freescale, that systems that implement the AVDD filter shown in Figure 14-2  
design in the pads for the removed capacitors (shown in Figure 14-1), to provide for the possible reintro-  
duction of the filter in Figure 14-1. This would be necessary in case there is a planned transition from the  
CBGA package to the HiTCE package of the PC7410.  
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PC7410  
14.2 Power Supply Voltage Sequency  
The notes in Table 6-1 on page 9 contain cautions about the sequencing of the external bus voltages  
and core voltage of the PC7410 (when they are different). These cautions are necessary for the long  
term reliability of the part. If they are violated, the electrostatic discharge (ESD) protection diodes will be  
forward-biased and excessive current can flow through these diodes. If the system power supply design  
does not control the voltage sequencing, one or both of the circuits of Figure 14-3 can be added to meet  
these requirements. The MUR420 Schottky diodes of Figure 14-3 control the maximum potential differ-  
ence between the external bus and core power supplies on power-up and the 1N5820 diodes regulate  
the maximum potential difference on power-down.  
Figure 14-3. Example Voltage Sequencing Circuits  
2.5V  
1.8V  
MUR420  
MUR420  
1N5820  
1N5820  
14.3 Decoupling Recommendations  
Due to the PC7410’s dynamic power management feature, large address and data buses and high oper-  
ating frequencies, the PC7410 can generate transient power surges and high frequency noise in its  
power supply, especially while driving large capacitive loads. This noise must be prevented from reach-  
ing other components in the PC7410 system and the PC7410 itself requires a clean, tightly regulated  
source of power. Therefore, it is recommended that the system designer place at least one decoupling  
capacitor at each VDD, OVDD, and L2OVDD pin of the PC7410. It is also recommended that these decou-  
pling capacitors receive their power from separate VDD, (L2)OVDD, and GND power planes in the PCB,  
utilizing short traces to minimize inductance.  
These capacitors should have a value of 0.01 µF or 0.1 µF. Only ceramic SMT (surface mount technol-  
ogy) capacitors should be used to minimize lead inductance, preferably 0508 or 0603 orientations where  
connections are made along the length of the part. Consistent with the recommendations of Dr. Howard  
Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993) and contrary to  
previous recommendations for decoupling PowerPC microprocessors, multiple small capacitors of equal  
value are recommended over using multiple values of capacitance.  
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,  
feeding the VDD, L2OVDD, and OVDD planes to enable quick recharging of the smaller chip capacitors.  
These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick  
response time necessary. They should also be connected to the power and ground planes through two  
vias to minimize inductance. Suggested bulk capacitors are 100 - 330 µF (AVX TPS tantalum or Sanyo  
OSCON).  
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PC7410  
14.4 Connection Recommendations  
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal  
level. Unused active low inputs should be tied to OVDD. Unused active high inputs should be connected  
to GND. All NC (no-connect) signals must remain unconnected.  
Power and ground connections must be made to all external VDD, OVDD, L2OVDD, and GND pins of the  
PC7410.  
See “L2 Clock AC Specifications” on page 24 for a discussion of the L2SYNC_OUT and L2SYNC_IN  
signals.  
14.5 Output Buffer DC Impedance  
The PC7410 60x and L2 I/O drivers are characterized over process, voltage and temperature. To mea-  
sure Z0, an external resistor is connected from the chip pad to OVDD or GND. Then the value of each  
resistor is varied until the pad voltage is OVDD/2 (see Figure 14-4).  
The output impedance is the average of two components, the resistances of the pull-up and pull-down  
devices. When data is held low, SW2 is closed (SW1 is open), and RN is trimmed until the voltage at the  
pad equals OVDD/2. RN then becomes the resistance of the pull-down devices. When data is held high,  
SW1 is closed (SW2 is open), and RP is trimmed until the voltage at the pad equals OVDD/2. RP then  
becomes the resistance of the pull-up devices. RP and RN are designed to be close to each other in  
value. Then Z0 = (RP + RN)/2.  
Figure 14-4 describes the driver impedance measurement circuit described above.  
Figure 14-4. Driver Impedance Measurement Circuit  
OVDD  
RN  
SW2  
Pad  
Data  
SW1  
RP  
OGND  
Alternately, the following is another method to determine the output impedance of the PC7410. A voltage  
source, Vforce, is connected to the output of the PC7410, as in Figure 14-4. Data is held low, the voltage  
source is set to a value that is equal to (L2)OVDD/2, and the current sourced by Vforce is measured. The  
voltage drop across the pull-down device, which is equal to (L2)OVDD/2, is divided by the measured cur-  
rent to determine the output impedance of the pull-down device, RN. Similarly, the impedance of the pull-  
up device is determined by dividing the voltage drop of the pull-up, (L2)OVDD/2, by the current sank by  
the pull-up when the data is high and Vforce is equal to (L2)OVDD/2. This method can be employed with  
either empirical data from a test setup or with data from simulation models, such as IBIS.  
46  
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PC7410  
RP and RN are designed to be close to each other in value. Then, Z0 = (RP + RN)/2. Figure 14-5 describes  
the alternate driver impedance measurement circuit.  
Figure 14-5. Alternate Driver Impedance Measurement Circuit  
(L2)OVDD  
BGA  
Pin  
Vforce  
Data  
OGND  
Table 14-1 summarizes the signal impedance results. The driver impedance values were characterized  
at 0°, 65°, and 105°C. The impedance increases with junction temperature and is relatively unaffected by  
bus voltage.  
Table 14-1. Impedance Characteristics with VDD = 1.8V, OVDD = 2.5V, TJ = 0°C - 105°C  
Impedance  
Processor bus  
41.5 – 54.3  
L2 Bus  
42.7 – 54.1  
39.3 – 50  
Symbol  
Unit  
RN  
RP  
Z0  
Z0  
37.3 – 55.3  
14.6 Pull-up Resistor Requirements  
The PC7410 requires pull-up resistors (1 k– 5 k) on several control pins of the bus interface to main-  
tain the control signals in the negated state after they have been actively negated and released by the  
PC7410 or other bus masters. These pins are: TS, ARTRY, SHDO, SHD1.  
Four test pins also require pull-up resistors (100– 1 k). These pins are CHK, L1_TSTCLK,  
L2_TSTCLK, and LSSD_MODE. These signals are for factory use only and must be pulled up to OVDD  
for normal machine operation.  
If pull-down resistors are used to configure BVSEL or L2VSEL, the resistors should be less than 250.  
(see Table 12-1 on page 33). Because PLL_CFG[0:3] must remain stable during normal operation,  
strong pull-up and pull-down resistors (1 kor less) are recommended to configure these signals in  
order to protect against erroneous switching due to ground bounce, power supply noise or noise  
coupling.  
In addition, CKSTP_OUT is an open-drain style output that requires a pull-up resistor (1 k–5 k) if it is  
used by the system. The CKSTP_IN signal should likewise be pulled up through a pull-up resistor (1 k–  
5 k) to prevent erroneous assertions of this signal.  
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PC7410  
During inactive periods on the bus, the address and transfer attributes may not be driven by any master  
and may, therefore, float in the high-impedance state for relatively long periods of time. Since the  
PC7410 must continually monitor these signals for snooping, this float condition may cause excessive  
power draw by the input receivers on the PC7410 or by other receivers in the system. These signals can  
be pulled up through weak (10 k) pull-up resistors by the system, address bus driven mode can be  
enabled (see the PC7410 RISC Microporcessor Family Users’ Manual for more information on this  
mode), or these signals may be otherwise driven by the system during inactive periods of the bus to  
avoid this additional power draw. The snooped address and transfer attribute inputs are: A[0:31],  
AP[0:3], TT[0:4], CI, WT, and GBL.  
In systems where GBL is not connected and other devices may be asserting TS for a snoopable transac-  
tion while not driving GBL to the processor, we recommend that a strong (1 k) pull-up resistor be used  
on GBL. Note that the PC7410 will only snoop transactions when GBL is asserted.  
The data bus input receivers are normally turned off when no read operation is in progress and, there-  
fore, do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may  
require pull-ups, or that those signals be otherwise driven by the system during inactive periods by the  
system. The data bus signals are: DH[0:31], DL[0:31], and DP[0:7].  
If address or data parity is not used by the system, and the respective parity checking is disabled through  
HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and  
should be left unconnected by the system. If parity checking is disabled through HID0, and parity gener-  
ation is not required by the PC7410 (note that the PC7410 always generates parity), then all parity pins  
may be left unconnected by the system. The L2 interface does not normally require pull-up resistors.  
14.7 JTAG Configuration Signals  
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the  
IEEE 1149.1 specification, but is provided on all processors that implement the PowerPC architecture.  
While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals,  
more reliable power-on reset performance will be obtained if the TRST signal is asserted during power-  
on reset.  
Because the JTAG interface is also used for accessing the common on-chip processor (COP) function,  
simply tying TRST to HRESET is not practical.  
The COP function of these processors allows a remote computer system (typically, a PC with dedicated  
hardware and debugging software) to access and control the internal operations of the processor. The  
COP interface connects primarily through the JTAG port of the processor, with some additional status  
monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order  
to fully control the processor. If the target system has independent reset sources, such as voltage moni-  
tors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must  
be merged into these signals with logic.  
The arrangement shown in Figure 14-6 on page 50 allows the COP port to independently assert  
HRESET or TRST, while ensuring that the target can drive HRESET as well. If the JTAG interface and  
COP header will not be used, TRST should be tied to HRESET through a 0isolation resistor so that it is  
asserted when the system reset signal (HRESET) is asserted ensuring that the JTAG scan chain is ini-  
tialized during power-on. While Freescale recommends that the COP header be designed into the  
system as shown in Figure 14-6, if this is not possible, the isolation resistor will allow future access to  
TRST in the case where a JTAG interface may need to be wired onto the system in debug situations.  
48  
0832F–HIREL–02/07  
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PC7410  
The COP header shown in Figure 14-6 on page 50 adds many benefits — breakpoints, watchpoints, reg-  
ister and memory examination/modification, and other standard debugger features are possible through  
this interface — and can be as inexpensive as an unpopulated footprint for a header to be added when  
needed.  
The COP interface has a standard header for connection to the target system, based on the 0.025"  
square-post 0.100" centered header assembly (often called a Berg header). The connector typically has  
pin 14 removed as a connector key.  
There is no standardized way to number the COP header shown in Figure 14-6; consequently, many dif-  
ferent pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then  
left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter  
clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended  
in Figure 14-6 is common to all known emulators.  
The QACK signal shown in Figure 14-6 is usually connected to the PCI bridge chip in a system and is an  
input to the PC7410 informing it that it can go into the quiescent state. Under normal operation this  
occurs during a low-power mode selection. In order for COP to work, the PC7410 must see this signal  
asserted (pulled down). While shown on the COP header, not all emulator products drive this signal. If  
the product does not, a pull-down resistor can be populated to assert this signal. Additionally, some emu-  
lator products implement open-drain type outputs and can only drive QACK asserted; for these tools, a  
pull-up resistor can be implemented to ensure this signal is deasserted when it is not being driven by the  
tool. Note that the pull-up and pull-down resistors on the QACK signal are mutually exclusive and it is  
never necessary to populate both in a system. To preserve correct power-down operation, QACK should  
be merged via logic so that it also can be driven by the PCI bridge.  
49  
0832F–HIREL–02/07  
e2v semiconductors SAS 2007  
PC7410  
Figure 14-6. COP Connector Diagram  
SRESET  
From Target  
Board Sources  
(if any)  
SRESET  
HRESET  
HRESET  
QACK  
(6)  
10 kΩ  
10 kΩ  
10 kΩ  
10 kΩ  
HRESET  
13  
11  
OV  
DD  
SRESET  
OV  
OV  
DD  
DD  
DD  
OV  
(5)  
0Ω  
TRST (6)  
TRST  
1
3
2
4
4
6
VDD_SENSE  
OV  
OV  
DD  
10 kΩ  
2 kΩ  
5
7
6
8
5(1)  
15  
DD  
CHKSTP_OUT  
CHKSTP_OUT  
10 kΩ  
9
10  
12  
OV  
OV  
DD  
Key  
11  
10 kΩ  
14(2)  
DD  
KEY  
No pin  
13  
15  
CHKSTP_IN  
TMS  
CHKSTP_IN  
TMS  
8
9
1
3
16  
TDO  
TDI  
TDO  
COP Connector  
Physical Pin Out  
TDI  
TCK  
7
2
TCK  
QACK  
QACK  
10  
NC  
NC  
2 k(3)  
OV  
DD  
12  
16  
10 k(4)  
Notes: 1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the PC7410. Connect  
pin 5 of the COP header to OVDD with a 10 kpull-up resistor.  
2. Key location; pin 14 is not physically present on the COP header.  
3. Component not populated. Populate only if debug tool does not drive QACK.  
4. Populate only if debug tool uses an open-drain type output and does not actively deassert QACK.  
5. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP  
header though an AND gate to TRST of the part. If the JTAG interface is not implemented, connect  
HRESET from the target source to TRST of the part through a 0isolation resistor.  
6. The COP port and target board should be able to independently assert HRESET and TRST to the pro-  
cessor in order to fully control the processor as shown above.  
50  
0832F–HIREL–02/07  
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PC7410  
Table 14-2. COP Pin Definitions  
Pins  
Signal  
TDO  
Connection  
TDO  
Special Notes  
1
2
3
QACK  
TDI  
QACK  
TDI  
Add 2K pull-down to ground. Must be merged with on-board QACK, if any  
Add 2K pull-down to ground. Must be merged with on-board TRST if any  
See Figure 14-6 on page 50  
4
TRST  
TRST  
5
6
7
RUN/STOP  
VDD_SENSE  
TCK  
No Connect  
VDD  
Used on 604e; leave no-connect for all other processors  
Add 2K pull-up to OVDD (for short circuit limiting protection only)  
TCK  
Optional. Add 10K pull-up to OVDD. Used on several emulator products. Useful for  
checkstopping the processor from a logic analyzer of other external trigger  
8
CKSTP_IN  
CKSTP_IN  
TMS  
9
TMS  
10  
11  
12  
13  
14  
15  
16  
N/A  
SRESET  
N/A  
SRESET  
HRESET  
Merge with on-board SRESET, if any  
HRESET  
N/A  
Merge with on-board HRESET  
Key location; pin should be removed  
Add 10K pull-up to OVDD  
CKSTP_OUT  
Ground  
CKSTP_OUT  
Digital Ground  
Boundary scan testing is enabled through the JTAG interface signals. (BSDL descriptions of the PC7410  
are available on the Internet at www.mot.com/PowerPC/teksupport.) The TRST signal is optional in the  
IEEE 1149.1 specification but is provided on all PowerPC implementations. While it is possible to force  
the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset  
performance will be obtained if the TRST signal is asserted during power-on reset. Since the JTAG inter-  
face is also used for accessing the common on-chip processor (COP) function of PowerPC processors,  
simply tying TRST to HRESET is not practical.  
The common on-chip processor (COP) function of PowerPC processors allows a remote computer sys-  
tem (typically a PC with dedicated hardware and debugging software) to access and control the internal  
operations of the processor. The COP interface connects primarily through the JTAG port of the proces-  
sor with some additional status monitoring signals. The COP port requires the ability to independently  
assert HRESET or TRST in order to fully control the processor. If the target system has independent  
reset sources, such as voltage monitors, watchdog timers, power supply failures or push-button  
switches, then the COP reset signals must be merged into these signals with logic.  
The arrangement shown in Figure 14-6 on page 50 allows the COP to independently assert HRESET or  
TRST, while ensuring that the target can drive HRESET as well. The pull-down resistor on TRST  
ensures that the JTAG scan chain is initialized during power-on if a JTAG interface cable is not attached;  
if it is attached, it is responsible for driving TRST when needed.  
51  
0832F–HIREL–02/07  
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PC7410  
The COP header shown in Figure 14-6 on page 50 adds many benefits – breakpoints, watchpoints, reg-  
ister and memory examination/modification and other standard debugger features are possible through  
this interface – and can be as inexpensive as an unpopulated footprint for a header to be added when  
needed.  
The COP interface has a standard header for connection to the target system, based on the 0.025”  
square-post 0.100” centered header assembly (often called a “Berg” header). The connector typically  
has pin 14 removed as a connector key, as shown in Figure 14-6.  
15. Ordering Information  
xx  
7410  
y
xxx  
y
nnnn  
L
x
Product  
Code(1)  
Part  
Identifier  
Temperature  
Package(1)  
Screening  
Level  
Max Internal  
Application  
Modifier (1)  
Revision  
Level(1)  
Processor Speed(1)  
(1)  
Range T  
J
400 MHz  
450 MHz  
500 MHz  
G: CBGA  
GS: CI-CBGA  
GH: HITCE  
L: 1.8V ± 100 mV  
N: 1.5V ± 50 mV  
PC(X)(2)  
7410  
V: -40˚C, +110˚C  
M: -55˚C, +125˚C  
U: Upscreening  
blank: Std  
E
Notes: 1. For availability of the different versions, contact your local e2v sales office.  
2. The letter X in the part number designates a "Prototype" product that has not been qualified by e2v. Reliability of a PCX part-  
number is not guaranteed and such part-number shall not be used in Flight Hardware. Product changes may still occur while  
shipping prototypes.  
16. Definitions  
16.1 Life Support Applications  
These products are not designed for use in life support appliances, devices or systems where malfunc-  
tion of these products can reasonably be expected to result in personal injury. e2v customers using or  
selling these products for use in such applications do so at their own risk and agree to fully indemnify e2v  
for any damages resulting from such improper use or sale.  
52  
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PC7410  
17. Document Revision History  
Table 17-1 provides a revision history for this hardware specification.  
Table 17-1. Document Revision History  
Rev. No  
Date  
Substantive Change(s)  
F
01/07  
Name change from Atmel to e2v  
Table 8-1 on page 18: Changed note 1 to specify that OVDD and L2OVDD power is typically < 5% of VDD power  
Figure 12-5 on page 37: revised diagram and dimensions to specify ‘cap regions’ versus individual cap  
measurements. Moved individual capacitor placement to separate figure  
Figure 12-6 on page 38: Added this figure to show each individual capacitor placement and value  
Figure 14-5 on page 47: updated COP Connector Diagram to recommend a weak pull-up resistor on TCK  
E
10/2004  
Table 9-1 on page 19: Changed measurement test condition IOH from -6mA to -5 mA for VOH and IOL from 6  
mA to 5 mA for VOL per product bulletin  
“PLL and DLL Power Supply Filtering” on page 43: revised text regarding AVDD filter selection for the CBGA  
package  
Product specification release subsequent to product qualification  
Motorola changed to Freescale  
Figure 12-5 on page 37: added package capacitor values  
Section "Thermal Management Assistant": deleted  
Section “Pull-up Resistor Requirements” on page 47: added recommendation that strong pull-up/down  
resistors be used on the PLL_CFG[0:3] signals  
Table 9-3 on page 21: removed mode input setup and hold times. These inputs adhere to the general input  
setup and hold specifications  
D
02/2004  
Figure 9-4 on page 24: revised mode input diagram to show sample points around HRESET negation  
Figure 14-6 on page 50: added note 6 to emphasize that COP emulator and target board need to be able to  
drive HRESET and TRST independently to the CPU  
Section “PLL and DLL Power Supply Filtering” on page 43: revised section for HCTE package. Added text and  
figure for AVDD filter for the CBGA package  
Section “Pull-up Resistor Requirements” on page 47: removed AACK, TEA, and TS from control signals  
requiring pull-ups. Removed TBST from snooped transfer attribute list. TBST is an output and is not snooped  
53  
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Table of Contents  
Features .................................................................................................... 1  
Description ............................................................................................... 1  
Screening ................................................................................................. 2  
Block Diagram .......................................................................................... 3  
General Parameters ................................................................................. 4  
Overview ................................................................................................... 4  
Signal Description ................................................................................... 8  
Detailed Specification ............................................................................. 9  
1
2
3
4
5
6
Applicable Documents ............................................................................ 9  
6.1 Design and Construction .........................................................................................9  
6.1.1 Terminal Connections .............................................................................9  
6.2 Absolute Maximum Ratings .....................................................................................9  
6.3 Recommended Operating Conditions ...................................................................11  
7
Thermal Characteristics ........................................................................ 12  
7.1 Package Characteristics ........................................................................................12  
7.1.1 Package Thermal Characteristics for HiTCE .........................................12  
7.1.2 Package Thermal Characteristics for CI-CGA .......................................13  
7.2 Internal Package Conduction Resistance .............................................................13  
7.3 Thermal Management Information ........................................................................13  
7.3.1 Adhesives and Thermal Interface Materials ..........................................14  
8
9
Power Consideration ............................................................................. 17  
8.1 Power Management ..............................................................................................17  
8.2 Power Dissipation ..................................................................................................18  
Electrical Characteristics ...................................................................... 19  
9.1 Static Characteristics .............................................................................................19  
9.2 Dynamic Characteristics ........................................................................................20  
9.2.1 Clock AC Specifications ........................................................................20  
9.2.2 Processor Bus AC Specifications ..........................................................21  
9.2.3 L2 Clock AC Specifications ...................................................................24  
9.2.4 L2 Bus AC Specifications ......................................................................26  
i
0832F–HIREL–02/07  
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PC7410  
9.2.5 IEEE 1149.1 AC Timing Specifications .................................................28  
10 Preparation for Delivery ........................................................................ 31  
10.1 Handling ..............................................................................................................31  
11 Package Mechanical Data ..................................................................... 31  
11.1 Parameters ..........................................................................................................31  
12 Pin Assignments .................................................................................... 32  
12.1 BGA360 Package ................................................................................................32  
12.2 Substrate Capacitors for the PC7410 ..................................................................38  
12.3 Substrate Capacitors for the PC7410 ..................................................................40  
13 Clock Selection ...................................................................................... 42  
14 System Design Information .................................................................. 43  
14.1 PLL and DLL Power Supply Filtering ..................................................................43  
14.2 Power Supply Voltage Sequency ........................................................................45  
14.3 Decoupling Recommendations ...........................................................................45  
14.4 Connection Recommendations ...........................................................................46  
14.5 Output Buffer DC Impedance ..............................................................................46  
14.6 Pull-up Resistor Requirements ............................................................................47  
14.7 JTAG Configuration Signals ................................................................................48  
15 Ordering Information ............................................................................. 52  
16 Definitions .............................................................................................. 52  
16.1 Life Support Applications .....................................................................................52  
17 Document Revision History .................................................................. 53  
Table of Contents ...................................................................................... i  
ii  
0832F–HIREL–02/07  
e2v semiconductors SAS 2007  
How to reach us  
Home page: www.e2v.com  
Asia Pacifiq  
Sales Office:  
e2v  
United Kingdom  
e2v  
Bank of China Tower  
30th floor office 7  
1 Garden Rd Central  
Hong Kong  
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Chelmsford  
Essex CM1 2QU  
Tel: +44 (0)1245 493 493  
Fax: +44 (0)1245 492 492  
Tel: +852 2251 8227/8/9  
Fax: +852 2251 8383  
USA  
Product Contact:  
e2v  
e2v  
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Avenue de Rochepleine  
BP 123 - 38521 Saint-Egrève Cedex  
France  
NY 10523-1482  
Tel: +1 914 592 6050  
Fax: +1 914 592 5148  
Tel: +33 (0)4 76 58 30 00  
Hotline:  
std-hotline@e2v.com  
France  
e2v  
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Tel: +33 (0) 1 6019 5500  
Fax: +33 (0) 1 6019 5529  
Whilst e2v has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any  
use thereof and also reserves the right to change the specification of goods without notice. e2v accepts no liability beyond that set out in its stan-  
dard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with informa-  
tion contained herein.  
0832F–HIREL–02/07  
e2v semiconductors SAS 2007  
PC7410  
iv  
0832F–HIREL–02/07  
e2v semiconductors SAS 2007  

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