PCX7447MGHU1200LC_技术文档

Features

• 3000 Dhrystone 2.1 MIPS at 1.3 GHz

• Selectable Bus Clock (30 CPU Bus Dividers up to 28x)

• 13 Selectable Core-to-L3 Frequency Divisors

• Selectable MPx/60x Interface Voltage (1.8V, 2.5V)

• Selectable L3 Interface of 1.8V or 2.5V

• P_DTypical 12.6W at 1 GHz at V_DD= 1.3V; 8.3W at 1 GHz at V_DD= 1.1V, Full Operating

Conditions

• Nap, Doze and Sleep Modes for Power Saving

• Superscalar (Four Instructions Fetched Per Clock Cycle)

• 4 GB Direct Addressing Range

PowerPC 7457

RISC

Microprocessor

• Virtual Memory: 4 Hexabytes (2⁵²)

• 64-bit Data and 32-bit Address Bus Interface

• Integrated L1: 32 KB Instruction and 32 KB Data Cache

• Integrated L2: 512 KB

• 11 Independent Execution Units and Three Register Files

• Write-back and Write-through Operations

• f_INTMax = 1 GHz (1.2 GHz to be Confirmed)

• f_BUSMax = 133 MHz/166 MHz

PC7457/47

Description

This document is primarily concerned with the PowerPC^™PC7457; however, unless

otherwise noted, all information here also applies to the PC7447. The PC7457 and

PC7447 are implementations of the PowerPC microprocessor family of reduced

instruction set computer (RISC) microprocessors. This document describes pertinent

electrical and physical characteristics of the PC7457.

Preliminary

Specification

α-site

The PC7457 is the fourth implementation of the fourth generation (G4) microproces-

sors from Motorola. The PC7457 implements the full PowerPC 32-bit architecture and

is targeted at networking and computing systems applications. The PC7457 consists

of a processor core, a 512 Kbyte L2, and an internal L3 tag and controller which sup-

port a glueless backside L3 cache through a dedicated high-bandwidth interface. The

PC7447 is identical to the PC7457 except it does not support the L3 cache interface.

The core is a high-performance superscalar design supporting a double-precision

floating-point unit and a SIMD multimedia unit. The memory storage subsystem sup-

ports the MPX bus interface to main memory and other system resources. The L3

interface supports 1, 2, or 4M bytes of external SRAM for L3 cache and/or private

memory data. For systems implementing 4M bytes of SRAM, a maximum of 2M bytes

may be used as cache; the remaining 2M bytes must be private memory.

Note that the PC7457 is a footprint-compatible, drop-in replacement in a PC7455

application if the core power supply is 1.3V.

Rev. 5345B–HIREL–02/04

Screening

•

CBGA Upscreenings Based on Atmel Standards

•

Full Military Temperature Range (T_j= -55°C, +125°C),

Industrial Temperature Range (T_j= -40°C, +110°C)

•

CBGA Package, HiTCE Package for the 7447 TBC

CBGA 483

GH suffix

HITCE 360

Ceramic Ball Grid Array (TBC)

G suffix

CBGA 360

Ceramic Ball Grid Array

2

PC7457/47 [Preliminary]

5345B–HIREL–02/04

General Parameters

Table 1 provides a summary of the general parameters of the PC7457.

Table 1. Device Parameters

Parameter

Technology

Die size

Description

0.13 µm CMOS, nine-layer metal

9.1 mm × 10.8 mm

58 million

Transistor count

Logic design

Fully-static

PC7447: surface mount 360 ceramic ball grid array (CBGA)

PC7457: surface mount 483 ceramic ball grid array (CBGA)

Packages

Core power supply

1.3V ±500 mV DC nominal or 1.1V ±50 mV (nominal, see Table 3 on

page 12

I/O power supply

1.8V ±5% DC, or 2.5V ±5% for recommended operating conditions

Features

This section summarizes features of the PC7457 implementation of the PowerPC archi-

tecture. Major features of the PC7457 are as follows:

•

High-performance, superscalar microprocessor

–

As many as 4 instructions can be fetched from the instruction cache at a time

As many as 3 instructions can be dispatched to the issue queues at a time

As many as 12 instructions can be in the instruction queue (IQ)

As many as 16 instructions can be at some stage of execution

simultaneously

–

Single-cycle execution for most instructions

One instruction per clock cycle throughput for most instructions

Seven-stage pipeline control

•

Eleven independent execution units and three register files

–

Branch processing unit (BPU) features static and dynamic branch prediction

128-entry (32-set, four-way set-associative) branch target instruction cache

(BTIC), a cache of branch instructions that have been encountered in

branch/loop code sequences. If a target instruction is in the BTIC, it is

fetched into the instruction queue a cycle sooner than it can be made

available from the instruction cache. Typically, a fetch that hits the BTIC

provides the first four instructions in the target stream

2048-entry branch history table (BHT) with two bits per entry for four levels of

prediction – not-taken, strongly not-taken, taken, and strongly taken

Up to three outstanding speculative branches

Branch instructions that don’t update the count register (CTR) or link register

(LR) are often removed from the instruction stream

Eight-entry link register stack to predict the target address of Branch

Conditional to Link Register (BCLR) instructions

4

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

–

Four integer units (IUs) that share 32 GPRs for integer operands

Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer

instructions except multiply, divide, and move to/from special-purpose

register instructions

IU2 executes miscellaneous instructions including the CR logical operations,

integer multiplication and division instructions, and move to/from special-

purpose register instructions

–

Five-stage FPU and a 32-entry FPR file

Fully IEEE 754-1985-compliant FPU for both single- and double-precision

operations

Supports non-IEEE mode for time-critical operations

Hardware support for denormalized numbers

Thirty-two 64-bit FPRs for single- or double-precision operands

–

Four vector units and 32-entry vector register file (VRs)

Vector permute unit (VPU)

Vector integer unit 1 (VIU1) handles short-latency AltiVec^™integer

instructions, such as vector add instructions (vaddsbs, vaddshs, and

vaddsws, for example)

Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer

instructions, such as vector multiply add instructions (vmhaddshs,

vmhraddshs, and vmladduhm, for example)

Vector floating-point unit (VFPU)

–

Three-stage load/store unit (LSU)

Supports integer, floating-point, and vector instruction load/store traffic

Four-entry vector touch queue (VTQ) supports all four architected AltiVec

data stream operations

Three-cycle GPR and AltiVec load latency (byte, half-word, word, vector)

with one-cycle throughput

Four-cycle FPR load latency (single, double) with one-cycle throughput

No additional delay for misaligned access within double-word boundary

Dedicated adder calculates effective addresses (EAs)

Supports store gathering

5

5345B–HIREL–02/04

Performs alignment, normalization, and precision conversion for floating-

point data

Executes cache control and TLB instructions

Performs alignment, zero padding, and sign extension for integer data

Supports hits under misses (multiple outstanding misses)

Supports both big- and little-endian modes, including misaligned little-endian

accesses

•

Three issue queues FIQ, VIQ, and GIQ can accept as many as one, two, and three

instructions, respectively, in a cycle. Instruction dispatch requires the following:

–

Instructions can be dispatched only from the three lowest IQ entries – IQ0,

IQ1, and IQ2

A maximum of three instructions can be dispatched to the issue queues per

clock cycle

Space must be available in the CQ for an instruction to dispatch (this

includes instructions that are assigned a space in the CQ but not in an issue

queue)

•

Rename buffers

–

16 GPR rename buffers

16 FPR rename buffers

16 VR rename buffers

•

Dispatch unit

–

Decode/dispatch stage fully decodes each instruction

Completion unit

–

The completion unit retires an instruction from the 16-entry completion

queue (CQ) when all instructions ahead of it have been completed, the

instruction has finished execution, and no exceptions are pending

–

Guarantees sequential programming model (precise exception model)

Monitors all dispatched instructions and retires them in order

Tracks unresolved branches and flushes instructions after a mispredicted

branch

–

Retires as many as three instructions per clock cycle

•

Separate on-chip L1 Instruction and data caches (Harvard Architecture)

–

32 Kbyte, eight-way set-associative instruction and data caches

Pseudo least-recently-used (PLRU) replacement algorithm

32-byte (eight-word) L1 cache block

Physically indexed/physical tags

Cache write-back or write-through operation programmable on a per-page or

per-block basis

–

Instruction cache can provide four instructions per clock cycle; data cache

can provide four words per clock cycle

–

Caches can be disabled in software

Caches can be locked in software

6

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

–

MESI data cache coherency maintained in hardware

Separate copy of data cache tags for efficient snooping

Parity support on cache and tags

No snooping of instruction cache except for icbi instruction

Data cache supports AltiVec LRU and transient instructions

Critical double- and/or quad-word forwarding is performed as needed.

Critical quad-word forwarding is used for AltiVec loads and instruction

fetches. Other accesses use critical double-word forwarding

•

Level 2 (L2) cache interface

–

On-chip, 512 Kbyte, eight-way set-associative unified instruction and data

cache

–

Fully pipelined to provide 32 bytes per clock cycle to the L1 caches

A total nine-cycle load latency for an L1 data cache miss that hits in L2

PLRU replacement algorithm

Cache write-back or write-through operation programmable on a per-page or

per-block basis

–

64-byte, two-sectored line size

Parity support on cache

•

Level 3 (L3) cache interface (not implemented on PC7447)

–

Provides critical double-word forwarding to the requesting unit

Internal L3 cache controller and tags

External data SRAMs

Support for 1, 2, and 4M bytes (MB) total SRAM space

Support for 1 or 2 MB of cache space

Cache write-back or write-through operation programmable on a per-page or

per-block basis

–

64-byte (1 MB) or 128-byte (2 MB) sectored line size

Private memory capability for half (1 MB minimum) or all of the L3 SRAM

space for a total of 1-, 2-, or 4-MB of private memory

–

Supports MSUG2 dual data rate (DDR) synchronous Burst SRAMs, PB2

pipelined synchronous Burst SRAMs, and pipelined (register-register) Late

Write synchronous Burst SRAMs

–

Supports parity on cache and tags

Configurable core-to-L3 frequency divisors

64-bit external L3 data bus sustains 64-bit per L3 clock cycle

•

Separate memory management units (MMUs) for Instructions and data

–

52-bit virtual address; 32- or 36-bit physical address

Address translation for 4 Kbyte pages, variable-sized blocks, and

256M bytes segments

–

Memory

programmable

as

write-back/write-through,

caching-

inhibited/caching-allowed, and memory coherency enforced/memory

coherency not enforced on a page or block basis

Separate IBATs and DBATs (eight each) also defined as SPRs

7

5345B–HIREL–02/04

–

Separate instruction and data translation lookaside buffers (TLBs)

Both TLBs are 128-entry, two-way set-associative, and use LRU

replacement algorithm

TLBs are hardware- or software-reloadable (that is, on a TLB miss a page

table search is performed in hardware or by system software)

•

Efficient data flow

–

Although the VR/LSU interface is 128 bits, the L1/L2/L3 bus interface allows

up to 256 bits

The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the

VRs

L2 cache is fully pipelined to provide 256 bits per processor clock cycle to

the L1 cache

As many as eight outstanding, out-of-order, cache misses are allowed

between the L1 data cache and L2/L3 bus

–

As many as 16 out-of-order transactions can be present on the MPX bus

Store merging for multiple store misses to the same line. Only coherency

action taken (address-only) for store misses merged to all 32 bytes of a

cache block (no data tenure needed)

–

Three-entry finished store queue and five-entry completed store queue

between the LSU and the L1 data cache

Separate additional queues for efficient buffering of outbound data (such as

castouts and write-through stores) from the L1 data cache and L2 cache

•

Multiprocessing support features include the following:

–

Hardware-enforced, MESI cache coherency protocols for data cache

Load/store with reservation instruction pair for atomic memory references,

semaphores, and other multiprocessor operations

Power and thermal management

–

1.6V processor core

The following three power-saving modes are available to the system:

Nap—Instruction fetching is halted. Only those clocks for the time base,

decrementer, and JTAG logic remain running. The part goes into the doze

state to snoop memory operations on the bus and then back to nap using a

QREQ/QACK processor-system handshake protocol

Sleep—Power consumption is further reduced by disabling bus snooping,

leaving only the PLL in a locked and running state. All internal functional

units are disabled

Deep sleep— When the part is in the sleep state, the system can disable the

PLL. The system can then disable the SYSCLK source for greater system

power savings. Power-on reset procedures for restarting and relocking the

PLL must be followed on exiting the deep sleep state

8

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

–

Thermal management facility provides software-controllable thermal

management. Thermal management is performed through the use of three

supervisor-level registers and a PC7457-specific thermal management

exception

Instruction cache throttling provides control of instruction fetching to limit

power consumption

•

Performance monitor can be used to help debug system designs and improve

software efficiency

In-system testability and debugging features through JTAG boundary-scan

capability

Testability

–

LSSD scan design

IEEE 1149.1 JTAG interface

Array built-in self test (ABIST) – factory test only

•

Reliability and serviceability

–

Parity checking on system bus and L3 cache bus

Parity checking on the L2 and L3 cache tag arrays

9

5345B–HIREL–02/04

Signal Description

Figure 2. PC7457 Microprocessor Signal Groups

(1)

L3_ADDR[17:0]

L3-DATA[0:63]

L3_DP[0:7]

18

64

8

L3 Cache

Address/Data

BR

1

Note: L3 cache interface is not supported

in the PC7441, PC7445, or the PC7447

Address

Arbitration

BG

L3_VSEL

1

L3_CLK[0:1]

2

L3 Cache

Clock/Control

A[0:35]

AP[0:4]

L3_ECHO_CLK[0:3]

L3_CNTL[0:1]

36

5

4

Address

Transfer

2

TS

TT[0:4]

TBST

TSIZ[0:2]

GBL

INT

1

5

1

3

1

2

1

4

1

SMI

MCP

Address

Transfer

Attributes

SRESET

HRESET

CKSTP_IN

CKSTP_OUT

TBEN

Interrupts/Resets

PC7457

WT

CI

AACK

ARTRY

QREQ

1

2

1

QACK

Address

Transfer

Termination

SHD0/SHD1

HIT

BVSEL

Processor

Status/Control

BMODE[0:1]

PMON_IN

PMON_OUT

SYSCLK

DBG

DTI[0:3]

DRDY

1

4

1

Data

Arbitration

(2)

PLL_CFG[0:3]

PLL_EXT

EXT_QUAL

CLK_OUT

TCK

Clock Control

D[0:63]

DP[0:7]

64

8

Data

Transfer

TA

TDI

Data

Transfer

Termination

1

TEA

TDO

Test Interface

(JTAG)

TMS

TRST

V

OV

GV

AV

DD

GND

Notes: 1. For the PC7457, there are 19 L3_ADDR signals, (L3_ADDR[0:18].

2. For the PC7447 and PM7457, there are 5 PLL_CFG signals, (PLL_CFG[0:4].

10

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

Detailed

Specification

Scope

This specification describes the specific requirements for the microprocessor PC7457 in

compliance with Atmel standard screening.

Applicable

Documents

1. MIL-STD-883: Test methods and procedures for electronics

2. MIL-PRF-38535: Appendix A: General specifications for microcircuits

Requirements

General

The microcircuits are in accordance with the applicable documents and as specified

herein.

Design and Construction

Terminal Connections

Depending on the package, the terminal connections are as shown in Table 16, Table 3

and Figure 2.

Absolute Maximum

Ratings

Table 2. Absolute Maximum Ratings⁽¹⁾

Symbol

Characteristic

Maximum Value

-0.3 to 1.60

Unit

V

(2)

V_DD

Core supply voltage

PLL supply voltage

(2)

AV_DD

-0.3 to 1.60

V

(3)(4)

OV_DD

GV_DD

BVSEL = 0

-0.3 to 1.95

V

Processor bus supply voltage

(3)(5)

(3)(6)

(3)(7)

(3)(8)

BVSEL = HRESET or OV_DD

L3VSEL = ¬HRESET

L3VSEL = 0

-0.3 to 2.7

V

-0.3 to 1.65

V

L3 bus supply voltage

-0.3 to 1.95

V

L3VSEL = HRESET or GV_DD

Processor bus

-0.3 to 2.7

V

(9)(10)

V_IN

-0.3 to OV_DD+ 0.3

-0.3 to GV_DD+ 0.3

-0.3 to OV_DD+ 0.3

-55 to 150

V

(9)(10)

Input voltage

L3 bus

V

JTAG signals

V

T_STG

Storage temperature range

°C

Notes: 1. Functional and tested operating conditions are given in Table 3 on page 12. Absolute maximum ratings are stress ratings

only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability

or cause permanent damage to the device.

2. Caution: V_DD/AV_DDmust not exceed OV_DD/GV_DDby more than 1V during normal operation; this limit may be exceeded for a

maximum of 20 ms during power-on reset and power-down sequences.

3. Caution: OV_DD/GV_DDmust not exceed V_DD/AV_DDby more than 2V during normal operation; this limit may be exceeded for a

maximum of 20 ms during power-on reset and power-down sequences.

4. BVSEL must be set to 0, such that the bus is in 1.8V mode.

5. BVSEL must be set to HRESET or 1, such that the bus is in 2.5V mode.

6. L3VSEL must be set to ¬HRESET (inverse of HRESET), such that the bus is in 1.5V mode.

11

5345B–HIREL–02/04

7. L3VSEL must be set to 0, such that the bus is in 1.8V mode.

8. L3VSEL must be set to HRESET or 1, such that the bus is in 2.5V mode.

9. Caution: V_INmust not exceed OV_DDor GV_DDby more than 0.3V at any time including during power-on reset.

10. V_INmay overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 3.

Recommended

Operating Conditions

Table 3. Recommended Operating Conditions⁽¹⁾

Recommended Value

Min Max

Symbol

Characteristic

Unit

V

V_DD

Core supply voltage

PLL supply voltage

1.3V ±50 mV or 1.1V ±50 mV

1.8V ±5%

(2)

AV_DD

V

OV_DD

GV_DD

BVSEL = 0

V

Processor bus supply voltage

BVSEL = HRESET or OV_DD

L3VSEL = 0

2.5V ±5%

V

1.8V ±5%

V

L3 bus supply voltage

L3VSEL = HRESET or GV_DD

L3VSEL = ¬HRESET

Processor bus

2.5V ±5%

V

(3)

GV_DD

1.5V ±5%

V

V_IN

T_j

GND

-55

OV_DD

GV_DD

OV_DD

125

V

Input voltage

L3 bus

V

JTAG signals

V

Die-junction temperature

°C

Notes: 1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not

guaranteed.

2. This voltage is the input to the filter discussed in Section “PLL Power Supply Filtering” on page 54 and not necessarily the

voltage at the AV_DDpin which may be reduced from V_DDby the filter.

3. ¬HRESET is the inverse of HRESET.

Figure 3. Overshoot/Undershoot Voltage

OV /GV

DD

+ 20%

DD

OV /GV

DD

+ 5%

DD

OV /GV

DD

V

IH

V

IL

GND

GND – 0.3V

GND – 0.7V

Not to exceed 10% of t

SYSCLK

12

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

The PC7457 provides several I/O voltages to support both compatibility with existing

systems and migration to future systems. The PC7457 core voltage must always be pro-

vided at nominal 1.3V (see Table 3 for actual recommended core voltage). Voltage to

the L3 I/Os and processor interface I/Os are provided through separate sets of supply

pins and may be provided at the voltages shown in Table 4. The input voltage threshold

for each bus is selected by sampling the state of the voltage select pins at the negation

of the signal HRESET. The output voltage will swing from GND to the maximum voltage

applied to the OV_DDor GV_DDpower pins.

Table 4. Input Threshold Voltage Setting

BVSEL

Signal

Processor Bus Input

L3VSEL

L3 Bus Input Threshold

is Relative to:

Threshold is Relative to: Signal⁽¹⁾

Notes

(2)(3)(5)

0

1.8V

0

1.8V

1.5V

2.5V

(2)(4)(5)

(2)

¬HRESET

HRESET

1

Not available

2.5V

¬HRESET

HRESET

1

(2)

2.5V

Notes: 1. Not implemented on PC7447.

2. Caution: The input threshold selection must agree with the OV_DD/GV_DDvoltages sup-

plied. See notes in Table 2.

3. If used, pull-down resistors should be less than 250Ω

4. Applicable to L3 bus interface only. ¬HRESET is the inverse of HRESET.

5. 1.8V I/O mode and 1.5V I/O mode are not supported in N spec at V_DD= 1.1V.

Thermal Characteristics

Package Characteristics

Table 5. Package Thermal Characteristics⁽¹⁾

Value

Symbol

Characteristic

PC7447

22

PC7457

20

Unit

°C/W

(2)(3)

R_θJA

Junction-to-ambient thermal resistance, natural convection

Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board

Junction-to-ambient thermal resistance, 200 ft./min. airflow, single-layer (1s) board

Junction-to-ambient thermal resistance, 200 ft./min. airflow, four-layer (2s2p) board

Junction-to-board thermal resistance

(2)(4)

R_θJMA

14

(2)(4)

R_θJMA

16

15

(2)(4)

R_θJMA

11

(5)

R_θJB

6

(6)

R_θJC

Junction-to-case thermal resistance

< 0.1

Notes: 1. See “Thermal Management Information” on page 15 for more details about thermal management.

2. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) tempera-

ture, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance.

3. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

4. Per JEDEC JESD51-6 with the board horizontal.

5. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

6. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1) with the calculated case temperature. The actual value of R_θJCfor the part is less than 0.1°C/W.

13

5345B–HIREL–02/04

Internal Package Conduction

Resistance

For the exposed-die packaging technology, shown in Table 4 on page 13, the intrinsic

conduction thermal resistance paths are as follows:

•

The die junction-to-case (actually top-of-die since silicon die is exposed) thermal

resistance

•

The die junction-to-ball thermal resistance

Figure 33 on page 58 depicts the primary heat transfer path for a package with an

attached heat sink mounted to a printed-circuit board.

Figure 4. C4 Package with Heat Sink Mounted to a Printed-Circuit Board

External Resistance

Radiation

Convection

Heat Sink

Thermal Interface Material

Die/Package

Die Junction

Package/Leads

Internal Resistance

Printed-Circuit Board

Radiation

Convection

External Resistance

Note the internal versus external package resistance.

Heat generated on the active side of the chip is conducted through the silicon, then

through the heat sink attach material (or thermal interface material), and finally to the

heat sink where it is removed by forced-air convection.

Because the silicon thermal resistance is quite small, for a first-order analysis, the tem-

perature drop in the silicon may be neglected. Thus, the thermal interface material and

the heat sink conduction/convective thermal resistances are the dominant terms.

14

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

Thermal Management

Information

This section provides thermal management information for the ceramic ball grid array

(CBGA) package for air-cooled applications. Proper thermal control design is primarily

dependent on the system-level design – the heat sink, airflow, and thermal interface

material. To reduce the die-junction temperature, heat sinks may be attached to the

package by several methods – spring clip to holes in the printed-circuit board or pack-

age, and mounting clip and screw assembly (see Figure 32 on page 55); however, due

to the potential large mass of the heat sink, attachment through the printed-circuit board

is suggested. If a spring clip is used, the spring force should not exceed 10 pounds.

Figure 5. Package Exploded Cross-sectional View with Several Heat Sink Options

Heat Sink

CBGA Package

Heat Sink

Clip

Thermal Interface

Material

Printed-Circuit Board

15

5345B–HIREL–02/04

Thermal Interface Materials

A thermal interface material is recommended at the package lid-to-heat sink interface to

minimize the thermal contact resistance. For those applications where the heat sink is

attached by spring clip mechanism, Figure 5 shows the thermal performance of three

thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint,

and a joint with thermal grease as a function of contact pressure.

The use of thermal grease significantly reduces the interface thermal resistance. That is,

the bare joint results in a thermal resistance approximately seven times greater than the

thermal grease joint.

Often, heat sinks are attached to the package by means of a spring clip to holes in the

printed-circuit board (see Figure 32 on page 55). Therefore, the synthetic grease offers

the best thermal performance, considering the low interface pressure and is recom-

mended due to the high power dissipation of the PC7457. Of course, the selection of

any thermal interface material depends on many factors – thermal performance require-

ments, manufacturability, service temperature, dielectric properties, cost, etc.

Figure 6. Thermal Performance of Select Thermal Interface Material

Silicone Sheet (0.006 in.)

Bare Joint

2

Floroether Oil Sheet (0.007 in.)

Graphite/Oil Sheet (0.005 in.)

Synthetic Grease

1.5

1

0.5

0

10

20

30

40

50

60

70

80

Contact Pressure (psi)

Heat Sink Selection Example

For preliminary heat sink sizing, the die-junction temperature can be expressed as

follows:

T_j= T_I+ T + (R_θJC+ R_θint+ R_θsa) × P_d

r

where:

T_jis the die-junction temperature

T_Iis the inlet cabinet ambient temperature

T_ris the air temperature rise within the computer cabinet

16

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

R_θJCis the junction-to-case thermal resistance

R_θintis the adhesive or interface material thermal resistance

R_θsais the heat sink base-to-ambient thermal resistance

P_dis the power dissipated by the device

During operation, the die-junction temperatures (T_j) should be maintained less than the

value specified in Table 3 on page 12. The temperature of air cooling the component

greatly depends on the ambient inlet air temperature and the air temperature rise within

the electronic cabinet. An electronic cabinet inlet-air temperature (T_a) may range from

30° to 40°C. The air temperature rise within a cabinet (T_r) may be in the range of 5° to

10°C.

The thermal resistance of the thermal interface material (R_θint) is typically about

1.5°C/W. For example, assuming a Ta of 30°C, a Tr of 5°C, a CBGA package R_θJC

=

0.1, and a typical power consumption (P_d) of 18.7W, the following expression for T_jis

obtained:

Die-junction temperature: T_j= 30°C + 5°C + (0.1°C/W + 1.5°C/W + θ_sa) × 18.7W

For this example, a R_θsavalue of 2.1°C/W or less is required to maintain the die junction

temperature below the maximum value of Table 3 on page 12.

Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances

are a common figure-of-merit used for comparing the thermal performance of various

microelectronic packaging technologies, one should exercise caution when only using

this metric in determining thermal management because no single parameter can ade-

quately describe three-dimensional heat flow. The final die-junction operating

temperature is not only a function of the component-level thermal resistance, but the

system-level design and its operating conditions. In addition to the component's power

consumption, a number of factors affect the final operating die-junction temperature –

airflow, board population (local heat flux of adjacent components), heat sink efficiency,

heat sink attach, heat sink placement, next-level interconnect technology, system air

temperature rise, altitude, etc.

Due to the complexity and the many variations of system-level boundary conditions for

today's microelectronic equipment, the combined effects of the heat transfer mecha-

nisms (radiation, convection, and conduction) may vary widely. For these reasons, we

recommend using conjugate heat transfer models for the board, as well as system-level

designs.

For system thermal modeling, the PC7447 and PC7457 thermal model is shown in Fig-

ure 4 on page 14. Four volumes will be used to represent this device. Two of the

volumes, solder ball, and air and substrate, are modeled using the package outline size

of the package. The other two, die, and bump and underfill, have the same size as the

die. The silicon die should be modeled 9.64 × 11 × 0.74 mm with the heat source applied

as a uniform source at the bottom of the volume. The bump and underfill layer is mod-

eled as 9.64 × 11 × 0.69 mm (or as a collapsed volume) with orthotropic material

properties: 0.6W/(m × K) in the xy-plane and 2W/(m × K) in the direction of the z-axis.

The substrate volume is 25 × 25 × 1.2 mm (PC7447) or 29 × 29 × 1.2 mm (PC7457), and

this volume has 18W/(m × K) isotropic conductivity. The solder ball and air layer is mod-

eled with the same horizontal dimensions as the substrate and is 0.9 mm thick. It can

also be modeled as a collapsed volume using orthotropic material properties:

0.034W/(m × K) in the xy-plane direction and 3.8W/(m × K) in the direction of the z-axis.

17

5345B–HIREL–02/04

Figure 7. Recommended Thermal Model of PC7447 and PC7457

Die

Bump and Underfill

z

Conductivity

Value

Unit

Substrate

Solder and Air

Bump and Underfill

k

x

0.6

2

W/(m x K)

Side View of Model (Not to Scale)

k

y

x

k

z

Substrate

18

Substrate

Die

k

Solder Ball and Air

k

x

0.034

3.8

k

y

k

z

y

Side View of Model (Not to Scale)

Power Consumption

Table 6. Power Consumption for PC7457

Processor (CPU) Frequency

Full-Power Mode

Core Power Supply

Typical⁽¹⁾⁽²⁾

600 MHz

1.1

1000 MHz

1.1

1000 MHz

1.3

1200 MHz

1.3

Unit

5.3

8.3

15.8

17.5

W

Maximum⁽¹⁾⁽³⁾

7.9

11.5

22.0

24.2

Nap Mode

Typical⁽¹⁾⁽²⁾

1.3

1.2

1.3

1.2

1.1

5.2

5.1

5.0

5.2

5.1

5.0

W

Sleep Mode

Typical⁽¹⁾⁽²⁾

Deep Sleep Mode (PLL Disabled)

Typical⁽¹⁾⁽²⁾

1.1

Notes: 1. These values apply for all valid processor bus and L3 bus ratios. The values do not

include I/O supply power (OV_DDand GV_DD) or PLL supply power (AV_DD). OV_DDand

GV_DDpower is system dependent, but is typically < 5% of V_DDpower. Worst case

power consumption for AV_DD< 3 mW

2. Typical power is an average value measured at the nominal recommended VDD (see

Table 3 on page 12) and 65 C while running the Dhrystone 2.1 benchmark and

achieving 2.3 Dhrystone MIPs/MHz.

18

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

3. Maximum power is the average measured at nominal V_DDand maximum operating

junction temperature (see Table 3 on page 12) while running an entirely cache-resi-

dent, contrived sequence of instructions which keep all the execution units maximally

busy.

4. Doze mode is not a user-definable state; it is an intermediate state between full-

power and either nap or sleep mode. As a result, power consumption for this mode is

not tested.

Electrical

Characteristics

Static Characteristics

Table 7 provides the DC electrical characteristics for the PC7457.

Table 7. DC Electrical Specifications (see Table 3 on page 12 for Recommended Operating Conditions)

Nominal Bus

Symbol

Characteristic

Voltage⁽¹⁾

Min

Max

GV_DD+ 0.3

OV_DD/GV_DD+ 0.3

GV_DD× 0.35

OV_DD/GV_DD× 0.35

0.7

Unit

V

(2)

V_IH

1.5

1.8

2.5

1.5

1.8

2.5

–

GV_DD× 0.65

V_IH

Input high voltage (all inputs including SYSCLK)

OV_DD/GV_DD× 0.65

V

1.7

-0.3

–

V

(2)(6)

V_IL

V

V_IL

Input low voltage (all inputs including SYSCLK)

Input leakage current, V_IN= GV_DD/OV_DD

V

(2)(3)

I_IN

30

µA

High-impedance (off-state)

(2)(3)(4)

ITSI

–

30

Leakage current, V_IN= GV_DD/OV_DD

(6)

V_OH

1.5

1.8

2.5

1.5

1.8

2.5

OV_DD/GV_DD– 0.45

–

V

V_OH

Output high voltage, I_OH= -5 mA

Output low voltage, I_OL= 5 mA

OV_DD/GV_DD– 0.45

1.8

–

V

(6)

V_OL

0.45

0.6

9.5

8.0

V

V_OL

–

V

–

V

Capacitance,

L3 interface⁽⁵⁾

–

pF

C_IN

–

V_IN= 0V, f = 1 MHz

All other inputs⁽⁵⁾

–

Notes: 1. Nominal voltages; see Table 3 on page 12 for recommended operating conditions.

2. For processor bus signals, the reference is OV_DDwhile GV_DDis the reference for the L3 bus signals.

3. Excludes test signals and IEEE 1149.1 boundary scan (JTAG) signals.

4. The leakage is measured for nominal OV_DD/GV_DDand V_DD, or both OV_DD/GV_DDand V_DDmust vary in the same direction (for

example, both OV_DDand V_DDvary by either +5% or -5%).

5. Capacitance is periodically sampled rather than 100% tested.

6. Applicable to L3 bus interface only

19

5345B–HIREL–02/04

Dynamic Characteristics This section provides the AC electrical characteristics for the PC7457. After fabrication,

functional parts are sorted by maximum processor core frequency as shown in section

“Clock AC Specifications” and tested for conformance to the AC specifications for that

frequency. The processor core frequency is determined by the bus (SYSCLK) frequency

and the settings of the PLL_CFG[0:4] signals. Parts are sold by maximum processor

core frequency; See “Ordering Information” on page 59.

Clock AC Specifications

Table 8 provides the clock AC timing specifications as defined in Figure 8 and repre-

sents the tested operating frequencies of the devices. The maximum system bus

frequency, f_SYSCLK, given in Table 8 is considered a practical maximum in a typical sin-

gle-processor system. The actual maximum SYSCLK frequency for any application of

the PC7457 will be a function of the AC timings of the PC7457, the AC timings for the

system controller, bus loading, printed-circuit board topology, trace lengths, and so

forth, and may be less than the value given in Table 8.

Table 8. Clock AC Timing Specifications (See Table 3 on page 12 for Recommended Operating Conditions)

Maximum Processor Core Frequency

600 MHz

867 MHz

1000 MHz

V_DD= 1.1V

Symbol

Characteristic

Min

Max

600

1200

167

30

Min

Max

867

1733

167

30

Min

Max

1000

2000

167

30

Unit

MHz

ns

(1)

f_CORE

Processor frequency

VCO frequency

500

1000

33

6

500

1000

33

6

500

1000

33

6

(1)

f_VCO

(1)(2)

f_SYSCLK

SYSCLK frequency

(2)

t_SYSCLK

SYSCLK cycle time

(3)

t_KRt_KF

SYSCLK rise and fall time

SYSCLK duty cycle measured at OV_DD/2

SYSCLK jitter⁽⁵⁾⁽⁶⁾

–

1

–

1

–

1

ns

,

(4)

t_KHKL/t_SYSCLK

40

–

60

40

–

60

–

%

±150

100

±150

100

–

ps

Internal PLL relock time⁽⁷⁾

–

µs

Maximum Processor Core Frequency

867 MHz

1000 MHz

V_DD= 1.3V

1200 MHz

V_DD= 1.3V

1267 MHz

V_DD= 1.3V

Symbol

Characteristic

Min

600

1200

33

Max

867

1733

167

30

Min

600

1200

33

Max

1000

2000

167

30

Min

600

1200

33

Max

1200

2400

167

30

Min

600

1200

33

Max

1267

2534

167

30

Unit

MHz

ns

(1)

f_CORE

Processor frequency

VCO frequency

(1)

f_VCO

(1)(2)

f_SYSCLK

SYSCLK frequency

SYSCLK cycle time

SYSCLK rise and fall time

(2)

t_SYSCLK

6

(3)

t_KRt_KF

,

–

1

–

1

–

1

–

1

ns

t_KHKL

t_SYSCLK

/

40

60

40

60

40

60

40

60

%

SYSCLK duty cycle measured at OV_DD/2

(4)

SYSCLK jitter⁽⁵⁾⁽⁶⁾

–

±150

100

–

±150

100

–

±150

100

–

±150

100

ps

µs

Internal PLL relock time⁽⁷⁾

20

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

Notes: 1. Caution: The SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus) fre-

quency, CPU (core) frequency and PLL (VCO) frequency don’t exceed their respective maximum or minimum operating

frequencies. Refer to the PLL_CFG[0:4] signal description in “PLL Configuration” on page 51 for valid PLL_CFG[0:4]

settings

2. Assumes lightly-loaded, single-processor system.

3. Rise and fall times for the SYSCLK input measured from 0.4V to 1.4V.

4. Timing is guaranteed by design and characterization.

5. This represents total input jitter, short-term and long-term combined, and is guaranteed by design.

6. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow

cascade connected PLL-based devices to track SYSCLK drivers with the specified jitter.

7. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for

PLL lock after a stable V_DDand SYSCLK are reached during the power-on reset sequence. This specification also applies

when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held

asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.

Figure 8 provides the SYSCLK input timing diagram.

Figure 8. SYSCLK Input Timing Diagram

C

V

IH

VM

t

VM

C

V

SYSCLK

IL

KHKL

t

KF

KR

SYSCLK

VM = Midpoint Voltage (OV_DD/2)

21

5345B–HIREL–02/04

Processor Bus AC

Specifications

Table 9 provides the processor bus AC timing specifications for the PC7457 as defined

in Figure 17 on page 34 and Figure 9 on page 23. Timing specifications for the L3 bus

are provided in section “L3 Clock AC Specifications” on page 24.

Table 9. Processor Bus AC Timing Specifications⁽¹⁾(at Recommended Operating Conditions, see Table 3 on page 12.)

All Speed Grades

Min

Symbol⁽²⁾

Parameter

V_DD= 1.1V V_DD= 1.3V

Max

Unit

Input setup times:

t_AVKH

t_DVKH

t_IVKH

A[0:35], AP[0:4]

2.0

1.8

–

D[0:63], DP[0:7]

AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,

TT[0:3], QACK, TA, TBEN, TEA, TS,

EXT_QUAL, PMON_IN, SHD[0:1],

BMODE[0:1], BMODE[0:1], BVSEL, L3VSEL

ns

(8)

t_MVKH

2

1.8

–

Input hold times:

t_AXKH

t_DXKH

t_IXKH

A[0:35], AP[0:4]

0

–

D[0:63], DP[0:7]

AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,

TT[0:3], QACK, TA, TBEN, TEA, TS, EXT_QUAL,

PMON_IN, SHD[0:1]

ns

(8)

t_MXKH

BMODE[0:1], BMODE[0:1], BVSEL, L3VSEL

0

–

Output valid times:

A[0:35], AP[0:4]

D[0:63], DP[0:7]

AACK, ARTRY, BR, CI, CKSTP_IN, DRDY, DTI[0:3],

t_KHAV

t_KHDV

t_KHOV

–

2

ns

GBL, HIT, PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3],

TS, SHD[0:1], WT

Output hold times:

A[0:35], AP[0:4]

D[0:63], DP[0:7]

AACK, ARTRY, BR, CI, CKSTP_IN, DRDY, DTI[0:3],

t_KHAX

t_KHDX

t_KHOX

0.5

–

GBL, HIT, PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3],

TS, SHD[0:1], WT

t_KHOE

t_KHOZ

SYSCLK to output enable

0.5

–

0.5

–

ns

SYSCLK to output high impedance (all except TS, ARTRY,

SHD0, SHD1)

3.5

(3)(4)(5)

t_KHTSPZ

SYSCLK to TS high impedance after precharge

Maximum delay to ARTRY/SHD0/SHD1 precharge

–

1

2

t_SYSCLK

(3)(5)(6)(7)

t_KHARP

(3)(5)(6)(7)

t_KHARPZ

SYSCLK to ARTRY/SHD0/SHD1 high impedance after

precharge

t_SYSCLK

Notes: 1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input

SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the sig-

nal in question. All output timings assume a purely resistive 50Ω load (see Figure 17 on page 34). Input and output timings

are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

22

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

2. The symbology used for timing specifications herein follows the pattern of t_{(signal)(state)(reference)(state)}for inputs and

t_{(reference)(state)(signal)(state)}for outputs. For example, t_IVKHsymbolizes the time input signals (I) reach the valid state (V) relative to

the SYSCLK reference (K) going to the high (H) state or input setup time. And t_KHOVsymbolizes the time from SYSCLK (K)

going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the time that the input signal

(I) went invalid (X) with respect to the rising clock edge (KH) (note the position of the reference and its state for inputs) and

output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX).

3. t_SYSCLKis the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period of

SYSCLK to compute the actual time duration (in ns) of the parameter in question.

4. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low then precharged high

before returning to high impedance as shown in Figure 10 on page 24. The nominal precharge width for TS is 0.5 × t_SYSCLK

,

that is, less than the minimum t_SYSCLKperiod, to ensure that another master asserting TS on the following clock will not con-

tend with the precharge. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for

precharge.The high-impedance behavior is guaranteed by design.

5. Guaranteed by design and not tested.

6. According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately following

AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any master asserting it low

in the first clock following AACK will then go to high impedance for one clock before precharging it high during the second

cycle after the assertion of AACK. The nominal precharge width for ARTRY is 1.0 t_SYSCLK; that is, it should be high imped-

ance as shown in Figure 10 on page 24 before the first opportunity for another master to assert ARTRY. Output valid and

output hold timing is tested for the signal asserted.The high-impedance behavior is guaranteed by design.

7. According to the MPX bus protocol, SHD0 and SHD1 can be driven by multiple bus masters beginning the cycle of TS. Tim-

ing is the same as ARTRY, that is, the signal is high impedance for a fraction of a cycle, then negated for up to an entire

cycle (crossing a bus cycle boundary) before being three-stated again. The nominal precharge width for SHD0 and SHD1 is

1.0 t_SYSCLK. The edges of the precharge vary depending on the programmed ratio of core to bus (PLL configurations).

8. BMODE[0:1] and BVSEL are mode select inputs and are sampled before and after HRESET negation. These parameters

represent the input setup and hold times for each sample. These values are guaranteed by design and not tested. These

inputs must remain stable after the second sample. See Figure 9 on page 23 for sample timing.

Figure 9. Mode Input Timing Diagram

VM

HRESET

t

MVRH

t

MXRH

Mode Signals

23

5345B–HIREL–02/04

Figure 10 provides the input/output timing diagram for the PC7457.

Figure 10. Input/Output Timing Diagram

SYSCLK

VM

t

AXKH

IXKH

t

AVKH

t

IVKH

All Inputs

t

KHAV

t

KHAX

t

KHDV

KHOV

KHDX

KHOX

All Outputs

(Except TS,

ARTRY, SHD0, SHD1)

t

KHOE

t

KHOZ

All Outputs

(Except TS,

ARTRY, SHD0, SHD1)

t

KHTSPZ

t

KHTSV

t

KHTSX

t

KHTSV

KHARV

TS

t

KHARPZ

t

KHARP

ARTRY,

SHD0,

SHD1

t

KHARX

Note:

VM = Midpoint Voltage (OV_DD/2)

L3 Clock AC Specifications

The L3_CLK frequency is programmed by the L3 configuration register core-to-L3 divi-

sor ratio. See Table 18 on page 51 for example core and L3 frequencies at various

divisors. Table 10 on page 25 provides the potential range of L3_CLK output AC timing

specifications as defined in Figure 11 on page 25.

The maximum L3_CLK frequency is the core frequency divided by two. Given the high

core frequencies available in the PC7457, however, most SRAM designs will be not be

able to operate in this mode using current technology and, as a result, will select a

greater core-to-L3 divisor to provide a longer L3_CLK period for read and write access

to the L3 SRAMs. Therefore, the typical L3_CLK frequency shown in Table 10 is consid-

ered to be the practical maximum in a typical system. The maximum L3_CLK frequency

for any application of the PC7457 will be a function of the AC timings of the PC7457, the

AC timings for the SRAM, bus loading, and printed-circuit board trace length, and may

be greater or less than the value given in Table 10. Note that SYSCLK input jitter and

L3_CLK[0:1] output jitter are already comprehended in the L3 bus AC timing specifica-

tions and do not need to be separately accounted for in an L3 AC timing analysis. Clock

skews, where applicable, do need to be accounted for in an AC timing analysis.

24

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

Motorola is similarly limited by system constraints and cannot perform tests of the L3

interface on a socketed part on a functional tester at the maximum frequencies of Table

10. Therefore, functional operation and AC timing information are tested at core-to-L3

divisors which result in L3 frequencies at 250 MHz or lower.

Table 10. L3_CLK Output AC Timing Specifications at Recommended Operating Conditions (see Table 3 on page 12)

All Speed Grades

Symbol

Parameter

Min

–

Typical

Max

Unit

MHz

ns

(1)

f_{L3_CLK}

L3 clock frequency

200

5

(1)

t_{L3_CLK}

L3 clock cycle time

–

(2)

t

_CHCL/t_{L3_CLK}

L3 clock duty cycle

–

50

–

%

(3)

t_L3CSKW1

L3 clock output-to-output skew (L3_CLK0 to L3_CLK1)

L3 clock output-to-output skew (L3_CLK[0:1] to L3_ECHO_CLK[1:3])

L3 clock jitter⁽⁵⁾

–

100

±75

ps

(4)

t_L3CSKW2

–

ps

–

ps

Notes: 1. The maximum L3 clock frequency (and minimum L3 clock period) will be system dependent. See “L3 Clock AC Specifica-

tions” on page 24 for an explanation that this maximum frequency is not functionally tested at speed by Motorola. The

minimum L3 clock frequency and period are f_SYSCLKand t_SYSCLK, respectively.

2. The nominal duty cycle of the L3 output clocks is 50% measured at midpoint voltage.

3. Maximum possible skew between L3_CLK0 and L3_CLK1. This parameter is critical to the address and control signals

which are common to both SRAM chips in the L3.

4. Maximum possible skew between L3_CLK0 and L3_ECHO_CLK1 or between L3_CLK1 and L3_ECHO_CLK3 for PB2 or

Late Write SRAM. This parameter is critical to the read data signals because the processor uses the feedback loop to latch

data driven from the SRAM, each of which drives data based on L3_CLK0 or L3_CLK1.

5. Guaranteed by design and not tested. The input jitter on SYSCLK affects L3 output clocks and the L3 address, data and

control signals equally and, therefore, is already comprehended in the AC timing and does not have to be considered in the

L3 timing analysis. The clock-to-clock jitter shown here is uncertainty in the internal clock period caused by supply voltage

noise or thermal effects. This is also comprehended in the AC timing specifications and need not be considered in the L3

timing analysis.

Figure 11. L3_CLK_OUT Output Timing Diagram

t

L3CF

L3_CLK

CHCL

L3CR

t

L3_CLK0

L3_CLK1

VM

t

L3CSKW1

For PB2 or Late Write:

L3_ECHO_CLK1

VM

t

L3CSKW2

L3_ECHO_CLK3

VM

t

L3CSKW2

25

5345B–HIREL–02/04

L3 Bus AC Specifications

The PC7457 L3 interface supports three different types of SRAM: source-synchronous,

double data rate (DDR) MSUG2 SRAM, Late Write SRAMs, and pipeline burst (PB2)

SRAMs. Each requires a different protocol on the L3 interface and a different routing of

the L3 clock signals. The type of SRAM is programmed in L3CR[22:23] and the PC7457

then follows the appropriate protocol for that type. The designer must connect and route

the L3 signals appropriately for each type of SRAM. Following are some observations

about the L3 interface.

•

The routing for the point-to-point signals (L3_CLK[0:1], L3DATA[0:63], L3DP[0:7],

and L3_ECHO_CLK[0:3]) to a particular SRAM must be delay matched

•

For 1M byte of SRAM, use L3_ADDR[16:0] (L3_ADDR[0] is LSB)

For 2M bytes of SRAM, use L3_ADDR[17:0] (L3_ADDR[0] is LSB)

No pull-up resistors are required for the L3 interface

For high speed operations, L3 interface address and control signals should be a "T"

with minimal stubs to the two loads; data and clock signals should be point-to-point

to their single load. Figure 12 shows the AC test load for the L3 interface.

Figure 12. AC Test Load for the L3 Interface

Z

= 50Ω

OV /2

DD

Output

0

R

= 50Ω

L

In general, if routing is short, delay-matched, and designed for incident wave reception

and minimal reflection, there is a high probability that the AC timing of the PC7457 L3

interface will meet the maximum frequency operation of appropriately chosen SRAMs.

This is despite the pessimistic, guard-banded AC specifications (see Table 12 on page

28, Table 13 on page 29, and Table 14 on page 32), the limitations of functional testers

described in Section “L3 Clock AC Specifications” on page 24 and the uncertainty of

clocks and signals which inevitably make worst-case critical path timing analysis

pessimistic.

More specifically, certain signals within groups should be delay-matched with others in

the same group while intergroup routing is less critical. Only the address and control sig-

nals are common to both SRAMs and additional timing margin is available for these

signals. The double-clocked data signals are grouped with individual clocks as shown in

Figure 13 on page 30 or Figure 15 on page 33, depending on the type of SRAM. For

example, for the MSUG2 DDR SRAM (see Figure 13); L3DATA[0:31], L3DP[0:3], and

L3_CLK[0] form a closely coupled group of outputs from the PC7457; while

L3DATA[0:15], L3DP[0:1], and L3_ECHO_CLK[0] form a closely coupled group of

inputs.

The PC7450 RISC Microprocessor Family User’s Manual refers to logical settings called

"sample points" used in the synchronization of reads from the receive FIFO. The compu-

tation of the correct value for this setting is system-dependent and is described in the

PC7450 RISC Microprocessor Family User’s Manual.

Three specifications are used in this calculation and are given in Table 11 on page 27. It

is essential that all three specifications are included in the calculations to determine the

sample points as incorrect settings can result in errors and unpredictable behavior. For

more information, see the PC7450 RISC Microprocessor Family User’s Manual.

26

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

Table 11. Sample Points Calculation Parameters

Symbol

t_AC

Parameter

Max

3/4

3

Unit

t_{L3_CLK}

ns

Delay from processor clock to internal_L3_CLK⁽¹⁾

Delay from internal_L3_CLK to L3_CLK[n] output pins⁽²⁾

Delay from L3_ECHO_CLK[n] to receive latch⁽³⁾

t_CO

t_ECI

3

ns

Notes: 1. This specification describes a logical offset between the internal clock edge used to

launch the L3 address and control signals (this clock edge is phase-aligned with the

processor clock edge) and the internal clock edge used to launch the L3_CLK[n] sig-

nals. With proper board routing, this offset ensures that the L3_CLK[n] edge will

arrive at the SRAM within a valid address window and provide adequate setup and

hold time. This offset is reflected in the L3 bus interface AC timing specifications, but

must also be separately accounted for in the calculation of sample points and, thus, is

specified here.

2. This specification is the delay from a rising or falling edge on the internal_L3_CLK

signal to the corresponding rising or falling edge at the L3CLK[n] pins.

3. This specification is the delay from a rising or falling edge of L3_ECHO_CLK[n] to

data valid and ready to be sampled from the FIFO.

Effects of L3OHCR Settings on

L3 Bus AC Specifications

The AC timing of the L3 interface can be adjusted using the L3 Output Hold Control

Register (L3OCHR).

Each field controls the timing for a group of signals. The AC timing specifications pre-

sented herein represent the AC timing when the register contains the default value of

0x0000_0000. Incrementing a field delays the associated signals, increasing the output

valid time and hold time of the affected signals. In the special case of delaying an

L3_CLK signal, the net effect is to decrease the output valid and output hold times of all

signals being latched relative to that clock signal. The amount of delay added is summa-

rized in Table 12 on page 28.

Note that these settings affect output timing parameters only and don’t impact input tim-

ing parameters of the L3 bus in any way.

27

5345B–HIREL–02/04

Table 12. Effect of L3OHCR Settings on L3 Bus AC Timing

Output Valid Time

Output Hold Time

Parameter

Symbol⁽²⁾

Field name⁽¹⁾

Affected Signals

Value

0b00

Change⁽³⁾

0

Symbol⁽²⁾

Change⁽³⁾

Unit

Notes

(4)

0

0b01

+50

L3_ADDR[18:0],

L3_CNTL[0:1]

t

L3AOH

L3CHOV

L3CHOX

0b10

+100

+150

0

+100

+150

0

0b11

(4)

(5)

(4)

0b000

0b001

0b010

0b011

0b100

0b101

0b110

0b111

0b000

0b001

0b010

0b011

0b100

0b101

0b111

-50

-100

-150

-200

-250

-300

-350

0

-100

-150

-200

-250

-300

-350

0

t

L3CHOV

All signals latched

by SRAM

connected to

L3_CLKn

t

L3CHOX

L3CHDV

t

L3CLKn_OH

L3CHDX

L3CLDV

t

L3CLDX

ps

+50

+100

+150

+200

+250

+350

+100

+150

+200

+250

+350

t

L3_DATA[n:n + 7],

L3_DP[n/8]

L3CHDV

L3CHDX

L3DOHn

t

L3CLDV

L3CLDX

Notes: 1. Refer to the PC7450 RISC Microprocessor Family User’s Manual for specific information regarding L3OHCR.

2. See Table 13 on page 29 and Table 14 on page 32 for more information.

3. Guaranteed by design; not tested or characterized.

4. Default value.

5. Increasing values of L3CLKn_OH delay the L3_CLKn signal, effectively decreasing the output valid and output hold times of

all signals latched relative to that clock signal by the SRAM; see Figure 13 on page 30 and Figure 15 on page 33.

L3 Bus AC Specifications for

DDR MSUG2 SRAMs

When using DDR MSUG2 SRAMs at the L3 interface, the parts should be connected as

shown in Figure 13.

Outputs from the PC7457 are actually launched on the edges of an internal clock phase-

aligned to SYSCLK (adjusted for core and L3 frequency divisors). L3_CLK0 and

L3_CLK1 are this internal clock output with 90° phase delay, so outputs are shown syn-

chronous to L3_CLK0 and L3_CLK1. Output valid times are typically negative when

referenced to L3_CLKn because the data is launched one-quarter period before

L3_CLKn to provide adequate setup time at the SRAM after the delay-matched address,

control, data, and L3_CLKn signals have propagated across the printed-wiring board.

Inputs to the PC7457 are source-synchronous with the CQ clock generated by the DDR

MSUG2 SRAMs.

28

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

These CQ clocks are received on the L3_ECHO_CLKn inputs of the PC7457. An inter-

nal circuit delays the incoming L3_ECHO_CLKn signal such that it is positioned within

the valid data window at the internal receiving latches. This delayed clock is used to

capture the data into these latches which comprise the receive FIFO. This clock is asyn-

chronous to all other processor clocks. This latched data is subsequently read out of the

FIFO synchronously to the processor clock. The time between writing and reading the

data is set by using the sample point settings defined in the L3CR register.

Table 13 provides the L3 bus interface AC timing specifications for the configuration as

shown in Figure 13, assuming the timing relationships shown in Figure 14 and the load-

ing shown in Figure 12 on page 26.

Table 13. L3 Bus Interface AC Timing Specifications for MSUG2 at Recommended Operating Conditions

(see Table 3 on page 12)

All Speed Grades

Symbol

Parameter

Min

Max

Unit

ns

t_L3CR, t_L3CF

L3_CLK rise and fall time⁽¹⁾

–

0.75

t

_L3DVEH, t_L3DVEL

Setup times: Data and parity^(2)(3)(4)

Input hold times: Data and parity⁽²⁾⁽⁴⁾

Valid times: Data and parity^(5)(6)(7)(8)

Valid times: All other outputs^(5)(7)(8)

Output hold times: Data and parity^(5)(6)(7)(8)

Output hold times: All other outputs^(5)(7)(8)

L3_CLK to high impedance: Data and parity

-0.35

–

t_L3DXEH, t_L3DXEL

t_L3CHDV, t_L3CLDV

t_L3CHOV

2.1

–

(-t_L3CLK/4) + 0.60

–

(t_L3CLK/4) + 0.65

t_L3CHDX, t_L3CLDX

t_L3CHOX

(t_L3CLK/4) - 0.60

(t_L3CLK/4) - 0.50

–

t_L3CLDZ

TBD

Notes: 1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GV_DD

.

2. For DDR, all input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the ris-

ing or falling edge of the input L3_ECHO_CLKn (see Figure 14 on page 31). Input timings are measured at the pins.

3. For DDR, the input data will typically follow the edge of L3_ECHO_CLKn as shown in Figure 14. For consistency with other

input setup time specifications, this will be treated as negative input setup time.

4. t_{L3_CLK}/4 is one-fourth the period of L3_CLKn. This parameter indicates that the PC7457 can latch an input signal that is

valid for only a short time before and a short time after the midpoint between the rising and falling (or falling and rising)

edges of L3_ECHO_CLKn at any frequency.

5. All output specifications are measured from the midpoint voltage of the rising (or for DDR write data, also the falling) edge of

L3_CLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a

purely resistive 50Ω load (see Figure 12 on page 26).

6. For DDR, the output data will typically lead the edge of L3_CLKn as shown in Figure 14 on page 31. For consistency with

other output valid time specifications, this will be treated as negative output valid time.

7. t_{L3_CLK}/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually launched

by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output valid and output hold

times such that the specified output signal will be valid for approximately one L3_CLK period starting three-fourths of a clock

prior to the edge on which the SRAM will sample it and ending one-fourth of a clock period after the edge it will be sampled.

8. Assumes default value of L3OHCR. See “Effects of L3OHCR Settings on L3 Bus AC Specifications” on page 27 for more

information.

29

5345B–HIREL–02/04

Figure 13 shows the typical connection diagram for the PC7457 interfaced to MSUG2 DDR SRAMs.

Figure 13. Typical Source Synchronous 4M bytes L3 Cache DDR Interface

SRAM 0

SA[18:0]

L3ADDR[18:0]

PC7457

B3

G

GND

NC

L3_CNTL[0]

L3_CNTL[1]

B1

B2

Denotes

Receive (SRAM

to PC7457)

L3_ECHO_CLK[0]

LBO

CQ

{L3DATA[0:15], L3DP[0:1]}

L3_CLK[0]

D[0:17]

CK

Aligned Signals

CQ

CK

NC

{L3DATA[16:31], L3DP[2:3]}

L3_ECHO_CLK[1]

(1)

GV /2

DD

D[18:35]

CQ

Denotes

Transmit

(PC7457 to SRAM)

Aligned Signals

SRAM 1

SA[18:0]

B1

B3

G

GND

NC

B2

L3ECHO_CLK[2]

CQ

LBO

CQ

{L3DATA[32:47], L3DP[4:5]}

D[0:17]

L3_CLK[1]

CQ

CK

NC

{L3DATA[48:63], L3DP[6:7]}

L3_ECHO_CLK[3]

(1)

D[18:35]

CQ

GV /2

DD

Note:

1. Or as recommended by SRAM manufacturer for single-ended clocking.

30

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

Figure 14 shows the L3 bus timing diagrams for the PC7457 interfaced to MSUG2 SRAMs.

Figure 14. L3 Bus Timing Diagrams for L3 Cache DDR SRAMs

Outputs

L3_CLK[0,1]

VM

t

L3CHOZ

L3CHOV

t

L3CHOX

ADDR, L3CNTL

L3DATA WRITE

t

L3CLDV

t

L3CLDZ

L3CHDV

t

L3CHDX

t

L3CLDX

Note:

t_L3CHDVand t_L3CLDVas drawn here will be negative numbers, that is, output valid time will be time before the clock edge.

Inputs

L3_ECHO_CLK[0,1,2,3]

VM

t

L3DXEL

t

L3DVEL

t

L3DVEH

L3 Data and Data

Parity Inputs

L3DXEH

Notes: 1. t_L3DVEHand t_L3DVELas drawn here will be negative numbers, that is, input setup time will be time after the clock edge.

2. VM = Midpoint Voltage (GV_DD/2)

31

5345B–HIREL–02/04

L3 Bus AC Specifications for

PB2 and Late Write SRAMs

When using PB2 or Late Write SRAMs at the L3 interface, the parts should be con-

nected as shown in Figure 15 on page 33. These SRAMs are synchronous to the

PC7457; one L3_CLKn signal is output to each SRAM to latch address, control, and

write data. Read data is launched by the SRAM synchronous to the delayed L3_CLKn

signal it received. The PC7457 needs a copy of that delayed clock which launched the

SRAM read data to know when the returning data will be valid. Therefore,

L3_ECHO_CLK1 and L3_ECHO_CLK3 must be routed halfway to the SRAMs and then

returned to the PC7457 inputs L3_ECHO_CLK0 and L3_ECHO_CLK2, respectively.

Thus, L3_ECHO_CLK0 and L3_ECHO_CLK2 are phase-aligned with the input clock

received at the SRAMs. The PC7457 will latch the incoming data on the rising edge of

L3_ECHO_CLK0 and L3_ECHO_CLK2.

Table 14 provides the L3 bus interface AC timing specifications for the configuration

shown in Figure 15, assuming the timing relationships of Figure 16 and the loading of

Figure 12 on page 26.

Table 14. L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs at Recommended Operating Condi-

tions (see Table 3 on page 12)

All Speed Grades

Symbol

t_L3CR, t_L3CF

t_L3DVEH

t_L3DXEH

t_L3CHDV

t_L3CHOV

t_L3CHDX

t_L3CHOX

t_L3CHDZ

t_L3CHOZ

Parameter

Min

–

Max

0.75

–

Unit

ns

L3_CLK rise and fall time⁽¹⁾⁽²⁾

Setup times: Data and parity⁽²⁾⁽³⁾

Input hold times: Data and parity⁽²⁾⁽³⁾

Valid times: Data and parity^(2)(4)(5)(6)

Valid times: All other outputs⁽⁵⁾⁽⁶⁾

Output hold times: Data and parity^(2)(4)(5)(6)

Output hold times: All other outputs^(2)(5)(6)

L3_CLK to high impedance: Data and parity⁽²⁾

L3_CLK to high impedance: All other outputs⁽²⁾

0.1

–

0.7

2.5

1.8

–

1.4

1.0

–

3.0

–

Notes: 1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GV_DD

.

2. Timing behavior and characterization are currently being evaluated.

3. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of

the input L3_ECHO_CLKn (see Figure 14 on page 31). Input timings are measured at the pins.

4. All output specifications are measured from the midpoint voltage of the rising edge of L3_CLKn to the midpoint of the signal

in question. The output timings are measured at the pins. All output timings assume a purely resistive 50Ω load (see Figure

14).

5. t_{L3_CLK}/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually launched

by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output valid and output hold

times such that the specified output signal will be valid for approximately one L3_CLK period starting three-fourths of a clock

before the edge on which the SRAM will sample it and ending one-fourth of a clock period after the edge it will be sampled.

6. Assumes default value of L3OHCR. See “Effects of L3OHCR Settings on L3 Bus AC Specifications” on page 27 for more

information.

32

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

Figure 15 shows the typical connection diagram for the PC7457 interfaced to PB2 SRAMs or Late Write SRAMs.

Figure 15. Typical Synchronous 1M Byte L3 Cache Late Write or PB2 Interface

SRAM 0

SA[16:0]

L3_ADDR[16:0]

PC7457

L3_CNTL[0]

L3_CNTL[1]

L3_ECHO_CLK[0]

{L3_DATA[0:15], L3_DP[0:1]}

SS

SW

Denotes

Receive (SRAM

to PC7457)

DQ[0:17]

GND

ZZ

G

Aligned Signals

L3_CLK[0]

K

{L3_DATA[16:31], L3_DP[2:3]}

(1)

GV /2

DD

DQ[18:36 ]

K

L3_ECHO_CLK[1]

Denotes

Transmit

SRAM 1

SA[16:0]

(PC7457 to SRAM)

Aligned Signals

SS

SW

L3_ECHO_CLK[2]

{L3_DATA[32:47], L3_DP[4:5]}

GND

ZZ

G

DQ[0:17]

K

L3_CLK[1]

{L3_DATA[48:63], L3_DP[6:7]}

(1)

DQ[18:36]

GV /2

DD

K

L3_ECHO_CLK[3]

Note:

1. Or as recommended by SRAM manufacturer for single-ended clocking.

33

5345B–HIREL–02/04

Figure 16 shows the L3 bus timing diagrams for the PC7457 interfaced to PB2 or Late Write SRAMs.

Figure 16. L3 Bus Timing Diagrams for Late Write or PB2 SRAMs

Outputs

L3_CLK[0,1]

VM

L3_ECHO_CLK[1,3]

t

L3CHOV

L3CHDV

L3CHOX

ADDR, L3_CNTL

L3DATA WRITE

t

L3CHOZ

t

L3CHDX

t

L3CHDZ

Inputs

L3_ECHO_CLK[0,2]

VM

t

L3DVEH

t

L3DXEH

Parity Inputs

L3 Data and Data

Note:

VM = Midpoint Voltage (GV_DD/2)

Figure 17. AC Test Load

Output

Z

= 50Ω

OV /2

DD

0

R

= 50Ω

L

34

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

IEEE 1149.1 AC Timing

Specifications

Table 15 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure

19 through Figure 22 on page 37.

Table 15. JTAG AC Timing Specifications (Independent of SYSCLK)⁽¹⁾at Recommended Operating Conditions

(see Table 3 on page 12)

Symbol

f_TCLK

Parameter

Min

0

Max

33.3

–

Unit

MHz

ns

TCK frequency of operation

TCK cycle time

t_TCLK

30

15

0

t_JHJL

TCK clock pulse width measured at 1.4V

TCK rise and fall times

TRST assert time

–

ns

t_JRand t_JF

2

ns

(2)

t_TRST

25

–

ns

Input Setup Times:

Boundary-scan data

TMS, TDI

(3)

t_DVJH

4

0

–

ns

t_IVJH

Input Hold Times:

Boundary-scan data

TMS, TDI

(3)

t_DXJH

20

25

–

t_IXJH

Valid Times:

Boundary-scan data

TDO

(4)

t_JLDV

4

20

25

t_JLOV

Output hold times:

Boundary-scan data

TDO

TBD

(4)

t_JLDX

t_JLOX

TCK to output high impedance:

Boundary-scan data

TDO

(4)(5)

t_JLDZ

3

19

9

ns

t_JLOZ

Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in ques-

tion. The output timings are measured at the pins. All output timings assume a purely resistive 50Ω load (see Figure 18).

Time-of-flight delays must be added for trace lengths, vias and connectors in the system.

2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

3. Non-JTAG signal input timing with respect to TCK.

4. Non-JTAG signal output timing with respect to TCK.

5. Guaranteed by design and characterization

Figure 18 provides the AC test load for TDO and the boundary-scan outputs of the PC7457.

Figure 18. Alternate AC Test Load for the JTAG Interface

Output

OV /2

DD

Z

= 50Ω

0

R

= 50Ω

L

35

5345B–HIREL–02/04

Figure 19. JTAG Clock Input Timing Diagram

TCLK

VM

t

JHJL

JR

JF

t

TCLK

Note:

VM = Midpoint Voltage (OV_DD/2)

Figure 20. TRST Timing Diagram

VM

TRST

t_TRST

Note:

VM = Midpoint Voltage (OV_DD/2)

Figure 21. Boundary-scan Timing Diagram

TCK

VM

t

DVJH

t

DXJH

Boundary

Data Inputs

Input

Data Valid

t

JLDV

t

JLDX

Boundary

Data Outputs

Output Data Valid

t

JLDZ

Boundary

Data Outputs

Output Data Valid

Note:

VM = Midpoint Voltage (OV_DD/2)

36

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

Figure 22. Test Access Port Timing Diagram

TCK

TDI, TMS

TDO

VM

t

IVJH

t

IXJH

Input Data

Valid

t

JLOV

JLOX

t

Output Data Valid

t

JLOZ

Output Data Valid

TDO

Note:

VM = Midpoint Voltage (OV_DD/2)

Preparation for

Delivery

Handling

MOS devices must be handled with certain precautions to avoid damage due to accu-

mulation of static charge. Input protection devices have been designed in the chip to

minimize the effect of static buildup. However, the following handling practices are

recommended:

•

Devices should be handled on benches with conductive and grounded surfaces.

Ground test equipment, tools and operator.

Do not handle devices by the leads.

Store devices in conductive foam or carriers.

Avoid use of plastic, rubber or silk in MOS areas.

Maintain relative humidity above 50% if practical.

37

5345B–HIREL–02/04

Package Mechanical The following sections provide the package parameters and mechanical dimensions for

the CBGA package.

Data

Package Parameters for The package parameters are as provided in the following list. The package type is

25 × 25 mm, 360-lead ceramic ball grid array (CBGA).

the PC7447, 360 CBGA

Package outline

Interconnects

25 mm × 25 mm

360 (19 × 19 ball array - 1)

1.27 mm (50 mil)

2.72 mm

Pitch

Minimum module height

Maximum module height

Ball diameter

3.24 mm

0.89 mm (35 mil)

38

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

Pin Assignment

Figure 23 shows the pinout of the PC7447, 360 CBGA package as viewed from the top

surface.

Figure 24 shows the side profile of the CBGA package to indicate the direction of the top

surface view.

Figure 23. Pinout of the PC7447, 360 CBGA Package as Viewed from the Top Surface

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Figure 24. Side View of the CBGA Package

View

Substrate Assembly

Encapsulant

Die

39

5345B–HIREL–02/04

Pinout Listings

Table 16 provides the pinout listing for the PC7447, 360 CBGA package. Table 15 pro-

vides the pinout listing for the PC7457, 483 CBGA package.

Note:

This pinout is not compatible with the PC750, PC7400, or PC7410 360 BGA package.

Table 16. Pinout Listing for the PC7447, 360 CBGA Package

Signal Name

Pin Number

Active

I/O

I/F Select⁽¹⁾

E11, H1, C11, G3, F10, L2, D11, D1, C10, G2, D12, L3, G4, T2, F4,

V1, J4, R2, K5, W2, J2, K4, N4, J3, M5, P5, N3, T1, V2, U1, N5, W1,

B12, C4, G10, B11

A[0:35]⁽²⁾

High

I/O

BVSEL

AACK

R1

Low

High

Low

–

Input

I/O

BVSEL

AP[0:4]

C1, E3, H6, F5, G7

ARTRY⁽³⁾

N2

A8

M1

G9

F8

D2

B7

J1

I/O

AV_DD

Input

Output

Input

Output

Input

Output

BG

Low

High

Low

High

BMODE0⁽⁴⁾

BMODE1⁽⁵⁾

BR

BVSEL⁽¹⁾⁽⁶⁾

CI⁽³⁾

CKSTP_IN

CKSTP_OUT

CLK_OUT

A3

B1

H2

R15, W15, T14, V16, W16, T15, U15, P14, V13, W13, T13, P13, U14,

W14, R12, T12, W12, V12, N11, N10, R11, U11, W11, T11, R10, N9,

P10, U10, R9, W10, U9, V9, W5, U6, T5, U5, W7, R6, P7, V6, P17,

R19, V18, R18, V19, T19, U19, W19, U18, W17, W18, T16, T18, T17,

W3, V17, U4, U8, U7, R7, P6, R8, W8, T8

D[0:63]

High

I/O

BVSEL

DBG

M2

Low

High

Low

High

Low

Input

I/O

BVSEL

DP[0:7]

DRDY⁽⁷⁾

DTI[0:3]⁽⁸⁾

EXT_QUAL⁽⁹⁾

GBL

T3, W4, T4, W9, M6, V3, N8, W6

R3

Output

Input

I/O

G1, K1, P1, N1

A11

E2

B5, C3, D6, D13, E17, F3, G17, H4, H7, H9, H11, H13, J6, J8, J10,

J12, K7, K3, K9, K11, K13, L6, L8, L10, L12, M4, M7, M9, M11, M13,

N7, P3, P9, P12, R5, R14, R17, T7, T10, U3, U13, U17, V5, V8, V11,

V15

GND

–

N/A

HIT⁽⁷⁾

B2

D8

D4

G8

B3

Low

High

Output

Input

BVSEL

HRESET

INT

L1_TSTCLK⁽⁹⁾

L2_TSTCLK⁽¹⁰⁾

40

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

Table 16. Pinout Listing for the PC7447, 360 CBGA Package (Continued)

Signal Name

Pin Number

Active

I/O

I/F Select⁽¹⁾

A6, A13, A14, A15, A16, A17, A18, A19, B13, B14, B15, B16, B17,

B18, B19, C13, C14, C15, C16, C17, C18, C19, D14, D15, D16, D17,

D18, D19, E12, E13, E14, E15, E16, E19, F12, F13, F14, F15, F16,

F17, F18, F19, G11, G12, G13, G14, G15, G16, G19, H14, H15, H16,

H17, H18, H19, J14, J15, J16, J17, J18, J19, K15, K16, K17, K18,

K19, L14, L15, L16, L17, L18, L19, M14, M15, M16, M17, M18, M19,

N12, N13, N14, N15, N16, N17, N18, N19, P15, P16, P18, P19

No Connect⁽¹¹⁾

–

LSSD_MODE^(6)(12)E8

Low

Input

BVSEL

MCP

OV_DD

C9

B4, C2, C12, D5, E18, F2, G18, H3, J5, K2, L5, M3, N6, P2, P8, P11,

R4, R13, R16, T6, T9, U2, U12, U16, V4, V7, V10, V14

–

N/A

PLL_CFG[0:4]

PMON_IN⁽¹³⁾

PMON_OUT

QACK

B8, C8, C7, D7, A7

High

Low

–

Input

Output

Input

Output

I/O

BVSEL

D9

A9

G5

QREQ

P4

SHD[0:1]⁽³⁾

E4, H5

SMI

F9

Input

Output

Input

Output

Input

I/O

SRESET

SYSCLK

TA

A2

A10

K6

Low

High

Low

High

Low

–

TBEN

E1

TBST

F11

TCK

C6

TDI⁽⁶⁾

B9

TDO

A4

TEA

L1

TEST[0:3]⁽¹²⁾

TEST[4]⁽⁹⁾

TMS⁽⁶⁾

A12, B6, B10, E10

D10

–

F1

High

Low

High

Low

TRST^(6)(14)

TS⁽³⁾

A5

L4

TSIZ[0:2]

TT[0:4]

WT⁽³⁾

G6, F7, E7

E5, E6, F6, E9, C5

D3

Output

I/O

Output

H8, H10, H12, J7, J9, J11, J13, K8, K10, K12, K14, L7, L9, L11, L13,

M8, M10, M12

V_DD

–

N/A

41

5345B–HIREL–02/04

Notes: 1. OV_DDsupplies power to the processor bus, JTAG, and all control signals; and V_DDsupplies power to the processor core and

the PLL (after filtering to become AV_DD). To program the I/O voltage, connect BVSEL to either GND (selects 1.8V) or to

HRESET (selects 2.5V). If used, the pull-down resistor should be less than 250Ω. For actual recommended value of V_INor

supply voltages see Figure 3 on page 12.

2. Unused address pins must be pulled down to GND.

3. These pins require weak pull-up resistors (for example, 4.7 kΩ) to maintain the control signals in the negated state after they

have been actively negated and released by the PC7447 and other bus masters.

4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET going

high.

5. This signal must be negated during reset, by pull up to OV_DDor negation by ¬HRESET (inverse of HRESET), to ensure

proper operation.

6. Internal pull up on die.

7. Ignored in 60x bus mode.

8. These signals must be pulled down to GND if unused, or if the PC7447 is in 60x bus mode.

9. These input signals are for factory use only and must be pulled down to GND for normal machine operation.

10. It is recommended this test signal be tied to HRESET; however, other configurations will not adversely affect performance.

11. These signals are for factory use only and must be left unconnected for normal machine operation.

12. These input signals are for factory use only and must be pulled up to OV_DDfor normal machine operation.

13. This pin can externally cause a performance monitor event. Counting of the event is enabled via software.

14. This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper operation

42

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

Mechanical Dimensions for the PC7447, 360 CBGA

Figure 25 provides the mechanical dimensions and bottom surface nomenclature for the PC7447, 360 CBGA package.

Figure 25. Mechanical Dimensions and Bottom Surface Nomenclature for the PC7447, 360 CBGA Package

2X

Capacitor Region

0.2

B

D

D1

D3

A1 CORNER

D2

A

0.15 A

Millimeters

E3

DIM

A

MIN

MAX

2.72

3.20

1

E4

E

A1

A2

A3

b

0.80

1.10

1.30

0.6

E2

E1

–

0.82

0.93

D

25 BSC

D1

D2

D3

D4

e

–

11.3

–

2X

8

0.2

D4

–

6.5

11.1

C

10.9

1.27 BSC

1 2 3 4 5 6 7 8 910111213141516171819

E

25 BSC

W

V

U

T

R

P

N

E1

E2

E3

E4

–

11.3

–

8

–

6.5

9.75

9.55

A3

M

L

K

J

A2

A1

H

G

F

E

D

C

B

A

0.35 A

360X

b

0.3

A B C

C

0.15

Notes: 1. Dimensioning and tolerance per ASME Y14.5M, 1994

2. Dimensions in millimeters

3. Top side A1 corner index is a metallized feature with various shapes. Bottom side A1 corner is designated with a ball missing

from the array

43

5345B–HIREL–02/04

Substrate Capacitors for the PC7447, 360 CBGA

Figure 26 shows the connectivity of the substrate capacitor pads for the PC7447, 360 CBGA. All capacitors are 100 nF.

Figure 26. Substrate Bypass Capacitors for the PC7447, 360 CBGA

Pad Number

Capacitor

A1 CORNER

-1

-2

C1

GND

V

DD

C2

DD

C3

OV

DD

C1-1 C2-1 C3-1

C4-1 C5-1

C4-2 C5-2

C6-1

C6-2

C4

V

DD

C5

DD

C1-2 C2-2 C3-2

C6

C7

C8

C9

OV

DD

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

V

DD

OV

DD

V

DD

OV

DD

C18-2 C17-2 C16-2 C15-2 C14-2 C13-2

C18-1 C17-1 C16-1 C15-1 C14-1 C13-1

V

DD

V

OV

DD

V

DD

Package Parameters for The package parameters are as provided in the following list. The package type is

29 × 29 mm, 483-lead ceramic ball grid array (CBGA).

the PC7457, 483 CBGA

Package outline

Interconnects

29 mm × 29 mm

483 (22 × 22 ball array - 1)

1.27 mm (50 mil)

–

Pitch

Minimum module height

Maximum module height

Ball diameter

3.22 mm

0.89 mm (35 mil)

44

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

Figure 27 shows the pinout of the PC7457, 483 CBGA package as viewed from the top

surface.

Figure 28 shows the side profile of the CBGA package to indicate the direction of the top

surface view.

Figure 27. Pinout of the PC7457, 483 CBGA Package as Viewed from the Top Surface

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

Figure 28. Side View of the CBGA Package

View

Substrate Assembly

Encapsulant

Die

45

5345B–HIREL–02/04

.

Table 17. Pinout Listing for the PC7457, 483 CBGA Package

Signal Name

Pin Number

Active

I/O

I/F Select⁽¹⁾

E10, N4, E8, N5, C8, R2, A7, M2, A6, M1, A10, U2, N2, P8, M8, W4,

N6, U6, R5, Y4, P1, P4, R6, M7, N7, AA3, U4, W2, W1, W3, V4,

AA1, D10, J4, G10, D9

A[0:35]⁽²⁾

High

I/O

BVSEL

AACK

U1

Low

High

Low

–

Input

I/O

BVSEL

N/A

AP[0:4]

L5, L6, J1, H2, G5

ARTRY⁽³⁾

T2

B2

R3

C6

C4

K1

G6

R1

F3

K6

N1

I/O

AVDD

Input

Output

Input

Output

Input

Output

BG

Low

High

Low

High

BVSEL

N/A

BMODE0⁽⁴⁾

BMODE1⁽⁵⁾

BR

BVSEL⁽⁶⁾⁽⁷⁾

CI⁽³⁾

BVSEL

CKSTP_IN

CKSTP_OUT

CLK_OUT

AB15, T14, R14, AB13, V14, U14, AB14, W16, AA11, Y11, U12,

W13, Y14, U13, T12, W12, AB12, R12, AA13, AB11, Y12, V11, T11,

R11, W10, T10, W11, V10, R10, U10, AA10, U9, V7, T8, AB4, Y6,

AB7, AA6, Y8, AA7, W8, AB10, AA16, AB16, AB17, Y18, AB18,

Y16, AA18, W14, R13, W15, AA14, V16, W6, AA12, V6, AB9, AB6,

R7, R9, AA9, AB8, W9

D[0:63]

High

I/O

BVSEL

DBG

V1

Low

High

Low

High

Low

Input

I/O

BVSEL

DP[0:7]

AA2, AB3, AB2, AA8, R8, W5, U8, AB5

DRDY⁽⁸⁾

DTI[0:3])⁽⁹⁾

EXT_QUAL⁽¹⁰⁾

GBL

T6

Output

Input

I/O

P2, T5, U3, P6

B9

M4

A22, B1, B5, B12, B14, B16, B18, B20, C3, C9, C21, D7, D13, D15,

D17, D19, E2, E5, E21, F10, F12, F14, F16, F19, G4, G7, G17, G21,

H13, H15, H19, H5, J3, J10, J12, J14, J17, J21, K5, K9, K11, K13,

K15, K19, L10, L12, L14, L17, L21, M3, M6, M9, M11, M13, M19,

N10, N12, N14, N17, N21, P3, P9, P11, P13, P15, P19, R17, R21,

T13, T15, T19, T4, T7, T9, U17, U21, V2, V5, V8, V12, V15, V19,

W7, W17, W21, Y3, Y9, Y13, Y15, Y20, AA5, AA17, AB1, AB22

GND

–

N/A

B13, B15, B17, B19, B21, D12, D14, D16, D18, D21, E19, F13, F15,

F17, F21, G19, H12, H14, H17, H21, J19, K17, K21, L19, M17, M21,

N19, P17, P21, R15, R19, T17, T21, U19, V17, V21, W19, Y21

(11)

GV_DD

–

N/A

HIT⁽⁸⁾

K2

A3

Low

Output

Input

BVSEL

HRESET

46

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

Table 17. Pinout Listing for the PC7457, 483 CBGA Package (Continued)

Signal Name

Pin Number

Active

Low

I/O

I/F Select⁽¹⁾

BVSEL

N/A

INT

J6

H4

J2

A4

Input

L1_TSTCLK⁽¹⁰⁾

L2_TSTCLK⁽¹²⁾

L3VSEL⁽⁶⁾⁽⁷⁾

High

H11, F20, J16, E22, H18, G20, F22, G22, H20, K16, J18, H22, J20,

J22, K18, K20, L16, K22, L18

L3ADDR[18:0]

High

Output

L3VSEL

L3_CLK[0:1]

V22, C17

L20, L22

High

Low

Output

L3VSEL

L3_CNTL[0:1]

AA19, AB20, U16, W18, AA20, AB21, AA21, T16, W20, U18, Y22,

R16, V20, W22, T18, U20, N18, N20, N16, N22, M16, M18, M20,

M22, R18, T20, U22, T22, R20, P18, R22, M15, G18, D22, E20,

H16, C22, F18, D20, B22, G16, A21, G15, E17, A20, C19, C18, A19,

A18, G14, E15, C16, A17, A16, C15, G13, C14, A14, E13, C13,

G12, A13, E12, C12

L3DATA[0:63]

High

I/O

L3VSEL

L3DP[0:7]

AB19, AA22, P22, P16, C20, E16, A15, A12

High

Low

–

I/O

Input

I/O

L3VSEL

BVSEL

N/A

L3_ECHO_CLK[0,2]

L3_ECHO_CLK[1,3]

LSSD_MODE^(7)(13)

MCP

V18, E18

P20, E14

F6

Input

–

B8

No Connect⁽¹⁴⁾

A8, A11, B6, B11, C11, D11, D3, D5, E11, E7, F2, F11, G2, H9

B3, C5, C7, C10, D2, E3, E9, F5, G3, G9, H7, J5, K3, L7, M5, N3,

P7, R4, T3, U5, U7, U11, U15, V3, V9, V13, Y2, Y5, Y7, Y10, Y17,

Y19, AA4, AA15

OV_DD

–

N/A

PLL_CFG[0:4]

PMON_IN⁽¹⁵⁾

PMON_OUT

QACK

A2, F7, C2, D4, H8

High

Low

–

Input

Output

Input

Output

I/O

BVSEL

E6

B4

K7

Y1

L4, L8

G8

G1

D6

N8

L3

QREQ

SHD[0:1]

SMI

Input

Output

Input

Output

Input

SRESET

SYSCLK

TA

Low

High

Low

High

Low

TBEN

TBST

B7

J7

TCK

TDI⁽⁷⁾

E4

H1

T1

TDO

TEA

47

5345B–HIREL–02/04

Table 17. Pinout Listing for the PC7457, 483 CBGA Package (Continued)

Signal Name

TEST[0:5]⁽¹³⁾

TEST[6]⁽¹⁰⁾

TMS⁽⁷⁾

Pin Number

Active

–

I/O

Input

I/O

I/F Select⁽¹⁾

BVSEL

B10, H6, H10, D8, F9, F8

A9

–

K4

High

Low

High

Low

TRST^(7)(16)

TS⁽³⁾

C1

P5

TSIZ[0:2]

TT[0:4]

L1,H3,D1

F1, F4, K8, A5, E1

L2

Output

I/O

WT⁽³⁾

Output

J9, J11, J13, J15, K10, K12, K14, L9, L11, L13, L15, M10, M12,

M14, N9, N11, N13, N15, P10, P12, P14

V_DD

–

N/A

VDD_SENSE[0:1]⁽¹⁷⁾G11, J8

–

N/A

Notes: 1. OV_DDsupplies power to the processor bus, JTAG, and all control signals except the L3 cache controls (L3CTL[0:1]); GV_DD

supplies power to the L3 cache interface (L3ADDR[0:17], L3DATA[0:63], L3DP[0:7], L3_ECHO_CLK[0:3], and L3_CLK[0:1])

and the L3 control signals L3_CNTL[0:1]; and V_DDsupplies power to the processor core and the PLL (after filtering to

become AV_DD). For actual recommended value of V_INor supply voltages, see Table 3 on page 12.

2. Unused address pins must be pulled down to GND.

3. These pins require weak pull-up resistors (for example, 4.7 kΩ) to maintain the control signals in the negated state after they

have been actively negated and released by the PC7457 and other bus masters.

4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET going

high.

5. This signal must be negated during reset, by pull up to OV_DDor negation by ¬HRESET (inverse of HRESET), to ensure

proper operation.

6. To program the processor interface I/O voltage, connect BVSEL to either GND (selects 1.8V) or to HRESET (selects 2.5V).

To program the L3 interface, connect L3VSEL to either GND (selects 1.8V) or to HRESET (selects 2.5V). If used, pull-down

resistors should be less than 250Ω.

7. Internal pull up on die.

8. Ignored in 60x bus mode.

9. These signals must be pulled down to GND if unused or if the PC7457 is in 60x bus mode.

10. These input signals for factory use only and must be pulled down to GND for normal machine operation.

11. Power must be supplied to GV_DD, even when the L3 interface is disabled or unused.

12. It is recommended that this test signal be tied to HRESET; however, other configurations will not adversely affect

performance.

13. These input signals are for factory use only and must be pulled up to OV_DDfor normal machine operation.

14. These signals are for factory use only and must be left unconnected for normal machine operation.

15. This pin can externally cause a performance monitor event. Counting of the event is enabled via software.

16. This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper operation.

17. These pins are internally connected to V_DD. They are intended to allow an external device to detect the core voltage level

present at the processor core. If unused, they must be connected directly to V_DDor left unconnected.

48

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

Mechanical Dimensions for the PC7457, 483 CBGA

Figure 25 provides the mechanical dimensions and bottom surface nomenclature for the PC7457, 483 CBGA package.

Figure 29. Mechanical Dimensions and Bottom Surface Nomenclature for the PC7457, 483 CBGA Package

2X

Capacitor Region

0.2

B

D

A

D1

0.15 A

D3

A1 CORNER

D2

E3

E4

E

E2

E1

Millimeters

2X

DIM

A

MIN

2.72

0.80

1.10

–

MAX

0.2

D4

3.20

1

C

A1

A2

A3

b

1.30

0.6

1 2 3 4 5 6 7 8 910111213141516171819202122

AB

AA

Y

W

V

U

T

R

P

N

M

L

K

J

0.82

29 BSC

–

0.93

D

D1

D2

D3

D4

e

12.5

–

8.5

A3

–

8.4

11.1

10.9

1.27 BSC

29 BSC

–

A2

A1

E

E1

E2

E3

E4

12.5

–

A

H

8.5

G

0.35 A

–

8.4

9.75

F

E

D

C

B

A

9.55

483X

b

0.3

A B C

C

0.15

Notes: 1. Dimensioning and tolerancing per ASME Y14.5M, 1994

2. Dimensions in millimeters

3. Top side A1 corner index is a metallized feature with various shapes. Bottom side. A1 corner is designated with a ball miss-

ing from the array

49

5345B–HIREL–02/04

Substrate Capacitors for the PC7457, 483 CBGA

Figure 26 shows the connectivity of the substrate capacitor pads for the PC7457, 483 CBGA. All capacitors are 100 nF.

Figure 30. Substrate Bypass Capacitors for the PC7457, 483 CBGA

Pad Number

A1 CORNER

Capacitor

-1

-2

C1

GND

OV

DD

C2

V

DD

C1-1 C2-1 C3-1

C1-2 C2-2 C3-2

C4-1 C5-1

C4-2 C5-2

C6-1

C6-2

C3

GV

DD

C4

V

DD

C5

DD

C6

GV

DD

C7

V

DD

C8

V

C9

GV

DD

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

V

DD

V

GV

DD

V

DD

OV

DD

V

DD

C18-2 C17-2 C16-2 C15-2 C14-2 C13-2

C18-1 C17-1 C16-1 C15-1 C14-1 C13-1

OV

DD

V

DD

V

OV

DD

V

DD

50

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

System Design

Information

This section provides system and thermal design recommendations for successful appli-

cation of the PC7457.

PLL Configuration

The PC7457 PLL is configured by the PLL_CFG[0:4] signals. For a given SYSCLK (bus)

frequency, the PLL configuration signals set the internal CPU and VCO frequency of

operation. The PLL configuration for the PC7457 is shown in Table 18 for a set of exam-

ple frequencies. In this example, shaded cells represent settings that, for a given

SYSCLK frequency, result in core and/or VCO frequencies that don’t comply with the

1 GHz column in Table 8 on page 20.

Table 18. PC7457 Microprocessor PLL Configuration Example for 1267 MHz Parts

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

Bus (SYSCLK) Frequency

Bus-to-Core

Multiplier

Core-to-VCO

Multiplier

33.3

MHz

50

MHz

66.6

MHz

75

MHz

83

MHz

100

MHz

133

MHz

167

MHz

PLL_CFG[0:4]

01000

2x

10000

10100

10110

10010

11010

01010

00100

00010

11000

01100

01111

01110

10101

10001

3x

4x

2x

667

(1333)

667

(1333)

835

(1670)

5x

733

(1466)

919

(1837)

5.5x

6x

600

(1200)

800

(1600)

1002

(2004)

650

(1300)

866

(1730)

1086

(2171)

6.5x

7x

700

(1400)

931

(1862)

1169

(2338)

623

(1245)

750

(1500)

1000

(2000)

1253

(2505)

7.5x

8x

600

(1200)

664

(1328)

800

(1600)

1064

(2128)

638

(1276)

706

(1412)

850

(1700)

1131

(2261)

8.5x

9x

600

(1200)

675

(1350)

747

(1494)

900

(1800)

1197

(2394)

633

(1266)

712

(1524)

789

(1578)

950

(1900)

1264

(2528)

9.5x

10x

10.5x

667

(1333)

750

(1500)

830

(1660)

1000

(2000)

700

(1400)

938

(1876)

872

(1744)

1050

(2100)

51

5345B–HIREL–02/04

Table 18. PC7457 Microprocessor PLL Configuration Example for 1267 MHz Parts (Continued)

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

Bus (SYSCLK) Frequency

Bus-to-Core

Multiplier

Core-to-VCO

Multiplier

33.3

MHz

50

MHz

66.6

MHz

75

MHz

83

MHz

100

MHz

133

MHz

167

MHz

PLL_CFG[0:4]

733

(1466)

825

(1650)

913

(1826)

1100

(2200)

10011

11x

11.5x

12x

2x

766

(532)

863

(1726)

955

(1910)

1150

(2300)

00000

10111

11111

01011

11100

11001

00011

11011

00001

00101

00111

01001

01101

11101

600

(1200)

800

(1600)

900

(1800)

996

(1992)

1200

(2400)

600

(1200)

833

(1666)

938

(1876)

1038

(2076)

1250

(2500)

12.5x

13x

650

(1300)

865

(1730)

975

(1950)

1079

(2158)

675

(1350)

900

(1800)

1013

(2026)

1121

(2242)

13.5x

14x

700

(1400)

933

(1866)

1050

(2100)

1162

(2324)

750

(1500)

1000

(2000)

1125

(2250)

1245

(2490)

15x

800

(1600)

1066

(2132)

1200

(2400)

16x

850

(1900)

1132

(2264)

17x

600

(1200)

900

(1800)

1200

(2400)

18x

667

(1334)

1000

(2000)

20x

700

(1400)

1050

(2100)

21x

800

(1600)

1200

(2400)

24x

933

(1866)

28x

00110

11110

PLL bypass

PLL off

PLL off, SYSCLK clocks core circuitry directly

PLL off, no core clocking occurs

Notes: 1. PLL_CFG[0:4] settings not listed are reserved.

2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO

frequencies which are not useful, not supported, or not tested for by the PC7455; See “Clock AC Specifications” on page 20.

for valid SYSCLK, core, and VCO frequencies.

3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled. However, the

bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL, must be driven at one-half the

frequency of SYSCLK and offset in phase to meet the required input setup t_IVKHand hold time t_IXKH(see Table 9 on page

22). The result is that the processor bus frequency is one-half SYSCLK while the internal processor is clocked at SYSCLK

frequency. This mode is intended for factory use and emulator tool use only.

Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.

52

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

4. In PLL-off mode, no clocking occurs inside the PC7455 regardless of the SYSCLK input.

The PC7457 generates the clock for the external L3 synchronous data SRAMs by divid-

ing the core clock frequency of the PC7457. The core-to-L3 frequency divisor for the L3

PLL is selected through the L3_CLK bits of the L3CR register. Generally, the divisor

must be chosen according to the frequency supported by the external RAMs, the fre-

quency of the PC7457 core, and timing analysis of the circuit board routing.

Table 19 shows various example L3 clock frequencies that can be obtained for a given

set of core frequencies.

Table 19. Sample Core-to-L3 Frequencies⁽¹⁾

Core

Frequency

(MHz)

÷2

÷2.5

200

213

220

240

260

266

280

293

320

347

373

400

420

440

460

480

500

520

÷3

÷3.5

143

152

157

171

186

190

200

209

230

248

266

285

300

314

329

343

357

371

÷4

÷4.5

111

118

122

133

144

148

156

163

178

192

207

222

233

244

256

267

278

289

÷5

÷5.5

91

÷6

÷6.5

77

÷7

71

÷7.5

67

÷8

63

500

533

250

266

275

300

325

333

350

367

400

433

467

500

525

550

575

600

638

650

167

178

183

200

217

222

233

244

266

289

311

333

350

367

383

400

417

433

125

133

138

150

163

167

175

183

200

217

233

250

263

275

288

300

313

325

100

107

110

120

130

133

140

147

160

173

187

200

191

200

209

218

227

236

83

97

89

82

76

71

67

550

100

109

118

121

127

133

145

157

170

182

191

200

209

218

227

236

92

85

79

73

69

600

100

108

111

117

122

133

145

156

166

175

183

192

200

208

217

92

86

80

75

650

100

102

108

113

123

133

144

154

162

169

177

185

192

200

93

87

81

666

95

89

83

700

100

105

114

124

133

143

150

157

164

171

179

186

93

88

733

98

92

800

107

115

124

133

140

147

153

160

167

173

100

108

117

125

131

138

144

150

156

163

866

933

1000

1050⁽²⁾

1100⁽²⁾

1150⁽²⁾

1200⁽²⁾

1250⁽²⁾

1300⁽²⁾

Notes: 1. The core and L3 frequencies are for reference only. Note that maximum L3 frequency is design dependent. Some examples

may represent core or L3 frequencies which are not useful, not supported, or not tested for the PC7457; see “L3 Clock AC

Specifications” on page 24 for valid L3_CLK frequencies and for more information regarding the maximum L3 frequency.

2. These core frequencies are not supported by all speed grades; see Table 8 on page 20.

53

5345B–HIREL–02/04

PLL Power Supply

Filtering

The AV_DDpower signal is provided on the PC7457 to provide power to the clock gener-

ation PLL. To ensure stability of the internal clock, the power supplied to the AV_DDinput

signal should be filtered of any noise in the 500 kHz to 10 MHz resonant frequency

range of the PLL. A circuit similar to the one shown in Figure 29 using surface mount

capacitors with minimum effective series inductance (ESL) is recommended.

The circuit should be placed as close as possible to the AV_DDpin to minimize noise cou-

pled from nearby circuits. It is often possible to route directly from the capacitors to the

AV_DDpin, which is on the periphery of the 360 CBGA footprint and very close to the

periphery of the 483 CBGA footprint, without the inductance of vias.

The PLL power supply filter provided in the PC7457 RISC Microprocessor Hardware

Specifications has been found to be less effective for Rev 1.1 devices with the low core

voltages described in this specification.

As a result, the recommended value for the resistor in the circuit is being evaluated and

a new recommendation is indicated in Figure 31. Motorola continues to evaluate the fil-

tering requirements of the PC7457 and will make updated recommendations as needed.

Note that this recommendation applies to Rev. 1.1 devices only.

Figure 31. PLL Power Supply Filter Circuit

400Ω

V

AV

DD

2.2 µF

Low ESL surface mount capacitor

GND

Decoupling

Recommendations

Due to the PC7457 dynamic power management feature, large address and data buses,

and high operating frequencies, the PC7457 can generate transient power surges and

high frequency noise in its power supply, especially while driving large capacitive loads.

This noise must be prevented from reaching other components in the PC7457 system,

and the PC7457 itself requires a clean, tightly regulated source of power. Therefore, it is

recommended that the system designer place at least one decoupling capacitor at each

V

_DD, OV_DD, and GV_DDpin of the PC7457. It is also recommended that these decoupling

capacitors receive their power from separate V_DD, OV_DD/GV_DD, and GND power planes

in the PCB, utilizing short traces to minimize inductance.

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic surface mount

technology (SMT) capacitors should be used to minimize lead inductance, preferably

0508 or 0603 orientations where connections are made along the length of the part.

Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital

Design: A Handbook of Black Magic (Prentice Hall, 1993) and contrary to previous rec-

ommendations for decoupling Motorola microprocessors, multiple small capacitors of

equal value are recommended over using multiple values of capacitance.

In addition, it is recommended that there be several bulk storage capacitors distributed

around the PCB, feeding the V_DD, GV_DD, and OV_DDplanes, to enable quick recharging

of the smaller chip capacitors. These bulk capacitors should have a low equivalent

series resistance (ESR) rating to ensure the quick response time necessary. They

should also be connected to the power and ground planes through two vias to minimize

inductance. Suggested bulk capacitors: 100 – 330 µF (AVX TPS tantalum or Sanyo

OSCON).

54

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

Connection

Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an

appropriate signal level. Unused active low inputs should be tied to OV_DD. Unused

active high inputs should be connected to GND. All NC (no-connect) signals must

remain unconnected. Power and ground connections must be made to all external V_DD

,

OV_DD, GV_DD, and GND pins in the PC7457. If the L3 interface is not used, GV_DDshould

be connected to the OV_DDpower plane, and L3VSEL should be connected to BVSEL;

the remainder of the L3 interface may be left unterminated.

Output Buffer DC

Impedance

The PC7457 processor bus and L3 I/O drivers are characterized over process, voltage,

and temperature.

To measure Z0, an external resistor is connected from the chip pad to OV_DDor GND.

Then, the value of each resistor is varied until the pad voltage is OV_DD/2 (see Figure 30

on page 50).

The output impedance is the average of two components, the resistances of the pull-up

and pull-down devices. When data is held low, SW2 is closed (SW1 is open), and RN is

trimmed until the voltage at the pad equals OV_DD/2. RN then becomes the resistance of

the pull-down devices. When data is held high, SW1 is closed (SW2 is open), and RP is

trimmed until the voltage at the pad equals OV_DD/2. RP then becomes the resistance of

the pull-up devices. RP and RN are designed to be close to each other in value. Then,

Z0 = (RP + RN)/2.

Figure 32. Driver Impedance Measurement

OV_DD

RN

SW2

Pad

Data

SW1

RP

OGND

Table 20 summarizes the signal impedance results. The impedance increases with junc-

tion temperature and is relatively unaffected by bus voltage.

Table 20. Impedance Characteristics with V_DD= 1.5V, OV_DD= 1.8V ±5%, T_j= 5° - 85°C

Impedance

Typical

Maximum

Processor bus

33 – 42

L3 Bus

34 – 42

32 – 44

Unit

Ω

Z₀

31 – 51

Ω

55

5345B–HIREL–02/04

Pull-up/Pull-down

Resistor Requirements

The PC7457 requires high-resistive (weak: 4.7 kΩ) pull-up resistors on several control

pins of the bus interface to maintain the control signals in the negated state after they

have been actively negated and released by the PC7457 or other bus masters. These

pins are TS, ARTRY, SHDO, and SHD1.

Some pins designated as being for factory test must be pulled up to OVDD or down to

GND to ensure proper device operation. For the PC7447, 360 BGA, the pins that must

be pulled up to OVDD are LSSD_MODE and TEST[0:3]; the pins that must be pulled

down to GND are L1_TSTCLK and TEST[4]. For the PC7457, 483 BGA, the pins that

must be pulled up to OVDD are LSSD_MODE and TEST[0:5]; the pins that must be

pulled down are L1_TSTCLK and TEST[6]. The CKSTP_IN signal should likewise be

pulled up through a pull-up resistor (weak or stronger: 4.7 – 1 kΩ) to prevent erroneous

assertions of this signal. In addition, the PC7457 has one open-drain style output that

requires a pull-up resistor (weak or stronger: 4.7 – 1 kΩ) if it is used by the system. This

pin is CKSTP_OUT.

If pull-down resistors are used to configure BVSEL or L3VSEL, the resistors should be

less than 250Ω (see Table 16 on page 40). Because PLL_CFG[0:4] must remain stable

during normal operation, strong pull-up and pull-down resistors (1 kΩ or less) are rec-

ommended to configure these signals in order to protect against erroneous switching

due to ground bounce, power supply noise or noise coupling.

During inactive periods on the bus, the address and transfer attributes may not be

driven by any master and may, therefore, float in the high-impedance state for relatively

long periods of time. Because the PC7457 must continually monitor these signals for

snooping, this float condition may cause excessive power draw by the input receivers on

the PC7457 or by other receivers in the system. It is recommended that these signals be

pulled up through weak (4.7 kΩ) pull-up resistors by the system, or that they may be oth-

erwise driven by the system during inactive periods of the bus. The snooped address

and transfer attribute inputs are A[0:35], AP[0:4], TT[0:4], CI, WT, and GBL.

If extended addressing is not used, A[0:3] are unused and must be pulled low to GND

through weak pull-down resistors. If the PC7457 is in 60x bus mode, DTI[0:3] must be

pulled low to GND through weak pull-down resistors.

The data bus input receivers are normally turned off when no read operation is in

progress and, therefore, don’t require pull-up resistors on the bus. Other data bus receiv-

ers in the system, however, may require pull-ups, or that those signals be otherwise

driven by the system during inactive periods by the system. The data bus signals are

D[0:63] and DP[0:7].

If address or data parity is not used by the system, and the respective parity checking is

disabled through HID0, the input receivers for those pins are disabled, and those pins

don’t require pull-up resistors and should be left unconnected by the system. If all parity

generation is disabled through HID0, then all parity checking should also be disabled

through HID0, and all parity pins may be left unconnected by the system.

The L3 interface does not normally require pull-up resistors.

56

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

JTAG Configuration

Signals

Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal

is optional in the IEEE 1149.1 specification, but is provided on all processors that imple-

ment the PowerPC architecture. While it is possible to force the TAP controller to the

reset state using only the TCK and TMS signals, more reliable power-on reset perfor-

mance will be obtained if the TRST signal is asserted during power-on reset. Because

the JTAG interface is also used for accessing the common on-chip processor (COP)

function, simply tying TRST to HRESET is not practical.

The COP function of these processors allows a remote computer system (typically, a PC

with dedicated hardware and debugging software) to access and control the internal

operations of the processor. The COP interface connects primarily through the JTAG

port of the processor, with some additional status monitoring signals. The COP port

requires the ability to independently assert HRESET or TRST in order to fully control the

processor. If the target system has independent reset sources, such as voltage moni-

tors, watchdog timers, power supply failures, or push-button switches, then the COP

reset signals must be merged into these signals with logic.

The arrangement shown in Figure 31 allows the COP port to independently assert

HRESET or TRST, while ensuring that the target can drive HRESET as well. If the JTAG

interface and COP header will not be used, TRST should be tied to HRESET through a

0Ω isolation resistor so that it is asserted when the system reset signal (HRESET) is

asserted, ensuring that the JTAG scan chain is initialized during power-on. While Motor-

ola recommends that the COP header be designed into the system as shown in Figure

31 on page 54, if this is not possible, the isolation resistor will allow future access to

TRST in the case where a JTAG interface may need to be wired onto the system in

debug situations.

The COP header shown in Figure 31 adds many benefits – breakpoints, watchpoints,

register and memory examination/modification, and other standard debugger features

are possible through this interface – and can be as inexpensive as an unpopulated foot-

print for a header to be added when needed.

The COP interface has a standard header for connection to the target system, based on

the 0.025" square-post, 0.100" centered header assembly (often called a Berg header).

The connector typically has pin 14 removed as a connector key.

There is no standardized way to number the COP header shown in Figure 31; conse-

quently, many different pin numbers have been observed from emulator vendors. Some

are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-

bottom, while still others number the pins counter clockwise from pin 1 (as with an IC).

Regardless of the numbering, the signal placement recommended in Figure 31 is com-

mon to all known emulators.

The QACK signal shown in Figure 31 is usually connected to the PCI bridge chip in a

system and is an input to the PC7457 informing it that it can go into the quiescent state.

Under normal operation this occurs during a low-power mode selection. In order for

COP to work, the PC7457 must see this signal asserted (pulled down). While shown on

the COP header, not all emulator products drive this signal. If the product does not, a

pull-down resistor can be populated to assert this signal. Additionally, some emulator

products implement open-drain type outputs and can only drive QACK asserted; for

these tools, a pull-up resistor can be implemented to ensure this signal is deasserted

when it is not being driven by the tool. Note that the pull-up and pull-down resistors on

the QACK signal are mutually exclusive and it is never necessary to populate both in a

system. To preserve correct power-down operation, QACK should be merged via logic

so that it also can be driven by the PCI bridge.

57

5345B–HIREL–02/04

Figure 33. JTAG Interface Connection

SRESET

From Target

Board Sources

(if any)

SRESET

HRESET

QACK

10 kΩ

HRESET

13

11

OV

DD

SRESET

OV

DD

OV

DD

OV

DD

(5)

0Ω

TRST

1

3

5

7

9

2

4

TRST

4

VDD_SENSE

6

OV

DD

10 kΩ

2 kΩ

6

(1)

5

OV

DD

8

CHKSTP_OUT

15

10 kΩ

10

OV

DD

Key

14

11 12

KEY

10 kΩ

(2)

OV

DD

13

CHKSTP_IN

TMS

No Pin

CHKSTP_IN

TMS

8

9

1

3

7

2

15

16

COP Connector

Physical Pin Out

TDO

TDI

TDO

TDI

TCK

QACK

NC

QACK

10

OV

DD

(3)

(6)

2 kΩ

12

(4)

10 kΩ

16

Notes: 1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the PC7457. Connect pin 5 of the COP

header to OV_DDwith a 10 kΩ pull-up resistor.

2. Key location; pin 14 is not physically present on the COP header.

3. Component not populated. Populate only if debug tool does not drive QACK.

4. Populate only if debug tool uses an open-drain type output and does not actively deassert QACK.

5. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP header though an

AND gate to TRST of the part. If the JTAG interface is not implemented, connect HRESET from the target source to TRST of

the part through a 0Ω isolation resistor.

6. Though defined as a No-Connect, it is a common and recommended practice to use pin 12 as an additional GND pin for

improved signal integrity.

58

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

Definitions

Datasheet Status

Description

Table 21. Datasheet Status

Datasheet Status

Validity

This datasheet contains target and goal

Objective specification

Target specification

specifications for discussion with customer and

application validation.

Before design phase

This datasheet contains target or goal

specifications for product development.

Valid during the design phase

Valid before characterization phase

This datasheet contains preliminary data.

Additional data may be published later; could

include simulation results.

Preliminary specification

α-site

This datasheet also contains characterization

results.

Preliminary specification β-site

Valid before the industrialization phase

Valid for production purposes

This datasheet contains final product

specification.

Product specification

Limiting Values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the

limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at

any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for

extended periods may affect device reliability.

Application Information

Where application information is given, it is advisory and does not form part of the specification.

Life Support

Applications

These products are not designed for use in life support appliances, devices or systems

where malfunction of these products can reasonably be expected to result in personal

injury. Atmel customers using or selling these products for use in such applications do

so at their own risk and agree to fully indemnify Atmel for any damages resulting from

such improper use or sale.

59

5345B–HIREL–02/04

Ordering Information

PC (X) 7457

V

G

U

L

x

1000

(1)

Revision Level

Rev. B, C

Prefix

Prototype

(1)

Application modifier

L: 1.3V ± 50 mV

N: 1.1V ± 50 mV

Type

(1)

Max internal processor speed

933 MHz

(1)

Temperature Range: T

V: -40˚C, 110˚C

j

1000 MHz

1200 MHz (TBC)

M: -55˚C +125˚C

Package

G: CBGA

(1)

Screening Level

U: Upscreening

PC (X) 7447

V

G

U

L

x

1000

(1)

Revision Level

Rev. B, C

Prefix

Prototype

(1)

Application modifier

L: 1.3V ± 50 mV

N: 1.1V ± 50 mV

Type

(1)

Max internal processor speed

933 MHz

(1)

Temperature Range: T

V: -40˚C, 110˚C

j

1000 MHz

1200 MHz (TBC)

M: -55˚C +125˚C

Package

G: CBGA

GH: HITCE (TBC)

(1)

Screening Level

U: Upscreening

Note:

1. For availability of the different versions, contact your local Atmel sales office.

60

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

Document Revision

History

Table 22 provides a revision history for this hardware specification.

Table 22. Document Revision History

Revision

Number

Substantive Change(s)

Figure 9 on page 22: Corrected pin lists for input and output AC timing to correctly show HIT as an output-only signal

Added specifications for 1267 MHz devices; removed specs for 1300 MHz devices.

B

Changed recommendations regarding use of L3 clock jitter in AC timing analysis in Section “L3 Clock AC

Specifications” on page 24; the L3 jitter is now fully comprehended in the AC timing specs and does not need to be

included in the timing analysis

61

5345B–HIREL–02/04

62

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

Table of Contents

Features ................................................................................................1

Des cription ...........................................................................................1

Screening ............................................................................................. 2

Block Diagram ......................................................................................3

General Parameters .............................................................................4

Features ................................................................................................4

Signal Des cription .............................................................................10

Detailed Specification .......................................................................11

Scope ..................................................................................................11

Applicable Documents ......................................................................11

Requirements .....................................................................................11

General................................................................................................................11

Design and Construction .................................................................................... 11

Absolute Maximum Ratings ................................................................................11

Recommended Operating Conditions................................................................. 12

Thermal Characteristics ......................................................................................13

Electrical Characteris tics ..................................................................19

Static Characteristics.......................................................................................... 19

Dynamic Characteristics .....................................................................................20

Preparation for Delivery ....................................................................37

Handling ..............................................................................................37

Package Mechanical Data .................................................................38

Package Parameters for the PC7447, 360 CBGA ..............................................38

Pin As s ignment ..................................................................................39

Pinout Lis tings ................................................................................... 40

Mechanical Dimens ions for the PC7447, 360 CBGA ......................43

Subs trate Capacitors for the PC7447, 360 CBGA ...........................44

i

5345B–HIREL–02/04

Package Parameters for the PC7457, 483 CBGA ............................44

Mechanical Dimens ions for the PC7457, 483 CBGA .......................49

Subs trate Capacitors for the PC7457, 483 CBGA........................... 50

Sys tem Des ign Information .............................................................. 51

PLL Configuration .............................................................................51

PLL Power Supply Filtering ................................................................................54

Decoupling Recommendations ...........................................................................54

Connection Recommendations........................................................................... 55

Output Buffer DC Impedance .............................................................................55

Pull-up/Pull-down Resistor Requirements .......................................................... 56

JTAG Configuration Signals ...............................................................................57

Definitions .......................................................................................... 59

Datas heet Status Des cription ...........................................................59

Life Support Applications ................................................................. 59

Ordering Information ......................................................................... 60

Document Revis ion His tory ..............................................................61

ii

PC7457/47 [Preliminary]

5345B–HIREL–02/04

PC7457/47 [Preliminary]

iii

5345B–HIREL–02/04

Atmel Corporation

Atmel Operations

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Memory

RF/Automotive

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

Tel: (49) 71-31-67-0

Fax: (49) 71-31-67-2340

Regional Headquarters

Microcontrollers

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Europe

Atmel Sarl

Route des Arsenaux 41

Case Postale 80

CH-1705 Fribourg

Switzerland

Tel: (41) 26-426-5555

Fax: (41) 26-426-5500

Fax: 1(719) 540-1759

Biometrics/Imaging/Hi-Rel MPU/

High Speed Converters/RF Datacom

Avenue de Rochepleine

La Chantrerie

BP 70602

44306 Nantes Cedex 3, France

Tel: (33) 2-40-18-18-18

Fax: (33) 2-40-18-19-60

BP 123

38521 Saint-Egreve Cedex, France

Tel: (33) 4-76-58-30-00

Fax: (33) 4-76-58-34-80

Asia

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimshatsui

East Kowloon

Hong Kong

Tel: (852) 2721-9778

Fax: (852) 2722-1369

ASIC/ASSP/Smart Cards

Zone Industrielle

13106 Rousset Cedex, France

Tel: (33) 4-42-53-60-00

Fax: (33) 4-42-53-60-01

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Fax: 1(719) 540-1759

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

Tel: (44) 1355-803-000

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Fax: (44) 1355-242-743

Literature Requests

www.atmel.com/literature

Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard

warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any

errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and

does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are

granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use

as critical components in life support devices or systems.

subsidiaries. PowerPC^™is the trademark of IBM Corporation. Motorola is the registered trademark of Motorola, Inc. AltiVec^™is a trademark

of Motorola, Inc. Other terms and product names may be the trademarks of others.

Printed on recycled paper.

5345B–HIREL–02/04


型号：	PCX7447MGHU1200LC
厂家：	ATMEL
描述：	RISC Microprocessor, 32-Bit, 1200MHz, CMOS, CBGA360, HITCE, CERAMIC, BGA-360
文件：	总66页 (文件大小：520K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCX7447MGHU1200LC [ATMEL]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E