T5744-TKQ [ATMEL]
UHF ASK Receiver; UHF ASK接收器
| 型号： | T5744-TKQ |
| 厂家： | 
ATMEL |
| 描述： | UHF ASK Receiver |
| 文件： | 总20页 (文件大小：280K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Minimal External Circuitry Requirements, no RF Components on the PC Board Except
Matching to the Receiver Antenna
• High Sensitivity, Especially at Low Data Rates
• SSO20 and SO20 package
• Fully Integrated VCO
• Supply Voltage 4.5 V to 5.5 V, Operating Temperature Range -40°C to 105°C
• Single-ended RF Input for Easy Adaptation to l/4 Antenna or Printed Antenna on PCB
• Low-cost Solution Due to High Integration Level
• Various Types of Protocols Supported (i.e., PWM, Manchester and Biphase)
• Distinguishes the Signal Strength of Several Transmitters via RSSI (Received Signal
Strength Indicator)
• ESD Protection According to MIL-STD. 883 (4KV HBM)
• High Image Frequency Suppression Due to 1 MHz IF in Conjunction with a SAW Front-
end Filter, up to 40 dB is thereby Achievable with Newer SAWs
• Power Management (Polling) is Possible by Means of a Separate Pin via the
Microcontroller
UHF ASK
Receiver
T5744
• Receiving Bandwidth BIF = 600 kHz
Description
The T5744 is a PLL receiver device for the receiving range of f0 = 300 MHz to
450 MHz. It is developed for the demands of RF low-cost data communication sys-
tems with low data rates and fits for most types of modulation schemes including
Manchester, Biphase and most PWM protocols. Its main applications are in the areas
of telemetering, security technology and keyless-entry systems.
Figure 1. System Block Diagram
UHF ASK/FSK
Remote control transmitter
UHF ASK
Remote control receiver
1 Li cell
T5744
U2741B
Data
interface
1...3
Demod.
IF Amp
µC
Encoder
M44Cx9x
PLL
Keys
Antenna Antenna
XTO
VCO
PLL
XTO
Power
amp.
LNA
VCO
Rev. 4521B–RKE–01/03
Pin Configuration
Figure 2. Pinning SO20 and SSO20
Pin Description
Pin
Symbol
Function
1
BR_0
Baud rate select LSB
Baud rate select MSB
Lower cut-off frequency data filter
Analog power supply
Analog ground
2
BR_1
3
CDEM
AVCC
AGND
DGND
MIXVCC
LNAGND
LNA_IN
n.c.
4
5
6
Digital ground
7
Power supply mixer
High-frequency ground LNA and mixer
RF input
8
9
10
11
12
13
14
15
Not connected
LFVCC
LF
Power supply VCO
Loop filter
LFGND
XTO
Ground VCO
Crystal oscillator
DVCC
Digital power supply
Selecting 433.92 MHz /315 MHz
Low: 315 MHz (USA)
16
MODE
High: 433.92 MHz (Europe)
17
18
RSSI
TEST
Output of the RSSI amplifier
Test pin, during operation at GND
Selecting operation mode
Low: sleep mode
High: receiving mode
19
20
ENABLE
DATA
Data output
2
T5744
4521B–RKE–01/03
T5744
Figure 3. Block Diagram
BR_0
BR_1
ASK-
Demodulator
and data filter
Dem_out
DATA
TEST
CDEM
Data interface
RSSI
RSSI
AVCC
RSSI IF Amp
Test
AGND
DGND
MODE
DVCC
4. Order
ENABLE
LFGND
LPF
3 MHz
MIXVCC
Standby logic
LFVCC
XTO
LF
IF Amp
VCO
XTO
LPF
3 MHz
LNAGND
LNA_IN
f
LNA
64
RF Front End
The RF front end of the receiver is a heterodyne configuration that converts the input
signal into a 1-MHz IF signal. According to Figure 3, the front end consists of an LNA
(Low-Noise Amplifier), LO (Local Oscillator), a mixer and RF amplifier.
The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO
(crystal oscillator) generates the reference frequency fXTO. The VCO (Voltage-Controlled
Oscillator) generates the drive voltage frequency fLO for the mixer. fLO is dependent on
the voltage at Pin LF. fLO is divided by factor 64. The divided frequency is compared to
fXTO by the phase frequency detector. The current output of the phase frequency detec-
tor is connected to a passive loop filter and thereby generates the control voltage VLF
for the VCO. By means of that configuration, VLF is controlled in a way that fLO/64 is
equal to fXTO. If fLO is determined, fXTO can be calculated using the following formula:
fXTO = fLO/64
The XTO is a one-pin oscillator that operates at the series resonance of the quartz crys-
tal. According to Figure 4, the crystal should be connected to GND via a capacitor CL.
The value of that capacitor is recommended by the crystal supplier. The value of CL
should be optimized for the individual board layout to achieve the exact value of fXTO and
hereby of fLO. When designing the system in terms of receiving bandwidth, the accuracy
of the crystal and the XTO must be considered.
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4521B–RKE–01/03
Figure 4. PLL Peripherals
VS
DVCC
CL
XTO
LFGND
R1 = 820 ꢀ
C9 = 4.7 nF
C10 = 1 nF
LF
R1
C9
VS
C10
LFVCC
The passive loop filter connected to Pin LF is designed for a loop bandwidth of BLoop =
100 kHz. This value for BLoop exhibits the best possible noise performance of the LO.
Figure 4 shows the appropriate loop filter components to achieve the desired loop
bandwidth
fLO is determined by the RF input frequency fRF and the IF frequency fIF using the follow-
ing formula:
fLO = fRF - fIF
To determine fLO, the construction of the IF filter must be considered at this point. The
nominal IF frequency is fIF = 1 MHz. To achieve a good accuracy of the filter's corner fre-
quencies, the filter is tuned by the crystal frequency fXTO. This means that there is a
fixed relation between fIF and fLO that depends on the logic level at pin mode. This is
described by the following formulas:
MODE = 0 USA fIF = fLO/314
MODE = 1 Europe fIF = fLO/432.92
The relation is designed to achieve the nominal IF frequency of fIF = 1 MHz for most
applications. For applications where fRF = 315 MHz, MODE must be set to '0'. In the
case of fRF = 433.92 MHz, MODE must be set to '1'. For other RF frequencies, fIF is
not equal to 1 MHz. fIF is then dependent on the logical level at Pin MODE and on fRF.
Table 1 summarizes the different conditions.
The RF input either from an antenna or from a generator must be transformed to the RF
input Pin LNA_IN. The input impedance of that pin is provided in the electrical parame-
ters. The parasitic board inductances and capacitances also influence the input
matching. The RF receiver T5744 exhibits its highest sensitivity at the best signal-to-
noise ratio in the LNA. Hence, noise matching is the best choice for designing the trans-
formation network.
A good practice when designing the network, is to start with power matching. From that
starting point, the values of the components can be varied to some extent to achieve the
best sensitivity.
If a SAW is implemented into the input network a mirror frequency suppression of
ꢀPRef = 40 dB can be achieved. There are SAWs available that exhibit a notch at
ꢀf = 2 MHz. These SAWs work best for an intermediate frequency of IF = 1 MHz. The
selectivity of the receiver is also improved by using a SAW. In typical automotive appli-
cations, a SAW is used.
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T5744
4521B–RKE–01/03
T5744
Figure 5 shows a typical input matching network for fRF = 315 MHz and fRF
=
433.92 MHz using a SAW. Figure 6 illustrates the input matching to 50 ꢁ without a
SAW. The input matching networks shown in Figure 6 are the reference networks for the
parameters given in the electrical characteristics.
Table 1. Calculation of LO and IF Frequency
Conditions
Local Oscillator Frequency
fLO = 314 MHz
Intermediate Frequency
fIF = 1 MHz
fRF = 315 MHz, MODE = 0
fRF = 433.92 MHz, MODE = 1
fLO = 432.92 MHz
fIF = 1 MHz
fRF
fLO
fIF = ---------
314
fLO = -------------------
300 MHz < fRF < 365 MHz, MODE = 0
365 MHz < fRF < 450 MHz, MODE = 1
1
1 + ---------
314
f
fLO
fIF = -----------------
432.92
fLO = -------------R---F-----------
1
1 + -----------------
432.92
Figure 5. Input Matching Network with SAW Filter
8
8
LNAGND
LNAGND
T5744
T5744
9
9
L
L
C3
C3
LNA_IN
LNA_IN
25n
25n
22p
47p
C16
C16
C17
8.2p
C17
22p
100p
100p
L3
L3
fRF = 433.92 MHz
TOKO LL2012
F27NJ
TOKO LL2012
F47NJ
fRF = 315 MHz
27n
47n
L2
L2
TOKO LL2012
TOKO LL2012
F82NJ
RFIN
RFIN
F33NJ
5
6
5
1
2
1
2
B3555
B3551
IN
IN
OUT
OUT
33n
82n
6
OUT_GND
OUT_GND
IN_GND
IN_GND
C2
C2
CASE_GND
3,4 7,8
CASE_GND
3,4 7,8
8.2p
10p
5
4521B–RKE–01/03
Figure 6. Input Matching Network without SAW Filter
fRF = 433.92 MHz
fRF = 315 MHz
8
8
9
LNAGND
LNAGND
T5744
T5744
9
LNA_IN
LNA_IN
25n
25n
C3
C3
15p
33p
RFIN
RFIN
3.3p
3.3p
100p
100p
22n
39n
TOKO LL2012
F22NJ
TOKO LL2012
F39NJ
Please note that for all coupling conditions (see Figure 5 and Figure 6), the bond wire
inductivity of the LNA ground is compensated. C3 forms a series resonance circuit
together with the bond wire. L = 25 nH is a feed inductor to establish a DC path. Its value
is not critical but must be large enough not to detune the series resonance circuit. For
cost reduction, this inductor can be easily printed on the PCB. This configuration
improves the sensitivity of the receiver by about 1 dB to 2 dB.
Analog Signal Processing
IF Amplifier
The signals coming from the RF front end are filtered by the fully integrated 4th-order IF
filter. The IF center frequency is fIF = 1 MHz for applications where fRF = 315 MHz or
fRF = 433.92 MHz is used. For other RF input frequencies, refer to Table 1 to determine
the center frequency.
The receiver T5744 employs an IF bandwidth of BIF = 600 kHz and can be used
together with the U2741B in ASK mode.
RSSI Amplifier
The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is
fed into the demodulator. The dynamic range of this amplifier is DRRSSI = 60 dB. If the
RSSI amplifier is operated within its linear range, the best S/N ratio is maintained. If the
dynamic range is exceeded by the transmitter signal, the S/N ratio is defined by the ratio
of the maximum RSSI output voltage and the RSSI output voltage due to a disturber.
The dynamic range of the RSSI amplifier is exceeded if the RF input signal is about
60 dB higher compared to the RF input signal at full sensitivity.
Pin RSSI
The output voltage of the RSSI amplifier (VRSSI) is available at Pin RSSI. Using the
RSSI output signal, the signal strength of different transmitters can be distinguished.
The usable input power range PRef is -100 dBm to -55 dBm.
Since different RF input networks may exhibit slightly different values for the LNA gain,
the sensitivity values given in the electrical characteristics refer to a specific input
matching. This matching is illustrated in Figure 6 and exhibits the best possible
sensitivity.
6
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4521B–RKE–01/03
T5744
Figure 7. RSSI Characteristics
3.0
2.8
2.6
2.4
2.2
max.
Tamb = 40°C
25°C
105°C
2.0
1.8
1.6
1.4
1.2
1.0
min.
-130.0
-110.0
-90.0
-70.0
-50.0
-30.0
PRef (dBm)
ASK Demodulator and
Data Filter
The signal coming from the RSSI amplifier is converted into the raw data signal by the
ASK demodulator.
An automatic threshold control circuit (ATC) is employed to set the detection reference
voltage to a value where a good signal-to-noise ratio is achieved. This circuit also
implies the effective suppression of any kind of inband noise signals or competing trans-
mitters. If the S/N ratio exceeds 10 dB, the data signal can be detected properly.
The output signal of the demodulator is filtered by the data filter before it is fed into the
digital signal processing circuit. The data filter improves the S/N ratio as its passband
can be adopted to the characteristics of the data signal. The data filter consists of a 1st-
order highpass and a 1st-order lowpass filter.
The highpass filter cut-off frequency is defined by an external capacitor connected to Pin
CDEM. The cut-off frequency of the highpass filter is defined by the following formula:
1
fcu_DF = -------------------------------------------------
2 P ꢂ P R1 P CDEM
Recommended values for CDEM are given in the electrical characteristics.
The cut-off frequency of the lowpass filter is defined by the selected baudrate range
(BR_Range). BR_Range is defined by the Pins BR_0 and BR_1. BR_Range must be
set in accordance to the used baudrate.
BR_1
BR_0
BR_Range
0
0
1
1
0
1
0
1
0
1
2
2
Each BR_Range is defined by a minimum and a maximum edge-to-edge time (tee_sig).
These limits are defined in the electrical characteristics. They should not be exceeded to
maintain full sensitivity of the receiver.
7
4521B–RKE–01/03
Receiving
Characteristics
The RF receiver T5744 can be operated with and without a SAW front-end filter. In a
typical automotive application, a SAW filter is used to achieve better selectivity. The
selectivity with and without a SAW front-end filter is illustrated in Figure 7. Note that the
mirror frequency is reduced by 40 dB. The plots are printed relatively to the maximum
sensitivity. If a SAW filter is used, an insertion loss of about 4 dB must be considered.
When designing the system in terms of receiving bandwidth, the LO deviation must be
considered as it also determines the IF center frequency. The total LO deviation is cal-
culated to be the sum of the deviation of the crystal and the XTO deviation of the T5744.
Low-cost crystals are specified to be within ±100 ppm. The XTO deviation of the T5744
is an additional deviation due to the XTO circuit. This deviation is specified to be
±30 ppm. If a crystal of ±100 ppm is used, the total deviation is ±130 ppm in that case.
Note that the receiving bandwidth and the IF-filter bandwidth are equivalent.
Figure 8. Receiving Frequency Response
0.0
without SAW
-20.0
-40.0
-60.0
-80.0
with SAW
-100.0
-6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0
1.0 2.0 3.0 4.0 5.0 6.0
df (MHz)
Basic Clock Cycle of the The complete timing of the digital circuitry and the analog filtering is derived from one
clock. According to Figure 9, this clock cycle TClk is derived from the crystal oscillator
Digital Circuitry
(XTO) in combination with a divider. The division factor is controlled by the logical state
at Pin MODE. According to chapter 'RF Front End', the frequency of the crystal oscillator
(fXTO) is defined by the RF input signal (fRFin) which also defines the operating frequency
of the local oscillator (fLO).
Figure 9. Generation of the Basic Clock Cycle
T
Clk
MODE
L : USA(:10)
Divider
:14/:10
16
H: Europe(:14)
f
DVCC
15
XTO
XTO
14
XTO
8
T5744
4521B–RKE–01/03
T5744
Pin MODE can now be set in accordance with the desired clock cycle TClk. TClk controls
the following application-relevant parameters:
Timing of the analog and digital signal processing
IF filter center frequency (fIF0
Most applications are dominated by two transmission frequencies: fSend = 315 MHz is
mainly used in USA, fSend = 433.92 MHz in Europe. In order to ease the usage of all TClk
)
-
dependent parameters, the electrical characteristics display three conditions for each
parameter.
•
•
•
Application USA
(fXTO = 4.90625 MHz, MODE = L, TClk = 2.0383 µs)
Application Europe
(fXTO = 6.76438 MHz, MODE = H, TClk = 2.0697 µs)
Other applications
(TClk is dependent on fXTO and on the logical state of Pin MODE. The electrical
characteristic is given as a function of TClk).
The clock cycle of some function blocks depends on the selected baud rate range
(BR_Range) which is defined by the Pins BR_0 and BR_1. This clock cycle TXClk is
defined by the following formulas for further reference:
BR_Range = BR_Range0: TXClk = 8 P TClk
BR_Range1: TXClk = 4 P TClk
BR_Range2: TXClk = 2 P TClk
BR_Range3: TXClk = 1 P TClk
Pin ENABLE
Via the Pin ENABLE the operating mode of the receiver can be selected (see Figure 10
and Figure 11).
If the Pin ENABLE is held to Low, the receiver remains in sleep mode. All circuits for sig-
nal processing are disabled and only the XTO is running in that case. The current
consumption is IS = ISoff in that case. During the sleep mode the receiver is not sensitive
to a transmitter signal.
To activate the receiver, the Pin ENABLE must be held to High. During the start-up
period, TStartup, all signal processing circuits are enabled and settled. The duration of the
start-up period depends on the selected baud-rate range (BR_Range).
After the start-up period, all circuits are in a stable condition and the receiver is in the
receiving mode.
In receiving mode, the internal data signal (Dem_out) is switched to Pin DATA. To avoid
incorrect timing at the begin of the data stream, the begin is synchronized to a falling
edge of the incoming data signal. The receiver stays in the receiving mode until it is
switched back to sleep mode via Pin ENABLE.
During start-up and receiving mode, the current consumption is IS = ISon
.
9
4521B–RKE–01/03
Figure 10. Enable Timing (1)
Dem_out
ENABLE
DATA
tee_sig
Sleep mode
IS = I Soff
Start-up mode
IS = I Son
Receiving mode
IS = I Son
TStart-up
Figure 11. Enable Timing (2)
Dem_out
ENABLE
DATA
tee_sig
Sleep mode
IS = I Soff
Start-up mode
IS = I Son
Receiving mode
IS = I Son
TStart-up
Digital Signal
Processing
The data from the ASK demodulator (Dem_out) is digitally processed in different ways
and as a result converted into the output signal DATA. This processing depends on the
selected baudrate range (BR_Range). Figure 12 illustrates how Dem_out is synchro-
nized by the extended basic clock cycle TXClk. Data can change its state only after TXClk
has elapsed. The edge-to-edge time period tee_sig of the DATA signal as a result is
always an integral multiple of TXClk
.
The minimum time period between two edges of the data signal is limited to tee_sig O
TDATA_min. This implies an efficient suppression of spikes at the DATA output. At the
same time it limits the maximum frequency of edges at DATA. This eases the interrupt
handling of a connected microcontroller.
10
T5744
4521B–RKE–01/03
T5744
Figure 12. Synchronization of the Demodulator Output
TXClk
Dem_out
Data_out (DATA)
tee_sig
Figure 13. Debouncing of the Demodulator Output
Dem_out
DATA
tDATA_min
tDATA_min
tDATA_min
tee
tee
tee
Absolute Maximum Ratings
Parameters
Symbol
VS
Min.
Max.
Unit
V
Supply voltage
6
Power dissipation
Ptot
450
150
+125
+105
10
mW
°C
Juntion temperature
Storage temperature
Ambient temperature
Maximum input level, input matched to 50 ꢀ
Tj
Tstg
-55
-40
°C
Tamb
Pin_max
°C
dBm
Thermal Resistance
Parameters
Symbol
RthJA
Value
100
Unit
K/W
K/W
Junction ambient SO20 package
Junction ambient SSO20 package
RthJA
100
11
4521B–RKE–01/03
Electrical Characteristics
All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless other-
wise specified. (VS = 5 V, Tamb = 25°C)
6.76438 MHz Osc.
(MODE:1)
4.90625 MHz Osc.
(MODE:0)
Variable Oscillator
Test Conditions
Parameters
Symbol
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
Min. Typ. Max.
Basic Clock Cycle of the Digital Circuitry
Basic clock
cycle
MODE = 0 (USA)
MODE = 1 (Europe)
2.0383
2.0383
1/(fxto/10)
1/(fxto/14)
1/(fxto/10)
1/(fxto/14)
µs
µs
TClk
2.0697
2.0697
Extended basic
clock cycle
BR_Range0
BR_Range1
BR_Range2
BR_Range3
16.6
8.3
4.1
16.6
8.3
4.1
16.3
8.2
4.1
16.3
8.2
4.1
8 P TClk
4 P TClk
2 P TClk
1 P TClk
8 P TClk
4 P TClk
2 P TClk
1 P TClk
µs
µs
µs
µs
TXClk
2.1
2.1
2.0
2.0
Start-up time
(see Figure 10
and Figure 11)
BR_Range0
BR_Range1
BR_Range2
BR_Range3
1855
1061
1061
663
1855
1061
1061
663
1827
1045
1045
653
1827
1045
1045
653
896.5
512.5
512.5
320.5
P TClk
896.5
512.5
512.5
320.5
P TClk
µs
µs
µs
µs
µs
TStartup
Receiving Mode
Intermediate
frequency
MODE=0 (USA)
MODE=1 (Europe)
MHz
MHz
fXTO P 64 / 314
fXTO P 64 / 432.92
fIF
1.0
1.0
Minimum time
period between
edges at
BR_Range0
BR_Range1
BR_Range2
BR_Range3
(Figure 13)
165
83
41.4
20.7
165
83
41.4
20.7
163
81
40.7
20.4
163
81
40.7
20.4
10 ´ TXClk
10 ´ TXClk
10 ´ TXCl
10´ TXClk
10 ´ TXClk
µs
µs
µs
µs
TDATA_min
10 ´ TXCl
10´ TXClk
10 ´ TXClk
Pin DATA
Edge to edge
time period of
the data signal
for full
BR_Range0
BR_Range1
BR_Range2
BR_Range3
(Figure 10)
400
200
100
50
8479
8479
8479
8479
400
200
100
50
8350
8350
8350
8350
µs
µs
µs
µs
BR_Range
Pꢀ
tee_sig
4097 P
TCLK
2 µs/TCLK
sensitivity
Electrical Characteristics (continued)
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Current consumption
Sleep mode (XTO active)
ISoff
190
276
µA
IC active (startup-, receiving
mode) Pin DATA = H
ISon
7.1
8.7
mA
LNA Mixer
Third-order intercept point
LNA/ mixer/ IF amplifier
input matched according to
Figure 6
IIP3
-28
dBm
LO spurious emission
at RFIn
Input matched according to
Figure 6, required according to
I-ETS 300220
ISLORF
-73
7
-57
dBm
dB
Noise figure LNA and mixer
(DSB)
Input matching according to
Figure 6
NF
LNA_IN input impedance
at 433.92 MHz
at 315 MHz
1.0 || 1.56
1.3 || 1.0
kW || pF
kW || pF
ZiLNA_IN
IP1db
1 dB compression point
(LNA, mixer, IF amplifier)
Input matched according to
Figure 6, referred to RFin
-40
dBm
12
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4521B–RKE–01/03
T5744
Electrical Characteristics (continued)
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Maximum input level
Input matched according to
Pin_max
-20
dBm
Figure 6, BER ? 10-3
Local Oscillator
Operating frequency range
VCO
fVCO
299
449
MHz
Phase noise VCO / LO
fosc = 432.92 MHz
at 1 MHz
L (fm)
-93
-113
-90
-110
dBC/Hz
dBC/Hz
at 10 MHz
Spurious of the VCO
VCO gain
at ± fXTO
-55
-47
dBC
KVCO
190
MHz/V
Loop bandwidth of the PLL
For best LO noise
(design parameter)
R1 = 820 ꢀ
BLoop
100
kHz
nF
C9 = 4.7 nF
C10 = 1 nF
Capacitive load at Pin LF
XTO operating frequency
CLF_tot
10
XTO crystal frequency,
appropriate load capacitance
must be connected to XTAL
f
XTAL = 6.764375 MHz (EU)
fXTO
6.764375
-30 ppm
4.90625
-30 ppm
6.764375
4.90625
6.764375
+30 ppm
4.90625
+30 ppm
MHz
MHz
fXTAL = 4.90625 MHz (US)
Series resonance resistor of
the crystal
fXTO = 6.764 MHz
4.906 MHz
150
220
ꢀ
ꢀ
RS
Co
Static capacitance of the
crystal
6.5
pF
Analog Signal Processing
Input sensitivity
Input matched according to
Figure 6
ASK (level of carrier)
PRef_ASK
BER ? 10-3 (Manchester),
fin = 433.92 MHz/ 315 MHz
T = 25°C, VS = 5 V, fIF = 1 MHz
BR_Range0 (1 kBd)
BR_Range1 (2 kBd)
BR_Range2 (4kBd)
BR_Range3 (8 kBd)
-107
-105
-103
-101
-110
-108
-106
-104
-112
-110
-108
-106
dBm
dBm
dBm
dBm
Sensitivity variation for the
full operating range
compared to
fin = 433.92 MHz/ 315 MHz
fIF = 1 MHz
PASK = PRef_ASK + DPRef
ꢁPRef
+2.5
-1.5
dB
Tamb = 25°C, VS = 5 V
Sensitivity variation for full
operating range including IF
filter compared to
fin = 433.92 MHz/ 315 MHz
fIF = 0.79 MHz to 1.21 MHz
fIF = 0.73 MHz to 1.27 MHz
ꢁPRef
+5.5
+7.5
-1.5
-1.5
dB
dB
Tamb = 25°C, VS = 5 V
PASK = PRef_ASK + DPRef
S/N ratio to suppress inband
noise signals
SNR
10
12
dB
13
4521B–RKE–01/03
Electrical Characteristics (continued)
Parameters
Test Conditions
Symbol
Min.
1.0
28
Typ.
Max.
3.0
Unit
Dynamic range RSSI
amplifier
DRRSSI
60
dB
RSSI output voltage range
RSSI gain
VRSSI
GRSSI
V
20
40
mV/dB
RI of Pin CDEM for cut-off
frequency calculation
1
fcu_DF = -------------------------------------------------
2 P ꢂ P R1 P CDEM
RI
55
kꢀ
Recommended CDEM for
best performance
BR_Range0
BR_Range1
BR_Range2
BR_Range3
33
18
10
6.8
nF
nF
nF
nF
CDEM
Upper cut-off frequency data
filter
Upper cut-off frequency
BR_Range0
BR_Range1
BR_Range2
BR_Range3
1.75
3.5
7.0
2.2
4.4
8.8
2.65
5.3
10.6
21.2
kHz
kHz
kHz
kHz
fu
14.0
17.6
Digital Ports
Data output
- Saturation voltage LOW
- Internal pull-up resistor
Iol = 1 mA
VOI
RPup
0.08
50
0.3
65
V
kꢀ
39
ENABLE input
- Low-level input voltage
- High-level input voltage
Sleep mode
Receiving mode
VIl
VIh
0.2 P VS
0.2 P VS
0.2 P VS
0.2 PꢂVS
0.2 P VS
V
V
0.8 P VS
0.8 P VS
0.8 P VS
0.8 P VS
MODE input
- Low-level input voltage
- High-level input voltage
Division factor = 10
Division factor = 14
VIl
VIh
V
V
BR_0 input
- Low-level input voltage
- High-level input voltage
VIl
VIh
V
V
BR_1 input
- Low-level input voltage
- High-level input voltage
VIl
VIh
V
V
TEST input
- Low-level input voltage
Test input must always be set to
LOW
VIl
V
14
T5744
4521B–RKE–01/03
T5744
Figure 14. Application Circuit: fRF = 433.92 MHz, without SAW Filter
VS
C7
C6
2.2uF
10%
10nF
10%
T5744
C14
1
2
3
20
19
18
17
16
BR_0
BR_1
CDEM
DATA
ENABLE
TEST
DATA
39nF 5%
ENABLE
RSSI
GND
RSSI
4
5
6
AVCC
AGND
DGND
MODE
C13
10nF 10%
15
14
DVCC
XTO
Q1
C11
7
MIXVCC
12pF
8
13
12
11
LNAGND
LNA_IN
NC
LFGND
LF
6.76438MHz
2% np0
9
C3 15pF
5% np0
10
LFVCC
C12
C15
C8
10nF 10%
150pF
10%
150pF
10%
KOAX
C16
R1
820
5%
100pF
C17
5% np0
3.3pF
5% np0
L2 TOKO LL2012 F22NJ
C9
C10
1nF
5%
22nH
5%
4.7nF
5%
Figure 15. Application Circuit: fRF = 315 MHz, without SAW Filter
VS
C6
C7
T5744
10nF
10%
2.2uF
10%
C14
1
2
3
20
19
18
17
16
DATA
BR_0
BR_1
CDEM
DATA
39nF 5%
ENABLE
RSSI
ENABLE
TEST
RSSI
GND
4
5
6
AVCC
AGND
DGND
MODE
DVCC
XTO
C13
15
14
10nF 10%
Q1
C11
7
MIXVCC
13
12
11
15pF
8
9
10
4.90625MHz
LNAGND
LNA_IN
NC
LFGND
LF
np0
2%
C3 33pF
5% np0
LFVCC
C12
10nF 10%
C15
C8
150pF
10%
150pF
10%
C16
100pF
KOAX
R1
820
5%
C17
3.3pF
5% np0
C9
C10
5% np0
L2 TOKO LL2012 F39NJ
4.7nF
5%
1nF
5%
39nH
5%
15
4521B–RKE–01/03
Figure 16. Application Circuit: fRF = 433.92 MHz, with SAW Filter
VS
C7
C6
T5744
2.2uF
10%
10nF
10%
C14
1
2
3
20
19
18
17
16
BR_0
BR_1
CDEM
DATA
ENABLE
TEST
DATA
39nF 5%
ENABLE
GND
RSSI
RSSI
4
5
6
AVCC
AGND
DGND
MODE
C13
10nF 10%
15
14
DVCC
XTO
Q1
C11
7
MIXVCC
6.76438MHz 12pF
np0
8
13
12
11
LNAGND
LNA_IN
NC
LFGND
LF
2%
9
C3 22pF
10
LFVCC
5% np0
C15
C8
C12
10nF 10%
150pF
10%
150pF
10%
C16
C17
8,2pF
np0
100pF
5%
5%
np0
L3 TOKO LL2012
F27 NJ
R1
27nH
5%
820
5%
L2 TOKO LL2012
C9
C10
KOAX
F33NJ
1
4.7nF
5%
1nF
5%
5
IN
OUT
2
6
IN_GND
OUT_GND
33nH
5%
3
7
8
CASE_GND
CASE_GND
CASE_GND
C2
4
CASE_GND
8.2pF
5% np0
B3555
Figure 17. Application Circuit: fRF = 315 MHz, witht SAW Filter
VS
C7
C6
T5744
2.2uF
10%
10nF
10%
C14
1
2
3
20
BR_0
BR_1
CDEM
DATA
ENABLE
TEST
DATA
39n F 5%
19
18
17
16
ENABLE
GND
RSSI
RSSI
4
5
6
AVCC
AGND
DGND
MODE
C13
10nF 10%
15
14
DVCC
XTO
Q1
C11
15pF
7
MIXVCC
8
9
13
12
11
LNAGND
LNA_IN
NC
LFGND
LF
4.90625MHz
2%
np0
10
C3 47pF
5% np0
LFVCC
C8
C15
C12
10nF 10%
150pF
10%
150pF
10%
C16
C17
22pF
np0
100pF
5%
5%
np0
L3 TOKO LL2012
F47NJ
R1
47nH
5%
820
5%
L2 TOKO LL2012
C9
C10
KOAX
F82NJ
4.7nF
5%
1nF
5%
1
5
IN
IN_GND
OUT
2
6
OUT_GND
82nH
C2
5%
10pF
3
4
7
8
CASE_GND
CASE_GND
CASE_GND
CASE_GND
5%
np0
B3551
16
T5744
4521B–RKE–01/03
T5744
Ordering Information
Extended Type Number
Package
SSO20
SSO20
SO20
Remarks
T5744-TKS
Tube
T5744-TKQ
Taped and reeled
Tube
T5744-TGS
T5744-TGQ
SO20
Taped and reeled
Package Information
9.15
8.65
Package SO20
Dimensions in mm
12.95
12.70
7.5
7.3
2.35
0.25
0.25
0.10
0.4
10.50
10.20
1.27
11.43
20
11
technical drawings
according to DIN
specifications
1
10
17
4521B–RKE–01/03
5.7
5.3
Package SSO20
Dimensions in mm
6.75
6.50
4.5
4.3
1.30
0.15
0.15
0.05
0.25
0.65
6.6
6.3
5.85
20
11
technical drawings
according to DIN
specifications
1
10
18
T5744
4521B–RKE–01/03
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4521B–RKE–01/03
xM
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