T5744-TKS_技术文档

T5744

UHF ASK Receiver

Description

The T5744 is a PLL receiver device for the receiving schemes including Manchester, Biphase and most PWM

range of f = 300 MHz to 450 MHz. It is developed for the protocols. Its main applications are in the areas of teleme-

0

demands of RF low-cost data communication systems tering, security technology and keyless-entry systems.

with low data rates and fits for most kind of modulation

F_De_Mat_inu_imre_als_{external circuitry requirements, no RF com-}

D Various kinds of protocols like PWM, Manchester and

ponents on the PC board except matching to the

receiver antenna

Biphase supported

D Distinguishing the signal strength of several transmit-

ters via RSSI (Received Signal Strength Indicator)

D High sensitivity, especially at low data rates

D SSO20 and SO20 package

D ESD protection according to MIL-STD. 883

(4KV HBM)

D Fully integrated VCO

D High image frequency suppression due to 1 MHz IF

in conjunction with a SAW front-end filter. Up to

40 dB is thereby achievable with newer SAWs.

D Supply voltage 4.5 V to 5.5 V,

operating temperature range –40°C to 105°C

D Single-ended RF input for easy adaptation to l/4 an-

D Power management (polling) is possible by means of

a separate pin via the mC

tenna or printed antenna on PCB

D Low-cost solution due to high integration level

D Receiving bandwidth B = 600 kHz

IF

System Block Diagram

UHF ASK/FSK

Remote control transmitter

UHF ASK

Remote control receiver

1 Li cell

T5744

U2741B

Data

interface

1...3

Demod.

IF Amp

mC

Encoder

PLL

M44Cx9x

Keys

Antenna Antenna

XTO

VCO

PLL

XTO

Power

amp.

LNA

VCO

Figure 1. System block diagram

Ordering Information

Extended Type Number

T5744-TKS

Package

Remarks

SSO20

SO20

Tube

T5744-TKQ

Taped and reeled

Tube

T5744-TGS

T5744-TGQ

SO20

Taped and reeled

Rev. A1, 01-Aug-01

1 (16)

Preliminary Information

T5744

Pin Description

1

Symbol

BR_0

Function

Baud rate select LSB

Baud rate select MSB

20

19

18

17

16

15

14

13

12

11

BR_0

BR_1

1

2

3

4

5

6

7

DATA

2

BR_1

ENABLE

TEST

3

CDEM

Lower cut-off frequency data fil-

ter

CDEM

4

5

6

7

8

AVCC

AGND

DGND

Analog power supply

Analog ground

RSSI

AVCC

AGND

Digital ground

MIXVCC Power supply mixer

MODE

DVCC

T5744

LNAGND High-frequency ground LNA and

mixer

DGND

9

LNA_IN RF input

XTO

MIXVCC

10

11

12

13

14

15

16

n.c.

LFVCC Power supply VCO

LF Loop filter

LFGND Ground VCO

Not connected

8

LFGND

LF

LNAGND

LNA_IN

9

XTO

Crystal oscillator

DVCC

Digital power supply

LFVCC

10

n.c.

MODE Selecting 433.92 MHz /315 MHz

Low: 315 MHz (USA)

High: 433.92 MHz (Europe)

Figure 2. Pinning SO20 and SSO20

17

18

RSSI

Output of the RSSI amplifier

TEST

Test pin, during operation at GND

19 ENABLE Selecting operation mode

Low: sleep mode

High: receiving mode

20

DATA

Data output

2 (16)

Rev. A1, 01-Aug-01

Preliminary Information

T5744

Block Diagram

BR_0 BR_1

ASK–

Demodulator

and data filter

Dem_out

DATA

TEST

CDEM

Data interface

RSSI

AVCC

RSSI IF Amp

Test

AGND

DGND

MODE

DVCC

4. Order

ENABLE

LFGND

LPF

3 MHz

MIXVCC

Standby logic

LFVCC

XTO

LF

IF Amp

VCO

XTO

LPF

3 MHz

LNAGND

LNA_IN

f

LNA

64

Figure 3. Block diagram

RF Front End

The RF front end of the receiver is a heterodyne configu- figuration, V is controlled in a way that f /64 is equal

LF

LO

ration that converts the input signal into a 1-MHz IF to f

. If f is determined, f can be calculated using

XTO

LO

XTO

signal. According to figure 3, the front end consists of an the following formula:

LNA (low noise amplifier), LO (local oscillator), a mixer

and RF amplifier.

f

= f /64

XTO LO

The LO generates the carrier frequency for the mixer via The XTO is a one-pin oscillator that operates at the series

a PLL synthesizer. The XTO (crystal oscillator) generates resonance of the quartz crystal. According to figure 4, the

the reference frequency f . The VCO (voltage-con- crystal should be connected to GND via a capacitor CL.

XTO

trolled oscillator) generates the drive voltage frequency The value of that capacitor is recommended by the crystal

for the mixer. f is dependent on the voltage at Pin supplier. The value of CL should be optimized for the in-

f

LO

LF. f is divided by factor 64. The divided frequency is dividual board layout to achieve the exact value of f

LO

XTO

compared to f

by the phase frequency detector. The and hereby of f . When designing the system in terms

XTO

LO

current output of the phase frequency detector is con- of receiving bandwidth, the accuracy of the crystal and

nected to a passive loop filter and thereby generates the the XTO must be considered.

control voltage V for the VCO. By means of that con-

LF

Rev. A1, 01-Aug-01

3 (16)

Preliminary Information

T5744

V

f_LO

432.92

S

MODE + 1 (Europe) f_IF+

DVCC

C_L

The relation is designed to achieve the nominal IF fre-

quency of f = 1 MHz for most applications. For

XTO

LFGND

LF

IF

applications where f = 315 MHz, MODE must be set to

RF

‘0’. In the case of f = 433.92 MHz, MODE must be set

RF

R1 = 820 W

C9 = 4.7 nF

C10 = 1 nF

to ‘1’. For other RF frequencies, f is not equal to 1 MHz.

IF

f

is then dependent on the logical level at Pin MODE and

IF

on f . Table 1 summarizes the different conditions.

RF

The RF input either from an antenna or from a generator

must be transformed to the RF input Pin LNA_IN. The in-

put impedance of that pin is provided in the electrical

parameters. The parasitic board inductances and capaci-

tances also influence the input matching. The RF receiver

T5744 exhibits its highest sensitivity at the best signal-to-

noise ratio in the LNA. Hence, noise matching is the best

choice for designing the transformation network.

R1

C9

V_S

C10

LFVCC

Figure 4. PLL peripherals

The passive loop filter connected to Pin LF is designed for

a loop bandwidth of BLoop = 100 kHz. This value for

BLoop exhibits the best possible noise performance of the

LO. Figure 4 shows the appropriate loop filter compo-

nents to achieve the desired loop bandwidth

A good practice when designing the network, is to start

with power matching. From that starting point, the values

of the components can be varied to some extent to achieve

the best sensitivity.

If a SAW is implemented into the input network a mirror

f

is determined by the RF input frequency f and the

RF

LO

frequency suppression of DP = 40 dB can be achieved.

Ref

IF frequency f using the following formula:

IF

There are SAWs available that exhibit a notch at

Df = 2 MHz. These SAWs work best for an intermediate

frequency of IF = 1 MHz. The selectivity of the receiver

is also improved by using a SAW. In typical automotive

applications, a SAW is used.

f

= f – f

LO

RF IF

To determine f , the construction of the IF filter must be

considered at this point. The nominal IF frequency is

f = 1 MHz. To achieve a good accuracy of the filter’s

corner frequencies, the filter is tuned by the crystal fre-

LO

IF

Figure 5 shows a typical input matching network for

quency f

. This means that there is a fixed relation

XTO

f

= 315 MHz and f = 433.92 MHz using a SAW. Fig-

RF

between f and f , that depends on the logic level at pin

mode. This is described by the following formulas:

IF

LO

ure 6 illustrates an according input matching to 50 W

without a SAW. The input matching networks shown in

figure 6 are the reference networks for the parameters

given in the electrical characteristics.

f_LO

MODE + 0 (USA) f_IF+

314

Table 1 Calculation of LO and IF frequency

Conditions

Local Oscillator Frequency

Intermediate Frequency

f

= 315 MHz, MODE = 0

f

= 314 MHz

= 432.92 MHz

f_RF

f

= 1 MHz

f_RF

RF

LO

IF

= 433.92 MHz, MODE = 1

f_LO

+

f_IF+

300 MHz < f < 365 MHz, MODE = 0

RF

1

314

1 ) ₃₁₄

f_RF

432.92

f_LO

+

f_IF+

365 MHz < f < 450 MHz, MODE = 1

RF

1

1 ) _432.92

4 (16)

Rev. A1, 01-Aug-01

Preliminary Information

T5744

8

9

8

9

LNAGND

T5744

L

C3

LNA_IN

25n

22p

47p

C16

C17

8.2p

C17

22p

100p

L3

TOKO LL2012

F27NJ

TOKO LL2012

F47NJ

f

= 433.92 MHz

f

= 315 MHz

RF

27n

47n

L2

TOKO LL2012

RF

IN

RF

IN

F33NJ

F82NJ

1

2

5

1

2

5

B3555

B3551

IN

OUT

OUT_GND

OUT

OUT_GND

33n

82n

6

IN_GND

C2

CASE_GND

3,4 7,8

CASE_GND

3,4 7,8

8.2p

10p

Figure 5. Input matching network with SAW filter

f

= 433.92 MHz

f

= 315 MHz

RF

8

9

8

LNAGND

T5744

9

LNA_IN

25n

C3

15p

33p

RF

IN

RF

IN

3.3p

100p

22n

39n

TOKO LL2012

F22NJ

TOKO LL2012

F39NJ

Figure 6. Input matching network without SAW filter

Please note that for all coupling conditions (see figures 5 RF input frequencies, refer to table 1 to determine the

and 6), the bond wire inductivity of the LNA ground is center frequency.

compensated. C3 forms a series resonance circuit to-

The receiver T5744 employs an IF bandwidth of

gether with the bond wire. L = 25 nH is a feed inductor to

B

= 600 kHz and can be used together with the U2741B

IF

establish a DC path. Its value is not critical but must be

large enough not to detune the series resonance circuit.

For cost reduction, this inductor can be easily printed on

the PCB. This configuration improves the sensitivity of

the receiver by about 1 dB to 2 dB.

in ASK mode.

RSSI Amplifier

The subsequent RSSI amplifier enhances the output

signal of the IF amplifier before it is fed into the demod-

ulator. The dynamic range of this amplifier is

Analog Signal Processing

DR

= 60 dB. If the RSSI amplifier is operated within

RSSI

IF Amplifier

its linear range, the best S/N ratio is maintained. If the dy-

The signals coming from the RF front end are filtered by namic range is exceeded by the transmitter signal, the S/N

th

the fully integrated 4 -order IF filter. The IF center fre- ratio is defined by the ratio of the maximum RSSI output

quency is

f

IF

= 1 MHz for applications where voltage and the RSSI output voltage due to a disturber.

f

= 315 MHz or f = 433.92 MHz is used. For other The dynamic range of the RSSI amplifier is exceeded if

RF

Rev. A1, 01-Aug-01

5 (16)

Preliminary Information

T5744

the RF input signal is about 60 dB higher compared to the The highpass filter cut-off frequency is defined by an ex-

RF input signal at full sensitivity.

ternal capacitor connected to Pin CDEM. The cut-off

frequency of the highpass filter is defined by the follow-

ing formula:

Pin RSSI

The output voltage of the RSSI amplifier (V

able at Pin RSSI. Using the RSSI output signal, the signal

strength of different transmitters can be distinguished.

) is avail-

RSSI

1

fcu_DF +

2 p R_I CDEM

The usable input-power range P

–55 dBm.

is –100 dBm to

Ref

Recommended values for CDEM are given in the electri-

cal characteristics.

Since different RF input networks may exhibit slightly

different values for the LNA gain, the sensitivity values

given in the electrical characteristics refer to a specific in-

put matching. This matching is illustrated in figure 6 and

exhibits the best possible sensitivity.

The cut-off frequency of the lowpass filter is defined by

the selected baudrate range (BR_Range). BR_Range is

defined by the Pins BR_0 and BR_1. BR_Range must be

set in accordance to the used baudrate.

BR_1

BR_0

BR_Range

3.0

0

1

0

1

0

1

0

1

2

3

max

2.8

2.6

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

T

= –40_C

25_C

amb

105_C

Each BR_Range is defined by a minimum and a maxi-

mum edge-to-edge time (t ). These limits are defined

in the electrical characteristics. They should not be ex-

ceeded to maintain full sensitivity of the receiver.

min

ee_sig

–130–120–110–100–90 –80 –70 –60 –50 –40 –30

( dBm )

Receiving Characteristics

P

Ref

The RF receiver T5744 can be operated with and without

a SAW front end filter. In a typical automotive applica-

tion, a SAW filter is used to achieve better selectivity. The

selectivity with and without a SAW front end filter is il-

lustrated in figure 7. Note that the mirror frequency is

reduced by 40 dB. The plots are printed relatively to the

maximum sensitivity. If a SAW filter is used, an insertion

loss of about 4 dB must be considered.

Figure 7. RSSI characteristics

ASK Demodulator and Data Filter

The signal coming from the RSSI amplifier is converted

into the raw data signal by the ASK demodulator.

An automatic threshold control circuit (ATC) is employed

to set the detection reference voltage to a value where a

good signal-to-noise ratio is achieved. This circuit also

implies the effective suppression of any kind of inband

noise signals or competing transmitters. If the S/N ratio

exceeds 10 dB, the data signal can be detected properly.

When designing the system in terms of receiving band-

width, the LO deviation must be considered as it also

determines the IF center frequency. The total LO devi-

ation is calculated to be the sum of the deviation of the

crystal and the XTO deviation of the T5744. Low-cost

The output signal of the demodulator is filtered by the crystals are specified to be within 100 ppm. The XTO

data filter before it is fed into the digital signal processing deviation of the T5744 is an additional deviation due to

circuit. The data filter improves the S/N ratio as its pass- the XTO circuit. This deviation is specified to be

band can be adopted to the characteristics of the data

signal. The data filter consists of a 1st-order highpass and ation is 130 ppm in that case. Note that the receiving

a 1st-order lowpass filter. bandwidth and the IF-filter bandwidth are equivalent.

30 ppm. If a crystal of 100 ppm is used, the total devi-

6 (16)

Rev. A1, 01-Aug-01

Preliminary Information

T5744

Most applications are dominated by two transmission fre-

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

quencies: f

= 315 MHz is mainly used in USA, f

Send

= 433.92 MHz in Europe. In order to ease the usage of all

-dependent parameters, the electrical characteristics

without SAW

T

Clk

display three conditions for each parameter.

D Application USA

(f

= 4.90625 MHz, MODE = L, T = 2.0383 µs)

Clk

XTO

D Application Europe

(f

= 6.76438 MHz, MODE = H, T = 2.0697 µs)

Clk

XTO

D Other applications

with SAW

(T is dependent on f

and on the logical state of

XTO

Clk

Pin MODE. The electrical characteristic is given as a

–6 –5 –4 –3 –2 –1

0

1

2

3

4

5

6

function of T ).

Clk

16564

df ( MHz )

The clock cycle of some function blocks depends on the

selected baud rate range (BR_Range) which is defined by

Figure 8. Receiving frequency response

the Pins BR_0 and BR_1. This clock cycle T

is de-

XClk

fined by the following formulas for further reference:

Basic Clock Cycle of the Digital Circuitry

BR_Range = BR_Range0: T

BR_Range1: T

= 8 × T

= 4 × T

= 2 × T

= 1 × T

XClk

Clk

The complete timing of the digital circuitry and the ana-

log filtering is derived from one clock. According to

BR_Range2: T

BR_Range3: T

figure 9, this clock cycle T is derived from the crystal

Clk

oscillator (XTO) in combination with a divider. The divi-

sion factor is controlled by the logical state at Pin MODE.

According to chapter ‘RF Front End’, the frequency of the

Pin ENABLE

Via the Pin ENABLE the operating mode of the receiver

can be selected (Figure 10, Figure 11).

crystal oscillator (f

) is defined by the RF input signal

XTO

(f

) which also defines the operating frequency of the

RFin

local oscillator (f ).

LO

If the Pin ENABLE is held to Low, the receiver remains

in sleep mode. All circuits for signal processing are dis-

abled and only the XTO is running in that case. The

T

Clk

current consumption is I = I

in that case. During the

S

Soff

MODE

16

sleep mode the receiver is not sensitive to a transmitter

signal.

L : USA(:10)

H: Europe(:14)

Divider

:14/:10

To activate the receiver, the Pin ENABLE must held to

f

DVCC

15

XTO

High. During the start-up period, T

, all signal proc-

Startup

essing circuits are enabled and settled. The duration of the

start-up period depends on the selected baud-rate range

(BR_Range).

XTO

14

XTO

After the start-up period all circuits are in a stable condi-

tion and the receiver is in the receiving mode.

In the receiving mode the internal data signal (Dem_out)

is switched to Pin DATA. To avoid a incorrect timing at

the begin of the data stream, the begin is synchronized to

a falling edge of the incoming data signal. The receiver

stays in the receiving mode until it is switched back to

sleep mode via Pin ENABLE.

Figure 9. Generation of the basic clock cycle

Pin MODE can now be set in accordance with the desired

clock cycle T . T controls the following application-

Clk Clk

relevant parameters:

D Timing of the analog and digital signal processing

During the start-up and the receiving mode the current

D IF filter center frequency (f

)

consumption is I = I

.

IF0

S

Son

Rev. A1, 01-Aug-01

7 (16)

Preliminary Information

T5744

Dem_out

ENABLE

DATA

t_{ee_sig}

Sleep mode

I_S= I _Soff

Start–up mode

Receiving mode

I_S= I _Son

T

Start–up

Figure 10. Enable timing (1)

Dem_out

ENABLE

DATA

t_{ee_sig}

Sleep mode

I_S= I _Soff

Start–up mode

Receiving mode

I_S= I _Son

T

Start–up

Figure 11. Enable timing (2)

of the DATA signal as a result is always an integral multi-

ple of T

Digital Signal Processing

XClk.

The data from the ASK demodulator (Dem_out) is digi-

tally processed in different ways and as a result converted

The minimum time period between two edges of the data

. This implies an

into the output signal DATA. This processing depends on signal is limited to tee_sig w T

DATA_min

the selected baud-rate range (BR_Range). Figure 12 illus- efficient suppression of spikes at the DATA output. At the

trates how Dem_out is synchronized by the extended same time it limits the maximum frequency of edges at

basic clock cycle T

. Data can change its state only af- DATA. This eases the interrupt handling of a connected

XClk

ter T

elapsed. The edge-to-edge time period tee_sig mC.

XClk

T_XClk

Dem_out

Data_out (DATA)

t_{ee_sig}

Figure 12. Synchronization of the demodulator output

8 (16)

Rev. A1, 01-Aug-01

Preliminary Information

T5744

Dem_out

DATA

t_{DATA_min}

t_ee

Figure 13. Debouncing of the demodulator output

t_ee

Absolute Maximum Ratings

Parameter

Symbol

Min.

Max.

6

Unit

V

Supply voltage

V

S

Power dissipation

P

450

150

+125

+105

10

mW

°C

tot

Junction temperature

T

j

Storage temperature

T

stg

–55

–40

°C

Ambient temperature

T

amb

°C

Maximum input level, input matched to 50 W

P

dBm

in_max

Thermal Resistance

Parameter

Symbol

Value

100

Unit

K/W

Junction ambient SO20 package

Junction ambient SSO20 package

R

thJA

140

Electrical Characteristics

All parameters refer to GND, T

= –40°C to +105°C, V = 4.5 V to 5.5 V, f = 433.92 MHz and f = 315 MHz, un-

amb

S

0

less otherwise specified. (V = 5 V, T

= 25°C)

S

amb

Parameter

Test Condition

Symbol

6.76438 MHz Osc.

(MODE: 1)

4.90625 MHz Osc.

(MODE: 0)

Variable Oscillator

Typ.

Unit

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Max.

Basic clock cycle of the digital circuitry

Basic clock

cycle

MODE = 0 (USA)

MODE = 1 (Europe)

T

2.0383

1/(f /10)

xto

1/(f /10)

xto

µs

Clk

2.0697

1/(f /14)

xto

Extended

basic clock

cycle

BR_Range0

BR_Range1

BR_Range2

BR_Range3

T

16.6

8.3

4.1

2.1

16.6

8.3

4.1

2.1

16.3

8.2

4.1

2.0

16.3

8.2

4.1

2.0

8 × T

µs

XClk

Clk

4 × T

Clk

4 × T

Clk

2 × T

Clk

1 × T

Clk

1 × T

Clk

Start-up

time

see figures

BR_Range0

BR_Range1

BR_Range2

BR_Range3

T

1855

1061

663

1855

1061

663

1827

1045

653

1827

1045

653

896.5

512.5

320.5

896.5

512.5

320.5

µs

Startup

10 and 11

× T

Clk

× T

Clk

Receiving mode

Intermedi-

f

IF

ate fre-

quency

MODE=0 (USA)

MODE=1 (Europe)

1.0

f

× 64 / 314

MHz

XTO

× 64 / 432.92

1.0

f

XTO

Rev. A1, 01-Aug-01

9 (16)

Preliminary Information

T5744

Electrical Characteristics (continued)

All parameters refer to GND, T

= –40°C to +105°C, V = 4.5 V to 5.5 V, f = 433.92 MHz and f = 315 MHz, un-

amb

S

0

less otherwise specified. (V = 5 V, T

= 25°C)

S

amb

Parameter

Test Condition

Symbol

6.76438 MHz Osc.

(MODE: 1)

4.90625 MHz Osc.

(MODE: 0)

Variable Oscillator

Typ. Max.

Unit

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Minimum

time period

between

edges at

Pin DATA

BR_Range0

BR_Range1

BR_Range2

BR_Range3

(figure 13)

T

DATA_min

165

83

41.4

20.7

165

83

41.4

20.7

163

81

40.7

20.4

163

81

40.7

20.4

10 × T

µs

XClk

10 × T

XCl

10× T

XClk

10 × T

XClk

10 × T

XClk

Edge to

edge time

period of

the data sig- BR_Range3

nal for full

sensitivity

BR_Range0

BR_Range1

BR_Range2

t

400

200

100

50

8479

400

200

100

50

8350

µs

ee_sig

BR_Range

4097

T

CLK

2 ms/T

CLK

(figure 10)

Parameters

Test Conditions / Pins

Symbol

Min.

Typ.

Max.

Unit

Current consumption

Sleep mode

(XTO active)

IS_off

190

276

µA

IC active

IS_on

7.1

8.7

mA

(startup-, receiving mode)

Pin DATA = H

LNA mixer

Third-order intercept point

LNA/ mixer/ IF amplifier

input matched according to fig-

ure 6

IIP3

–28

–73

7

dBm

dB

LO spurious emission

@ RF_In

Input matched according to fig-

ure 6, required according to

I–ETS 300220

IS_LORF

–57

Noise figure LNA and mixer Input matching according to fig-

NF

(DSB)

ure 6

LNA_IN input impedance

@ 433.92 MHz

@ 315 MHz

Zi_{LNA_IN}

IP_1db

1.0 || 1.56

1.3 || 1.0

kΩ || pF

1 dB compression point

(LNA, mixer, IF amplifier)

Input matched according to fig-

ure 6, referred to RF_in

–40

dBm

Maximum input level

Input matched according to fig-

ure 6, BER ≤ 10^–3

P_{in_max}

–20

dBm

Local oscillator

Operating frequency range

VCO

f_VCO

299

449

MHz

Phase noise VCO / LO

f_osc= 432.92 MHz

@ 1 MHz

L (fm)

–93

–113

–90

–110

dBC/Hz

@ 10 MHz

Spurious of the VCO

VCO gain

@

f_XTO

–55

190

100

–47

dBC

MHz/V

kHz

K_VCO

B_Loop

Loop bandwidth of the PLL For best LO noise

(design parameter)

R1 = 820 W

C9 = 4.7 nF

C10 = 1 nF

10 (16)

Rev. A1, 01-Aug-01

Preliminary Information

T5744

Electrical Characteristics (continued)

All parameters refer to GND, T

= –40°C to +105°C, V = 4.5 V to 5.5 V, f = 433.92 MHz and f = 315 MHz, un-

amb

S

0

less otherwise specified. (V = 5 V, T

= 25°C)

S

amb

Parameters

Test Conditions / Pins

Symbol

Min.

Typ.

Max.

Unit

Capacitive load at Pin LF

XTO operating frequency

C_{LF_tot}

f_XTO

10

nF

XTO crystal frequency,

appropriate load capacitance

must be connected to XTAL

f_XTAL= 6.764375 MHz (EU)

6.764375

–30 ppm

4.90625

–30 ppm

6.764375

4.90625

6.764375

+30 ppm

4.90625

+30 ppm

MHz

f_XTAL= 4.90625 MHz (US)

Series resonance resistor of

the crystal

f_XTO= 6.764 MHz

4.906 MHz

R_S

C_o

150

220

W

Static capacitance of the

crystal

6.5

pF

Analog signal processing

Input sensitivity

Input matched according to fig-

ure 6

P_{Ref_ASK}

ASK (level of carrier)

BER ≤ 10^–3(Manchester),

f_in= 433.92 MHz/ 315 MHz

T = 25°C, V_S= 5 V

_IF= 1 MHz

f

BR_Range0 (1 kBd)

BR_Range1 (2 kBd)

BR_Range2 (4kBd)

–107

–105

–103

–101

–110

–108

–106

–104

–112

–110

–108

–106

dBm

BR_Range3 (8 kBd)

f_in= 433.92 MHz/ 315 MHz

Sensitivity variation for the

full operating range

compared to T_amb= 25°C,

V_S= 5 V

DP_Ref

f

_IF= 1 MHz

P_ASK= P_{Ref_ASK}+ DP_Ref

+2.5

–1.5

dB

f_in= 433.92 MHz/ 315 MHz

DP

Ref

Sensitivity variation for full

operating range including IF

f_IF= 0.79 MHz to 1.21 MHz

f_IF= 0.73 MHz to 1.27 MHz

+5.5

+7.5

–1.5

dB

P_ASK= P_{Ref_ASK}+ DP_Ref

filter

compared

to

T_amb= 25°C, V_S= 5 V

S/N ratio to suppress inband

noise signals

SNR

10

60

12

dB

Dynamic range RSSI ampl.

RSSI output voltage range.

RSSI gain

DR_RSSI

V_RSSI

G_RSSI

R_I

dB

V

1.0

28

3.0

55

20

40

mV/dB

kOhm

1

RI of Pin CDEM for cut-off

frequency calculation

f_{cu_DF}

+

2 p R_I CDEM

Recommended CDEM for

best performance

BR_Range0

BR_Range1

BR_Range2

BR_Range3

CDEM

33

18

10

6.8

nF

Rev. A1, 01-Aug-01

11 (16)

Preliminary Information

T5744

Electrical Characteristics (continued)

All parameters refer to GND, T

= –40°C to +105°C, V = 4.5 V to 5.5 V, f = 433.92 MHz and f = 315 MHz, un-

amb

S

0

less otherwise specified. (V = 5 V, T

= 25°C)

S

amb

Parameters

Test Conditions / Pins

Symbol

Min.

Typ.

Max.

Unit

Upper cut-off frequency data Upper cut-off frequency

f_u

filter

BR_Range0

BR_Range1

BR_Range2

BR_Range3

1.75

3.5

7.0

2.2

4.4

8.8

2.65

5.3

10.6

21.2

kHz

14.0

17.6

Digital ports

Data output

– Saturation voltage LOW

– Internal pull-up resistor

I_ol= 1 mA

V_OI

R_Pup

0.08

50

0.3

65

V

kW

39

ENABLE input

– Low-level input voltage

– High-level input voltage

Sleep mode

Receiving mode

V_Il

V_Ih

0.2 × V_S

V

0.8 × V_S

MODE input

– Low-level input voltage

– High-level input voltage

Division factor = 10

Division factor = 14

V_Il

V_Ih

V

BR_0 input

– Low-level input voltage

– High-level input voltage

V_Il

V_Ih

V

BR_1 input

– Low-level input voltage

– High-level input voltage

V_Il

V_Ih

V

TEST input

– Low-level input voltage

Test input must always be set to

LOW

V_Il

V

12 (16)

Rev. A1, 01-Aug-01

Preliminary Information

T5744

Application Circuits

VS

C7

2.2uF

10%

C6

10nF

10%

T5744

C14

1

2

3

20

19

18

17

16

BR_0

BR_1

CDEM

DATA

ENABLE

TEST

DATA

39nF 5%

ENABLE

GND

RSSI

4

5

6

AVCC

AGND

DGND

MODE

C13

10nF 10%

15

14

DVCC

XTO

Q1

C11

7

MIXVCC

12pF

8

9

10

13

12

11

LNAGND

LNA_IN

NC

LFGND

LF

LFVCC

6.76438MHz

np0

2%

C3 15pF

5% np0

C12

10nF 10%

C15

150pF

10%

C8

150pF

10%

KOAX

C16

R1

820

5%

100pF

5% np0

C17

3.3pF

5% np0

L2 TOKO LL2012 F22NJ

22nH

5%

C9

4.7nF

5%

C10

1nF

5%

Figure 14. Application circuit: f_RF= 433.92 MHz, without SAW filter

VS

C6

10nF

10%

C7

2.2uF

10%

T5744

C14

1

20

DATA

BR_0

BR_1

CDEM

DATA

39nF 5%

19

18

17

16

2

3

ENABLE

TEST

GND

RSSI

4

5

6

AVCC

AGND

DGND

MODE

DVCC

XTO

C13

10nF 10%

15

14

Q1

C11

7

MIXVCC

13

12

11

15pF

8

9

10

4.90625MHz

LNAGND

LNA_IN

NC

LFGND

LF

LFVCC

np0

2%

C3 33pF

5% np0

C12

10nF 10%

C15

150pF

10%

C8

150pF

10%

C16

KOAX

R1

820

5%

C17

100pF

5% np0

L2 TOKO LL2012 F39NJ

39nH

5%

3.3pF

C9

4.7nF

5%

C10

1nF

5%

5% np0

Figure 15. Application circuit: f_RF= 315 MHz, without SAW filter

Rev. A1, 01-Aug-01

13 (16)

Preliminary Information

T5744

VS

C7

2.2uF

10%

C6

10nF

10%

T5744

C14

39nF 5%

1

2

3

20

19

18

17

16

BR_0

BR_1

CDEM

DATA

ENABLE

TEST

DATA

ENABLE

GND

RSSI

4

5

6

AVCC

AGND

DGND

MODE

C13

10nF 10%

15

14

DVCC

XTO

Q1

C11

7

MIXVCC

6.76438MHz 12pF

np0

8

13

12

11

LNAGND

LNA_IN

NC

LFGND

LF

LFVCC

2%

9

C3 22pF

5% np0

10

C15

150pF

10%

C8

150pF

10%

C12

10nF 10%

C16

C17

8,2pF

np0

L3 TOKO LL2012

F27 NJ

100pF

5%

np0

R1

820

5%

27nH

5%

L2 TOKO LL2012

C9

4.7nF

5%

C10

1nF

5%

KOAX

F33NJ

1

5

IN

OUT

2

6

IN_GND

OUT_GND

33nH

5%

3

4

7

8

CASE_GND

C2

8.2pF

5% np0

B3555

Figure 16. Application circuit: f_RF= 433.92 MHz, with SAW filter

VS

C7

2.2uF

10%

C6

10nF

10%

T5744

C14

1

2

3

20

19

18

17

16

BR_0

BR_1

CDEM

DATA

ENABLE

TEST

DATA

39n F 5%

ENABLE

GND

RSSI

4

5

6

AVCC

AGND

DGND

MODE

C13

10nF 10%

15

14

DVCC

XTO

Q1

C11

15pF

7

MIXVCC

8

9

10

13

12

11

LNAGND

LNA_IN

NC

LFGND

LF

LFVCC

4.90625MHz

2%

np0

C3 47pF

5% np0

C8

150pF

10%

C15

150pF

10%

C12

10nF 10%

C16

C17

22pF

100pF

5%

np0

5%

np0

L3 TOKO LL2012

F47NJ

R1

47nH

5%

820

5%

L2 TOKO LL2012

C9

C10

1nF

5%

KOAX

F82NJ

4.7nF

5%

1

5

IN

IN_GND

OUT

2

6

OUT_GND

82nH

5%

C2

10pF

3

4

7

8

CASE_GND

5%

np0

B3551

Figure 17. Application circuit: f_RF= 315 MHz, with SAW filter

14 (16)

Rev. A1, 01-Aug-01

Preliminary Information

T5744

Package Information

Package SO20

9.15

8.65

Dimensions in mm

12.95

12.70

7.5

7.3

2.35

0.25

0.10

0.4

10.50

10.20

1.27

11.43

20

11

technical drawings

according to DIN

specifications

13038

1

10

5.7

5.3

Package SSO20

Dimensions in mm

6.75

6.50

4.5

4.3

1.30

0.15

0.05

0.25

0.65

6.6

6.3

5.85

20

11

technical drawings

according to DIN

specifications

1

10

Rev. A1, 01-Aug-01

15 (16)

Preliminary Information

T5744

Ozone Depleting Substances Policy Statement

It is the policy of Atmel Germany GmbH to

1. Meet all present and future national and international statutory requirements.

2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems

with respect to their impact on the health and safety of our employees and the public, as well as their impact on

the environment.

It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as

ozone depleting substances (ODSs).

The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid

their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these

substances.

Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed

in the following documents.

1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively

2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental

Protection Agency (EPA) in the USA

3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.

Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances

and do not contain such substances.

11.

We reserve the right to make changes to improve technical design and may do so without further notice.

Parameters can vary in different applications. All operating parameters must be validated for each customer

application by the customer. Should the buyer use Atmel Wireless & Microcontrollers products for any unintended

or unauthorized application, the buyer shall indemnify Atmel Wireless & Microcontrollers against all claims,

costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death

associated with such unintended or unauthorized use.

Data sheets can also be retrieved from the Internet:

http://www.atmel–wm.com

Atmel Germany GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany

Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423

16 (16)

Rev. A1, 01-Aug-01

Preliminary Information


型号：	T5744-TKS
厂家：	TEMIC SEMICONDUCTORS
描述：	Telecom Circuit, 1-Func, PDSO20, SSO-20 电信光电二极管电信集成电路
文件：	总16页 (文件大小：157K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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