T6818 [ATMEL]
Triple Halfbridge DMOS OUTPUT DRIVER WITH SERIAL INPUT CONTROL; 带串行输入控制三重半桥DMOS输出驱动器
| 型号： | T6818 |
| 厂家： | 
ATMEL |
| 描述： | Triple Halfbridge DMOS OUTPUT DRIVER WITH SERIAL INPUT CONTROL |
| 文件： | 总16页 (文件大小：473K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Supply Voltage up to 40 V
• RDSon Typically 0.5 Ω at 25°C, Maximum 1 Ω at 150°C
• Up to 1.5 A Output Current
• Three Half-bridge Outputs Formed by Three High-side and Three Low-side Drivers
• Capable to Switch all Kinds of Loads Such as DC Motors, Bulbs, Resistors, Capacitors
and Inductors
• No Shoot-through Current
• Very Low Quiescent Current IS < 5 µA in Standby Mode versus Total Temperature
Range
• Outputs Short-circuit Protected
• Overtemperature Protection for Each Switch and Overtemperature Prewarning
• Undervoltage Protection
Triple Half-
bridge DMOS
Output Driver
with Serial Input
Control
• Various Diagnostic Functions Such as Shorted Output, Open-load, Overtemperature
and Power-supply Fail Detection
• Serial Data Interface, Daisy Chain Capable, up to 2 MHz Clock Frequency
• SO14 Power Package
Description
The T6818/T6828 are fully protected driver interfaces designed in 0.8-µm BCDMOS
technology. They are used to control up to 3 different loads by a microcontroller in
automotive and industrial applications.
T6818/T6828
Each of the 3 high-side and 3 low-side drivers is capable to drive currents up to 1.5 A.
The drivers are internally connected to form 3 half-bridges and can be controlled sep-
arately from a standard serial data interface. Therefore, all kinds of loads such as
bulbs, resistors, capacitors and inductors can be combined. The IC design especially
supports the application of H-bridges to drive DC motors.
Protection is guaranteed regarding short-circuit conditions, overtemperature and und-
ervoltage. Various diagnostic functions and a very low quiescent current in
stand-by-mode opens a wide range of applications. Automotive qualification (protec-
tion against conducted interferences, EMC protection and 2-kV ESD protection) gives
added value and enhanced quality for exacting requirements of automotive
applications.
Rev. 4530C–BCD–11/03
Figure 1. Block Diagram
O
C
S
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
n. n.
u. u.
n. n. n. n. n. n.
u. u. u. u. u. u.
3
VS
Input register
Output register
Serial interface
Charge
pump
n. n. n. n. n. n.
u. u. u. u. u. u.
DI
5
P
S
F
S
C
D
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
T
P
O
P
L
CLK
6
CS
4
UV
protection
Fault
Fault
Fault
detect
detect
detect
11
1
INH
10
VCC
Control
logic
Power-on
reset
DO
9
GND
GND
GND
GND
7
8
Fault
Fault
Fault
detect
detect
detect
Thermal
protection
14
2
12
OUT2
13
OUT1
OUT3
2
T6818/T6828
4530C–BCD–11/03
T6818/T6828
Pin Configuration
Figure 2. Pining SO14
GND
OUT3
VS
1
2
3
4
5
6
7
14 GND
13 OUT1
12 OUT2
11 VCC
10 INH
CS
DI
CLK
GND
9
8
DO
GND
Pin Description
Pin
Symbol
Function
T6818: ground; reference potential; internal connection to pin 7, 8 and 14; cooling tab
T6828: additional connection to heat slug
1
GND
Half-bridge output 3; formed by internally connected power MOS high-side switch 3 and low-side switch 3
with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and
open load
2
OUT3
3
4
VS
CS
Power supply for output stages OUT1, OUT2 and OUT3, internal supply
Chip select input; 5-V CMOS logic level input with internal pull up;
low = serial communication is enabled, high = disabled
Serial data input; 5-V CMOS logic level input with internal pull down; receives serial data from the control
device; DI expects a 16-bit control word with LSB being transferred first
5
6
DI
Serial clock input; 5-V CMOS logic level input with internal pull down;
controls serial data input interface and internal shift register (fmax = 2 MHz)
CLK
7
8
GND
GND
Ground; see pin 1
Ground; see pin 1
Serial data output; 5-V CMOS logic level tristate output for output (status) register data; sends 16-bit
status information to the microcontroller (LSB is transferred first); output will remain tristated unless
device is selected by CS = low, therefore, several ICs can operate on one data output line only.
9
DO
Inhibit input; 5-V logic input with internal pull down; low = standby,
high = normal operation
10
INH
11
12
13
14
VCC
OUT2
OUT1
GND
Logic supply voltage (5 V)
Half-bridge output 2; see pin 2
Half-bridge output 1; see pin 2
Ground; see pin 1
3
4530C–BCD–11/03
Functional Description
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI syn-
chronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0,
SRR) has to be transferred first. Execution of new input data is enabled on the rising
edge of the CS signal. When CS is high, pin DO is in tristate condition. This output is
enabled on the falling edge of CS. Output data will change their state with the rising
edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is
transferred first.
Figure 3. Data Transfer
CS
DI
SRR
LS1
HS1
LS2
HS2
LS3
HS3
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
OCS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
DO
TP
S1L
S1H
S2L
S2H
S3L
S3H
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
SCD
OPL
PSF
Table 1. Input Data Protocol
Bit
Input Register
Function
Status register reset (high = reset; the bits PSF, OPL and SCD in
the output data register are set to low)
0
SRR
1
2
LS1
HS1
LS2
HS2
LS3
HS3
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
OCS
n. u.
n. u.
Controls output LS1 (high = switch output LS1 on)
Controls output HS1 (high = switch output HS1 on)
3
See LS1
4
See HS1
5
See LS1
6
See HS1
7
Not used
8
Not used
9
Not used
10
11
12
13
14
15
Not used
Not used
Not used
Overcurrent shutdown (high = overcurrent shutdown is active)
Not used
Not used
4
T6818/T6828
4530C–BCD–11/03
T6818/T6828
Table 2. Output Data Protocol
Output (Status)
Bit
0
Register
Function
TP
Temperature prewarning: high = warning
1
Status LS1
Status HS1
Status LS2
Status HS2
Status LS3
Status HS3
n. u.
High = output is on, low = output is off; not affected by SRR
2
High = output is on, low = output is off; not affected by SRR
3
Description see LS1
Description see HS1
Description see LS1
Description see HS1
Not used
4
5
6
7
8
n. u.
Not used
9
n. u.
Not used
10
11
12
n. u.
Not used
n. u.
Not used
n. u.
Not used
Short circuit detected: set high when at least one high-side or low-
side switch is switched off by a short-circuit condition. Bits 1 to 6
can be used to detect the shorted switch.
13
SCD
Open load detected: set high, when at least one active high-side-
or low-side switch sinks/sources a current below the open load
threshold current.
14
15
OPL
PSF
Power-supply fail: undervoltage at pin VS detected
After power-on reset, the input register has the following status:
Bit 15 Bit 14
Bit 13
(OCS)
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(HS3)
(LS3)
(HS2)
(LS2)
(HS1) (LS1)
(SRR)
x
x
H
x
x
x
x
x
x
L
L
L
L
L
L
L
The following patterns are used to enable internal test modes of the IC. It is not recommended to use these patterns during
normal operation.
Bit 15 Bit 14
Bit 13
(OCS)
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(HS3)
(LS3)
(HS2)
(LS2)
(HS1) (LS1)
(SRR)
H
H
H
H
H
H
H
H
H
H
L
L
H
L
L
L
H
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
5
4530C–BCD–11/03
Power-supply Fail
In case of undervoltage at pin VS, the Power-Supply Fail bit (PSF) in the output register
is set and all outputs are disabled. To detect an undervoltage, its duration has to last
longer than the undervoltage detection delay time tdUV. The outputs are enabled immedi-
ately when supply voltage recovers normal operation value. The PSF bit stays high until
it is reset by the SRR bit in the input register.
Open-load Detection
If the current through a high-side or low-side switch in ON-state stays below the open-
load detection threshold, the open-load detection bit (OPL) in the output register is set.
The OPL bit stays high until it is reset by the SRR bit in the input register. To detect an
open load, its duration has to last longer than the open-load detection delay time tdSd
.
Overtemperature
Protection
If the junction temperature of one or more output stages exceeds the thermal prewarn-
ing threshold, TjPW set, the temperature prewarning bit (TP) in the output register is set.
When the temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP
is reset. The TP bit can be read without transferring a complete 16-bit data word. The
status of TP is available at pin DO with the falling edge of CS. After the microcontroller
has read this information, CS is set high and the data transfer is interrupted without
affecting the status of input and output registers.
If the junction temperature of one or more output stages exceeds the thermal shutdown
threshold, Tj switch off, all outputs are disabled and the corresponding bits in the output
register are set to low. The outputs can be enabled again when the temperature falls
below the thermal shutdown threshold, Tjswitchon and the SRR bit in the input register is
set to high. Hysteresis of thermal prewarning and shutdown threshold avoids
oscillations.
Short-circuit Protection
The output currents are limited by a current regulator. Overcurrent detection is activated
by writing a high to the OCS bit in the input register. When the current in an output stage
exceeds the overcurrent limitation and shutdown theshold, it is switched off after a delay
time (tdSd). The short-circuit detection bit (SCD) is set and the corresponding status bit in
the output register is set to low. For OCS = low the overcurrent shutdown is inactive.
The SCD bit is also set if the current exceeds the overcurrent limitation and shutdown
threshold, but the outputs are not affected. By writing a high to the SRR bit in the input
register the SCD bit is reset and the disabled outputs are enabled.
Inhibit
0 V applied to pin 10 (INH) inhibits the T6818/T6828.
All output switches are then turned off and switched to tristate. The data in the output
register are deleted. The current consumption is reduced to less than 5 µA at pin VS and
less than 25 µA at pin VCC. The output switches can be activated again by switching pin
10 (INH) to 5 V which initiates an internal power-on reset.
6
T6818/T6828
4530C–BCD–11/03
T6818/T6828
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All values refer to GND pins.
Parameters
Pin
Symbol
Value
Unit
Supply voltage
3
VVS
-0.3 to +40
V
Supply voltage
t < 0.5 s; IS > -2 A
3
VVS
-1
V
Logic supply voltage
Logic input voltage
Logic output voltage
Input current
11
4 to 6, 10
9
VVCC
VCS,VDI, VCLK, VINH
VDO
-0.3 to +7
-0.3 to VVCC+0.3
V
V
-0.3 to VVCC+0.3
V
4 to 6, 10
9
ICS,IDI, ICLK, IINH
IDO
IOut3, IOut2, IOut1
IOut3, IOut2, IOut1
-10 to +10
mA
mA
Output current
-10 to +10
Output current
2, 12 and 13
2, 12 and 13
Internally limited, see output specification
-0.3 to +40
Output voltage
V
A
Reverse conducting current
(tpulse = 150 µs)
2, 12 and 13
towards pin 3
IOut3, IOut2, IOut1
17
Junction temperature range
Storage temperature range
TJ
-40 to +150
-55 to +150
LC
LC
TSTG
Thermal Resistance
Parameters
Test Conditions
Symbol
Value
Unit
T6818
Measured to GND
Pins 1, 7, 8 and 14
Junction pin
RthJP
RthJA
30
65
K/W
K/W
Junction ambient
T6828
Measured to heat slug
GND pins 1, 7, 8 and 14
Junction pin
RthJP
RthJA
5
K/W
K/W
Junction ambient
30
Operating Range
Parameters
Symbol
Value
VUV(1) to 40
4.75 to 5.25
-0.3 to VVCC
2
Unit
V
Supply voltage
VVS
Logic supply voltage
Logic input voltage
VVCC
V
VCS,VDI, VCLK, VINH
V
Serial interface clock frequency
Junction temperature range
fCLK
Tj
MHz
LC
-40 to +150
Note:
1. Threshold for undervoltage detection
7
4530C–BCD–11/03
Noise and Surge Immunity
Parameters
Test Conditions
ISO 7637-1
Value
Level 4(1)
Level 5
2 kV
Conducted interferences
Interference suppression
ESD (Human Body Model)
ESD (Machine Model)
VDE 0879 Part 2
ESD S 5.1
JEDEC A115A
200 V
Note:
1. Test pulse 5: Vsmax = 40 V
Electrical Characteristics
7.5 V < VVS < 40 V; 4.75 V < VVCC < 5.25 V; INH = High; -40LC < Tj < 150LC; unless otherwise specified, all values refer to GND pins.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
1
Current Consumption
1.1
Quiescent current VS
VVS < 20 V, INH = low
3
IVS
1
5
µA
µA
A
A
4.75 V < VVCC < 5.25 V,
INH = low
1.2
1.3
1.4
Quiescent current VCC
11
IVCC
15
25
VVS <20 V normal
operating, all outputs off
Supply current VS
3
11
3
IVS
IVCC
IVS
4
6
mA
µA
A
A
A
A
4.75 V < VVCC < 5.25 V,
normal operating
Supply current VCC
Discharge current VS
Discharge current VS
350
500
5.5
10
VVS = 32.5 V,
INH = low
1.5
0.5
2.5
mA
mA
VVS = 40 V,
INH = low
1.6
2
3
IVS
Undervoltage Detection, Power-on Reset
Power-on reset
threshold
2.1
11
VVCC
tdPor
VUv
3.2
30
3.9
95
4.4
190
7.0
V
µs
V
A
A
A
A
A
Power-on reset
After switching on VCC
delay time
2.2
2.3
2.4
2.5
Undervoltage-detection
VCC = 5 V
3
3
5.6
threshold
Undervoltage-detection
VCC = 5 V
ꢀVUv
tdUV
0.6
V
hysteresis
Undervoltage-detection
delay time
10
40
µs
3
Thermal Prewarning and Shutdown
3.1
Thermal prewarning set
TjPW set
120
105
145
130
170
155
LC
LC
B
B
Thermal prewarning
reset
3.2
3.3
TjPW reset
Thermal prewarning
hysteresis
ꢀTjPW
15
LC
B
3.4
3.5
Thermal shutdown off
Thermal shutdown on
Tj switch off
Tj switch on
150
135
175
160
200
185
LC
LC
B
B
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Delay time between rising edge of input signal at pin CS after data transmission and switch on output stages to 90% of final
level. Device not in standby for t > 1 ms
8
T6818/T6828
4530C–BCD–11/03
T6818/T6828
Electrical Characteristics (Continued)
7.5 V < VVS < 40 V; 4.75 V < VVCC < 5.25 V; INH = High; -40LC < Tj < 150LC; unless otherwise specified, all values refer to GND pins.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Thermal shutdown
hysteresis
3.6
ꢀTj switch off
15
LC
B
Ratio thermal shutdown
off/thermal prewarning
set
Tj switch off/
TjPW set
3.7
1.05
1.05
1.2
1.2
B
B
Ratio thermal shutdown
on/thermal prewarning
reset
Tj switch on/
TjPW reset
3.8
4
Output Specification (OUT1-OUT3)
2, 12,
13
4.1
IOut 1-3 = -1.3 A
On resistance
RDS On1-3
RDS On1-3
IOut 1-3
1.1
1.1
ꢁ
ꢁ
A
A
A
2, 12,
13
4.2
4.3
4.4
IOut 1-3 = 1.3 A
VOut 1-3 = 0 V
High-side output
leakage current
2, 12,
13
,
-15
µA
output stages off
VOut 1-3 = VVS,
Low-side output
leakage current
2, 12,
13
IOut 1-3
VOut 1-3 - VVS
VOut 1-3
200
1.5
µA
V
A
A
A
A
output stages off
High-side switch
reverse diode forward IOut 1-3 = 1.5 A
voltage
2, 12,
13
4.5
4.6
4.7
Low-side switch reverse
IOut 1-3 = -1.5 A
2, 12,
13
-1.5
-2.5
V
diode forward voltage
High-side overcurrent
limitation and shutdown
threshold
2, 12,
13
IOut 1-3
-2
2
-1.5
2.5
A
Low-side overcurrent
limitation and shutdown
threshold
2, 12,
13
4.8
IOut 1-3
1.5
A
A
Overcurrent shutdown
delay time
4.9
tdSd
IOut1-3
IOut1-3
tdSd
10
-45
15
40
-15
45
µs
mA
mA
µs
A
A
A
A
A
A
A
High-side open-load
detection threshold
2, 12,
13
4.10
4.11
4.12
4.13
4.14
4.15
-30
30
Low-side open-load
detection threshold
2, 12,
13
Open-load detection
delay time
200
600
20
High-side output switch VVS = 13 V
tdon
µs
on delay(1)
RLoad = 30 ꢁ
Low-side output switch VVS = 13 V
on delay(1)
Load = 30 ꢁ
High-side output switch VVS = 13 V
off delay(1)
RLoad = 30 ꢁ
tdon
20
µs
R
tdoff
20
µs
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Delay time between rising edge of input signal at pin CS after data transmission and switch on output stages to 90% of final
level. Device not in standby for t > 1 ms
9
4530C–BCD–11/03
Electrical Characteristics (Continued)
7.5 V < VVS < 40 V; 4.75 V < VVCC < 5.25 V; INH = High; -40LC < Tj < 150LC; unless otherwise specified, all values refer to GND pins.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Low-side output switch VVS = 13 V
4.16
tdoff
3
µs
A
off delay(1)
RLoad = 30 ꢁ
Dead time between
4.17 corresponding high-
and low-side switches
VVS = 13 V
tdon - tdoff
1
µs
A
RLoad = 30 ꢁ
5
Logic Inputs DI, CLK, CS, INH
Input voltage low-level
threshold
0.3 Pꢂ
VVCC
5.1
4-6, 10
4-6, 10
4-6, 10
5, 6, 10
4
VIL
VIH
ꢀVI
IPD
IPU
V
V
A
A
B
A
A
Input voltage high-level
threshold
0.7ꢂPꢂ
VVCC
5.2
5.3
5.4
5.5
Hysteresis of input
voltage
50
10
700
65
mV
µA
µA
Pull-down current pin
DI, CLK, INH
VDI, VCLK, VINH = VCC
VCS = 0 V
Pull-up current
Pin CS
-65
-10
6
Serial Interface – Logic Output DO
6.1
Output-voltage low level IDOL = 2 mA
9
9
VDOL
VDOH
0.4
10
V
V
A
A
Output-voltage high
IDOL = -2 mA
level
VVCC -
0.7 V
6.2
VCS = VCC
Leakage current
(tristate)
6.3
9
IDO
-10
µA
A
0V < VDO < VVCC
7
Inhibit Input - Timing
Delay time from
standby to normal
operation
7.1
tdINH
100
µs
A
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Delay time between rising edge of input signal at pin CS after data transmission and switch on output stages to 90% of final
level. Device not in standby for t > 1 ms
10
T6818/T6828
4530C–BCD–11/03
T6818/T6828
Serial Interface – Timing
No.
Parameters
Test Conditions
Pin
Timing Chart No.(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
DO enable after
CS falling edge
8.1
CDO = 100 pF
9
1
tENDO
200
ns
D
DO disable after
CS rising edge
8.2
CDO = 100 pF
9
2
tDISDO
200
ns
D
8.3
8.4
8.5
8.6
8.7
8.8
8.9
DO fall time
CDO = 100 pF
CDO = 100 pF
CDO = 100 pF
9
9
9
4
4
4
6
6
6
6
6
5
5
-
-
tDOf
tDOr
100
100
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D
D
D
D
D
D
D
D
D
D
D
D
D
DO rise time
DO valid time
CS setup time
CS setup time
CS high time
CLK high time
10
4
tDOVal
tCSSethl
tCSSetlh
tCSh
225
225
500
225
225
500
225
225
40
8
9
5
tCLKh
8.10 CLK low time
8.11 CLK period time
8.12 CLK setup time
8.13 CLK setup time
8.14 DI setup time
8.15 DI hold time
6
tCLKl
-
tCLKp
7
tCLKSethl
tCLKSetlh
tDIset
3
11
12
tDIHold
40
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. See Figure 4 on page 12
11
4530C–BCD–11/03
Figure 4. Serial Interface Timing with Chart Numbers
1
2
CS
DO
9
CS
4
7
CLK
5
3
6
8
DI
11
CLK
10
12
DO
Inputs DI, CLK, CS: High level = 0.7 × VCC, low level = 0.3 × VCC
Output DO: High level = 0.8 × VCC, low level = 0.2 × VCC
12
T6818/T6828
4530C–BCD–11/03
T6818/T6828
Application Circuit
VCC
U5021M
Enable
Watchdog
VS
O
C
S
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
BYT41D
3
VS
n. n.
u. u.
n. n. n. n. n. n.
u. u. u. u. u. u.
VBatt
+
Input register
Output register
13 V
Serial interface
Charge
pump
n. n. n. n. n. n.
u. u. u. u. u. u.
DI
P
S
F
S
C
D
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
O
P
L
T
P
5
6
CLK
CS
VCC
UV
4
Fault
detect
Fault
detect
Fault
detect
protection
VCC
11
INH
VCC
10
Control
logic
5 V
+
Power-on
reset
DO
1
GND
9
7
GND
Fault
detect
Fault
detect
Fault
detect
8
Thermal
GND
protection
14
GND
2
12
OUT2
13
OUT1
OUT3
VCC
M
M
Application Notes
It is strongly recommended to connect the blocking capacitors at VCC and VS as close as
possible to the power supply and GND pins.
Recommended value for capacitors at VS:
Electrolytic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. Value
for electrolytic capacitor depends on external loads, conducted interferences and
reverse conducting current IOut1,2,3 (see “Absolute Maximum Ratings” on page 7).
Recommended value for capacitors at VCC
:
Electrolytic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF.
To reduce thermal resistance it is recommended to place cooling areas on the PCB as
close as possible to the GND pins.
Negative spikes at the output pins (e.g. negative spikes caused by an inductive load
switched off with a high side driver) may activate the overtemperature protection func-
tion of the T6818/T6828. In this condition, all outputs will be switched off simultaneously.
If this behavior is not acceptable or compatible with your application functionally, it is
necessary, that for switching on required outputs again, the SRR bit (Status Register
Reset) is set, to ensure a reset of the overtemperature function.
13
4530C–BCD–11/03
Ordering Information
Extended Type Number
Package
SO14
Remarks
T6818-TUS
Power package, tubed
T6818-TUQ
SO14
Power package, taped and reeled
Power package with heat slug, tubed
Power package with heat slug, taped and reeled
T6828-TUS
SO14
T6828-TUQ
SO14
Package Information
5.2
4.8
Package SO14
Dimensions in mm
8.75
7.62
3.7
1.4
0.25
0.2
0.4
3.8
0.10
1.27
6.15
5.85
14
8
technical drawings
according to DIN
specifications
1
7
14
T6818/T6828
4530C–BCD–11/03
T6818/T6828
15
4530C–BCD–11/03
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Regional Headquarters
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
Literature Requests
www.atmel.com/literature
Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard
warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any
errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and
does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are
granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use
as critical components in life support devices or systems.
© Atmel Corporation 2003. All rights reserved.
Atmel® and combinations thereof are the registered trademarks of Atmel Corporation or its subsidiaries.
Other terms and product names may be the trademarks of others.
Printed on recycled paper.
4530C–BCD–11/03
相关型号：
©2020 ICPDF网 联系我们和版权申明