TH7422BVWOSNGS [ATMEL]
Analog Circuit, 1 Func, CQCC84, CERAMIC, J LEAD PACKAGE-84;型号: | TH7422BVWOSNGS |
厂家: | ATMEL |
描述: | Analog Circuit, 1 Func, CQCC84, CERAMIC, J LEAD PACKAGE-84 |
文件: | 总20页 (文件大小:1116K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TH7422B
NEAR INFRARED InGaAs LINEAR SENSOR
300 PIXELS
DESCRIPTION
This device is based on a 300 InGaAs photodiode linear
array, with a 26µm pitch, using an in line pixel layout.
Two 150:1 CCD multiplexors chips, offering memory and
delayed readout capability, are hybridized on both sides of
the photodiode array so as to build a complete module.
Specially designed to allow an accurate butting, those mo-
dules could be tied together on request so as to provide an
array extension with only one dead pixel at the splice.
This device is also available in a full CMOS interface ver-
sion : TH 74KA22B or TH 74KB22B.
APPLICATIONS
MAIN FEATURES
n Suited for spectroscopy application
n NIR multichannel spectroscopy
n Fluorescence free Raman spectrophotometry
n On-line inspection and monitoring
n Pollution and environment monitoring
n Food analysis
n Near infrared spectral response: 0.8µm to 1.7µm
n Room temperature operation
n Low noise
n High detectivity, low cross talk
n High linearity, high Modulation Transfer Function (MTF)
n High output data rate : up to 6 MHz
n Intrinsic antiblooming
n Biomedical analysis
n Built in thermoelectric cooler and temperature sensor
available
n Accurate mechanical indexes (ready to mount)
SELECTION GUIDE
NUMBER OF
VIDEO OUTPUTS
REFERENCE
PIXEL COUNT
LAYOUT
PIXEL AREA
PITCH
TH7422B
TH7423A
TH7424A
TH7425A
299
150
150
150
In line
In line
In line
In line
20x100µm²
38x300µm²
38x500µm²
38x900µm²
26µm
52µm
52µm
52µm
2
1
1
2
March 1998
1/20
TH7422B
GEOMETRICAL CHARACTERISTICS
ELEMENT BLOCK DIAGRAM
2/20
TH7422B
ABSOLUTE MAXIMUM RATINGS
Supply voltages (compare to Vss, at any pin)
Transient voltages (compare to Vss, at any pin)
DC current (at any pin),
0 to +20V
0 to +25V
10mA
Except
except
- thermoelectric cooler pins
- temperature sensor
6A
+/-3mA
Operating temperature (temperature variation limited to 6°C/min)
Storage temperature (temperature variation limited to 6°C/min)
Electrostatic discharge sensitivity, MIL-STD-883 method 3015
-40 to +85°C
-40 to +85°C
device Class 1
Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent devices failure. Functionality at
or above these limits is not implied. Exposure to maximum ratings for extended periods may affect device reliability.
To avoid any performance degradation,the device must be handled with grounded bracelet and stored in the conductive
packing used for shipment.
TABLE 1 - ELECTRO-OPTICAL CHARACTERISTICS
15°C internal operating temperature, 3ms integration time, typical voltage input (otherwise specified).
TH 7422B
Parameter
Symbol
Unit
Remarks
Min.
Typ.
Max.
Dark voltage signal
mean
V
10
mV
mV
pA
See Fig. 6
D
isolated pixels
(photodiode dark current)
100
( I )
0.6
See note (1)
D
Noise in darkness
(rms)
mean
200
µV
mV
σV
D
isolated pixels
1
Absolute photo response
mean
R
33
1
Vcm²/µJ
See Fig. 3-4-5
non uniformity
PRNU
+/-10
1.73
0.73
%
%
non linearity over 1.5V range
Spectral response
Cut-off wavelength
Temperature shift
lc
dλc/dT
1.66
1.68
1.1
µm
nm/°C
At 50% R(l) max
Modulation transfer function
along array
At 19.2 lp/mm
See note (2)
MTF
Vsat
0.55
2.5
0.68
Output saturation voltage
V
Depends on preload
level. See Fig. 7
NEP
D*
0.4
40
2
fW
fW
BW=1Hz
Noise equivalent power at λ=1.65µm
BW=167Hz
BW=167Hz
-2
nWcm
12
1/2 -1
W BW=1Hz
8.10
cmHz
cmHz
Specific detectivity at λ=1.65µm
12
1/2 -1
W BW=167Hz
1.5.10
Electron to voltage conversion factor
Quantum efficiency
Fc
QE
0.26
0.8
µV/e
e/ph
See Fig. 5
Image grade
J
K
O
E
1
5
10
NA
See note (3)
(number of blemishes)
Electrical sample
-19
Note : 1 Already taken into account in mean V (V = Id TI Fc ; TI=Integration time ; q = 1.6 10
C)
D
D
q
Note : 2 “Maximum value” is the theoretical value computed using the corresponding diode size
Note : 3 a pixel is considered as a blemish if :
- its dark voltage is higher than isolated pixel max value
- its noise is higher than isolated pixel noise max value
- its PRNU is higher than +/- 10 %
or
or
3/20
TH7422B
TABLE 2 - CONNECTION DIAGRAMS
EVEN
ODD
Mo- Sym-
Mo- Sym-
dule bol
#
Pin n°
Designation
Pin n°
Designation
dule bol
#
1...2
NC
Not connected
44...51
TC+ Thermoelectric cooler (positive node)
see notes (2) (3)
3...6
7...9
10
TS
Temperature sensor see note (3)
Not connected
52...55
56
NC
Not connected
NC
O
O
O
O
O
O
O
VG1 Lateral skimming gate bias
DNC Do not connect see note (4)
NC Not connected
57
Photodiode lateral transfer clock
Electrical injection clock
φX
11...14
15
58
φPL
E
E
E
E
VDD Output amplifier drain & RE
VOS Video output signal (pixels 0-298)
GND Video ground
59
VGL1 Preload skimming gate bias
VGL2 Preload storage gate bias
16
60
17
61
Shift register clock 2 (gated by RE)
φL2
18
VSS CCD substrate bias (phases return)
62
RE
Read enable control signal
(pixels 1-299)
19
20
E
E
CCD reset clock
63
64
O
O
Shift register clock 1
φR
φL1
VDR Reset bias
VN
Photodiode substrate bias
see note (1)
21
22
E
E
VGS Output gate bias
65
66
O
O
VGS Output gate bias
VDR Reset bias
VN
Photodiode substrate bias see
note (1)
23
24
E
E
Shift register clock 1
67
68
O
O
CCD reset clock
φL1
φR
RE
Read enable control signal
(pixels 0-298)
VSS CCD substrate bias (phases return)
25
26
E
E
E
E
E
E
Shift register clock 2 (gated by RE)
69
70
O
O
O
GND Video ground
φL2
VGL2 Preload storage gate bias
VGL1 Preload skimming gate bias
VOS Video output signal (pixels 1-299)
VDD Output amplifier drain & RE supplies
27
71
28
Electrical injection clock
72...75
76
NC
Not connected
φPL
φX
29
Photodiode lateral transfer clock
DNC Do not connect see note (4)
30
VG1 Lateral skimming gate bias
NC Not connected
77...79
80...83
NC
TS
NC
Not connected
31...34
35...42
Temperature sensor see note (3)
Not connected
TC- Thermoelectric cooler (negative node) 84
see notes (2) (3)
43
NC
Not connected
Note : 1 Pin 22 and 64 are internally connected together
Note : 2 In each group every pins must be connected and tied together in order to lower pin current density
Note : 3 Not connected on non cooled package
Note : 4 DNC (Do Not Connect). Pins which are internally connected and must not be used.
4/20
TH7422B
PIN DESCRIPTION
Odd and Even channels are fully independent, therefore same pin function will be found on odd and even sides.
This is the preload injection stage electrical input. Each Φ
pulse down overfills preload storage capacitance with
PL
PL
electrons. Φ
is connected to a diode cathode which anode is internally tied to Vss.
PL
V
V
This is the preload stage skimming gate. Its bias determines the voltage up to which preload storage capacitance
will be biased. Thus it drives preload level.
GL1
GL2
L1
This is the storage capacitance grid bias. It determines the bottom voltage of preload storing well, while V
deter-
GL1
mines its top level. Preload capacitance thus is charged up proportionately to (V
- V
) bias difference.
GL2
GL1
This is the main register storage grid clock. Charges are stored under Φ
when transfer is disabled (RE at low le-
L1
vel). Φ is also used for lateral transfers to input nodes.
L1
This is the main register transfer grid clock. Φ is used to isolate Φ content during lateral transfers. The main re-
L2
L2
L1
gister is beginning and ending with Φ
which therefore controls main register access and outputs. Φ
is gated by
L2
L2
RE input, it is internally pulled down when RE is low, preventing transfers, preload injection, read out and isolating
each Φ well.
L1
RE
This is the “Read Enable” input. When high, it allows Φ
input connection to main register, when low, main register
L2
corresponding grids are pulled down whatever Φ
This input helps to serially read out two or more multiplexors with one single Φ
input level is.
L2
signal for all. Data are stored into
L2
the main register as long as RE is low, thus read out can occur later on.
This is the lateral transfer grid command. Lateral transfer is allowed when Φ is at high level. Φ is common to all
X
X
X
input nodes, all photodiode information is collected at the same time.
V
This is the lateral input stage skimming grid bias. This grid determines photodiodes reset bias, always the same
from integration time to integration time. After photodiode reset (input node capacitance reset) extra charges leading
G1
to overcrossing V
level are skimmed back into Φ main register wells.
G1
L1
V
V
This is the InGaAs photodiode common cathode bias. V is available on odd and even side, however, both pins are
N
N
connected together, to photodiode substrate.
This is main register output grid bias. It is used to isolate read out capacitance from main register. It allows charges
GS
to be read out when Φ is at low level.
L2
5/20
TH7422B
V
V
This is the read out capacitance reset bias. After each single read out, read out capacitance is cleared off (reset) to
level, during Φ clock high state.
DR
DD
V
DR
R
This is the output amplifier power supply (high side). It also supplies the “Read Enable” switching device which ex-
plains that I is different whether RE is at high or low level.
DD
G
This is the output amplifier low side power supply. G
is linked to V
through a diode, G
being the cathode
ND
ND
ND
SS
node. Thus G
must always be more positive than or equal to Vss.
ND
It must be noticed that “RE” switching device is powered from V
to V . G
is specific to output amplifier.
ND
DD
SS
V
V
This is the amplifier output.
OS
SS
S
This is the CCD multiplexor substrate bias. All applied biases and clock levels must be more positive or equal to V
.
SS
T
These are the internal temperature sensor connections. Temperature sensor is floating with respect to all other pin
connections. Pins 3 to 6 are internally connected together as well as pin 80 to 83.
TC+ This is the internal thermoelectric cooler positive input (current enters) (all pins must be externally connected in or-
der to lower current density into each pin).
TC-
This is the internal thermoelectric cooler negative input (current goes out). Thermoelectric cooler connections are
floating, with respect to all other pins. All pins must be externally connected in order to lower individual pin current
density. It is advised to avoid pulsed current regulations to drive TE cooler, since it may result in EMC troubleshoo-
ting inside component cavity.
FUNCTIONAL DESCRIPTION
Individual InGaAs diodes are reversed bias. The cathode node is common to all diodes and connected to a fixed potential
Vn. The anode of each diode is wire bonded to a lateral entrance of the readout CCD stage.
These diodes behave as capacitors whose leakage current depends on dark current and illumination. This current tends to
decrease the voltage across the capacitor. Each diode capacity is first preloaded with a calibrated amount of negative char-
ges (Qb). After an integration time (TI), the amount of removed charges (QI) figures out the cumulated light absorption. So
the measurement of the remaining charge amount (Qs) in the diode capacitor gives access to QI (QI = Qb - Qs). This is
called “Vidicon” readout mode.
CCD multiplexors fulfill all those operations. They provide preloading and readout functions for the separate odd and even
pixel groups. The main CCD features consist in a two phase register (φ and φ ) with longitudinal and lateral transfer ca-
L1
L2
pability. Following is a description of how those devices keep photodiodes under control and capture pixel signals.
Four main functions can be considered :
- Preload
The potential gap between the two gates [V
and spilling occurs using an injection diode φ
-V
] defines a potential well for preload calibration (Qb), its filling
GL1 GL2
.
PL
- Main register charge handling
At each individual transfer step, Qs moves out of the 150th stage, while Qb moves in the first stage. The longitudinal
register stage requires a series of at least 150 steps to complete the preloading cycle. This transfer operation is inhi-
bited if RE (read enable) input is maintained at a low level.
- Photodiode information collection (and reset)
The lateral input stage consists in 150 input diodes, each of them directly wire bonded to one photodiode, and con-
trolled under a single common biasing gate V
and a lateral transfer gate φ .
G1
x
At the end of integration time (see timing diagram Figure 1) :
- the preload charges Qb, stored in the register, are transferred simultaneously to the 150 photodiodes when φ is at
x
high level and φ at low level, allowing the photodiode reset.
L1
- charges in excess (identifies as Qs) are collected back to the register by forcing φ at high level. At this step the
L1
register current information is the mirror image of the collected photo signal and, all photodiodes are reseted while a
new TI starts.
To isolate each stage from the other one, φ must be at low level during all lateral transfer operations.
L2
- Data read-out
At the end of the photodiode reset operation :
- if RE is forced to low level (Timing Diagram - Figure 1), all Qs information remain stored in the register and so, rea-
dout is delayed .According to this situation a next photodiode reset procedure can’t be operated until the full longitu-
dinal transfer takes place (150 steps minimum).
6/20
TH7422B
- if RE is activated or always at high level (Timing Diagram Figure 2), each stored charge is transferred to the rea-
dout capacitance; this continuous readout mode is recommended for long integration time.
Qs conversion into voltage is supported by the readout stage capacitance, linked to a low output impedance ampli-
fier. This capacitance is reset at V
bias, before each pixel readout operation (high level φ ).
DR
R
Due to the “Vidicon” read out mode, Qb level needs adjustment so as to provide enough carriers to sustain photocurrent
and dark current during the integration time. Pixel antiblooming is also resulting from “Vidicon mode” since photodiodes
cannot consume more electrons than Qb.
Antismearing (frame to frame antiblooming) efficiency depends on the photodiode reset conditions, reverse bias recovering
need a minimum Qb condition such as :
Qb>Clat .V
D
where : - Clat is the individual lateral input node capacitance, Clat ~1.8 pF (including photodiode, bonding pads...)
where : - V is the photodiode bias : V = V - 0.78V - 8.7
D
D
N
G1
7/20
TH7422B
MULTIPLEXOR TIMING DIAGRAM
* First Even output data is always at preload level (multiplexor corresponding input is not connected — See “Element Block Diagram”)
8/20
TH7422B
Note
TABLE 3 - STATIC CHARACTERISTICS
Pin n°
Symbol
Function
Value
Unit
EVEN/ODD
Min
Typ
Max
V
15/71
Output amplifier
17.5
18
18.5
V
(1)
(2)
DD
DD
I
with Read Enable disabled
with Read Enable activated
0.7
1.1
mA
mA
V
20/66
Reset bias
15.3
11
15.5
11.3
16.5
11.5
V
V
(1)
DR
V
22/64
internally connected
Photodiode substrate bias
N
G
V
V
17/69
18/68
30/56
27/59
26/60
21/65
Video ground
0
2
V
V
V
V
V
V
(3)
ND
SS
G1
Register substrate
Lateral skimming gate
Preload skimming gate
Preload storage gate
Register output gate
1.9
2.8
3
2
3
2.1
5
V
V
(4)
(4)
GL1
GL2
4
5
V
6.2
6.5
7
GS
Note : 1 V
-V
> 1.8V
Note : 2 For each V Pin
DD DR
DD
Note : 3 Recommendation: tied to VSS or, for best operation, hold at +0.5V above V
Note : 4 V
GL1
Note : 4 to get V
SS
and V
GL1
are used to calibrate preloading level see Fig. 7; to minimise noise effect, it is recommended
from the same low noise supply.
GL2
GL2
and V
TABLE 4 - DYNAMIC CHARACTERISTICS
Pin n°
Symbol
Function
Value
Typ
Unit
Note
EVEN/ODD
Min
Max
23/63
25/61
28/58
19/67
29/57
24/62
Longitudinal transfer stage
(120 pF typical)
0.1
9
0.3
9.5
0.7
V
V
Φ
Φ
Φ
Φ
Φ
low
L1
L2
PL
R
10.5
high
(120 pF typical if all RE enabled)
0.1
9
0.3
9.5
0.7
10.5
V
V
low
high
Preload injection diode
(10 pF typ.)
5.8
9.5
6
12
6.7
12.5
V
V
low
high
Read out reset gate
(10 pF typ.)
0.1
11.5
0.3
12
0.7
12.5
V
V
low
high
Lateral transfer stage
(10 pF typ.)
0.1
7.8
0.3
8
0.7
8.2
V
V
low
high
X
Read enable
(15 pF typ.)
0.1
0.2
0.4
15
V
V
RE low
high
(Φ
high
L2
+2,5V)
TABLE 5 - MISCELLANEOUS DATA
Value
Typ
3
Symbol
Pin n°
Function
Thermo cooler
Unit
Note
Min
Max
I
35 to 42
44 to 51
16,70
6
A
(5)
TH
V
Video signal DC level (wrt Vss)
Output impedance
12
1.2
100
V
KΩ
Ω
(7)
(7)
(6)
OS(DC)
Z
O
Rpt
(at 0°C)
3 to 6
80 to 83
Temperature sensor resistance
(recommended max. current 1 mA)
F
Transfer frequency
0.5
3
MHz
P
Note : 5 See Fig. 8a, 8b, 8c, 8d.
Note : 6 See Fig. 9.
Note : 7 Short circuit to Gnd or Vss exceeding 1 min duration may permanently damage the device
9/20
TH7422B
TABLE 6 - TIMING AND SWITCHING CHARACTERISTICS
Parameter
Symbol
Value
Typ.
3
Unit
Note
Min.
0.05
0.33
Max.
INTEGRATION TIME
CLOCK PERIOD
TI
ms
µs
Tck
2
(3)
(4)
READ ENABLE
Duration
TRE
tr/tf
149.5Tck+t1 +t2
25
µs
ns
ns
RE RE
Rise time or fall time
Delay
250
t1RE
0
150
5
120
Set-up RE
t2RE
850
ns
LATERAL TRANSFER
Duration
22
25
µs
ns
µs
µs
ns
TΦx
tr/tf
150
(4)
Φx rise time or fall time
Φ1 low level hold time
Φ2 low level hold time
Delay
Tx1
Tx2
1
4
1.7
20
100
980
tΦx
Readout delay
100
200
ns
tΦ1
LONGITUDINAL TRANSFER
ΦL1 rise time or fall time
tr/tf
tr/tf
25
25
150
150
ns
ns
ns
ns
ns
(4)
(4)
ΦL2 rise time or fall time
Preload duration
35
240
25
TΦPL
tr/tf
Preload rise time or fall time
Preload delay
50
(4)
(1)
tPL
0
80
Skimming time
tsk
70
500
ns
READOUT DIODE RESET
Duration
35
0
240
25
ns
ns
ns
(2)
(4)
(2)
TΦR
tr/tf
tR
Rise time or fall time
Delay
120
10
VIDEO SIGNAL SET-UP TIME
t
100
ns
video
Note : 1 Better if no clock transition occurs during “tsk” time.
Note : 2 tR + TΦR < ΦL2 high level duration.
Note : 3 Duty cycle: 50%
Note : 4 Rise time (tr) and fall time (tf) specified between 10% and 90%
10/20
TH7422B
ELECTRO-OPTICAL TYPICAL CHARACTERISTICS
Figure 3 : Silicon Window typical spectral response
Figure 4 : Clear window typical spectral response
Figure 5 : Clear window & Silicon window quantum efficiency
Figure 6 : Dark voltage per 1ms integration time
Figure 6 : vs internal operating temperature
Figure 7 : Typical preload voltage vs V
and V
gate voltages
GL2
GL1
11/20
TH7422B
THERMAL CHARACTERISTICS (single stage TE cooled package -subvariant N- only)
Figure 8a : Internal temperature vs.
Figure 8b : Internal to rear face temperature gap vs.
Figure 8a : Thermo-electric cooler current
Figure 8b : Thermo-electric cooler current
Figure 8c : Thermo-electric cooler voltage vs.
Figure 8c : Thermo-electric cooler current
Figure 8d : Rear face power dissipation vs.
Figure 8d : Thermo-electric cooler current
Figure 9 : Pt resistance variation R = R(T°C) - R(0°C) vs. temperature
-3
-3
-6
-6
2
2
-12
3
T°C<0
T°C>0
Rpt = 100 {1+[3.90802 10 T] - [0.580195 10 T ] - [4.7350 10 (T-100) T ]}
Rpt = 100 {1+[3.90802 10 T] - [0.580195 10 T ]}
12/20
TH7422B
OUTLINE DRAWING
In the standard version devices are hermetically sealed in a Jlead 84 like package with a near IR transparent window (see
next drawing). The package basement includes a thermoelectric cooler and a temperature sensor, see Figures 8-9 for ther-
mal characteristics.
Silicon, with an antireflective coating is the window material. An optional version used an AR coated glass and an additional
frame (numerical aperture f/3) to prevent parasitic lateral visible light.
The photodiode array location is mechanically indexed upon the package rear face (opposite to the window) for fast accu-
rate mounting.
PACKAGE VARIANT (N)
(Thermoelectric cooler version)
13/20
TH7422B
ORDERING INFORMATION
T
H
7
4
2
2
B
V(1) W(2) a*
b*
c*
G
d*
(1) Temperature range
V = -40 to 85°C (see § c*)
(2) Package family
Ceramic Jlead type
a* Image grade
J, K, O, E see Table 1
b* Package variant
S = standard silicon window
R = clear glass window
N = non sealed removable window
c* Package sub-variant
(The detector temperature depends on the surrounding ambient and on device energy budget which is directly
related to the built in thermo-cooler option efficiency.)
-
=
=
without thermo-electric cooler; from -40 to +15°C full performances(derated over)
1 stage thermo-electric cooler; from -40 to +60°C full performances (derated over)
N
P = 3 stages thermo-electric cooler; from -40 to +85°C full performances
d* Quality level
- = standard
D/T = industrial level
B/T = military levels
S = space level
14/20
TH7422B
APPLICATION INFORMATION
- Preload generation
Preload is fed up when Φ is at low level. This process needs few time to be completed ( > 35 ns). Then skimming is nee-
PL
ded to calibrate Qb. This step needs as much as possible time. Therefore it is recommended to activate Φ
as soon as
PL
Φ
is at low level, in order to spend most of Φ low level duration for skimming.
L2
L2
Qb depends on (V
- V
) difference, thus noise on Qb may result from differential fluctuations between V
and V
.
GL2
GL2
GL1
GL1
It is therefore recommended to get V
and V
biases on each side (Odd or Even) from the same power supply line.
GL1
GL2
- Preload level adjustment
Preload level must be chosen so as to covered both expected maximum signal and dark current resulting signal. It must be noti-
ced that the “Vidicon mode” implies output signal has the largest amplitude in darkness (since most of Qb is to be readout).
Since output signal treatment difficulty may arise from its large amplitude it is better to reduce as much as possible its dyna-
mic, thus to reduce preload level to the minimum required.
From Figure 6, dark voltage can be deduced, photosignal is computed from Figures 3 & 4 and application data (light flux, in-
tegration time). Preload must be 200 mV in excess to dark voltage and maximum photosignal sum. Preload can be adjusted
with (V
- V
) biases, as indicated in Figure 7, however it is recommended to act first on V
. Direct read out of pre-
GL2
GL1
GL2
load level is possible in forcing Φ at low level avoiding lateral transfer and photodiode read out.
X
7
TH7422B maximum preload is about 2.5 V (corresponding to 10 electrons).
- Photodiode information collection
As explained this operation needs two steps :
a). Qb injection into input nodes.
b). Skimming back into main register of extra charges.
Step a) needs at least 1 µs to be completed (TX1). However, step b) is a longer process, which duration influences lateral
transfer efficiency. It has been measured that 20 µs is needed for less than 1 % transfer non efficiency which raises to 2 %
for 4 µs skimming time (TX2).
Thus it is recommended to allow as long as possible skimming time, compatible with application requirement.
- Output signal format
Figures 1 and 2 give details on output signal. Each reset (Φ ) pulse pulls up the output at reset level related to VDR bias.
R
Using typical biases, reset level reaches about 12 volts with respect to Vss. Notice that Φ must be pulsed only when Φ
R
L2
is at high level.
Just after reset pulse, output level is stabilizing to a steady level called “floating diode level”. This level is the very reset level
to be taken into account for useful signal amplitude measurement. It is about 200 mV lower than reset level.
Then on Φ falling edge, charges coming from main register last stage arrive. Consequently, output signal drops down.
L2
The new steady level reached, counted from “floating diode” level represents the useful information - Uos -
Uos amplitude is maximum when no lateral transfer has occurred, since it represents preload level. In darkness, after pho-
todiode read out (lateral transfer) Uos is reduced by dark voltage signal. Under illumination Uos is still smaller until satura-
tion occurs (whole preload consumption), in this situation “floating diode” level is maintained until next pixel readout.
- Read enable operation
RE input simplifies device operation since it allows to use continuous Φ clocks. However, one can force RE at high level
L2
and generate external Φ interruption during Φ transfer. In this case, first pixel data will be read out at first falling edge of
L2
X
st
Φ
. After 150 Φ periods all pixel data will have been read out, on 151
Φ
period, output will be unused preload and so
L2
L2
L2
on until next Φ cycle.
X
When using RE input, it must be noticed that RE duration must at least allow 150 main register transfers (Φ periods) in
L2
order to guaranty that all main register stages contain a preload (Qb) before next Φ cycle. Otherwise all photodiodes will
X
not be properly reset at next Φ cycle.
X
When RE is low, output signal is continuously at floating diode level, with Φ transparencies.
R
- Interlacing odd even
As odd and even sides are fully separated, it is possible to drive odd and even side with 180° phase shifted Φ and Φ
L1
L2
(Φ , Φ with same phase with respect to their Φ ), Φ being identicals.In this manner Odd output signals will be delayed
PL
R
L2
X
by half a Tck period with respect to Even outputs allowing, after common sampling, natural multiplexing and double pixel
data rate. This opportunity is presented in application hints (Figures 10 to 12).
- Mechanical mounting
Accurate mechanical references are provided in N and P subvariant packages (see ordering information and outline drawings).
If optics are mechanically referred to these packages rear face, no tuning strategy could be implemented for scale manufacturing.
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TH7422B
APPLICATION HINTS
Figure 10 : Application hint : device operation
16/20
TH7422B
Figure 11 : Application hint : signal treatment
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TH7422B
Figure 12 : Timing diagramm for fig 10 &11 (Output data : 1 MHz)
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TH7422B
NOTE
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TH7422B
Information furnished is believed to be accurate and reliable. However THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES
assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. THOMSON-CSF
SEMICONDUCTEURS SPECIFIQUES products are not authorized for use as critical components in life support devices or
systems without express written approval from THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES.
CSF SEMICONDUCTEURS SPECIFIQUES - Printed in France - All rights reserved.
1998 THOMSON-
This product is manufactured by THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES - 38521 SAINT-EGREVE / FRANCE.
For further information please contact : THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES - Route Départementale
128 - B.P. 46 - 91401 ORSAY Cedex / FRANCE - Tél. : (33)(0) 1.69.33.00.00 / Téléfax : (33)(0) 1.69.33.03.21.
E-mail : lafrique@tcs.thomson.fr - Internet : http://www.tcs.thomson-csf.com
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