TS80C31X2-MCE [ATMEL]

8-bit CMOS Microcontroller ROMless; 8位CMOS微控制器无ROM
TS80C31X2-MCE
型号: TS80C31X2-MCE
厂家: ATMEL    ATMEL
描述:

8-bit CMOS Microcontroller ROMless
8位CMOS微控制器无ROM

微控制器和处理器 外围集成电路 异步传输模式 ATM 时钟
文件: 总42页 (文件大小:368K)
中文:  中文翻译
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Features  
80C31 Compatible  
8031 pin and instruction compatible  
Four 8-bit I/O ports  
Two 16-bit timer/counters  
128 bytes scratchpad RAM  
High-Speed Architecture  
40 MHz @ 5V, 30MHz @ 3V  
X2 Speed Improvement capability (6 clocks/machine cycle)  
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to 60 MHz @ 5V, 40 MHz @ 3V)  
Dual Data Pointer  
8-bit CMOS  
Microcontroller  
ROMless  
Asynchronous port reset  
Interrupt Structure with  
5 Interrupt sources,  
4 priority level interrupt system  
Full duplex Enhanced UART  
Framing error detection  
TS80C31X2  
AT80C31X2  
Automatic address recognition  
Power Control modes  
Idle mode  
Power-down mode  
Power-off Flag  
Once mode (On-chip Emulation)  
Power supply: 4.5-5.5V, 2.7-5.5V  
Temperature ranges: Commercial (0 to 70oC) and Industrial (-40 to 85oC)  
Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1 (13.9 footprint)  
1. Description  
TS80C31X2 is high performance CMOS and ROMless versions of the 80C51 CMOS  
single chip 8-bit microcontroller.  
The TS80C31X2 retains all features of the TSC80C31 with 128 bytes of internal RAM,  
a 5-source, 4 priority level interrupt system, an on-chip oscilator and two  
timer/counters.  
In addition, the TS80C31X2 has a dual data pointer, a more versatile serial channel  
that facilitates multiprocessor communication (EUART) and a X2 speed improvement  
mechanism.  
The fully static design of the TS80C31X2 allows to reduce system power consumption  
by bringing the clock frequency down to any value, even DC, without loss of data.  
The TS80C31X2 has 2 software-selectable modes of reduced activity for further  
reduction in power consumption. In the idle mode the CPU is frozen while the timers,  
the serial port and the interrupt system are still operating. In the power-down mode the  
RAM is saved and all other functions are inoperative.  
4428E–8051–02/08  
2. Block Diagram  
(1) (1)  
XTAL1  
XTAL2  
RAM  
128x8  
EUART  
ALE/PROG  
PSEN  
C51  
CORE  
IB-bus  
CPU  
EA  
(1)  
(1)  
Timer 0  
Timer 1  
INT  
Ctrl  
Parallel I/O Ports & Ext. Bus  
RD  
Port 0Port 1  
Port 3  
Port 2  
WR  
(1) (1)  
(1) (1)  
(1): Alternate function of Port 3  
2
AT/TS80C31X2  
4428E–8051–02/08  
AT/TS80C31X2  
4. SFR Mapping  
The Special Function Registers (SFRs) of the TS80C31X2 fall into the following categories:  
• C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1  
• I/O port registers: P0, P1, P2, P3  
• Timer registers: TCON, TH0, TH1, TMOD, TL0, TL1  
• Serial I/O port registers: SADDR, SADEN, SBUF, SCON  
• Power and clock control registers: PCON  
• Interrupt system registers: IE, IP, IPH  
• Others: CKCON  
Table 4-1.  
All SFRs with their address and their reset value  
Bit  
addressable  
Non Bit addressable  
0/8  
1/9  
2/A  
3/B  
4/C  
5/D  
6/E  
7/F  
F8h  
F0h  
E8h  
E0h  
D8h  
D0h  
C8h  
C0h  
FFh  
F7h  
EFh  
E7h  
DFh  
D7h  
CFh  
C7h  
B
0000 0000  
ACC  
0000 0000  
PSW  
0000 0000  
IP  
SADEN  
B8h  
B0h  
A8h  
A0h  
98h  
90h  
88h  
80h  
BFh  
B7h  
AFh  
A7h  
9Fh  
97h  
8Fh  
87h  
XXX0 0000  
0000 0000  
P3  
IPH  
XXX0 0000  
1111 1111  
IE  
SADDR  
0XX0 0000  
0000 0000  
P2  
AUXR1  
1111 1111  
XXXX XXX0  
SCON  
SBUF  
0000 0000  
XXXX XXXX  
P1  
1111 1111  
TCON  
TMOD  
TL0  
TL1  
TH0  
TH1  
CKCON  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
XXXX XXX0  
P0  
PCON  
SP  
DPL  
DPH  
0000 0111  
0000 0000  
0000 0000  
1111 1111  
00X1 0000  
0/8  
1/9  
2/A  
3/B  
4/C  
5/D  
6/E  
7/F  
Reserved  
3
4428E–8051–02/08  
5. Pin Configuration  
P1.0 / T2  
40  
39  
38  
1
2
VCC  
P0.0 / A0  
P0.1 / A1  
P1.1 / T2EX  
P1.2  
3
4
P1.3  
37 P0.2 / A2  
P0.3 / A3  
36  
P0.4 / A4  
P1.4  
P1.5  
5
35  
6
7
8
6
5 4 3 2 1  
44 43 42 41 40  
P0.5 / A5  
34  
P1.6  
P1.5  
P1.6  
39  
38  
7
8
P0.4/AD4  
P0.5/AD5  
P0.6/AD6  
P0.7/AD7  
EA  
P0.6 / A6  
P0.7 / A7  
33  
32  
31  
30  
P1.7  
RST  
9
P1.7  
37  
36  
9
EA/VPP  
ALE/PROG  
PSEN  
P3.0/RxD 10  
RST  
10  
PDIL/  
P3.1/TxD  
11  
P3.0/RxD  
NIC*  
11  
12  
13  
35  
34  
33  
12  
P3.2/INT0  
29  
28  
27  
26  
CDIL40  
NIC*  
PLCC44  
P2.7 / A15  
P2.6 / A14  
P3.3/INT1 13  
P3.1/TxD  
P3.2/INT0  
P3.3/INT1  
P3.4/T0  
P3.5/T1  
ALE  
14  
15  
16  
P3.4/T0  
P3.5/T1  
P3.6/WR  
14  
15  
16  
32  
31  
30  
PSEN  
P2.5 / A13  
P2.7/A15  
P2.6/A14  
P2.5/A13  
P2.4 / A12  
P2.3 / A11  
25  
17  
18  
19  
20  
24  
23  
22  
21  
P3.7/RD  
XTAL2  
17  
29  
P2.2 / A10  
P2.1 / A9  
P2.0 / A8  
18 19 20 21 22 23 24 25 26 27 28  
XTAL1  
VSS  
44 43 42 41 40 39 38 37 36 35 34  
P1.5  
P1.6  
P0.4/AD4  
P0.5/AD5  
P0.6/AD6  
P0.7/AD7  
EA  
33  
1
2
32  
31  
P1.7  
3
4
30  
29  
28  
27  
RST  
P3.0/RxD  
NIC*  
5
6
PQFP44  
VQFP44  
NIC*  
P3.1/TxD  
P3.2/INT0  
P3.3/INT1  
P3.4/T0  
P3.5/T1  
ALE  
7
8
26  
25  
24  
23  
PSEN  
P2.7/A15  
P2.6/A14  
P2.5/A13  
9
10  
11  
12 13 14 15 16 17 18 19 20 21 22  
*NIC: No Internal Connection  
4
AT/TS80C31X2  
4428E–8051–02/08  
AT/TS80C31X2  
Pin Number  
Mnemonic  
VSS  
DIL  
LCC  
22  
VQFP 1.4  
Type  
Name And Function  
20  
16  
39  
I
I
Ground: 0V reference  
Vss1  
VCC  
1
Optional Ground: Contact the Sales Office for ground connection.  
Power Supply: This is the power supply voltage for normal, idle and power-down  
operation  
40  
44  
38  
I
39-  
32  
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written  
to them float and can be used as high impedance inputs. Port 0 pins must be  
polarized to Vcc or Vss in order to prevent any parasitic current consumption. Port 0  
is also the multiplexed low-order address and data bus during access to external  
program and data memory. In this application, it uses strong internal pull-up when  
emitting 1s.  
P0.0-P0.7  
43-36  
37-30  
I/O  
P1.0-P1.7  
P2.0-P2.7  
1-8  
2-9  
40-44  
1-3  
I/O  
I/O  
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that  
have 1s written to them are pulled high by the internal pull-ups and can be used as  
inputs. As inputs, Port 1 pins that are externally pulled low will source current  
because of the internal pull-ups.  
21-  
28  
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that  
have 1s written to them are pulled high by the internal pull-ups and can be used as  
inputs. As inputs, Port 2 pins that are externally pulled low will source current  
because of the internal pull-ups. Port 2 emits the high-order address byte during  
fetches from external program memory and during accesses to external data  
memory that use 16-bit addresses (MOVX @DPTR).In this application, it uses  
strong internal pull-ups emitting 1s. During accesses to external data memory that  
use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.  
24-31  
18-25  
10-  
17  
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that  
have 1s written to them are pulled high by the internal pull-ups and can be used as  
inputs. As inputs, Port 3 pins that are externally pulled low will source current  
because of the internal pull-ups. Port 3 also serves the special features of the  
80C51 family, as listed below.  
P3.0-P3.7  
11,  
5,  
I/O  
13-19  
7-13  
10  
11  
12  
13  
14  
15  
16  
17  
9
11  
13  
14  
15  
16  
17  
18  
19  
10  
5
7
I
O
I
RXD (P3.0): Serial input port  
TXD (P3.1): Serial output port  
8
INT0 (P3.2): External interrupt 0  
INT1 (P3.3): External interrupt 1  
T0 (P3.4): Timer 0 external input  
T1 (P3.5): Timer 1 external input  
WR (P3.6): External data memory write strobe  
RD (P3.7): External data memory read strobe  
9
I
10  
11  
12  
13  
4
I
I
O
O
I
Reset  
ALE  
Reset: A high on this pin for two machine cycles while the oscillator is running,  
resets the device. An internal diffused resistor to VSS permits a power-on reset using  
only an external capacitor to VCC.  
30  
33  
27  
O (I)  
Address Latch Enable: Output pulse for latching the low byte of the address during  
an access to external memory. In normal operation, ALE is emitted at a constant  
rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external  
timing or clocking. Note that one ALE pulse is skipped during each access to  
external data memory.  
PSEN  
29  
32  
26  
O
Program Store ENable: The read strobe to external program memory. When  
executing code from the external program memory, PSEN is activated twice each  
machine cycle, except that two PSEN activations are skipped during each access to  
external data memory. PSEN is not activated during fetches from internal program  
memory.  
5
4428E–8051–02/08  
EA  
31  
19  
18  
35  
21  
20  
29  
15  
14  
I
I
External Access Enable: EA must be externally held low to enable the device to  
fetch code from external program memory locations.  
XTAL1  
XTAL2  
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock  
generator circuits.  
O
Crystal 2: Output from the inverting oscillator amplifier  
6
AT/TS80C31X2  
4428E–8051–02/08  
AT/TS80C31X2  
6. TS80C31X2 Enhanced Features  
In comparison to the original 80C31, the TS80C31X2 implements some new features, which  
are  
:
• The X2 option.  
• The Dual Data Pointer.  
• The 4 level interrupt priority system.  
• The power-off flag.  
• The ONCE mode.  
• Enhanced UART  
6.1  
X2 Feature  
The TS80C31X2 core needs only 6 clock periods per machine cycle. This feature called ”X2”  
provides the following advantages:  
• Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.  
• Save power consumption while keeping same CPU power (oscillator power saving).  
• Save power consumption by dividing dynamically operating frequency by 2 in operating and  
idle modes.  
• Increase CPU power by 2 while keeping same crystal frequency.  
In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 sig-  
nal and the main clock input of the core (phase generator). This divider may be disabled by  
software.  
6.1.1  
Description  
The clock for the whole circuit and peripheral is first divided by two before being used by the  
CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2  
mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to  
60%. Figure 6-1. shows the clock generation block diagram. X2 bit is validated on XTAL1÷2 ris-  
ing edge to avoid glitches when switching from X2 to STD mode. Figure 6-2. shows the mode  
switching waveforms.  
Figure 6-1. Clock Generation Diagram  
XTAL1:2  
2
state machine: 6 clock cycles.  
CPU control  
XTAL1  
0
1
FXTAL  
FOSC  
X2  
CKCON reg  
7
4428E–8051–02/08  
Figure 6-2. Mode Switching Waveforms  
XTAL1  
XTAL1:2  
X2 bit  
CPU clock  
STD Mode  
X2 Mode  
STD Mode  
The X2 bit in the CKCON register (See Table 6-1.) allows to switch from 12 clock cycles per  
instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD  
mode). Setting this bit activates the X2 feature (X2 mode).  
CAUTION  
In order to prevent any incorrect operation while operating in X2 mode, user must be aware that  
all peripherals using clock frequency as time reference (UART, timers) will have their time refer-  
ence divided by two. For example a free running timer generating an interrupt every 20 ms will  
then generate an interrupt every 10 ms. UART with 4800 baud rate will have 9600 baud rate.  
Table 6-1.  
CKCON Register  
CKCON - Clock Control Register (8Fh)  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
X2  
Bit  
Bit  
Number  
Mnemonic  
Description  
Reserved  
7
6
5
4
3
2
1
-
The value read from this bit is indeterminate. Do not set this bit.  
Reserved  
-
-
-
-
-
-
The value read from this bit is indeterminate. Do not set this bit.  
Reserved  
The value read from this bit is indeterminate. Do not set this bit.  
Reserved  
The value read from this bit is indeterminate. Do not set this bit.  
Reserved  
The value read from this bit is indeterminate. Do not set this bit.  
Reserved  
The value read from this bit is indeterminate. Do not set this bit.  
Reserved  
The value read from this bit is indeterminate. Do not set this bit.  
CPU and peripheral clock bit  
Clear to select 12 clock periods per machine cycle (STD mode, FOSC=FXTAL/2).  
Set to select 6 clock periods per machine cycle (X2 mode, FOSC=FXTAL).  
0
X2  
Reset Value = XXXX XXX0b  
Not bit addressable  
For further details on the X2 feature, please refer to ANM072 available on the web  
(http://www.atmel-wm.com)  
8
AT/TS80C31X2  
4428E–8051–02/08  
AT/TS80C31X2  
7. Dual Data Pointer Register Ddptr  
The additional data pointer can be used to speed up code execution and reduce code size in a  
number of ways.  
The dual DPTR structure is a way by which the chip will specify the address of an external data  
memory location. There are two 16-bit DPTR registers that address the external memory, and a  
single bit called  
DPS = AUXR1/bit0 (See Table 5.) that allows the program code to switch between them (Refer  
to Figure 7-1).  
Figure 7-1. Use of Dual Pointer  
External Data Memory  
7
0
DPS  
DPTR1  
DPTR0  
AUXR1(A2H)  
DPH(83H) DPL(82H)  
Table 7-1.  
AUXR1: Auxiliary Register 1  
7
-
6
5
-
4
-
3
-
2
-
1
-
0
-3  
DPS  
Bit  
Bit  
Number  
Mnemonic  
Description  
Reserved  
7
6
5
4
3
2
1
-
The value read from this bit is indeterminate. Do not set this bit.  
Reserved  
The value read from this bit is indeterminate. Do not set this bit.  
-
-
-
-
-
-
Reserved  
The value read from this bit is indeterminate. Do not set this bit.  
Reserved  
The value read from this bit is indeterminate. Do not set this bit.  
Reserved  
The value read from this bit is indeterminate. Do not set this bit.  
Reserved  
The value read from this bit is indeterminate. Do not set this bit.  
Reserved  
The value read from this bit is indeterminate. Do not set this bit.  
Data Pointer Selection  
Clear to select DPTR0.  
Set to select DPTR1.  
0
DPS  
Reset Value = XXXX XXX0  
Not bit addressable  
9
4428E–8051–02/08  
8. Application  
Software can take advantage of the additional data pointers to both increase speed and reduce  
code size, for example, block operations (copy, compare, search ...) are well served by using  
one data pointer as a ’source’ pointer and the other one as a "destination" pointer.  
ASSEMBLY LANGUAGE  
; Block move using dual data pointers  
; Destroys DPTR0, DPTR1, A and PSW  
; note: DPS exits opposite of entry state  
; unless an extra INC AUXR1 is added  
;
00A2  
AUXR1 EQU 0A2H  
;
0000 909000  
0003 05A2  
0005 90A000  
0008  
MOV DPTR,#SOURCE  
; address of SOURCE  
; switch data pointers  
; address of DEST  
INC  
AUXR1  
MOV DPTR,#DEST  
LOOP:  
0008 05A2  
000A E0  
000B A3  
000C 05A2  
000E F0  
000F A3  
0010 70F6  
0012 05A2  
INC  
AUXR1  
; switch data pointers  
MOVX A,@DPTR  
; get a byte from SOURCE  
; increment SOURCE address  
; switch data pointers  
INC  
INC  
DPTR  
AUXR1  
MOVX @DPTR,A  
; write the byte to DEST  
; increment DEST address  
; check for 0 terminator  
; (optional) restore DPS  
INC  
JNZ  
INC  
DPTR  
LOOP  
AUXR1  
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR.  
However, note that the INC instruction does not directly force the DPS bit to a particular state,  
but simply toggles it. In simple routines, such as the block move example, only the fact that DPS  
is toggled in the proper sequence matters, not its actual value. In other words, the block move  
routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruc-  
tion (INC AUXR1), the routine will exit with DPS in the opposite state.  
10  
AT/TS80C31X2  
4428E–8051–02/08  
AT/TS80C31X2  
9. TS80C31X2 Serial I/O Port  
The serial I/O port in the TS80C31X2 is compatible with the serial I/O port in the 80C31.  
It provides both synchronous and asynchronous communication modes. It operates as an Uni-  
versal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2  
and 3). Asynchronous transmission and reception can occur simultaneously and at different  
baud rates  
Serial I/O port includes the following enhancements:  
• Framing error detection  
• Automatic address recognition  
9.1  
Framing Error Detection  
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To  
enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 9-1).  
Figure 9-1. Framing Error Block Diagram  
SM0/FE SM1  
SM2  
REN  
TB8  
RB8  
TI  
RI  
SCON (98h)  
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)  
SM0 to UART mode control (SMOD = 0)  
PCON (87h)  
SMOD1 SMOD0  
-
POF  
GF1  
GF0  
PD  
IDL  
To UART framing error control  
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.  
An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by  
two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table  
9-3.) bit is set.  
Software may examine FE bit after each reception to check for data errors. Once set, only soft-  
ware or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear  
FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure 9-  
2. and Figure 9-3.).  
Figure 9-2. UART Timings in Mode 1  
RXD  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
Start  
bit  
Data byte  
Stop  
bit  
RI  
SMOD0=X  
FE  
SMOD0=1  
11  
4428E–8051–02/08  
Figure 9-3. UART Timings in Modes 2 and 3  
RXD  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
Start  
bit  
Data byte  
Ninth Stop  
bit bit  
RI  
SMOD0=0  
RI  
SMOD0=1  
FE  
SMOD0=1  
9.2  
Automatic Address Recognition  
The automatic address recognition feature is enabled when the multiprocessor communication  
feature is enabled (SM2 bit in SCON register is set).  
Implemented in hardware, automatic address recognition enhances the multiprocessor commu-  
nication feature by allowing the serial port to examine the address of each incoming command  
frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON  
register to generate an interrupt. This ensures that the CPU is not interrupted by command  
frames addressed to other devices.  
If desired, you may enable the automatic address recognition feature in mode 1. In this configu-  
ration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received  
command frame address matches the device’s address and is terminated by a valid stop bit.  
To support automatic address recognition, a device is identified by a given address and a broad-  
cast address.  
NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2  
bit in SCON register in mode 0 has no effect).  
9.3  
Given Address  
Each device has an individual address that is specified in SADDR register; the SADEN register  
is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given  
address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The  
following example illustrates how a given address is formed.  
To address a device by its individual address, the SADEN mask byte must be 1111 1111b.  
For example:  
SADDR  
SADEN  
Given  
01010110b  
11111100b  
010101XXb  
The following is an example of how to use given addresses to address different slaves:  
SlaveA:  
SADDR  
SADEN  
Given  
11110001b  
11111010b  
11110X0Xb  
SlaveB:  
SADDR  
SADEN  
Given  
11110011b  
11111001b  
11110XX1b  
12  
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4428E–8051–02/08  
AT/TS80C31X2  
SlaveC:  
SADDR  
SADEN  
Given  
11110010b  
11111101b  
111100X1b  
The SADEN byte is selected so that each slave may be addressed separately.  
For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate  
with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b).  
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves  
B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111  
0011b).  
To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1  
clear, and bit 2 clear (e.g. 1111 0001b).  
9.4  
Broadcast Address  
A broadcast address is formed from the logical OR of the SADDR and SADEN registers with  
zeros defined as don’t-care bits, e.g.:  
SADDR  
SADEN  
Broadcast=SADDRORSADEN  
01010110b  
11111100b  
1111111Xb  
The use of don’t-care bits provides flexibility in defining the broadcast address, however in most  
applications, a broadcast address is FFh. The following is an example of using broadcast  
addresses:  
SlaveA:  
SlaveB:  
SlaveC:  
SADDR  
SADEN  
Broadcast 11111X11b,  
11110001b  
11111010b  
SADDR  
SADEN  
Broadcast 11111X11B,  
11110011b  
11111001b  
SADDR=  
SADEN  
Broadcast 11111111b  
11110010b  
11111101b  
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of  
the slaves, the master must send an address FFh. To communicate with slaves A and B, but not  
slave C, the master can send and address FBh.  
9.5  
Reset Addresses  
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast  
addresses are XXXX XXXXb(all don’t-care bits). This ensures that the serial port will reply to any  
address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not  
support automatic address recognition.  
Table 9-1.  
SADEN - Slave Address Mask Register (B9h)  
7
6
5
4
3
2
1
0
Reset Value = 0000 0000b  
Not bit addressable  
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4428E–8051–02/08  
Table 9-2.  
SADDR - Slave Address Register (A9h)  
7
6
5
4
3
2
1
0
Reset Value = 0000 0000b  
Not bit addressable  
14  
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Table 9-3.  
SCON Register -- SCON - Serial Control Register (98h)  
7
6
5
4
3
2
1
0
FE/SM0  
SM1  
SM2  
REN  
TB8  
RB8  
TI  
RI  
Bit  
Bit  
Number  
Mnemonic  
Description  
Framing Error bit (SMOD0=1)  
Clear to reset the error state, not cleared by a valid stop bit.  
Set by hardware when an invalid stop bit is detected.  
7
FE  
SMOD0 must be set to enable access to the FE bit  
Serial port Mode bit 0  
Refer to SM1 for serial port mode selection.  
SM0  
SM1  
SMOD0 must be cleared to enable access to the SM0 bit  
Serial port Mode bit 1  
SM0  
SM1 Mode Description Baud Rate  
6
5
0
0
1
1
0
1
0
1
0
1
2
3
Shift Register FXTAL/12 (/6 in X2 mode)  
8-bit UART Variable  
9-bit UART XTAL/64 or FXTAL/32 (/32, /16 in X2 mode)  
9-bit UART Variable  
F
Serial port Mode 2 bit / Multiprocessor Communication Enable bit  
Clear to disable multiprocessor communication feature.  
Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should be  
cleared in mode 0.  
SM2  
Reception Enable bit  
4
3
REN  
TB8  
Clear to disable serial reception.  
Set to enable serial reception.  
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3.  
Clear to transmit a logic 0 in the 9th bit.  
Set to transmit a logic 1 in the 9th bit.  
Receiver Bit 8 / Ninth bit received in modes 2 and 3  
Cleared by hardware if 9th bit received is a logic 0.  
Set by hardware if 9th bit received is a logic 1.  
2
RB8  
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.  
Transmit Interrupt flag  
1
0
TI  
Clear to acknowledge interrupt.  
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes.  
Receive Interrupt flag  
Clear to acknowledge interrupt.  
RI  
Set by hardware at the end of the 8th bit time in mode 0, see Figure 9-2. and Figure 9-3. in the other modes.  
Reset Value = 0000 0000b  
Bit addressable  
15  
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Table 9-4.  
7
PCON Register -- PCON - Power Control Register (87h)  
6
5
-
4
3
2
1
0
SMOD1  
SMOD0  
POF  
GF1  
GF0  
PD  
IDL  
Bit  
Bit  
Number  
Mnemonic  
Description  
Serial port Mode bit 1  
7
6
5
4
SMOD1  
Set to select double baud rate in mode 1, 2 or 3.  
Serial port Mode bit 0  
Clear to select SM0 bit in SCON register.  
Set to to select FE bit in SCON register.  
SMOD0  
Reserved  
-
The value read from this bit is indeterminate. Do not set this bit.  
Power-Off Flag  
Clear to recognize next reset type.  
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.  
POF  
General purpose Flag  
3
2
1
0
GF1  
GF0  
PD  
Cleared by user for general purpose usage.  
Set by user for general purpose usage.  
General purpose Flag  
Cleared by user for general purpose usage.  
Set by user for general purpose usage.  
Power-Down mode bit  
Cleared by hardware when reset occurs.  
Set to enter power-down mode.  
Idle mode bit  
IDL  
Clear by hardware when interrupt or reset occurs.  
Set to enter idle mode.  
Reset Value = 00X1 0000b  
Not bit addressable  
Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect  
the value of this bit.  
16  
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10. Interrupt System  
The TS80C31X2 has a total of 5 interrupt vectors: two external interrupts (INT0 and INT1), two  
timer interrupts (timers 0 and 1) and the serial port interrupt. These interrupts are shown in Fig-  
ure 10-1.  
Figure 10-1. Interrupt Control System  
High priority  
interrupt  
IPH, IP  
3
INT0  
IE0  
0
3
0
TF0  
INT1  
TF1  
Interrupt  
polling  
sequence, decreasing  
3
0
3
0
3
0
IE1  
from high to low priority  
RI  
TI  
Low priority  
interrupt  
Individual Enable  
Global Disable  
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit  
in the Interrupt Enable register (See Table 10-2.Table 10-3.). This register also contains a global  
disable bit, which must be cleared to disable all interrupts at once.  
Each interrupt source can also be individually programmed to one out of four priority levels by  
setting or clearing a bit in the Interrupt Priority register (See Table 10-3.) and in the Interrupt Pri-  
ority High register (See Table 10-4.). shows the bit values and priority levels associated with  
each combination.  
Table 10-1. Priority Level Bit Values  
IPH.x  
IP.x  
0
Interrupt Level Priority  
0
0
1
1
0 (Lowest)  
1
1
0
2
1
3 (Highest)  
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A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-prior-  
ity interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source.  
If two interrupt requests of different priority levels are received simultaneously, the request of  
higher priority level is serviced. If interrupt requests of the same priority level are received simul-  
taneously, an internal polling sequence determines which request is serviced. Thus within each  
priority level there is a second priority structure determined by the polling sequence.  
Table 10-2. IE Register -- IE - Interrupt Enable Register (A8h)  
7
6
-
5
-
4
3
2
1
0
EA  
ES  
ET1  
EX1  
ET0  
EX0  
Bit  
Bit  
Number Mnemonic  
Description  
Enable All interrupt bit  
Clear to disable all interrupts.  
Set to enable all interrupts.  
7
EA  
If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its  
own interrupt enable bit.  
Reserved  
6
5
-
-
The value read from this bit is indeterminate. Do not set this bit.  
Reserved  
The value read from this bit is indeterminate. Do not set this bit.  
Serial port Enable bit  
Clear to disable serial port interrupt.  
Set to enable serial port interrupt.  
4
3
2
1
0
ES  
Timer 1 overflow interrupt Enable bit  
Clear to disable timer 1 overflow interrupt.  
Set to enable timer 1 overflow interrupt.  
ET1  
EX1  
ET0  
EX0  
External interrupt 1 Enable bit  
Clear to disable external interrupt 1.  
Set to enable external interrupt 1.  
Timer 0 overflow interrupt Enable bit  
Clear to disable timer 0 overflow interrupt.  
Set to enable timer 0 overflow interrupt.  
External interrupt 0 Enable bit  
Clear to disable external interrupt 0.  
Set to enable external interrupt 0.  
Reset Value = 0XX0 0000b  
Bit addressable  
18  
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Table 10-3. IP Register -- IP - Interrupt Priority Register (B8h)  
7
6
5
4
3
2
1
0
-
-
-
PS  
PT1  
PX1  
PT0  
PX0  
Bit  
Bit  
Number Mnemonic  
Description  
Reserved  
The value read from this bit is indeterminate. Do not set this bit.  
7
6
5
4
3
2
1
0
-
Reserved  
The value read from this bit is indeterminate. Do not set this bit.  
-
Reserved  
-
The value read from this bit is indeterminate. Do not set this bit.  
Serial port Priority bit  
Refer to PSH for priority level.  
PS  
PT1  
PX1  
PT0  
PX0  
Timer 1 overflow interrupt Priority bit  
Refer to PT1H for priority level.  
External interrupt 1 Priority bit  
Refer to PX1H for priority level.  
Timer 0 overflow interrupt Priority bit  
Refer to PT0H for priority level.  
External interrupt 0 Priority bit  
Refer to PX0H for priority level.  
Reset Value = XXX0 0000b  
Bit addressable  
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Table 10-4. IPH Register -- IPH - Interrupt Priority High Register (B7h)  
7
6
5
4
3
2
1
0
-
-
-
PSH  
PT1H  
PX1H  
PT0H  
PX0H  
Bit  
Bit  
Number Mnemonic  
Description  
Reserved  
The value read from this bit is indeterminate. Do not set this bit.  
7
6
5
-
-
-
Reserved  
The value read from this bit is indeterminate. Do not set this bit.  
Reserved  
The value read from this bit is indeterminate. Do not set this bit.  
Serial port Priority High bit  
PS Priority Level  
PSH  
0
0
1
1
0
1
0
1
Lowest  
4
3
2
1
0
PSH  
PT1H  
PX1H  
PT0H  
PX0H  
Highest  
Timer 1 overflow interrupt Priority High bit  
PT1 Priority Level  
PT1H  
0
0
1
1
0
1
0
1
Lowest  
Highest  
External interrupt 1 Priority High bit  
PX1 Priority Level  
PX1H  
0
0
1
1
0
1
0
1
Lowest  
Highest  
Timer 0 overflow interrupt Priority High bit  
PT0H  
PT0 Priority Level  
0
0
1
1
0
1
0
1
Lowest  
Highest  
External interrupt 0 Priority High bit  
PX0H  
PX0 Priority Level  
0
0
1
1
0
1
0
1
Lowest  
Highest  
Reset Value = XXX0 0000b  
Not bit addressable  
20  
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11. Idle mode  
An instruction that sets PCON.0 causes that to be the last instruction executed before going into  
the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the  
interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirely : the Stack  
Pointer, Program Counter, Program Status Word, Accumulator and all other registers maintain  
their data during Idle. The port pins hold the logical states they had at the time Idle was acti-  
vated. ALE and PSEN hold at logic high levels.  
There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0  
to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced, and follow-  
ing RETI the next instruction to be executed will be the one following the instruction that put the  
device into idle.  
The flag bits GF0 and GF1 can be used to give and indication if an interrupt occured during nor-  
mal operation or during an Idle. For example, an instruction that activates Idle can also set one  
or both flag bits. When Idle is terminated by an interrupt, the interrupt service routine can exam-  
ine the flag bits.  
The over way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is  
still running, the hardware reset needs to be held active for only two machine cycles (24 oscilla-  
tor periods) to complete the reset.  
11.1 Power-Down Mode  
To save maximum power, a power-down mode can be invoked by software (Refer to Table 9-4.,  
PCON register).  
In power-down mode, the oscillator is stopped and the instruction that invoked power-down  
mode is the last instruction executed. The internal RAM and SFRs retain their value until the  
power-down mode is terminated. VCC can be lowered to save further power. Either a hardware  
reset or an external interrupt can cause an exit from power-down. To properly terminate power-  
down, the reset or external interrupt should not be executed before VCC is restored to its normal  
operating level and must be held active long enough for the oscillator to restart and stabilize.  
Only external interrupts INT0 and INT1 are useful to exit from power-down. For that, interrupt  
must be enabled and configured as level or edge sensitive interrupt input.  
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed  
in Figure 11-1. When both interrupts are enabled, the oscillator restarts as soon as one of the  
two inputs is held low and power down exit will be completed when the first input will be  
released. In this case the higher priority interrupt service routine is executed.  
Once the interrupt is serviced, the next instruction to be executed after RETI will be the one fol-  
lowing the instruction that put TS80C31X2 into power-down mode.  
21  
4428E–8051–02/08  
Figure 11-1. Power-Down Exit Waveform  
INT0  
INT1  
XTAL1  
Active phase  
Power-down phase Oscillator restart phase  
Active phase  
Exit from power-down by reset redefines all the SFRs, exit from power-down by external inter-  
rupt does no affect the SFRs.  
Exit from power-down by either reset or external interrupt does not affect the internal RAM  
content.  
Note:  
NOTE: If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is  
unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and idle mode is  
not entered.  
Table 11-1. The state of ports during idle and power-down modes  
Program  
Memory  
Mode  
Idle  
ALE  
PSEN  
PORT0  
Floating  
Floating  
PORT1  
Port Data  
Port Data  
PORT2  
Address  
Port Data  
PORT3  
Port Data  
Port Data  
External  
External  
1
0
1
0
Power Down  
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12. ONCETM Mode (ON Chip Emulation)  
The ONCE mode facilitates testing and debugging of systems using TS80C31X2 without remov-  
ing the circuit from the board. The ONCE mode is invoked by driving certain pins of the  
TS80C31X2; the following sequence must be exercised:  
• Pull ALE low while the device is in reset (RST high) and PSEN is high.  
• Hold ALE low as RST is deactivated.  
While the TS80C31X2 is in ONCE mode, an emulator or test CPU can be used to drive the cir-  
cuit Table 26. shows the status of the port pins during ONCE mode.  
Normal operation is restored when normal reset is applied.  
Table 12-1. External Pin Status during ONCE Mode  
ALE  
PSEN  
Port 0  
Port 1  
Port 2  
Port 3  
XTAL1/2  
Weak pull-up  
Weak pull-up  
Float  
Weak pull-up  
Weak pull-up  
Weak pull-up  
Active  
23  
4428E–8051–02/08  
13. Power-Off Flag  
The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start”  
reset.  
A cold start reset is the one induced by VCC switch-on. A warm start reset occurs while VCC is still  
applied to the device and could be generated for example by an exit from power-down.  
The power-off flag (POF) is located in PCON register (See Table 13-1.). POF is set by hardware  
when VCC rises from 0 to its nominal voltage. The POF can be set or cleared by software allow-  
ing the user to determine the type of reset.  
The POF value is only relevant with a Vcc range from 4.5V to 5.5V. For lower Vcc value, reading  
POF bit will return indeterminate value.  
Table 13-1. PCON Register -- PCON - Power Control Register (87h)  
7
6
5
-
4
3
2
1
0
SMOD1  
SMOD0  
POF  
GF1  
GF0  
PD  
IDL  
Bit  
Bit  
Number Mnemonic  
Description  
Serial port Mode bit 1  
7
6
5
4
SMOD1  
SMOD0  
-
Set to select double baud rate in mode 1, 2 or 3.  
Serial port Mode bit 0  
Clear to select SM0 bit in SCON register.  
Set to to select FE bit in SCON register.  
Reserved  
The value read from this bit is indeterminate. Do not set this bit.  
Power-Off Flag  
Clear to recognize next reset type.  
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.  
POF  
General purpose Flag  
3
2
1
0
GF1  
GF0  
PD  
Cleared by user for general purpose usage.  
Set by user for general purpose usage.  
General purpose Flag  
Cleared by user for general purpose usage.  
Set by user for general purpose usage.  
Power-Down mode bit  
Cleared by hardware when reset occurs.  
Set to enter power-down mode.  
Idle mode bit  
IDL  
Clear by hardware when interrupt or reset occurs.  
Set to enter idle mode.  
Reset Value = 00X1 0000b  
Not bit addressable  
24  
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AT/TS80C31X2  
14. Electrical Characteristics  
14.1 Absolute Maximum Ratings (1)  
Ambiant Temperature Under Bias:  
C = commercial0°C to 70°C  
I = industrial -40°C to 85°C  
Storage Temperature-65°C to + 150°C  
Voltage on VCC to VSS-0.5 V to + 7 V  
Voltage on VPP to VSS-0.5 V to + 13 V  
Voltage on Any Pin to VSS-0.5 V to VCC + 0.5 V  
Power Dissipation1 W(2)  
Note:  
1. Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent  
damage to the device. This is a stress rating only and functional operation of the device at  
these or any other conditions above those indicated in the operational sections of this specifi-  
cation is not implied. Exposure to absolute maximum rating conditions may affect device  
reliability.  
2. This value is based on the maximum allowable die temperature and the thermal resistance of  
the package.  
14.2 Power consumption measurement  
Since the introduction of the first C51 devices, every manufacturer made operating Icc measure-  
ments under reset, which made sense for the designs were the CPU was running under reset. In  
Atmel Wireless & Microcontrollers new devices, the CPU is no more active during reset, so the  
power consumption is very low but is not really representative of what will happen in the cus-  
tomer system. That’s why, while keeping measurements under Reset, Atmel Wireless &  
Microcontrollers presents a new way to measure the operating Icc:  
Using an internal test ROM, the following code is executed:  
Label:  
SJMP Label (80 FE)  
Ports 1, 2, 3 are disconnected, Port 0 is tied to FFh, EA = Vcc, RST = Vss, XTAL2 is not con-  
nected and XTAL1 is driven by the clock.  
This is much more representative of the real operating Icc.  
25  
4428E–8051–02/08  
14.3 DC Parameters for Standard Voltage  
T
T
A
= 0°C to +70°C; VSS = 0 V; VCC = 5 V 10%; F = 0 to 40 MHz.  
= -40°C to +85°C; VSS = 0 V; VCC = 5 V 10%; F = 0 to 40 MHz.  
A
Table 14-1. DC Parameters in Standard Voltage  
Symbol  
VIL  
Parameter  
Min  
-0.5  
Typ  
Max  
Unit  
V
Test Conditions  
Input Low Voltage  
0.2 VCC - 0.1  
VCC + 0.5  
VCC + 0.5  
VIH  
Input High Voltage except XTAL1, RST  
Input High Voltage, XTAL1, RST  
0.2 VCC + 0.9  
0.7 VCC  
V
VIH1  
V
0.3  
0.45  
1.0  
V
V
V
IOL = 100 µA(4)  
IOL = 1.6 mA(4)  
IOL = 3.5 mA(4)  
VOL  
VOL1  
VOL2  
Output Low Voltage, ports 1, 2, 3 (6)  
Output Low Voltage, port 0 (6)  
0.3  
0.45  
1.0  
V
V
V
IOL = 200 µA(4)  
IOL = 3.2 mA(4)  
IOL = 7.0 mA(4)  
0.3  
0.45  
1.0  
V
V
V
IOL = 100 µA(4)  
IOL = 1.6 mA(4)  
IOL = 3.5 mA(4)  
Output Low Voltage, ALE, PSEN  
IOH = -10 µA  
IOH = -30 µA  
VCC - 0.3  
VCC - 0.7  
VCC - 1.5  
V
V
V
VOH  
VOH1  
VOH2  
Output High Voltage, ports 1, 2, 3  
Output High Voltage, port 0  
IOH = -60 µA  
VCC = 5 V 10%  
IOH = -200 µA  
IOH = -3.2 mA  
IOH = -7.0 mA  
VCC = 5 V 10%  
VCC - 0.3  
VCC - 0.7  
VCC - 1.5  
V
V
V
IOH = -100 µA  
IOH = -1.6 mA  
IOH = -3.5 mA  
VCC = 5 V 10%  
VCC - 0.3  
VCC - 0.7  
VCC - 1.5  
V
V
V
Output High Voltage,ALE, PSEN  
RRST  
IIL  
RST Pulldown Resistor  
50  
90 (5)  
200  
-50  
kΩ  
µA  
µA  
µA  
Logical 0 Input Current ports 1, 2 and 3  
Input Leakage Current  
Vin = 0.45 V  
0.45 V < Vin < VCC  
Vin = 2.0 V  
ILI  
10  
ITL  
Logical 1 to 0 Transition Current, ports 1, 2, 3  
-650  
Fc = 1 MHz  
CIO  
IPD  
Capacitance of I/O Buffer  
Power Down Current  
10  
50  
pF  
TA  
= 25°C  
20 (5)  
µA  
2.0 V < VCC < 5.5 V(3)  
1 + 0.4 Freq  
(MHz)  
ICC  
Power Supply Current Maximum values, X1  
mode: (7)  
under  
RESET  
VCC = 5.5 V(1)  
@12MHz 5.8  
mA  
mA  
@16MHz 7.4  
3 + 0.6 Freq  
(MHz)  
@12MHz 10.2  
ICC  
Power Supply Current Maximum values, X1  
mode: (7)  
operating  
VCC = 5.5 V(8)  
@16MHz 12.6  
26  
AT/TS80C31X2  
4428E–8051–02/08  
AT/TS80C31X2  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions  
0.25+0.3 Freq  
(MHz)  
ICC  
Power Supply Current Maximum values, X1  
mode: (7)  
VCC = 5.5 V(2)  
@12MHz 3.9  
@16MHz 5.1  
idle  
mA  
14.4 DC Parameters for Low Voltage  
T
T
A
= 0°C to +70°C; VSS = 0 V; VCC = 2.7 V to 5.5 V 10%; F = 0 to 30 MHz.  
= -40°C to +85°C; VSS = 0 V; VCC = 2.7 V to 5.5 V 10%; F = 0 to 30 MHz.  
A
Table 14-2. DC Parameters for Low Voltage  
Symbol  
VIL  
Parameter  
Min  
-0.5  
Typ  
Max  
0.2 VCC - 0.1  
VCC + 0.5  
VCC + 0.5  
0.45  
Unit  
V
Test Conditions  
Input Low Voltage  
VIH  
Input High Voltage except XTAL1, RST  
Input High Voltage, XTAL1, RST  
Output Low Voltage, ports 1, 2, 3 (6)  
Output Low Voltage, port 0, ALE, PSEN (6)  
Output High Voltage, ports 1, 2, 3  
Output High Voltage, port 0, ALE, PSEN  
Logical 0 Input Current ports 1, 2 and 3  
Input Leakage Current  
0.2 VCC + 0.9  
0.7 VCC  
V
VIH1  
VOL  
VOL1  
VOH  
VOH1  
IIL  
V
V
IOL = 0.8 mA(4)  
IOL = 1.6 mA(4)  
IOH = -10 µA  
0.45  
V
0.9 VCC  
0.9 VCC  
V
V
IOH = -40 µA  
-50  
10  
µA  
µA  
µA  
kΩ  
Vin = 0.45 V  
ILI  
0.45 V < Vin < VCC  
Vin = 2.0 V  
ITL  
Logical 1 to 0 Transition Current, ports 1, 2, 3  
RST Pulldown Resistor  
-650  
200  
RRST  
50  
90 (5)  
Fc = 1 MHz  
CIO  
Capacitance of I/O Buffer  
10  
pF  
TA = 25°C  
20 (5)  
10 (5)  
50  
30  
VCC = 2.0 V to 5.5 V(3)  
VCC = 2.0 V to 3.3 V(3)  
IPD  
Power Down Current  
µA  
1 + 0.2 Freq  
(MHz)  
@12MHz 3.4  
ICC  
Power Supply Current Maximum values, X1  
mode: (7)  
under  
RESET  
VCC = 3.3 V(1)  
mA  
@16MHz 4.2  
1 + 0.3 Freq  
(MHz)  
@12MHz 4.6  
ICC  
Power Supply Current Maximum values, X1  
mode: (7)  
VCC = 3.3 V(8)  
operating  
mA  
mA  
@16MHz 5.8  
0.15 Freq  
(MHz) + 0.2  
ICC  
Power Supply Current Maximum values, X1  
mode: (7)  
idle  
VCC = 3.3 V(2)  
@12MHz 2  
@16MHz 2.6  
Note:  
1. ICC under reset is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL  
= 5 ns (see Figure 14-5.), VIL = VSS + 0.5 V,  
27  
4428E–8051–02/08  
VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal  
oscillator used..  
2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns,  
VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 14-  
3.).  
3. Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC  
XTAL2 NC.; RST = VSS (see Figure 14-4.).  
;
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed  
on the VOLs of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharg-  
ing into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus  
operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may  
exceed 0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary.  
5. Typicals are based on a limited number of samples and are not guaranteed. The values listed  
are at room temperature and 5V.  
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:  
Maximum IOL per port pin: 10 mA  
Maximum IOL per 8-bit port:  
Port 0: 26 mA  
Ports 1, 2 and 3: 15 mA  
Maximum total IOL for all output pins: 71 mA  
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guar-  
anteed to sink current greater than the listed test conditions.  
7. For other values, please contact your sales office.  
8. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL  
5 ns (see Figure 14-5.), VIL = VSS + 0.5 V,  
=
VIH = VCC - 0.5V; XTAL2 N.C.; EA = Port 0 = VCC; RST = VSS. The internal ROM runs the code  
80 FE (label: SJMP label). ICC would be slightly higher if a crystal oscillator is used. Measure-  
ments are made with OTP products when possible, which is the worst case.  
VCC  
ICC  
VCC  
VCC  
P0  
VCC  
RST  
EA  
XTAL2  
XTAL1  
(NC)  
CLOCK  
SIGNAL  
VSS  
All other pins are disconnected.  
Figure 14-1. ICC Test Condition, under reset  
28  
AT/TS80C31X2  
4428E–8051–02/08  
AT/TS80C31X2  
VCC  
ICC  
VCC  
P0  
VCC  
Reset = Vss after a high pulse  
during at least 24 clock cycles  
RST  
EA  
XTAL2  
XTAL1  
(NC)  
CLOCK  
SIGNAL  
All other pins are disconnected.  
VSS  
Figure 14-2. Operating ICC Test Condition  
VCC  
ICC  
VCC  
P0  
VCC  
Reset = Vss after a high pulse  
during at least 24 clock cycles  
RST  
EA  
(NC)  
CLOCK  
SIGNAL  
XTAL2  
XTAL1  
VSS  
All other pins are disconnected.  
Figure 14-3. ICC Test Condition, Idle Mode  
VCC  
ICC  
VCC  
VCC  
P0  
Reset = Vss after a high pulse  
during at least 24 clock cycles  
RST  
EA  
(NC)  
XTAL2  
XTAL1  
VSS  
All other pins are disconnected.  
Figure 14-4. ICC Test Condition, Power-Down Mode  
29  
4428E–8051–02/08  
VCC-0.5V  
0.7VCC  
0.2VCC-0.1  
0.45V  
TCHCL  
TCLCH  
TCLCH = TCHCL = 5ns.  
Figure 14-5. Clock Signal Waveform for ICC Tests in Active and Idle Modes  
14.5 AC Parameters  
14.5.1  
Explanation of the AC Symbols  
Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The  
other characters, depending on their positions, stand for the name of a signal or the logical sta-  
tus of that signal. The following is a list of all the characters and what they stand for.  
Example:TAVLL = Time for Address Valid to ALE Low.  
T
LLPL = Time for ALE Low to PSEN Low.  
T
T
A
A
= 0 to +70°C (commercial temperature range); VSS = 0 V; VCC = 5 V 10%; -M and -V ranges.  
= -40°C to +85°C (industrial temperature range); VSS = 0 V; VCC = 5 V 10%; -M and -V  
ranges.  
T
T
A
= 0 to +70°C (commercial temperature range); VSS = 0 V; 2.7 V < VCC < 5.5 V; -L range.  
= -40°C to +85°C (industrial temperature range); VSS = 0 V; 2.7 V < VCC < 5.5 V; -L range.  
A
Table 14-3. gives the maximum applicable load capacitance for Port 0, Port 1, 2 and 3, and ALE  
and PSEN signals. Timings will be guaranteed if these capacitances are respected. Higher  
capacitance values can be used, but timings will then be degraded.  
Table 14-3. Load Capacitance versus speed range, in pF  
-M  
-V  
50  
50  
30  
-L  
Port 0  
100  
80  
100  
80  
Port 1, 2, 3  
ALE / PSEN 100  
100  
Table 8-5., Table 8-8. and Table 8-11. give the description of each AC symbols.  
Table 14-6., Table 14-9. and Table 14-12. give for each range the AC parameter.  
30  
AT/TS80C31X2  
4428E–8051–02/08  
AT/TS80C31X2  
Table 14-7., Table 14-10. and Table 14-13. give the frequency derating formula of the AC  
parameter. To calculate each AC symbols, take the x value corresponding to the speed grade  
you need (-M, -V or -L) and replace this value in the formula. Values of the frequency must be  
limited to the corresponding speed grade:  
Table 14-4. Max frequency for derating formula regarding the speed grade  
-M X1 mode -M X2 mode -V X1 mode -V X2 mode -L X1 mode -L X2 mode  
Freq (MHz) 40  
20  
50  
40  
25  
30  
30  
20  
50  
T (ns)  
25  
33.3  
33.3  
Example:  
TLLIV in X2 mode for a -V part at 20 MHz (T = 1/20E6 = 50 ns):  
x= 25 (Table 14-7.)  
T= 50ns  
TLLIV= 2T - x = 2 x 50 - 25 = 75ns  
Table 14-5. External Program Memory Characteristics  
Parameter  
Symbol  
T
Oscillator clock period  
TLHLL  
TAVLL  
TLLAX  
TLLIV  
TLLPL  
TPLPH  
TPLIV  
TPXIX  
TPXIZ  
TPXAV  
TAVIV  
TPLAZ  
ALE pulse width  
Address Valid to ALE  
Address Hold After ALE  
ALE to Valid Instruction In  
ALE to PSEN  
PSEN Pulse Width  
PSEN to Valid Instruction In  
Input Instruction Hold After PSEN  
Input Instruction FloatAfter PSEN  
PSEN to Address Valid  
Address to Valid Instruction In  
PSEN Low to Address Float  
31  
4428E–8051–02/08  
Table 14-6. AC Parameters for Fix Clock  
-V  
-L  
-L  
-V  
X2 mode  
X2 mode  
20 MHz  
standard mode  
30 MHz  
standard mode 40  
MHz  
-M  
30 MHz  
Speed  
Symbol  
T
40 MHz  
60 MHz equiv.  
40 MHz equiv.  
Units  
Min  
Max  
Min  
33  
25  
4
Max  
Min  
25  
Max  
Min  
50  
35  
5
Max  
Min  
33  
Max  
25  
40  
10  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
TLHLL  
TAVLL  
TLLAX  
TLLIV  
42  
52  
12  
13  
4
12  
5
13  
70  
35  
45  
25  
78  
50  
65  
30  
98  
55  
TLLPL  
TPLPH  
TPLIV  
TPXIX  
TPXIZ  
TAVIV  
TPLAZ  
15  
55  
9
17  
60  
10  
50  
18  
75  
35  
0
0
0
0
0
18  
85  
10  
12  
53  
10  
20  
95  
10  
10  
80  
10  
18  
122  
10  
Table 14-7. AC Parameters for a Variable Clock: derating formula  
Standard  
Symbol  
TLHLL  
TAVLL  
TLLAX  
TLLIV  
Type  
Min  
Clock  
2 T - x  
T - x  
T - x  
4 T - x  
T - x  
3 T - x  
3 T - x  
x
X2 Clock  
T - x  
-M  
10  
15  
15  
30  
10  
20  
40  
0
-V  
8
-L  
15  
20  
20  
35  
15  
25  
45  
0
Units  
ns  
Min  
0.5 T - x  
0.5 T - x  
2 T - x  
0.5 T - x  
1.5 T - x  
1.5 T - x  
x
13  
13  
22  
8
ns  
Min  
ns  
Max  
Min  
ns  
TLLPL  
TPLPH  
TPLIV  
TPXIX  
TPXIZ  
TAVIV  
ns  
Min  
15  
25  
0
ns  
Max  
Min  
ns  
ns  
Max  
Max  
Max  
T - x  
5 T - x  
x
0.5 T - x  
2.5 T - x  
x
7
5
15  
45  
10  
ns  
40  
10  
30  
10  
ns  
TPLAZ  
ns  
32  
AT/TS80C31X2  
4428E–8051–02/08  
AT/TS80C31X2  
14.5.2  
External Program Memory Read Cycle  
12 TCLCL  
TLHLL  
TLLIV  
TLLPL  
ALE  
TPLPH  
PSEN  
TPXAV  
TPXIZ  
TLLAX  
TPLIV  
TPLAZ  
TAVLL  
TPXIX  
INSTR IN  
PORT 0  
PORT 2  
INSTR IN  
A0-A7  
A0-A7  
INSTR IN  
TAVIV  
ADDRESS A8-A15  
ADDRESS  
OR SFR-P2  
ADDRESS A8-A15  
Figure 14-6. External Program Memory Read Cycle  
Table 14-8. External Data Memory Characteristics  
Symbol  
Parameter  
TRLRH  
TWLWH  
TRLDV  
TRHDX  
TRHDZ  
TLLDV  
TAVDV  
TLLWL  
TAVWL  
TQVWX  
TQVWH  
TWHQX  
TRLAZ  
TWHLH  
RD Pulse Width  
WR Pulse Width  
RD to Valid Data In  
Data Hold After RD  
Data Float After RD  
ALE to Valid Data In  
Address to Valid Data In  
ALE to WR or RD  
Address to WR or RD  
Data Valid to WR Transition  
Data set-up to WR High  
Data Hold After WR  
RD Low to Address Float  
RD or WR High to ALE high  
33  
4428E–8051–02/08  
Table 14-9. AC Parameters for a Fix Clock  
-V  
-L  
-V  
X2 mode  
X2 mode  
20 MHz  
-L  
standard mode 40  
MHz  
Speed  
-M  
30 MHz  
standard mode  
30 MHz  
40 MHz  
60 MHz equiv.  
40 MHz equiv.  
Units  
Symbol  
TRLRH  
TWLWH  
TRLDV  
TRHDX  
TRHDZ  
TLLDV  
Min  
Max  
Min  
85  
Max  
Min  
135  
135  
Max  
Min  
125  
125  
Max  
Min  
175  
175  
Max  
130  
130  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
85  
100  
60  
102  
95  
137  
0
0
0
0
0
30  
18  
98  
35  
165  
175  
95  
25  
42  
160  
165  
100  
155  
160  
105  
222  
235  
130  
TAVDV  
TLLWL  
TAVWL  
TQVWX  
TQVWH  
TWHQX  
TRLAZ  
100  
70  
50  
75  
30  
47  
7
55  
80  
45  
70  
5
70  
103  
13  
10  
15  
160  
15  
107  
9
165  
17  
155  
10  
213  
18  
0
0
0
0
0
TWHLH  
10  
40  
7
27  
15  
35  
5
45  
13  
53  
34  
AT/TS80C31X2  
4428E–8051–02/08  
AT/TS80C31X2  
Table 14-10. AC Parameters for a Variable Clock: derating formula  
Standard  
Symbol  
TRLRH  
TWLWH  
TRLDV  
TRHDX  
TRHDZ  
TLLDV  
Type  
Min  
Min  
Max  
Min  
Max  
Max  
Max  
Min  
Max  
Min  
Min  
Min  
Min  
Max  
Min  
Max  
Clock  
6 T - x  
6 T - x  
5 T - x  
x
X2 Clock  
3 T - x  
3 T - x  
2.5 T - x  
x
-M  
20  
20  
25  
0
-V  
15  
15  
23  
0
-L  
25  
25  
30  
0
Units  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
2 T - x  
8 T - x  
9 T - x  
3 T - x  
3 T + x  
4 T - x  
T - x  
T - x  
20  
40  
60  
25  
25  
25  
15  
15  
10  
0
15  
35  
50  
20  
20  
20  
10  
10  
8
25  
45  
65  
30  
30  
30  
20  
20  
15  
0
4T -x  
TAVDV  
TLLWL  
4.5 T - x  
1.5 T - x  
1.5 T + x  
2 T - x  
0.5 T - x  
3.5 T - x  
0.5 T - x  
x
TLLWL  
TAVWL  
TQVWX  
TQVWH  
TWHQX  
TRLAZ  
TWHLH  
TWHLH  
7 T - x  
T - x  
x
0
T - x  
0.5 T - x  
0.5 T + x  
15  
15  
10  
10  
20  
20  
T + x  
14.5.3  
External Data Memory Write Cycle  
TWHLH  
ALE  
PSEN  
WR  
TLLWL  
TWLWH  
TQVWX  
TWHQX  
TLLAX  
A0-A7  
TQVWH  
DATA OUT  
PORT 0  
TAVWL  
ADDRESS  
OR SFR-P2  
PORT 2  
ADDRESS A8-A15 OR SFR P2  
Figure 14-7. External Data Memory Write Cycle  
35  
4428E–8051–02/08  
14.5.4  
External Data Memory Read Cycle  
TWHLH  
TLLDV  
ALE  
PSEN  
RD  
TLLWL  
TRLRH  
TRLDV  
TRHDZ  
TAVDV  
TLLAX  
TRHDX  
DATA IN  
PORT 0  
A0-A7  
TRLAZ  
TAVWL  
ADDRESS  
OR SFR-P2  
PORT 2  
ADDRESS A8-A15 OR SFR P2  
Figure 14-8. External Data Memory Read Cycle  
Table 14-11. Serial Port Timing - Shift Register Mode  
Symbol  
Parameter  
TXLXL  
TQVHX  
TXHQX  
TXHDX  
TXHDV  
Serial port clock cycle time  
Output data set-up to clock rising edge  
Output data hold after clock rising edge  
Input data hold after clock rising edge  
Clock rising edge to input data valid  
Table 14-12. AC Parameters for a Fix Clock  
-V  
-L  
-V  
X2 mode  
30 MHz  
X2 mode  
20 MHz  
-L  
standard mode 40  
MHz  
-M  
40 MHz  
standard mode  
30 MHz  
Speed  
60 MHz equiv.  
40 MHz equiv.  
Units  
Symbol  
TXLXL  
Min  
Max  
Min  
200  
117  
13  
Max  
Min  
300  
200  
30  
Max  
Min  
300  
200  
30  
Max  
Min  
400  
283  
47  
Max  
300  
200  
30  
ns  
ns  
ns  
ns  
ns  
TQVHX  
TXHQX  
TXHDX  
TXHDV  
0
0
0
0
0
117  
34  
117  
117  
200  
36  
AT/TS80C31X2  
4428E–8051–02/08  
AT/TS80C31X2  
Table 14-13. AC Parameters for a Variable Clock: derating formula  
Standard  
Symbol  
TXLXL  
Type  
Min  
Min  
Min  
Min  
Max  
Clock  
X2 Clock  
6 T  
-M  
-V  
-L  
Units  
ns  
12 T  
TQVHX  
TXHQX  
TXHDX  
TXHDV  
10 T - x  
2 T - x  
x
5 T - x  
T - x  
50  
20  
0
50  
20  
0
50  
20  
0
ns  
ns  
x
ns  
10 T - x  
5 T- x  
133  
133  
133  
ns  
14.5.5  
Shift Register Timing Waveforms  
0
1
2
3
4
5
6
7
8
INSTRUCTION  
ALE  
TXLXL  
CLOCK  
TXHQX  
1
TQVXH  
0
2
3
4
5
6
7
OUTPUT DATA  
TXHDX  
SET TI  
TXHDV  
WRITE to SBUF  
INPUT DATA  
VALID  
VALID  
VALID  
VALID  
VALID  
VALID  
VALID  
VALID  
SET RI  
CLEAR RI  
Figure 14-9. Shift Register Timing Waveforms  
Table 14-14. External Clock Drive Characteristics (XTAL1)  
Symbol  
Parameter  
Oscillator Period  
High Time  
Min  
25  
5
Max  
Units  
ns  
TCLCL  
TCHCX  
TCLCX  
TCLCH  
TCHCL  
ns  
Low Time  
5
ns  
Rise Time  
5
5
ns  
Fall Time  
ns  
TCHCX/TCLCX  
Cyclic ratio in X2 mode  
40  
60  
%
37  
4428E–8051–02/08  
14.5.6  
External Clock Drive Waveforms  
VCC-0.5 V  
0.45 V  
0.7VCC  
0.2VCC-0.1 V  
TCHCL  
TCHCX  
TCLCH  
TCLCX  
TCLCL  
Figure 14-10. External Clock Drive Waveforms  
AC Testing Input/Output Waveforms  
14.5.7  
VCC-0.5 V  
0.45 V  
0.2VCC+0.9  
0.2VCC-0.1  
INPUT/OUTPUT  
Figure 14-11. AC Testing Input/Output Waveforms  
AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing  
measurement are made at VIH min for a logic “1” and VIL max for a logic “0”.  
14.5.8  
Float Waveforms  
FLOAT  
VLOAD  
VOH-0.1 V  
VOL+0.1 V  
VLOAD+0.1 V  
VLOAD-0.1 V  
Figure 14-12. Float Waveforms  
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage  
occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH  
20mA.  
14.5.9  
Clock Waveforms  
Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by  
two.  
38  
AT/TS80C31X2  
4428E–8051–02/08  
AT/TS80C31X2  
Figure 14-13. Clock Waveforms  
STATE1  
P1P2  
STATE2  
P1P2  
STATE3  
P1P2  
STATE4  
P1P2  
STATE4  
STATE5  
P1P2  
STATE6  
P1P2  
STATE5  
P1P2  
INTERNAL  
CLOCK  
P1P2  
XTAL2  
ALE  
THESE SIGNALS ARE NOT ACTIVATED DURING THE  
EXECUTION OF A MOVX INSTRUCTION  
EXTERNAL PROGRAM MEMORY FETCH  
PSEN  
PCL OUT  
PCL OUT  
PCL OUT  
DATA  
P0  
SAMPLE  
DATA  
SAMPLE  
FLOAT  
DATA  
SAMPLE  
FLOAT  
FLOAT  
INDICATES ADDRESS  
P2 (EXT)  
READ CYCLE  
RD  
PCL OUT (IF PROGRAM  
MEMORY IS EXTERNAL)  
P0  
P2  
DPL OR Rt  
FLOAT  
INDICATES DPH OR P2 SFR TO PCH  
WRITE CYCLE  
WR  
PCL OUT (EVEN IF  
MEMORY IS INTERNAL)  
P0  
DPL OR Rt  
DATA OUT  
PCL OUT (IF PROGRAM  
MEMORY IS EXTERNAL)  
P2  
INDICATES DPH OR P2 SFR TO PCH  
PORT OPERATION  
OLD DATA  
NEW DATA  
P0 PINS SAMPLED  
P0 PINS SAMPLED  
MOV DEST P0  
P1, P2, P3 PINS  
P1, P2, P3 PINS  
MOV DEST PORT (P1, P2,  
(INCLUDES INT0, INT1, TO, T1)  
RXD SAMPLED  
RXD SAMPLED  
SERIAL PORT SHIFT CLOCK  
TXD (MODE 0)  
This diagram indicates when signals are clocked internally. The time it takes the signals to prop-  
agate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on  
variables such as temperature and pin loading. Propagation also varies from output to output  
and component. Typically though (TA=25°C fully loaded) RD and WR propagation delays are  
approximately 50ns. The other signals are typically 85 ns. Propagation delays are incorporated  
in the AC specifications.  
39  
4428E–8051–02/08  
15. Ordering Information  
Temperature  
Range  
Part Number(3)  
TS80C31X2-MCA  
TS80C31X2-MCB  
TS80C31X2-MCC  
TS80C31X2-MCE  
TS80C31X2-LCA  
TS80C31X2-LCB  
TS80C31X2-LCC  
TS80C31X2-LCE  
TS80C31X2-VCA  
TS80C31X2-VCB  
TS80C31X2-VCC  
TS80C31X2-VCE  
TS80C31X2-MIA  
TS80C31X2-MIB  
TS80C31X2-MIC  
TS80C31X2-MIE  
TS80C31X2-LIA  
TS80C31X2-LIB  
TS80C31X2-LIC  
TS80C31X2-LIE  
TS80C31X2-VIA  
TS80C31X2-VIB  
TS80C31X2-VIC  
TS80C31X2-VIE  
Memory Size  
Supply Voltage  
Max Frequency  
Package  
Packing  
OBSOLETE  
AT80C31X2-3CSUM  
AT80C31X2-SLSUM  
AT80C31X2-RLTUM  
AT80C31X2-3CSUL  
AT80C31X2-SLSUL  
AT80C31X2-RLTUL  
ROMLess  
ROMLess  
ROMLess  
ROMLess  
ROMLess  
ROMLess  
5V 10%  
5V 10%  
Industrial & Green  
Industrial & Green  
Industrial & Green  
Industrial & Green  
Industrial & Green  
Industrial & Green  
40 MHz(1)  
40 MHz(1)  
40 MHz(1)  
30 MHz(1)  
30 MHz(1)  
30 MHz(1)  
PDIL40  
PLCC44  
VQFP44  
PDIL40  
Stick  
Stick  
Tray  
Stick  
Stick  
Tray  
5V 10%  
2.7 to 5.5V  
2.7 to 5.5V  
2.7 to 5.5V  
PLCC44  
VQFP44  
40  
AT/TS80C31X2  
4428E–8051–02/08  
AT/TS80C31X2  
Temperature  
Range  
Part Number(3)  
AT80C31X2-3CSUV  
AT80C31X2-SLSUV  
AT80C31X2-RLTUV  
Memory Size  
ROMLess  
ROMLess  
ROMLess  
Supply Voltage  
5V 10%  
Max Frequency  
60 MHz(3)  
Package  
Packing  
Stick  
Industrial & Green  
Industrial & Green  
Industrial & Green  
PDIL40  
PLCC44  
VQFP44  
5V 10%  
60 MHz(3)  
Stick  
5V 10%  
60 MHz(3)  
Tray  
Notes: 1. 20 MHz in X2 Mode.  
2. Tape and Reel available for SL, PQFP and RL packages.  
3. 30 MHz in X2 Mode.  
41  
4428E–8051–02/08  
Atmel Corporation  
Atmel Operations  
2325 Orchard Parkway  
San Jose, CA 95131, USA  
Tel: 1(408) 441-0311  
Fax: 1(408) 487-2600  
Memory  
RF/Automotive  
Theresienstrasse 2  
Postfach 3535  
2325 Orchard Parkway  
San Jose, CA 95131, USA  
Tel: 1(408) 441-0311  
Fax: 1(408) 436-4314  
74025 Heilbronn, Germany  
Tel: (49) 71-31-67-0  
Fax: (49) 71-31-67-2340  
Regional Headquarters  
Microcontrollers  
2325 Orchard Parkway  
San Jose, CA 95131, USA  
Tel: 1(408) 441-0311  
Fax: 1(408) 436-4314  
1150 East Cheyenne Mtn. Blvd.  
Colorado Springs, CO 80906, USA  
Tel: 1(719) 576-3300  
Europe  
Atmel Sarl  
Route des Arsenaux 41  
Case Postale 80  
CH-1705 Fribourg  
Switzerland  
Fax: 1(719) 540-1759  
Biometrics/Imaging/Hi-Rel MPU/  
High Speed Converters/RF Datacom  
Avenue de Rochepleine  
BP 123  
38521 Saint-Egreve Cedex, France  
Tel: (33) 4-76-58-30-00  
Fax: (33) 4-76-58-34-80  
La Chantrerie  
BP 70602  
Tel: (41) 26-426-5555  
Fax: (41) 26-426-5500  
44306 Nantes Cedex 3, France  
Tel: (33) 2-40-18-18-18  
Fax: (33) 2-40-18-19-60  
Asia  
Room 1219  
ASIC/ASSP/Smart Cards  
Zone Industrielle  
13106 Rousset Cedex, France  
Tel: (33) 4-42-53-60-00  
Fax: (33) 4-42-53-60-01  
Chinachem Golden Plaza  
77 Mody Road Tsimshatsui  
East Kowloon  
Hong Kong  
Tel: (852) 2721-9778  
Fax: (852) 2722-1369  
1150 East Cheyenne Mtn. Blvd.  
Colorado Springs, CO 80906, USA  
Tel: 1(719) 576-3300  
Japan  
9F, Tonetsu Shinkawa Bldg.  
1-24-8 Shinkawa  
Chuo-ku, Tokyo 104-0033  
Japan  
Fax: 1(719) 540-1759  
Scottish Enterprise Technology Park  
Maxwell Building  
Tel: (81) 3-3523-3551  
Fax: (81) 3-3523-7581  
East Kilbride G75 0QR, Scotland  
Tel: (44) 1355-803-000  
Fax: (44) 1355-242-743  
Literature Requests  
www.atmel.com/literature  
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any  
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-  
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Printed on recycled paper.  
4428E–8051–02/08  

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