TSC21020F-20MB-E [ATMEL]
Rad. Hard 32/40-bit IEEE Floating Point DSP; 弧度。硬四十分之三十二位IEEE浮点DSP
| 型号： | TSC21020F-20MB-E |
| 厂家： | 
ATMEL |
| 描述： | Rad. Hard 32/40-bit IEEE Floating Point DSP |
| 文件： | 总50页 (文件大小：696K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
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Superscalar IEEE Floating-Point-Processor
Off-Chip Harvard Architecture Maximizes Signal Processing Performance
50 ns, 20 MIPS Instruction Rate, Single Cycle Execution
60 MFLOPS Peak, 40 MFLOPS Sustained Performance
1024-Point Complex FFT Benchmark: 0.975 ms
Divide (y/x): 300 ns
Inverse Square Root (1/ /x): 450 ns
32-bit Single-Precision and 40-bit Extended-Precision IEEE Floating-Point Data
Formats
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32-bit Fixed-Point Formats, Integer and Fractional, with 80-bit Accumulators
IEEE Exception Handling with Interrupt on Exception
Three Independent Computation Units: Multiplier, ALU, and Barrel Shifter
Dual Data Address Generators with Indirect, Immediate, Modulo, and Bit Reverse
Addressing Modes
Rad. Hard
32/40-bit IEEE
Floating Point
DSP
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Two Off-Chip Memory Transfers in Parallel with Instruction Fetch and Single-Cycle
Multiply and ALU Operations
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Multiply with Add and Subtract for FFT Butterfly Computation
Efficient Program Sequencing with Zero Overhead Looping: Single-Cycle Loop Setup
Single-Cycle Register File Context Switch
23ns External RAM Access Time for Zero-Wait-State, 40 ns Instruction Execution
IEEE JTAG Standard 1149.1 Test Access Port and On-chip Emulation Circuitry
223 CPGA package for breadboarding
TSC21020F
256 Multi-layer Quad Flat Pack, Flat Leads, For Flight Models
Fully compatible with Analog Devices ADSP-21020
No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm2
Tested up to a Total Dose of 100 krads (Si) according to MIL STD 883 Method 1019
SEU Error Note in GEO Orbit Better than 5E-7 Error/Device/Day (worst case)
For 25 MHz Specification, Contact Atmel for Availability
Quality Grades - ESCC with 9512/002 and QML-Q or V with 5962-99539
Introduction
Atmel is manufacturing a radiation hard version of the Analog Devices ADSP-21020
32/40-bit Floating-Point DSP.
The product is pin and code compatible with ADI product, making system develop-
ment straight forward and cost effective, using existing development tools and
algorithms.
Notes: 1. Design using patent from INPG-CNRS Denis BESSOT/Raoul VELAZCO
2. Product licensed from Analog Devices Inc.
Rev. 4153I-AERO–04/07
1
Functional Block Diagram
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TSC21020F
4153H–AERO–04/07
TSC21020F
General Description
The TSC21020F is single-chip IEEE floating-point processor optimized for digital signal
processing applications (1). Its architecture is similar to that of Analog Devices' ADSP-
2100 family of fixed-point DSP processors.
Fabricated in a high-speed, low-power and radiation hard CMOS process, the
TSC21020F has a 50ns instruction cycle time. With a high-performance On-chip instruc-
tion cache, the TSC21020F can execute every instruction in a single cycle.
The TSC21020F features:
Independent Parallel
Computation Units
The arithmetic/logic unit (ALU), multiplier and shifter perform single-cycle instructions.
The units are architecturally arranged in parallel, maximizing computational throughput.
A single multifunction instruction executes parallel ALU and multiplier operations. These
computation units support IEEE 32-bit single-precision floating-point, extended preci-
sion 40-bit floating-point, and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is used for transferring data between the computa-
tion units and the data buses, and for storing intermediate results. This 10-port (16-
register) register file, combined with the TSC21020F's Harvard architecture, allows
unconstrained data flow between computation units and off-chip memory.
Single-Cycle Fetch of
Instruction and Two
Operands
The TSC21020F uses a modified Harvard architecture in which data memory stores
data and program memory stores both instructions and data. Because of its separate
program and data memory buses and On-chip instruction cache, the processor can
simultaneously fetch an operand from data memory, an operand from program memory,
and an instruction from the cache, all in a single cycle.
Memory Interface
Instruction Cache
Addressing of external memory devices by the TSC21020F is facilitated by On-chip
decoding of high-order address lines to generate memory bank select signals. Separate
control lines are also generated for simplified addressing of page-mode DRAM. The
TSC21020F provides programmable memory wait states, and external memory
acknowledge controls allow interfacing to peripheral devices with variable access times.
The TSC21020F includes a high performance instruction cache that enables three-bus
operation for fetching an instruction and two data values. The cache is selective-only the
instructions whose fetches conflict with program memory data accesses are cached.
This allows full-speed execution of core, looped operations such as digital filter multiply-
accumulates and FFT butterfly processing.
Hardware Circular
Buffers
The TSC21020F provides hardware to implement circular buffers in memory, which are
common in digital filters and Fourier transform implementations. It handles address
pointer wraparound, reducing overhead (thereby increasing performance) and simplify-
ing implementation. Circular buffers can start and end at any location.
Flexible Instruction Set
The TSC21020F's 48-bit instruction word accommodates a variety of parallel opera-
tions, for concise programming. For example, the TSC21020F can conditionally execute
a multiply, an add, a subtract and a branch in a single instruction.
1.
It is fully compatible with Analog Devices ADSP-21020
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Development System The TSC21020F is supported with a complete set of software and hardware develop-
ment tools from Analog Devices. The ADSP-21000 Family Development System from
Analog Devices includes development software, an evaluation board and an in-circuit
emulator.
Assembler
Creates relocatable, COFF (Common Object File Format) object files from ADSP-21xxx
assembly source code. It accepts standard C preprocessor directives for conditional
assembly and macro processing. The algebraic syntax of the ADSP-21xxx assembly
language facilitates coding and debugging of DSP algorithms.
Linker/Librarian
The Linker processes separately assembled object files and library files to create a sin-
gle executable program. It assigns memory locations to code and to data in accordance
with a user-defined architecture file that describes the memory and I/O configuration of
the target system. The Librarian allows you to group frequently used object files into a
single library file that can be linked with your main program.
Simulator
The Simulator performs interactive, instruction-level simulation of ADSP-21xxx code
within the hardware configuration described by a system architecture file. It flags illegal
operations and supports full symbolic disassembly. It provides an easy-to-use, window
oriented, graphical user interface that is identical to the one used by the ADSP- 21020
EZ-ICE Emulator. Commands are accessed from pull-down menus with a mouse.
PROM Splitter
Formats an executable file into files that can be used with an industry-standard PROM
programmer.
C Compiler and Runtime The C Compiler complies with ANSI specifications. It takes advantage of the
TSC21020F's high-level language architectural features and incorporates optimizing
algorithms to speed up the execution of code. It includes an extensive runtime library
with over 100 standard and DSP-specific functions.
Library
C Source Level
Debugger
A full-featured C source level debugger that works with the simulator or EZ-ICE emula-
tor to allow debugging of assembler source, C source, or mixed assembler and C.
Numerical C Compiler
Supports ANSI Standard (X3J11.1) Numerical C as defined by the Numeric C Exten-
sions Group. The compiler accepts C source input containing Numerical C extensions
for array selection, vector math operations, complex data types, circular pointers, and
variably dimensioned arrays, and outputs ADSP-21xxx assembly language source
code.
ADSP- 21020 EZ-LAB®
Evaluation Board
The EZ-LAB Evaluation Board is a general-purpose, standalone TSC21020F system
that includes 32K words of program memory and 32K words of data memory as well as
analog I/O. A PC RS-232 download path enables the user to download and run pro-
grams directly on the EZ-LAB. In addition, it may be used in conjunction with the EZ-ICE
Emulator to provide a powerful software debug environment.
ADSP- 21020 EZ-ICE®
Emulator
This in-circuit emulator provides the system designer with a PC-based development
environment that allows non-intrusive access to the TSC21020F's internal registers
through the processor's 5-pin JTAG Test Access Port. This use of On-chip emulation
circuitry enables reliable, full-speed performance in any target. The emulator uses the
same graphical user interface as the ADSP- 21020 Simulator, allowing an easy transi-
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4153H–AERO–04/07
TSC21020F
tion from software to hardware debug. (See "Target System Requirements for Use of
EZ-ICE Emulator" on page 27.)
®
EZ-LAB and EZ-ICE are registered trademarks of Analog Devices, Inc.
Additional Information
This data sheet provides a general overview of TSC21020F functionality. For additional
information on the architecture and instruction set of the processor, refer to the ADSP-
21020 User's Manual. For development system and programming reference informa-
tion, refer to the ADSP-21000 Family Development Software Manuals and the ADSP-
21020 Programmer's Quick Reference.
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Architecture
Overview
Figure 1 shows a block diagram of the TSC21020F. The processor features:
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Three Computation Units (ALU, Multiplier, and Shifter) with a Shared Data Register
File
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Two Data Address Generators (DAG 1, DAG 2)
Program Sequencer with Instruction Cache
32-bit Timer
Memory Buses and Interface
JTAG Test Access Port and On-chip Emulation Support
Computation Units
The TSC21020F contains three independent computation units: an ALU, a multiplier
with fixed-point accumulator, and a shifter. In order to meet a wide variety of processing
needs, the computation units process data in three formats: 32-bit fixed-point, 32-bit
floating-point and 40-bit floating-point. The floating-point operations are single-precision
IEEE-compatible (IEEE Standard 754/854). The 32-bit floating-point format is the stan-
dard IEEE format, whereas the 40-bit IEEE extended- precision format has eight
additional LSBs of mantissa for greater accuracy.
The multiplier performs floating-point and fixed-point multiplication as well as fixed-point
multiply/add and multiply/subtract operations. Integer products are 64 bits wide, and the
accumulator is 80 bits wide. The ALU performs 45 standard arithmetic and logic opera-
tions, supporting both fixed-point and floating-point formats. The shifter performs 19
different operations on 32-bit operands. These operations include logical and arithmetic
shifts, bit manipulation, field deposit, and extract and derive exponent operations.
The computation units perform single-cycle operations; there is no computation pipeline.
The three units are connected in parallel rather than serially, via multiple-bus connec-
tions with the 10-port data register file. The output of any computation unit may be used
as the input of any unit on the next cycle. In a multifunction computation, the ALU and
multiplier perform independent, simultaneous operations.
Data Register File
The TSC21020F's general-purpose data register file is used for transferring data
between the computation units and the data buses, and for storing intermediate results.
The register file has two sets (primary and alternate) of sixteen 40-bit registers each, for
fast context switching.
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TSC21020F
Figure 1. TSC21020F Block Diagram
With a large number of buses connecting the registers to the computation units, data
flow between computation units and from/to off-chip memory is unconstrained and free
from bottlenecks. The 10-port register file and Harvard architecture of the TSC21020F
allow the following nine data transfers to be performed every cycle:
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Off-chip read/write of two operands to or from the register file
Two operands supplied to the ALU
Two operands supplied to the multiplier
Two results received from the ALU and multiplier (three, if the ALU operation is a
combined addition/subtraction).
The processor's 48-bit orthogonal instruction word supports fully parallel data transfer
and arithmetic operations in the same instruction.
Address Generators and Two dedicated address generators and a program sequencer supply addresses for
memory accesses. Because of this, the computation units need never be used to calcu-
Program Sequencer
late addresses. Because of its instruction cache, the TSC21020F can simultaneously
fetch an instruction and data values from both off-chip program memory and off-chip
data memory in a single cycle.
The data address generators (DAGs) provide memory addresses when external mem-
ory data is transferred over the parallel memory ports to or from internal registers. Dual
data address generators enable the processor to output two simultaneous addresses for
dual operand reads and writes. DAG 1 supplies 32-bit addresses to data memory. DAG
2 supplies 24-bit addresses to program memory for program memory data accesses.
Each DAG keeps track of up to eight address pointers, eight modifiers, eight buffer
length values and eight base values. A pointer used for indirect addressing can be mod-
ified by a value in a specified register, either before (premodify) or after (post-modify)
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4153H–AERO–04/07
the access. To implement automatic modulo addressing for circular buffers, the
TSC21020F provides buffer length registers that can be associated with each pointer.
Base values for pointers allow circular buffers to be placed at arbitrary locations. Each
DAG register has an alternate register that can be activated for fast context switching.
The program sequencer supplies instruction addresses to program memory. It controls
loop iterations and evaluates conditional instructions. To execute looped code with zero
overhead, the TSC21020F maintains an internal loop counter and loop stack. No explicit
jump or decrement instructions are required to maintain the loop.
The TSC21020F derives its high clock rate from pipelined fetch, decode and execute
cycles. Approximately 70% of the machine cycle is available for memory accesses; con-
sequently, TSC21020F systems can be built using slower and therefore less expensive
memory chips.
Instruction Cache
The program sequencer includes a high performance, selective instruction cache that
enables three-bus operation for fetching an instruction and two data values. This two-
way, set-associative cache holds 32 instructions. The cache is selective (only the
instructions whose fetches conflict with program memory data accesses are cached), so
the TSC21020F can perform a program memory data access and can execute the cor-
responding instruction in the same cycle. The program sequencer fetches the instruction
from the cache instead of from program memory, enabling the TSC21020F to simulta-
neously access data in both program memory and data memory.
Context Switching
Many of the TSC21020F's registers have alternate register sets that can be activated
during interrupt servicing to facilitate a fast context switch. The data registers in the reg-
ister file, DAG registers and the multiplier result register all have alternate sets.
Registers active at reset are called primary registers; the others are called alternate reg-
isters. Bits in the MODE1 control register determine which registers are active at any
particular time.
The primary/alternate select bits for each half of the register file (top eight or bottom
eight registers) are independent. Likewise, the top four and bottom four register sets in
each DAG have independent primary/alternate select bits. This scheme allows passing
of data between contexts.
Interrupts
The TSC21020F has four external hardware interrupts, nine internally generated inter-
rupts, and eight software interrupts. For the external interrupts and the internal timer
interrupt, the TSC21020F automatically stacks the arithmetic status and mode (MODE1)
registers when servicing the interrupt, allowing five nesting levels of fast service for
these interrupts.
An interrupt can occur at any time while the TSC21020F is executing a program. Inter-
nal events that generate interrupts include arithmetic exceptions, which allow for fast
trap handling and recovery.
Timer
The programmable interval timer provides periodic interrupt generation. When enabled,
the timer decrements a 32-bit count register every cycle. When this count register
reaches zero, the TSC21020F generates an interrupt and asserts its TIMEXP output.
The count register is automatically reloaded from a 32-bit period register and the count
resumes immediately.
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TSC21020F
System Interface
Figure 2 shows an TSC21020F basic system configuration.
The external memory interface supports memory- mapped peripherals and slower mem-
ory with a user-defined combination of programmable wait states and hardware
acknowledge signals. Both the program memory and data memory interfaces support
addressing of page-mode DRAMs.
The TSC21020F's internal functions are supported by four internal buses: the program
memory address (PMA) and data memory address (DMA) buses are used for
addresses associated with program and data memory. The program memory data
(PMD) and data memory data (DMD) buses are used for data associated with the two
memory spaces. These buses are extended off chip. Four data memory select (DMS)
signals select one of four user-configurable banks of data memory. Similarly, two pro-
gram memory select (PMS) signals select between two user-configurable banks of
program memory. All banks are independently programmable for 0-7 wait states.
The PX registers permit passing data between program memory and data memory
spaces. They provide a bridge between the 48-bit PMD bus and the 40-bit DMD bus or
between the 40-bit register file and the PMD bus.
The PMA bus is 24 bits wide allowing direct access of up to 16M words of mixed instruc-
tion code and data. The PMD is 48 bits wide to accommodate the 48-bit instruction
width. For access of 40-bit data the lower 8 bits are unused. For access of 32-bit data
the lower 16 bits are ignored.
The DMA bus is 32 bits wide allowing direct access of up to 4 Gigawords of data. The
DMD bus is 40 bits wide. For 32-bit data, the lower 8 bits are unused. The DMD bus pro-
vides a path for the contents of any register in the processor to be transferred to any
other register or to any external data memory location in a single cycle. The data mem-
ory address comes from one of two sources: an absolute value specified in the
instruction code (direct addressing) or the output of a data address generator (indirect
addressing).
Figure 2. Basic System Configuration
External devices can gain control of the processor's memory buses from the
TSC21020F by means of the bus request/grant signals (BR and BG). To grant its buses
in response to a bus request, the TSC21020F halts internal operations and places its
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4153H–AERO–04/07
program and data memory interfaces in a high impedance state. In addition, three-state
controls (DTMS and PMTS) allow an external device to place either the program or data
memory interface in a high impedance state without affecting the other interface and
without halting the TSC21020F unless it requires a memory access from the affected
interface. The three-state controls make it easy for an external cache controller to hold
the TSC21020F off the bus while it updates an external cache memory.
JTAG Test and Emulation The TSC21020F implements the boundary scan testing provisions specified by IEEE
Standard 1149.1 of the Joint Testing Action Group (JTAG). The TSC21020F's test
Support
access port and On-chip JTAG circuitry is fully compliant with the IEEE 1149.1 specifi-
cation. The test access port enables boundary scan testing of circuitry connected to the
TSC21020F's I/O pins.
The TSC21020F also implements On-chip emulation through the JTAG test access port.
The processor's eight sets of breakpoint range registers enable program execution at
full speed until reaching a desired breakpoint address range. The processor can then
halt and allow reading/writing of all the processor's internal registers and external mem-
ories through the JTAG port.
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TSC21020F
Pin Descriptions
This section describes the pins of the TSC21020F. When groups of pins are identified
with subscripts, e.g. PMD47-0, the highest numbered pin is the MSB (in this case,
PMD47). Inputs identified as synchronous (S) must meet timing requirements with
respect to CLKIN (or with respect to TCK for TMS, TDI, and TRST). Those that are
asynchronous (A) can be asserted asynchronously to CLKIN.
Note:
O = Output; I = Input; S = Synchronous; A = Asynchronous; P = Power Supply; G =
Ground.
Pin Name
Type
Function
Program Memory Address. The TSC21020F outputs an address in
program memory on these pins.
PMA23-0
O
Program Memory Data. The TSC21020F inputs and outputs data and
instructions on these pins. 32-bit fixed-point data and 32-bit single-
precision floating-point data is transferred over bits 47-16 of the PMD
bus.
PMD47-0
I/O
O
Program Memory Select lines. These pins are asserted as chip selects
for the corresponding banks of program memory. Memory banks must
be defined in the memory control registers. These pins are decoded
program memory address lines and provide an early indication of a
possible bus cycle.
PMS1-0
Program Memory Read strobe. This pin is asserted when the
TSC21020F reads from program memory.
PMRD
PMWR
PMACK
O
O
Program Memory Write strobe. This pin is asserted when the
TSC21020F writes to program memory.
Program Memory Acknowledge. An external device de-asserts this
input to add wait states to a memory access.
I/S
Program Memory Page Boundary. The TSC21020F asserts this pin to
signal that a program memory page boundary has been crossed.
Memory pages must be defined in the memory control registers.
PMPAGE
O
Program Memory Three-State Control. PMTS places the program
memory address, data, selects, and strobes in a high-impedance state.
If PMTS is asserted while a PM access is occurring, the processor will
halt and the memory access will not be completed. PMACK must be
asserted for at least one cycle when PMTS is de-asserted to allow any
pending memory access to complete properly. PMTS should only be
asserted (low) during an active memory access cycle.
PMTS
I/S
Data Memory Address. The TSC21020F outputs an address in data
memory on these pins.
DMA31-0
DMD39-0
O
Data Memory Data. The TSC21020F inputs and outputs data on these
pins. 32-bit fixed-point data and 32-bit single-precision floating-point
data is transferred over bits 39-8 of the DMD bus.
I/O
Data Memory Select lines. These pins are asserted as chip selects for
the corresponding banks of data memory. Memory banks must be
defined in the memory control registers. These pins are decoded data
memory address lines and provide an early indication of a possible bus
cycle.
DMS3-0
O
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Pin Name
Type
Function
Data Memory Read strobe. This pin is asserted when the TSC21020F
reads from data memory.
DMRD
O
Data Memory Write strobe. This pin is asserted when the TSC21020F
writes to data memory.
DMWR
O
Data Memory Acknowledge. An external device de-asserts this input to
add wait states to a memory access.
DMACK
I/S
Data Memory Page Boundary. The TSC21020F asserts this pin to
signal that a data memory page boundary has been crossed. Memory
pages must be defined in the memory control registers.
DMPAGE
O
I/S
I
Data Memory Three-State Control. DMTS places the data memory
address, data, selects, and strobes in a high-impedance state. If DMTS
is asserted while à DM access is occurring, the processor will halt and
the memory access will not be completed. DMACK must be asserted
for at least one cycle when DMTS is de-asserted to allow any pending
memory access to complete properly. DMTS should only be asserted
(low) during an active memory access cycle.
DMTS
External clock input to the TSC21020F. The instruction cycle rate is
equal to CLKIN. CLKIN may not be halted, changed, or operated below
the specified frequency.
CLKIN
Sets the TSC21020F to a known state and begins execution at the
program memory location specified by the hardware reset vector
(address). This input must be asserted (low) at power-up.
RESET
IRQ3-0
I/A
I/A
Interrupt request lines; may be either edge-riggered or level-sensitive.
External Flags. Each is configured via control bits as either an input or
output. As an input, it can be tested as a condition. As an output, it can
be used to signal external peripherals.
FLAG3-0
I/O/A
Bus Request. Used by an external device to request control of the
memory interface. When BR is asserted, the processor halts execution
after completion of the current cycle, places all memory data,
addresses, selects, and strobes in a high-impedance state, and
asserts BG. The processor continues normal operation when BR is
released.
BR
BG
I/A
Bus Grant. Acknowledges a bus request (BR), indicating that the
external device may take control of the memory interface. BG is
asserted (held low) until BR is released.
O
O
Timer Expired. Asserted for four cycles when the value of TCOUNT is
decremented to zero.
TIMEXP
RCOMP
Not available
Can be set to any voltage level.
EVDD
EGND
IVDD
P
G
P
Power supply (for output drivers), nominally + 5V dc (10 pins).
Power supply return (for output drivers); (16 pins).
Power supply (for internal circuitry), nominally + 5V dc (4 pins).
Power supply return (for internal circuitry); (7 pins).
IGND
G
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TSC21020F
Pin Name
Type
Function
TCK
I
Test Clock. Provides an asynchronous clock for JTAG boundary scan.
Test Mode Select. Used to control the test state machine. TMS has a
20 kΩ internal pull-up resistor.
TMS
I/S
Test Data Input. Provides serial data for the boundary scan logic. TDI
has a 20 kΩ internal pull-up resistor.
TDI
I/S
O
TDO
Test Data Output. Serial scan output of the boundary scan path.
Test Reset. Resets the test state machine. TRST must be asserted
(pulsed low) after power-up or held low for proper operation of the
TSC21020F. TRST has a 20 kΩ internal pull-up resistor.
TRST
NC
I/A
No Connect. No Connects are reserved pins that must be left open and
unconnected.
Table 1. PGA Pin Configuration
PGA
Pin
PGA
Pin
Pin
Pin
PGA
Location
PGA
Location
Location
Name
Location
Name
Name
Name
G16
G17
F18
F17
F16
F15
E18
E17
E16
D18
E15
D17
D16
C18
C17
D15
B18
B17
C16
D14
C15
B16
DMA0
B5
DMD25
DMD26
DMD27
DMD28
DMD29
DMD30
DMD31
DMD32
DMD33
DMD34
DMD35
DMD36
DMD37
DMD38
DMD39
DMS0
K1
L3
PMD9
L16
U12
T11
T14
R12
S13
U16
U14
H18
A3
TIMEXP
RCOMP
CLKIN
TRST
TD0
DMA1
B6
PMD10
PMD11
PMD12
PMD13
PMD14
PMD15
PMD16
PMD17
PMD18
PMD19
PMD20
PMD21
PMD22
PMD23
PMD24
PMD25
PMD26
PMD27
PMD28
PMD29
PMD30
DMA2
D6
L2
DMA3
C6
M1
M2
M3
M4
N2
N3
P1
P2
N4
S1
P3
R2
P4
R3
S2
T1
S3
R4
T2
DMA4
A8
DMA5
C7
TDI
DMA6
D7
TMS
DMA7
B7
TCK
DMA8
B8
EGND
EGND
EGND
EGND
EGND
EGND
EGND
EGND
EGND
EGND
EGND
EGND
EGND
EGND
DMA9
A10
C8
DMA10
DMA11
DMA12
DMA13
DMA14
DMA15
DMA16
DMA17
DMA18
DMA19
DMA20
DMA21
A7
D8
A11
A15
E1
B9
C9
B10
D10
C11
A12
B11
T13
S11
B12
G1
L1
DMS1
L18
R1
DMS2
DMS3
R18
T18
U5
DMWR
DMRD
DMPAGE
U7
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Table 1. PGA Pin Configuration (Continued)
PGA
Pin
PGA
Pin
Pin
Pin
PGA
Location
PGA
Location
Location
Name
Location
Name
Name
Name
A16
D13
C14
B15
B14
D12
C13
A14
B13
C12
H3
DMA22
DMA23
DMA24
DMA25
DMA26
DMA27
DMA28
DMA29
DMA30
DMA31
DMD0
S12
T12
L17
M18
M15
M16
M17
N17
N16
N15
P18
P17
R17
S18
P15
P16
S17
R16
R15
U18
S16
T17
U17
R14
S15
T16
F2
DMTS
DMACK
PMA0
PMA1
PMA2
PMA3
PMA4
PMA5
PMA6
PMA7
PMA8
PMA9
PMA10
PMA11
PMA12
PMA13
PMA14
PMA15
PMA16
PMA17
PMA18
PMA19
PMA20
PMA21
PMA22
PMA23
PMD0
PMD1
PMD2
PMD3
PMD4
PMD5
PMD6
PMD7
PMD8
U1
PMD31
PMD32
PMD33
PMD34
PMD35
PMD36
PMD37
PMD38
PMD39
PMD40
PMD41
PMD42
PMD43
PMD44
PMD45
PMD46
PMD47
PMS0
U11
U15
D11
G4
EGND
EGND
IGND
IGND
IGND
IGND
IGND
IGND
IGND
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
IVDD
IVDD
IVDD
IVDD
NC
T3
R5
S4
U2
G15
L4
S5
T4
L15
R7
R6
U3
R11
A5
U4
S6
A9
H4
DMD1
T6
A13
J1
E2
DMD2
S7
G3
D1
DMD3
U6
J18
N1
DMD4
T7
D2
DMD5
R8
N18
U9
F3
DMD6
S8
C1
DMD7
R13
T15
U8
U13
K18
D9
C2
DMD8
PMS1
F4
DMD9
PMWR
PMRD
PMPAGE
PMTS
E3
DMD10
DMD11
DMD12
DMD13
DMD14
DMD15
DMD16
DMD17
DMD18
DMD19
DMD20
DMD21
DMD22
DMD23
DMD24
S9
J4
D3
S14
T8
J15
R9
B1
E4
U10
A17
A18
H16
H15
H17
G18
J17
J16
K16
K15
R10
PMACK
BG
C10
S10
T10
T9
B2
NC
C3
BR
NC
A2
FLAG0
FLAG1
FLAG2
FLAG3
IRQ0
NC
D4
F1
K17
T5
NC
B3
J3
NC
A4
H2
G2
NC
C4
H1
B4
J2
IRQ1
D5
K4
IRQ2
A6
K3
IRQ3
C5
K2
RESET
14
TSC21020F
4153H–AERO–04/07
TSC21020F
Table 2. MQFP Pin Configuration
MQFP_F
Location
Pin
MQFP_F
Location
Pin
MQFP_F
Location
Pin
MQFP_F
Location
Pin
Name
Name
Name
Name
1
IGND
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
IGND
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
IGND
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
IGND
2
IVDD
IVDD
IVDD
IVDD
3
DMD19
DMD18
DMD17
DMD16
EGND
DMD15
DMD14
DMD13
DMD12
EVDD
DMD11
DMD10
DMD9
DMD8
IGND
PMD25
PMD26
PMD27
EVDD
PMA19
PMA18
PMA17
PMA16
EGND
PMA15
PMA14
PMA13
PMA12
EVDD
PMA11
PMA10
PMA9
PMA8
IGND
DMA15
EGND
DMA16
DMA17
DMA18
DMA19
EVDD
DMA20
DMA21
DMA22
DMA23
EGND
DMA24
DMA25
IGND
4
5
6
7
PMD28
PMD29
PMD30
PMD31
EGND
PMD32
PMD33
PMD34
PMD35
EVDD
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
IGND
IVDD
IVDD
IVDD
IVDD
EGND
DMD7
DMD6
DMD5
DMD4
EVDD
DMD3
DMD2
DMD1
DMD0
EGND
PMD0
PMD1
PMD2
IGND
PMD36
PMD37
PMD38
PMD39
EGND
PMD40
PMD41
PMD42
PMD43
EVDD
EGND
PMA7
PMA6
PMA5
PMA4
EVDD
PMA3
PMA2
PMA1
PMA0
EGND
TIMEXP
EVDD
EGND
IGND
DMA26
DMA27
EVDD
DMA28
DMA29
DMA30
DMA31
EGND
DMPAGE
BR
PMD44
PMD45
PMD46
PMD47
IGND
BG
DMS0
DMS1
EVDD
IGND
IVDD
IVDD
IVDD
IVDD
PMD3
EGND
IRQ3
DMS2
15
4153H–AERO–04/07
Table 2. MQFP Pin Configuration (Continued)
MQFP_F
Location
Pin
MQFP_F
Location
Pin
MQFP_F
Location
Pin
MQFP_F
Location
Pin
Name
Name
Name
Name
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
EVDD
PMD4
PMD5
PMD6
PMD7
EGND
PMD8
PMD9
PMD10
PMD11
EVDD
PMD12
PMD13
IGND
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
PMTS
PMWR
PMACK
PMRD
RCMP
EVDD
RESET
CLKIN
DMRD
DMACK
DMWR
EVDD
DMTS
IGND
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
IRQ2
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
DMS3
IRQ1
DMD39
DMD38
EGND
IRQ0
EVDD
FLAG0
FLAG1
FLAG2
FLAG3
EGND
DMA0
DMA1
DMA2
DMA3
IGND
DMD37
DMD36
DMD35
DMD34
EVDD
DMD33
DMD32
DMD31
DMD30
IGND
IVDD
IVDD
IVDD
IVDD
PMD14
PMD15
EGND
PMD16
PMD17
PMD18
PMD19
EVDD
PMD20
PMD21
PMD22
PMD23
EGND
PMD24
TCK
EVDD
DMA4
DMA5
DMA6
DMA7
EGND
DMA8
DMA9
DMA10
DMA11
EVDD
DMA12
DMA13
DMA14
EGND
TMS
DMD29
DMD28
DMD27
DMD26
EVDD
TDI
TDO
TRST
PMPAGE
PMS0
PMS1
EGND
PMA23
PMA22
PMA21
PMA20
EVDD
DMD25
DMD24
DMD23
EGND
DMD22
DMD21
DMD20
EVDD
Instruction Set
Summary
The TSC21020F instruction set provides a wide variety of programming capabilities.
Every instruction assembles into a single word and can execute in a single processor
cycle. Multifunction instructions enable simultaneous multiplier and ALU operations, as
well as computations executed in parallel with data transfers. The addressing power of
the TSC21020F gives flexibility in moving data both internally and externally. The
TSC21020F assembly language uses an algebraic syntax for ease of coding and
readability.
16
TSC21020F
4153H–AERO–04/07
TSC21020F
The instruction types are grouped into four categories:
•
•
•
•
Compute and Move or Modify
Program Flow Control
Immediate Move
Miscellaneous
The instruction types are numbered; there are 22 types. Some instructions have more
than one syntactical form; for example, Instruction 4 has four distinct forms. The instruc-
tion number itself has no bearing on programming, but corresponds to the opcode
recognized by the TSC21020F device.
Because of the width and orthogonality of the instruction word, there are many possible
instructions. For example, the ALU supports 21 fixed-point operations and 24 floating-
point operations; each of these operations can be the compute portion of an instruction.
The following pages provide an overview and summary of the TSC21020F instruction
set. For complete information, see the ADSP-21020 User's Manual from Analog
Devices. For additional reference information, see the ADSP- 21020 Programmer's
Quick Reference from Analog Devices.
This section also contains several reference tables for using the instruction set.
•
•
•
•
Table 3 describes the notation and abbreviations used.
Table 4 lists all condition and termination code mnemonics.
Table 5 lists all register mnemonics.
Table 6 through 9 list the syntax for all compute (ALU, multiplier, shifter or
multifunction) operations.
•
Table 10 lists interrupts and their vector addresses.
17
4153H–AERO–04/07
Compute and Move or Modify Instructions
1.
compute,
compute ;
|
|
DM(Ia, Mb) = dreg1
dreg1= DM(Ia, Mb)
|
|
|
|
PM(Ic, Md) = dreg2
dreg2 =PM5Ic, Md)
|
|
2.
IF condition
IF condition
3a.
compute,
|
|
|
|
DM(Mb, Ia)
PM(Ic, Md)
DM(Mb, Ia)
PM(Md, Ic)
|
|
|
|
= ureg ;
= ureg ;
3b.
IF condition
compute,
3c.
3d.
4a.
4b.
4c.
4d.
IF condition
IF condition
IF condition
IF condition
IF condition
IF condition
compute,
compute,
compute,
compute,
compute,
compute,
ureg =
ureg =
|
|
|
|
DM(Ia, Mb)
PM(Ic, Md)
DM(Mb, Ia)
PM(Md, Ic)
|
;
;
|
|
|
|
|
|
|
DM(Ia, < data6 >)
|
= dreg ;
PM(Ic, < data6 >)
|
DM(Ia, < data6 >,Ia)
|
|
|
|
= dreg ;
PM(Ic, < data6 >,Ic)
dreg =
|
|
|
|
DM(Mb, Ia)
PM(Md, Ic)
dreg =
DM(Ia, < data6 >,Ia)
PM(Ic, < data6 >,Ic)
|
|
;
5.
IF condition
IF condition
compute, ureg1 = ureg2;
6a.
shiftimm,
shiftimm,
compute,
|
|
|
|
DM(Ia, Mb)
PM(Ic, Md)
DM(Ia, Mb)
PM(Ic, Md)
|
|
|
|
= dreg ;
= dreg ;
6b.
7.
IF condition
IF condition
MODIFY
|
|
DM(Ia, Mb)
PM(Ic, Md)
|
|
;
Program Flow Control Instructions
8.
IF condition
IF condition
IF condition
LCNTR =
|
|
JUMP| |
CALL| |(PC, < reladdr24 >)
< addr24 >
|
|
(
(
|
DB
LA
DB,LA
DB );
LA
DB,LA
|
);
|
|
|
|
|
|
9.
|
|
JUMP| |
CALL| |(PC, < reladdr6 >)
< Md, Ic >
|
|
|
|
|
|
11.
|
|
RTS
RTI
|
(
|
DB
|
), compute ;
|
|
LA
|
|
DB,LA
|
< addr24 >
12.
13.
|
|
< data16 >
ureg
|
|
DO
,DO
|
|
|
UNTIL LCE;
|
< addr24 >
(PC, < reladdr24 >)
|
UNTIL termination;
|
|
(PC, < reladdr24 >)
|
Note:
DB = Delayed Branch
LA = Loop abort (pop loop PC stacks on branch)
Immediate Move Instructions
14a.
|
DM < addr32 >
|
= ureg ;
18
TSC21020F
4153H–AERO–04/07
TSC21020F
|
PM < addr24 >
|
14b.
15a.
15b.
16.
ureg =
|
|
DM < addr32 >| ;
PM < addr24 >
= ureg ;
|
|
|
DM (< data32 >, Ia)
PM (< data24 >, Ic)
|
|
ureg =
|
|
DM < data32 >, Ia
PM < data24 >, Ic
|
|
;
|
|
DM(Ia,Mb)
PM(Ic,Md)
|
|
= < data32 >;
17.
ureg = < data32 >;
Miscellaneous Instructions
18.
BIT
|
|
|
|
|
SET
CLR
TGL
TST
XOR
|
|
|
|
sreg < data32 > :
|
19a. MODIFY
19b. BITREV
|
|
(Ia, < data32 >
Ic < data32 >
| ;
|
(Ia, < data32 >) ;
20.
|
|
PUSH
POP
|
|
LOOP,
|
|
PUSH
POP
|
|
STS ;
21.
22.
NOP;
IDLE;
Table 3. Syntax Notation Conventions
Notation Meaning
Explicit syntax - assembler keyword (notation only; assembler is not case-
UPPERCASE sensitive and lowercase is the preferred programming convention)
;
Instruction terminator
,
Separates parallel operations in an instruction
Optional part of instruction
italics
|
between lines
|
List of options (choose one)
<datan>
<addrn>
<reladdrn>
compute
n-bit immediate data value
n-bit immediate address value
n-bit immediate PC-relative address value
ALU, multiplier, shifter or multifunction operation (from Tables 4-7)
Shifter immediate operation (from Table 6)
Status condition (from Table 2)
shiftimm
condition
termination
Termination condition (from Table 2)
19
4153H–AERO–04/07
Table 3. Syntax Notation Conventions
Notation
ureg
sreg
dreg
Ia
Meaning
Universal register (from Table 3)
System register (from Table 3)
R15-R0, F15-F0; register file location
I7-I0; DAG1 index register
M7-M0; DAG1 modify register
I15-I8; DAG2 index register
M15-M8; DAG2 modify register
Mb
Ic
Md
20
TSC21020F
4153H–AERO–04/07
TSC21020F
Table 4. Condition and Termination Codes
Name
Description
eq
ALU equal to zero
ALU not equal to zero
ALU greater than or equal to zero
ALU less than zero
ALU less than or equal to zero
ALU greater than zero
ALU carry
ne
ge
lt
le
gt
ac
not ac
av
Not ALU carry
ALU overflow
not av
mv
Not ALU overflow
Multiplier overflow
Not multiplier overflow
Multiplier sign
not mv
ms
not ms
sv
Not multiplier sign
Shifter overflow
Not shifter overflow
Shifter zero
not sv
sz
not sz
flag0_in
not flag0_in
flag1_in
not flag1_in
flag2_in
not flag2_in
flag3_in
not flag3_in
tf
Not shifter zero
Flag 0
Not Flag 0
Flag 1
Not Flag 1
Flag 2
Not Flag 2
Flag 3
Not Flag 3
Bit test flag
not tf
lce
Not bit test flag
Loop counter expired (DO UNTIL)
Loop counter not expired (IF)
Always False (DO UNTIL)
Always True (IF)
not lce
forever
true
Note:
In a conditional instruction, the execution of the entire instruction is based on the speci-
fied condition.
21
4153H–AERO–04/07
Table 5. Universal Registers
Name
Function
Register file
R15-R0
Register file locations
Program Sequencer
PC(1)
Program counter; address of instruction currently executing
PCSTK
Top of PC stack
PCSTKP
FADDR(1)
DADDR(1)
LADDR
PC stack pointer
Fetch address
Decode address
Loop termination address, code; top of loop address stack
Current loop counter; top of loop count stack
Loop count for next nested counter-controlled loop
CURLCNTR
LCNTR
Data Address Generators
I7-I0
DAG1 index registers
M7-M0
L7-L0
DAG1 modify registers
DAG1 length registers
DAG1 base registers
DAG2 index registers
DAG2 modify registers
DAG2 length registers
DAG2 base registers
B7-B0
I15-I8
M15-M8
L15-L8
B15-B8
Bus Exchange
PX1
PMD-DMD bus exchange 1 (16 bits)
PMD-DMD bus exchange 2 (32 bits)
48-bit PX1 and PX2 combination
PX2
PX
Timer
TPERIOD
TCOUNT
Timer period
Timer counter
Memory Interface
DMWAIT
Wait state and page size control for data memory
DMBANK1
DMBANK2
Data memory bank 1 upper boundary
Data memory bank 2 upper boundary
22
TSC21020F
4153H–AERO–04/07
TSC21020F
Table 5. Universal Registers (Continued)
Name
Function
DMBANK3
DMADR(1)
PMWAIT
Data memory bank 3 upper boundary
Copy of last data memory address
Wait state and page size control for program memory
Program memory bank 1 upper boundary
Copy of last program memory address
PMBANK1
PMADR(1)
System Register
Mode control bits for bit-reverse, alternate registers, interrupt nesting and
enable, ALU saturation, floating-point rounding mode and boundary
MODE1
Mode control bits for interrupt sensitivity, cache disable and freeze, timer
enable, and I/O flag configuration
MODE2
IRPTL
Interrupt latch
IMASK
IMASKP
ASTAT
Interrupt mask
Interrupt mask pointer (for nesting)
Arithmetic status flags, bit test, I/O flag values, and compare accumulator
Sticky arithmetic status flags, circular buffer overflow flags, stack status flags
(not sticky)
STKY
USTAT1
USTAT2
User status register 1
User status register 2
Note:
1. Read-only
Refer to User's Manual for bit-level definitions of each register.
Table 6. ALU Compute Operations
Fixed-Point
Floating-Point
Fn = Fx + Fy
Rn = Rx + Ry
Rn = Rx - Ry
Fn = Fx - Fy
Rn = Rx + Ry, Rm = Rx - Ry
Rn = Rx + Ry + CI
Rn = Rx - Ry + CI - 1
Rn = (Rx + Ry)/2
COMP(Rx, Ry)
Fn = Fx + Fy, Fm = Fx - Fy
Fn = ABS (Fx + Fy)
Fn = ABS (Fx - Fy)
Fn = (Fx + Fy)/2
COMP(Fx, Fy)
Fn = -Fx
Rn = -Rx
Rn = ABS Rx
Fn = ABS Fx
Rn = PASS Rx
Fn = PASS Fx
Rn = MIN(Rx, Ry)
Rn = MAX(Rx, Ry)
Fn = MIN(Fx, Fy)
Fn = MAX(Fx, Fy)
23
4153H–AERO–04/07
Table 6. ALU Compute Operations (Continued)
Fixed-Point
Floating-Point
Rn = CLIP Rx BY Ry
Rn = Rx + CI
Fn = CLIP Fx BY Fy
Fn = RND Fx
Rn = Rx + CI - 1
Rn = Rx + 1
Fn = SCALB Fx BY Ry
Rn = MANT Fx
Rn = Rx - 1
Rn = LOGB Fx
Rn = Rx AND Ry
Rn = Rx OR Ry
Rn = Rx XOR Ry
Rn = NOT Rx
Rn = FIX Fx BY Ry
Rn = FIX Fx
Fn = FLOAT Rx BY Ry
Fn = FLOAT Rx
Fn = RECIPS Fx
Fn = RSQRTS Fx
Fn = Fx COPYSIGN Fy
Note:
Rn, Rx, Ry R15-R0; register file location, fixed-point
Fn, Fx, Fy F15-F0; register file location, floating point
24
TSC21020F
4153H–AERO–04/07
TSC21020F
Multiplier Compute
Operations
Rn
MRF
MRB
= Rx *Ry(
S
S
U
)
Fn
= Fx * Fy
F
I
U
FR
F
I
F
I
+ Rx * Ry S S
U U
)
Rx * Ry (S S
U U
)
Rn
=
MR F
Rn = MR F
Rn = MR B
MRF MR F
MRB = MR B
Rn = MR B
MR F = MR F
MRB = MR B
FR
FR
=
(SF)
RND MRF
(SI)
(UI)
(SF)
(UF)
Rn
Rn
Rn = SAT MRF
RND MRB
RND MRF
RND MRB
Rn = SAT MRB
MRF = SAT MRF
MRB = SAT MRB
(UF)
MR F
MRB
= 0
= Rn
MRF
MRB
Rn
=
xF
MR
MRxB
MRxF
MRxB
Rn, Rx, Ry R15-R0; register file location, fixed-point
Fn, Fx, Fy F15-F0; register file location, floating-point
MRxF
MRxB
MR2F, MR1F, MR0F; multiplier result accumulators, foreground
MR2B, MR1B, MR0B; multiplier result accumulators, background
(
|
x-input| |y-input| |data format
|)
|
rounding
|
S
Signed input
U
I
F
Unsigned input
Integer input(s)
Fractional input(s)
FR
(SF)
(SSF)
Fractional inputs, Rounded output
Default format for 1-input operations
Default format for 2-input operations
25
4153H–AERO–04/07
Table 7. Shifter and Shifter Immediate Compute Operations
Shifter
Shifter Immediate
Rn = LSHIFT Rx BY Ry
Rn = Rn OR LSHIFT Rx BY Ry
Rn = ASHIFT Rx BY Ry
Rn = Rn OR ASHIFT Rx BY Ry
Rn = ROT Rx BY RY
Rn = BCLR Rx BY Ry
Rn = BSET Rx BY Ry
Rn = BTGL Rx BY Ry
BTST Rx BY Ry
Rn = LSHIFT Rx BY<data8>
Rn = Rn OR LSHIFT Rx BY<data8>
Rn = ASHIFT Rx BY<data8>
Rn = Rn OR ASHIFT Rx BY<data8>
Rn = ROT Rx BY<data8>
Rn = FDEP Rx BY Ry
Rn = Rn OR FDEP Rx BY Ry
Rn = FDEP Rx BY Ry (SE)
Rn = Rn OR FDEP Rx BY Ry (SE)
Rn = FEXT Rx BY Ry
Rn = FEXT Rx BY Ry (SE)
Rn = EXP Rx
Rn = BCLR Rx BY<data8>
Rn = BSET Rx BY<data8>
Rn = BTGL Rx BY<data8>
BTST Rx BY<data8>
Rn = FDEP Rx BY <bit6>: <len6>
Rn = Rn OR FDEP Rx BY <bit6>: <len6>
Rn = FDEP Rx BY <bit6>: <len6> (SE)
Rn = Rn OR FDEP Rx BY (bit6>: <len6> (SE)
Rn = FEXT Rx BY <bit6>: <len6>
Rn = FEXT Rx BY <bit6>: <len6> (SE)
Rn = EXP Rx (EX)
Rn = LEFTZ Rx
Rn = LEFTO Rx
Note:
Rn, Rx, Ry R15-R0; register file location, fixed-point
<bit6>: <len6> 6-bit immediate bit position and length values (for shifter immediate
operations)
Table 8. Multifunction Compute Operations
Fixed-Point
Rm = R3-0 (1) R7-4 (SSFR), Ra = R11-8 + R15-12
Rm = R3-0 (1) R7-4 (SSFR), Ra = R11-8 - R15-12
Rm = R3-0 (1) R7-4 (SSFR), Ra = (R11-8 + R15-12)/2
MRF = MRF + R3-0 (1) R7-4 (SSF), Ra = R11-8 + R15-12
MRF = MRF + R3-0 (1) R7-4 (SSF), RA = R11-8 - R15-12
MRF = MRF + R3-0 (1) R7-4 (SSF), Ra = (R11-8 + R15-12)/2
Rm = MRF + R3-0 (1) R7-4 (SSFR), Ra = R11-8 + R15-12
Rm = MRF + R3-0 (1) R7-4 (SSFR), Ra = R11-8 - R15-12
Rm = MRF + R3-0 (1) R7-4 (SSFR), Ra = (R11-8 + R15-12)/2
MRF = MRF - R3-0 (1) R7-4 (SSF), Ra = R11-8 + R15-12
MRF = MRF - R3-0 (1) R7-4 (SSF), Ra = R11-8 - R15-12
MRF = MRF - R3-0 (1) R7-4 (SSF), Ra = R11-8 + R15-12)/2
Rm = MRF - R3-0 (1) R7-4 (SSFR), Ra = R11-8 + R15-12
Rm = MRF - R3-0 (1) R7-4 (SSFR), Ra = R11-8 - R15-12
Rm = MRF - R3-0 (1) R7-4 (SSFR), Ra = (R11-8 + R15-12)/2
Rm = R3-0 (1) R7-4 (SSFR), Ra = R11-8 + R15-12,
Rs = R11-8 - R15-12
26
TSC21020F
4153H–AERO–04/07
TSC21020F
Table 9. Multifunction Compute Operations
Floating-Point
Fm = F3-0 (1) F7-4, Fa = F11-8 + F15-12
Fm = F3-0 (1) F7-4, Fa = F11-8 - F15-12
Fm = F3-0 (1) F7-4, Fa = FLOAT R11-8 by R15-12
Fm = F3-0 (1) F7-4, Fa = FIX R11-8 by R15-12
Fm = F3-0 (1) F7-4, Fa = (F11-8 + F15-12)/2
Fm = F3-0 (1) F7-4, Fa = ABS F11-8
Fm = F3-0 (1) F7-4, Fa = MAX (F11-8, F15-12)
Fm = F3-0 (1) F7-4, Fa = MIN (F11-8 + F15-12)
Fm = F3-0 (1) F7-4, Fa = F11-8 + F15-12,
Fs = F11-8 - F15-12
Ra, Rm Any register file location (fixed-point)
R3-0 R3, R2, R1, R0
R7-4 R7, R6, R5, R4
R11-8 R11, R10, R9, R8
R15-12 R15, R14, R13, 12
Fa, Fm Any register file location (floating-point)
F3-0 F3, F2, F1, F0
F7-4 F7, F6, F5, F4
F11-8 F11, F10, F9, F8
F15-12 F15, F14, F13, F12
(SSF) X-input signed, Y-input signed, fractional inputs
(SSFR) X-input signed, Y-input signed, fractional inputs, rounded output
Table 10. Interrupt Vector Addresses and Priorities
No
0
Vector Address (Hex) Function
0x00
0x08
0x10
0x18
0x20
0x28
0x30
0x38
0x40
0x48
0x50
0x58
0x60
Reserved
Reset
1(1)
2
Reserved
3
Status stack or loop stack overflow or PC stack full
Timer = 0 (high priority option)
IRQ3 asserted
4
5
6
IRQ2 asserted
7
IRQ1 asserted
8
IRQ0 asserted
9
Reserved
10
11
12
Reserved
DAG 1 circular buffer 7 overflow
DAG 2 circular buffer 15 overflow
27
4153H–AERO–04/07
Table 10. Interrupt Vector Addresses and Priorities (Continued)
No
13
Vector Address (Hex) Function
0x68
Reserved
14
0x70
Timer = 0 (low priority option)
Fixed-point overflow
Floating-point overflow
Floating-point underflow
Floating-point invalid operation
Reserved
15
0x78
16
0x80
17
0x88
18
0x90
19-23
0x98-0xB8
24-31
Note:
0xC0-OxF8
User software interrupts
1. Nonmaskable
28
TSC21020F
4153H–AERO–04/07
TSC21020F
Electrical Characteristics
Absolute Maximum Ratings
*Note:
Stresses above those listed under "Absolute
Supply Voltage.....................................................-0.5V to + 7V
Maximum Ratings" may cause permanent dam-
age to the device. These are stress ratings only
and functional operation of the device at these or
any other conditions above those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Input Voltage............................................ -0.5V to VDD + 0.5V
Output Voltage Swing .............................. -0.5V to VDD + 0.5V
Load Capacitance..........................................................200 pF
Operating Temperature Range (Ambient)..... -55°C to + 125°C
Storage Temperature Range ........................ -65°C to + 150°C
Recommended Operating Conditions
Mil Range
Parameter
Min
4.50
-55
Max
5.50
+125
Unit
V
V
DDSupply Voltage
TAMBAmbient Operating Temperature
°C
ESD Sensitivity
The TSC21020F features proprietary input protection circuitry to dissipate high-energy
discharges (Human Body Model). Per method 3015 of MIL-STD-883, the TSC21020F
has been classified as a Class 2 devices, with the ability to withstand up to 2000V ESD.
Prosper ESD precautions are strongly recommended to avoid functional damage or per-
formance degradation. Charges readily accumulate on the human body and test
equipment and discharge without detection. Unused devices must be stored in conduc-
tive foam or shunts, and the foam should be discharged to the destination socket before
devices are removed.
DC Parameters
Parameter
Test Conditions
VDD = max
Min
2.0
3.0
Max
Unit
V
V
IH Hi-Level Input Voltage1
VIHCR Hi-Level Input Voltage2, 12
VIL Lo-Level Input Voltage1, 12
VILC Lo-Level Input Voltage2
VOH Hi-Level Output Voltage3, 11
VDD = max
V
VDD = min
0.8
0.6
V
VDD = min
V
VDD = min, IOH = -1.0 mA
VDD = min, IOL = 4.0 mA
VDD = max, VIN = VDD max
VDD = max, VIN = 0V
VDD = max, VIN = 0V
VDD = max, VIN = 0V
2.4
V
V
OL Lo-Level Output Voltage3, 11
0.4
10
V
IIH Hi-Level Input Current4, 5
IIL Lo-Level Input Current4
IILT Lo-Level Input Current5
IOZL Tristate Leakage Current6
IDDIN Supply Current (Internal)7
µA
µA
µA
µA
mA
10
350
10
tCK = 50 ns, VDD = max, VIHCR = 3.0V,
VIH = 2.4V, VIL = VILC = 0.4V
430
29
4153H–AERO–04/07
Parameter
Test Conditions
Min
Max
150
10
Unit
mA
pF
IDDIDLE Supply Current (Idle)8
CIN Input Capacitance9, 10
VDD = max, VIN = 0V or VDD max
fIN = 1 MHz, TCASE = 255C, VIN = 2.5V
Notes: 1. Applies to: PMD47-0, PMACK, PMTS, DMD39-0, DMACK, DMTS, IRQ3-0, FLAG3-0, BR, TMS, TDI.
2. Applies to: CLKIN, TCK.
3. Applies to: PMA23-0, PMD47-0, PMS1-0, PMRD, PMWR, PMPAGE, DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR,
DMPAGE, FLAG3-0, TIMEXP, BG.
4. Applies to: PMACK, PMTS, DMACK, DMTS, IRQ3-0, BR, CLKIN, RESET, TCK.
5. Applies to: TMS, TDI, TRST.
6. Applies to: PMA23-0, PMD47-0, PMS1-0, PMRD, PMWR, PMPAGE, DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR,
DMPAGE, FLAG3-0, TDO.
7. Applies to IVDD pins. At tCK = 50ns, IDDIN (typical) = 350 mA. See "Power Dissipation" for calculation of external (EVDD)
supply current for total supply current.
8. Applies to IVDD pins. Idle refers to TSC21020F state of operation during execution of the IDLE instruction.
9. Guaranteed but not tested.
10. Applies to all signal pins.
11. Although specified for TTL outputs, all TSC21020F outputs are CMOS-compatible and will drive to VDD and GND assuming
no dc loads.
12. Applies to RESET, TRST.
AC Parameters
See Figure 15 for voltage reference levels. Use the exact timing information given. Do
not attempt to derive parameters from the addition or subtraction of others. While addi-
tion or subtraction would yield meaningful results for an individual device, the values
given in this data sheet reflect statistical variations and worst cases. Consequently, you
cannot meaningfully add parameters to derive other specifications.
30
TSC21020F
4153H–AERO–04/07
TSC21020F
Clock Signal
20 MHz
Parameter
Min
50
Max
Unit
ns
TCK CLKIN Period
150
tCKH CLKIN Width High
tCKL CLKIN Width Low
10
ns
10
ns
Figure 3. Clock
Reset
Frequency
Dependency(1)
20 MHz
Parameter
Min
Max
Min
Max
Unit
ns
tWRST(2) RESET Width Low
200
29
4tCK
tSRST(3) RESET Setup
before CLKIN High
50
29 + DT/2
30
ns
Notes: 1. DT = tCK - 50 ns
2. Applies after the power-up sequence is complete. At power up, the Internal Phase
Locked Loop requires no more than 1000CLKIN cycles while RESET is low, assum-
ing stable VDD and CLKIN (not including clock oscillator start-up time).
3. Specification only applies in cases where multiple TSC21020F processors are
required to execute in program counter lock-step (all processors start execution at
location 8 in the same cycle). See the Hardware Configuration chapter of the
ADSP-21020 User's Manual from Analog Devices for reset sequence information.
31
4153H–AERO–04/07
Figure 4. Reset
Interrupts
20 MHz
Min
38
Parameter
Frequency
Dependency(1)
Unit
ns
tSIR IRQ3-0 Setup before CLKIN High
tHIR IRQ3-0 Hold after CLKIN High
38 + 3DT/4
tCK + 5
0
ns
t
IPW IRQ3-0 Pulse Width
55
ns
Note: 1. DT = tCK - 50 ns
Meeting setup and hold guarantees interrupts will be latched in that cycle. Meeting
the pulse width is not necessary if the setup and hold is met. Likewise, meeting the
setup and hold is not necessary if the pulse width is met. See the Hardware Config-
uration chapter of the ADSP-21020 User's Manual from Analog Devices for interrupt
servicing information.
Figure 5. Interrupts
Timer
Frequency
Dependency(1)
20 MHz
Max
Unit
Parameter
Min
Max
tDTEX CLKIN High to TIMEXP
24
ns
Note:
1. DT = tCK - 50 ns
Figure 6. TIMEXP
32
TSC21020F
4153H–AERO–04/07
TSC21020F
Flags
Frequency
Dependency(1)
20 MHz
Parameter
Min
Max
Min
Max
Unit
tSFI (2) FLAG3-0IN Setup before CLKIN
High
19
19 +
5DT/16
ns
0
12 +
7DT/16
ns
ns
ns
tHFI (2) FLAG3-0IN Hold after CLKIN High
tDWRFI (2) FLAG3-0IN Delay from xRD,
xWR Low
12
24
tHFIWR (2) FLAG3-0IN Hold after xRD, xWR
Deasserted
0
tDFO FLAG3-0OUT Delay from CLKIN High
ns
ns
ns
t
HFO FLAG3-0OUT Hold after CLKIN High
5
1
tDFOE CLKIN High to FLAG3-0OUT
Enable(3)
tDFOD CLKIN High to FLAG3-0OUT Disable
Notes: 1. DT = tCK - 50 ns
24
ns
2. Flag inputs meeting these setup and hold times will affect conditional operations in
the next instruction cycle. See the Hardware Configuration chapter of the ADSP-
21020 User's Manual from Analog Devices for additional flag servicing information.
3. Guaranteed by design.
Figure 7. Flags
33
4153H–AERO–04/07
Bus Request/Bus Grant
Frequency
Dependency(1)
20 MHz
Unit
Parameter
Min
Max
Min
Max
tHBR BR Hold after CLKIN High
tSBR BR Setup before CLKIN High
0
ns
ns
ns
18
-2
18+5DT/16
tDMDBGL Memory Interface Disable
to BG Low(2)
tDME CLKIN High to Memory
Interface Enable
25
25 + DT/2
ns
tDBGL CLKIN High to BG Low
22
22
ns
ns
tDBGH CLKIN High to BG High
Notes: 1. DT = tCK - 50 ns
Memory Interface = PMA23-0, PMD47-0, PMS1-0, PMRD, PMWR, PMPAGE,
DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR, DMPAGE.
Buses are not granted until completion of current memory access.
See the Memory Interface chapter of the ADSP-21020 User's Manual from
Analog Devices for BG, BR cycle relationships.
2. Guaranteed by design.
Figure 8. Bus Request/Bus Grant
34
TSC21020F
4153H–AERO–04/07
TSC21020F
External Memory Three-State Control
Frequency
Dependency(1)
20 MHz
Parameter
Min
Max
Min
Max
Unit
tSTS XTS, Setup before CLKIN
High
14
50
14 + DT/4
tCK
ns
tDADTS XTS Delay after
Address, Select
28
16
28 + 7DT/8
16 + DT/2
ns
ns
ns
ns
tDSTS XTS, Delay after XRD,
XWR Low
tDTSD Memory Interface
Disable before CLKIN High
0
0
DT/4
tDTSAE XTS High to Address,
Select Enable
Notes: 1. DT = tCK - 50 ns
XTS should only be asserted (low) during an active memory access cycle.
Memory Interface = PMA23-0, PMD47-0, PMS1-0, PMRD, PMWR, PMPAGE,
DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR, DMPAGE.
Address = PMA23-0, DMA31-0, Select = PMS1-0, DMS3-0
x = PM or DM.
Figure 9. External Memory Three-State Control
35
4153H–AERO–04/07
Memory Read
Frequency
Dependency(1)
20 MHz
Max
Parameter
Unit
Min
Min
Max
tDAD Address, Select to Data Valid
tDRLD xRD Low to Data Valid
37
24
37 + DT
ns
ns
ns
24 + 5DT/8
tHDA Data Hold from Address,
Select
0
tHDRH Data Hold from xRD High
tDAAK xACK Delay from Address
tDRAK xACK Delay from xRD Low
-1
ns
ns
ns
ns
27
15
27 + 7DT/8
15 + DT/2
tSAK xACK Setup before CLKIN
High
14
14 + DT/4
8 + 3DT/8
t
HAK xACK Hold after CLKIN High
0
8
ns
ns
ns
tDARL Address, Select to xRD Low
tDAP xPAGE Delay from Address,
Select
1
tDCKRL CLKIN High to xRD Low
16
26
26
16 + DT/4 26 + DT/4
ns
ns
26 +
5DT/8
tRW xRD Pulse Width
17
17 +
3DT/8
ns
t
RWR xRD High to xRD, xWR Low
Notes: 1. DT = tCK - 50 ns
2. x = PM or DM; Address = PMA23-0, DMA31-0; Data = PMD47-0, DMD39-0;
Select = PMS1-0, DMS3-0.
36
TSC21020F
4153H–AERO–04/07
TSC21020F
Figure 10. Memory Read
Memory Write
Frequency
Dependency(1)
20 MHz
Max
Parameter
Unit
Min
Min
Max
tDAAK xACK Delay from
Address, Select
27
27 + 7DT/8
ns
ns
ns
ns
ns
ns
ns
ns
tDWAK xACK Delay from xWR
Low
15
15 + DT/2
tSAK xACK Setup before CLKIN
High
14
0
14 + DT/4
tHAK xACK Hold after CLKIN
High
tDAWH Address, Select to xWR
Deasserted
37
11
26
23
37 +
15DT/16
tDAWL Address, Select to xWR
Low
11 + 3DT/8
26 +
9DT/16
tWW xWR Pulse Width
tDDWH Data Setup before xWR
High
23 + DT/2
37
4153H–AERO–04/07
Frequency
Dependency(1)
20 MHz
Max
Parameter
Unit
Min
Min
Max
tDWHA Address, Select Hold
after xWR Deasserted(2)
1
1 + DT/16
ns
ns
ns
ns
ns
ns
ns
tHDWH Data Hold after xWR
Deasserted(2)
0
DT/16
tDAP xPAGE Delay from
Address, Select
1
tDCKWL CLKIN High to xWR
Low
16
17
13
0
26
16 + DT/4 26 + DT/4
tWWR xWR High to xWR or xRD
Low
17 +
7DT/16
tDDWR Data Disable before
xWR or xRD Low
13 + 3DT/8
DT/16
tWDE xWR Low to Data Enabled
Notes: 1. DT = tC - 50 ns
2. See "System Hold Time Calculation" in "Test Conditions" section for calculating hold
times given capacitive and DC loads.
x = PM or DM; Address = PMA23-0, DMA31-0; Data = PMD47-0, DMD39-0; Select
= PMS1-0, DMS3-0; guaranteed by design.
Figure 11. Memory Write
38
TSC21020F
4153H–AERO–04/07
TSC21020F
IEEE 1149.1 Test Access Port
Frequency
Dependency(1)
20 MHz
Parameter
Unit
Min
50
5
Max
Min
Max
tTCK TCK Period
tCK
ns
ns
tSTAP TDI, TMS Setup before TCK
High
tHTAP TDI, TMS Hold after TCK High
6
7
ns
ns
tSSYS System Inputs Setup before
TCK High
tHSYS System Inputs Hold after TCK
High
9
ns
tTRSTW TRST Pulse Width
200
ns
ns
ns
tDTDO TDO Delay from TCK Low
15
26
tDSYS System Outputs Delay from
TCK Low
Note:
1. DT = tCK - 50 ns
System Inputs = PMD47-0, PMACK, PMTS, DMD39-0, DMACK, DMTS, CLKIN,
IRQ3-0, RESET, FLAG3-0, BR.
System Outputs = PMA23-0, PMS1-0, PMRD, PMWR, PMD47-0, PMPAGE,
DMA31-0, DMS3-0, DMRD, DMWR, DMPAGE, FLAG3-0, BG, TIMEXP.
See the IEEE 1149.1 Test Access Port chapter of the ADSP-21020 User's Manual
from Analog Devices for further detail.
Figure 12. IEEE 1149.1 Test Access Port
39
4153H–AERO–04/07
Figure 13. Output Enable/Disable
Test Conditions
Output Disable Time
Output pins are considered to be disable when they stop driving, go into a high-imped-
ance state, and start to decay from their output high or low voltage. The time for the
voltage on the bus to decay by ∆V is dependent on the capacitive load, CL, and the load
current, IL. It can be approximated by the following equation:
CL∆V
-------------
=
tDECAY
IL
The output disable time (tDIS) is the difference between tMEASURED and tDECAY as shown
in Figure 13. The time tMEASURED is the interval from when the reference signal switches
to when the output voltage decays ∆V from the measured output high or output low volt-
age. tDECAY is calculated with ∆V equal to 0.5V, and test loads CL and IL.
Output Enable Time
Output pins are considered to be enabled when they have made a transition from a
high-impedance state to when they start driving. The output enable time (tENA) is the
interval from when a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown in the Output Enable
/Disable diagram. If multiple pins (such as the data bus) are enabled, the measurement
value is that of the first pin to start driving.
40
TSC21020F
4153H–AERO–04/07
TSC21020F
Figure 14. Equivalent Device Loading for AC Measurements (Includes all Fixtures)
Example System Hold
Time Calculation
To determine the data output hold time in a particular system, first calculate tDECAY using
the above equation. Choose ∆V to be the difference between the TSC21020F's output
voltage and the input threshold for the device requiring the hold time. A typical ∆V will be
0.4V. CL is the total bus capacitance (per data line), and IL is the total leakage or three-
state current (per data line). The hold time will be tDECAY plus the minimum disable time
(i.e. tHDWD for the write cycle).
Figure 15. Voltage Reference Levels for AC Measurements (Except Output
Enable/Disable)
Capacitive Loading
Output delays are based on standard capacitive loads: 100 pF on address, select, page
and strobe pins, and 50 pF on all others (see Figure 14). For different loads, these tim-
ing parameters should be derated. See the Hardware Configuration chapter of the
ADSP-21020 User's Manual from Analog Devices for further information on derating of
timing specifications.
Figures 16 and 17 show how the output rise time varies with capacitance. Figures 18
and 19 show how output delays vary with capacitance. Note that the graphs may not be
linear outside the ranges shown.
41
4153H–AERO–04/07
Figure 16. Typical Output Rise Time vs. Load Capacitance (at Maximum Case
Temperature)
10
9.9
9
8
7
6
(1)
5
4
3
2
1.6
1
0
25
50
75
100
125
150
175
200
LOAD CAPACITANCE –pF
Note:
(1) OUTPUT PINS BG, TIMEXP, PMD47–0,
DMD39–0, FLAG3–0
Figure 17. Typical Output Rise Time vs. Load Capacitance (at Maximum Case
Temperature)
5
4.8
4
3
(1)
2
1
1
0
25
50
75
100
125
150
175
200
LOAD CAPACITANCE – pF
Note:
(1) OUTPUT PINS PMA23–0, PMS1–0, PMPAGE, DMA31–0,
DMS3–0, DMPAGE, TDO, PMRD, PMWR, DMRD, DMWR
42
TSC21020F
4153H–AERO–04/07
TSC21020F
Figure 18. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case
Temperature)
12
10
8.3
8
6
4
(1)
2
0
–1.7
–2
25
50
75
100
125
150
175
200
LOAD CAPACITANCE – pF
Note:
(1) OUTPUT PINS BG, TIMEXP, FLAG3–0,
PMD47–0, DMD39–0
Figure 19. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case
Temperature)
4
3
2.8
2
1
(1)
0
–1
–2
–2.2
–3
25
50
75
100
125
150
175
200
LOAD CAPACITANCE – pF
Note:
(1) OUTPUT PINS PMA–23, PMS1–0, PMPAGE, DMA31–0,
DMS3–0, DMPAGE, TDO, PMRD, PMWR, DMRD, DMWR
Power Dissipation
Total power dissipation has two components: one due to internal circuitry and one due
to the switching of external output drivers.
Internal power dissipation is dependent on the instruction execution sequence and the
data values involved. Internal power dissipation is calculated in the following way:
PINT = IDDIN x VDD
The external component of total power dissipation is caused by the switching of output
pins. Its magnitude depends on:
1) the number of output pins that switch during each cycle(O),
2) the maximum frequency at which they can switch (f),
3) their load capacitance (C), and
43
4153H–AERO–04/07
4) their voltage swing (VDD).
It is calculated by:
PEXT = O x C x VDD2 x f
The load capacitance should include the processor's package capacitance (CIN). The
switching frequency includes driving the load high and then back low. Address and data
pins can drive high and low at a maximum rate of 1/(2tCK). The write strobes can switch
every cycle at a frequency of 1/tCK. Select pins switch at 1/(2tCK), but 2 DM and 2 PM
selects can switch on each cycle. If only one bank is accessed, no select line will switch.
For instance, the maximum power dissipation will be:
PINT Max = IDDINMax x VDDMax = 0,430 x 5,5 = 2,36W
PEXT Max = 0 x C x VDD Max2 x f
= 164 x 10-11 x 5.52 x 20.106 = 0.99W
Pmax = 3.4W
Power and Ground Guidelines
2
Pin Type
# Pins
% Switch
xC
xf
xVDD
PEXT
PMA
PMS
15
2
50
0
68 pF
68 pF
68 pF
18 pF
48 pF
48 pF
48 pF
18 pF
5 MHz
5 MHz
10 MHz
5 MHz
5 MHz
5 MHz
10 MHz
5 MHz
25V
25V
25V
25V
25V
25V
25V
25V
0.064W
0.000W
0.017W
0.036W
0.045W
0.000W
0.012W
0.036W
PMWR
PMD
1
-
32
15
2
50
50
0
DMA
DMS
DMWR
DMD
1
-
32
50
P
EXT = 0.210W
To achieve its fast cycle time, including instruction fetch, data access, and execution,
the TSC21020F is designed with high speed drivers on all output pins. Large peak cur-
rents may pass through a circuit board's ground and power lines, especially when many
output drivers are simultaneously charging or discharging their load capacitances.
These transient currents can cause disturbances on the power and ground lines. To
minimize these effects, the TSC21020F provides separate supply pins for its internal
logic (IGND and IVDD) and for its external drivers (EGND and EVDD).
All GND pins should have a low impedance path to ground. A ground plane is required
in TSC21020F systems to reduce this impedance, minimizing noise.
The EVDD and IVDD pins should be bypassed to the ground plane using approximately
14 high-frequency capacitors (0.1 µF ceramic). Keep each capacitor's lead and trace
length to the pins as short as possible. This low inductive path provides the TSC21020F
with the peak currents required when its output drivers switch. The capacitors' ground
leads should also be short and connect directly to the ground plane. This provides a low
impedance return path for the load capacitance of the TSC21020F's output drivers.
If a VDD plane is not used, the following recommendations apply. Traces from the + 5V
supply to the 10 EVDD pins should be designed to satisfy the minimum VDD specifica-
tion while carrying average dc currents of [IDDEX/10 x (number of EVDD pins per trace)].
IDDEX is the calculated external supply current. A similar calculation should be made for
the four IVDD pins using the IDDIN specification. The traces connecting +5V to the IVDD
pins should be separate from those connecting to the EVDD pins.
44
TSC21020F
4153H–AERO–04/07
TSC21020F
A low frequency bypass capacitor (20 µF tantalum) located near the junction of the
IVDD and EVDD traces is also recommended.
Target System
Requirements for Use of
EZ-ICE Emulator
The ADSP-21020 EZ-ICE uses the IEEE 1149.1 JTAG test access port of the
TSC21020F to monitor and control the target board processor during emulation. The
EZ-ICE probe requires that CLKIN, TMS, TCK, TRST, TDI, TDO, and GND be made
accessible on the target system via a 12-pin connector (pin strip header) such as that
shown in Figure 20. The EZ-ICE probe plugs directly onto this connector for chip-on-
board emulation; you must add this connector to your target board design if you intend
to use the ADSP-21020 EZ-ICE. Figure 21 shows the dimensions of the EZ-ICE probe;
be sure to allow enough space in your system to fit the probe onto the 12-pin connector.
Figure 20. Target Board Connector for EZ-ICE Emulator (Jumpers In Place)
Figure 21. EZ-ICE Probe
The 12-pin, 2-row pin strip header is keyed at the Pin 1 location - you must clip Pin 1 off
of the header. The pins must be 0.025 inch square and at least 0.20 inch in length. Pin
spacing is 0.1 x 0.1 inches.
45
4153H–AERO–04/07
The tip of the pins must be at least 0.10 inch higher than the tallest component under the
probe to allow clearance for the bottom of the probe. Pin strip headers are available
from vendors such as 3M, McKenzie, and Samtec.
The length of the traces between the EZ-ICE probe connector and the TSC21020F test
access port pins should be less than 1 inch. Note that the EZ-ICE probe adds two TTL
loads to the CLKIN pin of the TSC21020F.
The BMTS, BTCK, BTRST, and BTDI signals are provided so that the test access port
can also be used for board-level testing. When the connector is not being used for emu-
lation, place jumpers between the BXXX pins and the XXX pins as shown in Figure 20. If
you are not going to use the test access port for board test, tie BTRST to GND and tie or
pull up BTCK to VDD. The TRST pin must be asserted (pulsed low) after power up
(through BTRST on the connector) or held low for proper operation of the TSC21020F.
46
TSC21020F
4153H–AERO–04/07
TSC21020F
Ordering Information
Part Number
TSC21020F-20MA-E
TSC21020F-20MB-E
5962-9953901QXC
5962-9953901VXC
951200201
Temperature Range
Speed
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
Package
PGA223
Quality Flow
Engineering Samples
Engineering Samples
QML-Q
25°C
25°C
MQFP-F256
MQFP-F256
MQFP-F256
MQFP-F256
DIE
-55 to +125°C
-55 to +125°C
-55 to +125°C
25°C
QML-V
ESCC
TSC21020F-20MC-E
TSC21020F-20MC-SV
Engineering Samples
QML-V
-55 to +125°C
DIE
Package Drawings
223-pin Ceramic Pin Grid Array
Bottom View
MM
Inches
Symbol
Min.
2.54
Max
3.30
Min.
.100
Max
A
.130
47
4153H–AERO–04/07
C
D
E
H
L
2.54 BSC
.100 BSC
46.74
46.74
0.41
47.75
47.75
0.51
1.840
1.840
0.16
1.880
1.880
0.20
3.05
3.56
.120
.140
Q
1.14
1.40
0.45
.055
256-pin MQFP-F Package Top View
Mils
MM
Symbol
Min.
0.095
0.004
2.095
1.450
2.095
1.450
Max
Min.
2.41
Max
3.18
A
C
0.125
0.008
2.195
1.470
2.195
1.470
0.10
0.20
D
53.23
36.83
53.23
36.83
55.74
37.34
55.74
37.34
D1
E
E1
e
0.020 BSC
0.508 BSC
f
0.006
0.081
0.002
0.323
0.010
0.101
0.014
0.362
0.15
2.06
0.05
8.20
0.25
2.56
0.36
9.20
A1
A2
L
N1
64
64
48
TSC21020F
4153H–AERO–04/07
TSC21020F
N2
64
64
49
4153H–AERO–04/07
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