TSC80251G2D-L16CB [ATMEL]
B/16-BIT MICROCONTROLLER WITH SERIAL COMMUNICATION INTERFACES; 具有串行通信接口B / 16位微控制器
| 型号： | TSC80251G2D-L16CB |
| 厂家： | 
ATMEL |
| 描述： | B/16-BIT MICROCONTROLLER WITH SERIAL COMMUNICATION INTERFACES |
| 文件： | 总76页 (文件大小：1181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Pin and Software Compatibility with Standard 80C51 Products and 80C51Fx/Rx/Rx+
• Plug-In Replacement of Intel’s 8xC251Sx
• C251 Core: Intel’s MCS®251 D-step Compliance
• 40-byte Register File
• Registers Accessible as Bytes, Words or Dwords
• Three-stage Instruction Pipeline
• 16-bit Internal Code Fetch
• Enriched C51 Instruction Set
• 16-bit and 32-bit ALU
• Compare and Conditional Jump Instructions
• Expanded Set of Move Instructions
• Linear Addressing
8/16-bit
Microcontroller
with Serial
Communication
Interfaces
• 1 Kbyte of On-Chip RAM
• External Memory Space (Code/Data) Programmable from 64 kilobytes to 256 kilobytes
• TSC87251G2D: 32 kilobytes of On-Chip EPROM/OTPROM
– SINGLE PULSE Programming Algorithm
• TSC83251G1D: 16 kilobytes of On-Chip Masked ROM
• TSC83251G1D: 32 kilobytes of On-Chip Masked ROM
• TSC80251G1D: ROMless Version
• Four 8-bit Parallel I/O Ports (Ports 0, 1, 2 and 3 of the Standard 80C51)
• Serial I/O Port: Full Duplex UART (80C51 Compatible) With Independent Baud Rate
Generator
• SSLC: Synchronous Serial Link Controller
• TWI Multi-master Protocol
TSC80251G2D
TSC83251G2D
TSC87251G2D
AT80251G2D
AT83251G2D
AT87251G2D
• μWire and SPI Master and Slave Protocols
• Three 16-bit Timers/Counters (Timers 0, 1 and 2 of the Standard 80C51)
• EWC: Event and Waveform Controller
• Compatible with Intel’s Programmable Counter Array (PCA)
• Common 16-bit Timer/Counter Reference with Four Possible Clock Sources (Fosc/4,
Fosc/12, Timer 1 and External Input)
• Five Modules, Each with Four Programmable Modes:
– 16-bit Software Timer/Counter
– 16-bit Timer/Counter Capture Input and Software Pulse Measurement
– High-speed Output and 16-bit Software Pulse Width Modulation (PWM)
– 8-bit Hardware PWM Without Overhead
• 16-bit Watchdog Timer/Counter Capability
• Secure 14-bit Hardware Watchdog Timer
• Power Management
• Power-On Reset (Integrated on the Chip)
• Power-Off Flag (Cold and Warm Resets)
• Software Programmable System Clock
• Idle Mode
• Power-down Mode
• Keyboard Interrupt Interface on Port 1
• Non Maskable Interrupt Input (NMI)
• Real-Time Wait States Inputs (WAIT#/AWAIT#)
• ONCE Mode and Full Speed Real-time In-circuit Emulation Support (Third Party
Vendors)
• High Speed Versions:
– 4.5V to 5.5V
– 16 MHz and 24 MHz
• Typical Operating Current: 35 mA at 24 MHz
24 mA at 16 MHz
• Typical Power-down Current: 2 μA
• Low Voltage Version:
– 2.7V to 5.5V
Rev. 4135D–8051–08/05
– 16 MHz
1
• Typical Operating Current:11 mA at 3V
• Typical Power-down Current: 1 μA
• Temperature Ranges: Commercial (0°C to +70°C), Industrial (-40°C to +85°C)
• Option: Extended Range (-55°C to +125°C)
• Packages: PDIL 40, PLCC 44 and VQFP 44, CDIL 40 and CQPJ 44 with Window
• Options: Known Good Dice and Ceramic Packages
Description
The TSC80251G2D products are derivatives of the Atmel Microcontroller family based on the 8/16-bit C251 Architecture.
This family of products is tailored to 8/16-bit microcontroller applications requiring an increased instruction throughput, a
reduced operating frequency or a larger addressable memory space. The architecture can provide a significant code size
reduction when compiling C programs while fully preserving the legacy of C51 assembly routines.
The TSC80251G2D derivatives are pin and software compatible with standard 80C51/Fx/Rx/Rx+ with extended on-chip
data memory (1 Kbyte RAM) and up to 256 kilobytes of external code and data. Additionally, the TSC83251G2D and
TSC87251G2D provide on-chip code memory: 32 kilobytes ROM and 32 kilobytes EPROM/OTPROM respectively.
They provide transparent enhancements to Intel’s 8xC251Sx family with an additional Synchronous Serial Link Controller
(SSLC supporting TWI, μWire and SPI protocols), a Keyboard interrupt interface, a dedicated Baud Rate Generator for
UART, and Power Management features.
TSC80251G2D derivatives are optimized for speed and for low power consumption on a wide voltage range.
Note:
1. This Datasheet provides the technical description of the TSC80251G2D derivatives. For further information on the device
usage, please request the TSC80251 Programmer’s Guide and the TSC80251G1D Design Guide and errata sheet.
Typical Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ISDN Terminals
High-Speed Modems
PABX (SOHO)
Line Cards
DVD ROM and Players
Printers
Plotters
Scanners
Banking Machines
Barcode Readers
Smart Cards Readers
High-End Digital Monitors
High-End Joysticks
High-end TV’s
2
AT/TSC8x251G2D
4135D–8051–08/05
AT/TSC8x251G2D
Block Diagram
P3(A16) P2(A15-8) P1(A17) P0(AD7-0)
PSEN#
ALE/PROG#
EA#/VPP
AWAIT#
ROM
EPROM
OTPROM
32 KB
Timers 0, 1 and 2
RAM
PORTS 0-3
1 Kbyte
UART
Baud Rate Generator
16-bit Memory Code
16-bit Memory Address
Event and Waveform
Controller
TWI/SPI/mWire
Controller
Bus Interface Unit
Watchdog Timer
RST
Power Management
XTAL2
Clock Unit
Clock System Prescaler
XTAL1
Keyboard Interface
CPU
NMI
Interrupt Handler
Unit
VDD
VSS
VSS1
VSS2
3
4135D–8051–08/05
Pin Description
Pinout
Figure 1. TSC80251G2D 40-pin DIP package
P1.0/T2
P1.1/T2EX
1
2
3
4
5
6
7
8
9
40
39
38
37
36
VDD
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P1.2/ECI
P1.3/CEX0
P1.4/CEX1/SS#
P1.5/CEX2/MISO
P1.6/CEX3/SCL/SCK/WAIT#
P1.7/A17/CEX4/SDA/MOSI/WCLK
RST
35 P0.4/AD4
34 P0.5/AD5
33 P0.6/AD6
32 P0.7/AD7
31 EA#/VPP
30 ALE/PROG#
29 PSEN#
P3.0/RXD 10
P3.1/TXD 11
P3.2/INT0# 12
P3.3/INT1# 13
P3.4/T0 14
TSC80251G2D
28 P2.7/A15
27 P2.6/A14
26 P2.5/A13
25 P2.4/A12
24 P2.3/A11
23 P2.2/A10
22 P2.1/A9
21 P2.0/A8
P3.5/T1 15
P3.6/WR# 16
P3.7/A16/RD# 17
XTAL2 18
XTAL1 19
VSS 20
Figure 2. TSC80251G2D 44-pin PLCC Package
P1.5/CEX2/MISO
P1.6/CEX3/SCL/SCK/WAIT#
P1.7/A17/CEX4/SDA/MOSI/WCLK
7
8
9
39 P0.4/AD4
38 P0.5/AD5
37 P0.6/AD6
36 P0.7/AD7
35 EA#/VPP
34 NMI
RST 10
P3.0/RXD 11
AWAIT#
TSC80251G2D
12
P3.1/TXD 13
P3.2/INT0# 14
P3.3/INT1# 15
P3.4/T0 16
33 ALE/PROG#
32 PSEN#
31 P2.7/A15
30 P2.6/A14
29 P2.5/A13
P3.5/T1 17
4
AT/TSC8x251G2D
4135D–8051–08/05
AT/TSC8x251G2D
Figure 3. TSC80251G2D 44-pin VQFP Package
P1.5/CEX2/MISO
P1.6/CEX3/SCL/SCK/WAIT#
P1.7/A17/CEX4/SDA/MOSI/WCLK
1
2
3
4
5
6
7
8
33
32
31
30
29
28
27
26
25
24
23
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA#/VPP
NMI
ALE/PROG#
PSEN#
P2.7/A15
P2.6/A14
P2.5/A13
RST
P3.0/RXD
AWAIT#
P3.1/TXD
P3.2/INT0#
P3.3/INT1#
P3.4/T0
TSC80251G2D
9
10
11
P3.5/T1
5
4135D–8051–08/05
Table 1. TSC80251G2D Pin Assignment
DIP
PLCC
VQFP Name
DIP
PLCC
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
VQFP Name
1
39
40
41
42
43
44
1
VSS1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
VSS2
1
2
2
P1.0/T2
21
22
23
24
25
26
27
28
29
30
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN#
3
P1.1/T2EX
P1.2/ECI
3
4
4
5
P1.3/CEX0
P1.4/CEX1/SS#
P1.5/CEX2/MISO
P1.6/CEX3/SCL/SCK/WAIT#
P1.7/A17/CEX4/SDA/MOSI/WCLK
RST
5
6
6
7
7
8
2
8
9
3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
4
10
5
P3.0/RXD
ALE/PROG#
NMI
6
AWAIT#
11
12
13
14
15
16
17
18
19
20
7
P3.1/TXD
31
32
33
34
35
36
37
38
39
40
EA#/VPP
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
8
P3.2/INT0#
P3.3/INT1#
P3.4/T0
9
10
11
12
13
14
15
16
P3.5/T1
P3.6/WR#
P3.7/A16/RD#
XTAL2
XTAL1
VSS
6
AT/TSC8x251G2D
4135D–8051–08/05
AT/TSC8x251G2D
Signals
Table 2. Product Name Signal Description
Signal
Name
Alternate
Function
Type Description
18th Address Bit
Output to memory as 18th external address bit (A17) in extended bus
applications, depending on the values of bits RD0 and RD1 in UCONFIG0
byte (see Table 13, Page 20).
A17
O
P1.7
P3.7
17th Address Bit
Output to memory as 17th external address bit (A16) in extended bus
applications, depending on the values of bits RD0 and RD1 in UCONFIG0
byte (see Table 13, Page 20).
A16
O
Address Lines
Upper address lines for the external bus.
A15:8(1)
AD7:0(1)
O
P2.7:0
P0.7:0
Address/Data Lines
Multiplexed lower address lines and data for the external memory.
I/O
Address Latch Enable
ALE signals the start of an external bus cycle and indicates that valid
address information are available on lines A16/A17 and A7:0. An external
latch can use ALE to demultiplex the address from address/data bus.
ALE
O
–
Real-time Asynchronous Wait States Input
When this pin is active (low level), the memory cycle is stretched until it
becomes high. When using the Product Name as a pin-for-pin replacement
for a 8xC51 product, AWAIT# can be unconnected without loss of
compatibility or power consumption increase (on-chip pull-up).
AWAIT#
CEX4:0
I
–
Not available on DIP package.
PCA Input/Output pins
I/O CEXx are input signals for the PCA capture mode and output signals for
the PCA compare and PWM modes.
P1.7:3
External Access Enable
EA# directs program memory accesses to on-chip or off-chip code memory.
For EA# = 0, all program memory accesses are off-chip.
EA#
I
For EA# = 1, an access is on-chip ROM if the address is within the range of
the on-chip ROM; otherwise the access is off-chip. The value of EA# is
latched at reset.
–
For devices without ROM on-chip, EA# must be strapped to ground.
PCA External Clock input
ECI is the external clock input to the 16-bit PCA timer.
ECI
O
P1.2
P1.5
SPI Master Input Slave Output line
When SPI is in master mode, MISO receives data from the slave
peripheral. When SPI is in slave mode, MISO outputs data to the master
controller.
MISO
I/O
SPI Master Output Slave Input line
MOSI
I/O When SPI is in master mode, MOSI outputs data to the slave peripheral.
When SPI is in slave mode, MOSI receives data from the master controller.
P1.7
External Interrupts 0 and 1
INT1#/INT0# inputs set IE1:0 in the TCON register. If bits IT1:0 in the
TCON register are set, bits IE1:0 are set by a falling edge on INT1#/INT0#.
INT1:0#
I
P3.3:2
If bits IT1:0 are cleared, bits IE1:0 are set by a low level on INT1#/INT0#.
7
4135D–8051–08/05
Table 2. Product Name Signal Description (Continued)
Signal
Name
Alternate
Function
Type Description
Non Maskable Interrupt
Holding this pin high for 24 oscillator periods triggers an interrupt.
When using the Product Name as a pin-for-pin replacement for a 8xC51
product, NMI can be unconnected without loss of compatibility or power
consumption increase (on-chip pull-down).
NMI
I
–
Not available on DIP package.
Port 0
P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s
P0.0:7
P1.0:7
I/O written to them float and can be used as high impedance inputs. To avoid
any paraitic current consumption, Floating P0 inputs must be polarized to
AD7:0
V
DD or VSS
.
Port 1
I/O P1 is an 8-bit bidirectional I/O port with internal pull-ups. P1 provides
interrupt capability for a keyboard interface.
–
Port 2
P2.0:7
P3.0:7
I/O
A15:8
–
P2 is an 8-bit bidirectional I/O port with internal pull-ups.
Port 3
I/O
P3 is an 8-bit bidirectional I/O port with internal pull-ups.
Programming Pulse input
PROG#
PSEN#
RD#
I
The programming pulse is applied to this input for programming the on-chip
EPROM/OTPROM.
–
–
Program Store Enable/Read signal output
PSEN# is asserted for a memory address range that depends on bits RD0
and RD1 in UCONFIG0 byte (see ).
O
O
Read or 17th Address Bit (A16)
Read signal output to external data memory depending on the values of
bits RD0 and RD1 in UCONFIG0 byte (see Table 13, Page 20).
P3.7
Reset input to the chip
Holding this pin high for 64 oscillator periods while the oscillator is running
resets the device. The Port pins are driven to their reset conditions when a
voltage greater than VIH1 is applied, whether or not the oscillator is running.
This pin has an internal pull-down resistor which allows the device to be
reset by connecting a capacitor between this pin and VDD.
Asserting RST when the chip is in Idle mode or Power-Down mode returns
the chip to normal operation.
RST
I
–
Receive Serial Data
RXD
SCL
SCK
I/O RXD sends and receives data in serial I/O mode 0 and receives data in
serial I/O modes 1, 2 and 3.
P3.0
P1.6
P1.6
TWI Serial Clock
When TWI controller is in master mode, SCL outputs the serial clock to
slave peripherals. When TWI controller is in slave mode, SCL receives
I/O
clock from the master controller.
SPI Serial Clock
I/O When SPI is in master mode, SCK outputs clock to the slave peripheral.
When SPI is in slave mode, SCK receives clock from the master controller.
TWI Serial Data
SDA is the bidirectional TWI data line.
SDA
SS#
I/O
P1.7
P1.4
SPI Slave Select Input
When in Slave mode, SS# enables the slave mode.
I
8
AT/TSC8x251G2D
4135D–8051–08/05
AT/TSC8x251G2D
Table 2. Product Name Signal Description (Continued)
Signal
Name
Alternate
Function
Type Description
Timer 1:0 External Clock Inputs
T1:0
T2
I/O When timer 1:0 operates as a counter, a falling edge on the T1:0 pin
increments the count.
–
Timer 2 Clock Input/Output
I/O For the timer 2 capture mode, T2 is the external clock input. For the Timer 2
clock-out mode, T2 is the clock output.
P1.0
Timer 2 External Input
In timer 2 capture mode, a falling edge initiates a capture of the timer 2
T2EX
I
registers. In auto-reload mode, a falling edge causes the timer 2 register to
be reloaded. In the up-down counter mode, this signal determines the
count direction: 1 = up, 0 = down.
P1.1
Transmit Serial Data
TXD
VDD
VPP
VSS
O
PWR
I
TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial
I/O modes 1, 2 and 3.
P3.1
Digital Supply Voltage
Connect this pin to +5V or +3V supply voltage.
–
–
–
Programming Supply Voltage
The programming supply voltage is applied to this input for programming
the on-chip EPROM/OTPROM.
Circuit Ground
Connect this pin to ground.
GND
Secondary Ground 1
This ground is provided to reduce ground bounce and improve power
supply bypassing. Connection of this pin to ground is recommended.
However, when using the TSC80251G2D as a pin-for-pin replacement for a
8xC51 product, VSS1 can be unconnected without loss of compatibility.
VSS1
GND
–
Not available on DIP package.
Secondary Ground 2
This ground is provided to reduce ground bounce and improve power
supply bypassing. Connection of this pin to ground is recommended.
However, when using the TSC80251G2D as a pin-for-pin replacement for a
8xC51 product, VSS2 can be unconnected without loss of compatibility.
VSS2
GND
–
Not available on DIP package.
Real-time Synchronous Wait States Input
The real-time WAIT# input is enabled by setting RTWE bit in WCON
(S:A7h). During bus cycles, the external memory system can signal
‘system ready’ to the microcontroller in real time by controlling the WAIT#
input signal.
WAIT#
I
P1.6
Wait Clock Output
The real-time WCLK output is enabled by setting RTWCE bit in WCON
(S:A7h). When enabled, the WCLK output produces a square wave signal
with a period of one half the oscillator frequency.
WCLK
WR#
O
O
I
P1.7
P3.6
–
Write
Write signal output to external memory.
Input to the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to this
pin. If an external oscillator is used, its output is connected to this pin.
XTAL1 is the clock source for internal timing.
XTAL1
9
4135D–8051–08/05
Table 2. Product Name Signal Description (Continued)
Signal
Name
Alternate
Function
Type Description
Output of the on-chip inverting oscillator amplifier
XTAL2
O
To use the internal oscillator, a crystal/resonator circuit is connected to this
pin. If an external oscillator is used, leave XTAL2 unconnected.
–
Note:
The description of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the Non-Page mode chip con-
figuration. If the chip is configured in Page mode operation, port 0 carries the lower
address bits (A7:0) while port 2 carries the upper address bits (A15:8) and the data
(D7:0).
10
AT/TSC8x251G2D
4135D–8051–08/05
AT/TSC8x251G2D
Address Spaces
The TSC80251G2D derivatives implement four different address spaces:
•
•
•
•
On-chip ROM program/code memory (not present in ROMless devices)
On-chip RAM data memory
Special Function Registers (SFRs)
Configuration array
Program/Code Memory
The TSC83251G2D and TSC87251G2D implement 32 KB of on-chip program/code
memory. Figure 4 shows the split of the internal and external program/code memory
spaces. If EA# is tied to a high level, the 32-Kbyte on-chip program memory is mapped
in the lower part of segment FF: where the C251 core jumps after reset. The rest of the
program/code memory space is mapped to the external memory. If EA# is tied to a low
level, the internal program/code memory is not used and all the accesses are directed to
the external memory.
The TSC83251G2D products provide the internal program/code memory in a masked
ROM memory while the TSC87251G2D products provide it in an EPROM memory. For
the TSC80251G2D products, there is no internal program/code memory and EA# must
be tied to a low level.
Figure 4. Program/Code Memory Mapping
Program/code
External Memory Space
Program/code
Segments
On-chip ROM/EPROM
Code Memory
FF:FFFFh
32 KB
FF:8000h
FF:7FFFh
32 KB
64 KB
EA# = 0
EA# = 1
32 KB
FF:0000h
FE:FFFFh
FE:0000h
FD:FFFFh
Reserved
02:0000h
01:FFFFh
01:0000h
00:FFFFh
128 KB
00:0000h
Note:
Special care should be taken when the Program Counter (PC) increments:
If the program executes exclusively from on-chip code memory (not from external mem-
ory), beware of executing code from the upper eight bytes of the on-chip ROM
(FF:7FF8h-FF:7FFFh). Because of its pipeline capability, the TSC80251G2D derivative
may attempt to prefetch code from external memory (at an address above FF:7FFFh)
and thereby disrupt I/O Ports 0 and 2. Fetching code constants from these 8 bytes does
not affect Ports 0 and 2.
When PC reaches the end of segment FF:, it loops to the reset address FF:0000h (for
11
4135D–8051–08/05
compatibility with the C51 Architecture). When PC increments beyond the end of seg-
ment FE:, it continues at the reset address FF:0000h (linearity). When PC increments
beyond the end of segment 01:, it loops to the beginning of segment 00: (this prevents
from its going into the reserved area).
Data Memory
The TSC80251G2D derivatives implement 1 Kbyte of on-chip data RAM. Figure 5
shows the split of the internal and external data memory spaces. This memory is
mapped in the data space just over the 32 bytes of registers area (see TSC80251 Pro-
grammers’ Guide). Hence, the part of the on-chip RAM located from 20h to FFh is bit
addressable. This on-chip RAM is not accessible through the program/code memory
space.
For faster computation with the on-chip ROM/EPROM code of the
TSC83251G2D/TSC87251G2D, its upper 16 KB are also mapped in the upper part of
the region 00: if the On-Chip Code Memory Map configuration bit is cleared (EMAP# bit
in UCONFIG1 byte, see Figure ). However, if EA# is tied to a low level, the
TSC80251G2D derivative is running as a ROMless product and the code is actually
fetched in the corresponding external memory (i.e. the upper 16 KB of the lower 32 KB
of the segment FF:). If EMAP# bit is set, the on-chip ROM is not accessible through the
region 00:.
All the accesses to the portion of the data space with no on-chip memory mapped onto
are redirected to the external memory.
Figure 5. Data Memory Mapping
Data External
Memory Space
On-chip ROM/EPROM
Code Memory
Data Segments
FF:FFFFh
32 KB
32 KB
FF:8000h
FF:7FFFh
16 KB
16 KB
EA# = 0
EA# = 1
FF:0000h
FE:FFFFh
64 KB
FE:0000h
FD:FFFFh
EMAP# = 0
Reserved
02:0000h
01:FFFFh
64 KB
01:0000h
00:FFFFh
RAM Data
16 KB
EMAP# = 1
00:C000h
00:BFFFh
1 Kbyte
ª47 KB
00:0420h
32 bytes reg.
12
AT/TSC8x251G2D
4135D–8051–08/05
AT/TSC8x251G2D
Special Function
Registers
The Special Function Registers (SFRs) of the TSC80251G2D derivatives fall into the
categories detailed in Table 1 to Table 9.
SFRs are placed in a reserved on-chip memory region S: which is not represented in the
data memory mapping (Figure 5). The relative addresses within S: of these SFRs are
provided together with their reset values in Table . They are upward compatible with the
SFRs of the standard 80C51 and the Intel’s 80C251Sx family. In this table, the C251
core registers are identified by Note 1 and are described in the TSC80251 Program-
mer’s Guide. The other SFRs are described in the TSC80251G1D Design Guide. All the
SFRs are bit-addressable using the C251 instruction set.
Table 1. C251 Core SFRs
Mnemonic Name
Mnemonic Name
Stack Pointer High - MSB of
SPX
ACC(1)
B(1)
Accumulator
SPH(1)
DPL(1)
DPH(1)
Data Pointer Low byte - LSB of
DPTR
B Register
Data Pointer High byte - MSB
of DPTR
PSW
Program Status Word
PSW1
SP(1)
Program Status Word 1
Data Pointer Extended Low
byte of DPX - Region number
DPXL(1)
Stack Pointer - LSB of SPX
Note:
1. These SFRs can also be accessed by their corresponding registers in the register
file.
Table 2. I/O Port SFRs
Mnemonic
Name
Port 0
Port 1
Mnemonic
Name
Port 2
Port 3
P0
P1
P2
P3
Table 3. Timers SFRs
Mnemonic
Name
Mnemonic
Name
Timer/Counter 0 Low
Byte
Timer/Counter 0 and 1
Modes
TL0
TMOD
Timer/Counter 0 High
Byte
Timer/Counter 2
Control
TH0
TL1
T2CON
T2MOD
Timer/Counter 1 Low
Byte
Timer/Counter 2 Mode
Timer/Counter 2
Reload/Capture Low
Byte
Timer/Counter 1 High
Byte
TH1
TL2
RCAP2L
Timer/Counter 2
Reload/Capture High
Byte
Timer/Counter 2 Low
Byte
RCAP2H
WDTRST
Timer/Counter 2 High
Byte
TH2
WatchDog Timer Reset
Timer/Counter 0 and 1
Control
TCON
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Table 4. Serial I/O Port SFRs
Mnemonic
Name
Mnemonic
SADDR
BRL
Name
SCON
Serial Control
Serial Data Buffer
Slave Address
Baud Rate Reload
SBUF
Slave Address
Mask
SADEN
BDRCON
Baud Rate Control
Table 5. SSLC SFRs
Mnemonic
Name
Mnemonic
Name
Synchronous Serial
control
Synchronous Serial
Address
SSCON
SSADR
Synchronous Serial
Data
Synchronous Serial
Bit Rate
SSDAT
SSCS
SSBR
Synchronous Serial
Control and Status
Table 6. Event Waveform Control SFRs
Mnemonic Name
Mnemonic Name
EWC-PCA Compare Capture
Module 0 Low Register
CCON
CMOD
CL
EWC-PCA Timer/Counter Control
EWC-PCA Timer/Counter Mode
CCAP0L
CCAP1L
CCAP2L
CCAP3L
CCAP4L
CCAP0H
CCAP1H
CCAP2H
CCAP3H
CCAP4H
EWC-PCA Compare Capture
Module 1 Low Register
EWC-PCA Timer/Counter Low
Register
EWC-PCA Compare Capture
Module 2 Low Register
EWC-PCA Timer/Counter High
Register
EWC-PCA Compare Capture
Module 3 Low Register
CH
EWC-PCA Compare Capture
Module 4 Low Register
CCAPM0 EWC-PCA Timer/Counter Mode 0
CCAPM1 EWC-PCA Timer/Counter Mode 1
CCAPM2 EWC-PCA Timer/Counter Mode 2
CCAPM3 EWC-PCA Timer/Counter Mode 3
CCAPM4 EWC-PCA Timer/Counter Mode 4
EWC-PCA Compare Capture
Module 0 High Register
EWC-PCA Compare Capture
Module 1 High Register
EWC-PCA Compare Capture
Module 2 High Register
EWC-PCA Compare Capture
Module 3 High Register
EWC-PCA Compare Capture
Module 4 High Register
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Table 7. System Management SFRs
Mnemonic Name
Mnemonic Name
PCON
Power Control
CKRL
Clock Reload
Synchronous Real-Time Wait State
Control
POWM
Power Management
WCON
Table 8. Interrupt SFRs
Mnemonic Name
Mnemonic Name
IE0
Interrupt Enable Control 0
IPL0
IPH1
IPL1
Interrupt Priority Control Low 0
IE1
Interrupt Enable Control 1
Interrupt Priority Control High 1
Interrupt Priority Control Low 1
IPH0
Interrupt Priority Control High 0
Table 9. Keyboard Interface SFRs
Mnemonic Name
Mnemonic Name
P1LS Port 1 Level Selection
P1IE
P1F
Port 1 Input Interrupt Enable
Port 1 Flag
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Table 10. SFR Descriptions
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
CH
0000 0000
CCAP0H
0000 0000
CCAP1H
0000 0000
CCAP2H
0000 0000
CCAP3H
0000 0000
CCAP4H
0000 0000
F8h
F0h
E8h
E0h
D8h
D0h
C8h
C0h
B8h
B0h
A8h
A0h
98h
90h
88h
80h
FFh
F7h
EFh
E7h
DFh
D7h
CFh
C7h
BFh
B7h
AFh
A7h
9Fh
97h
8Fh
87h
B(1)
0000 0000
CL
0000 0000
CCAP0L
0000 0000
CCAP1L
0000 0000
CCAP2L
0000 0000
CCAP3L
0000 0000
CCAP4L
0000 0000
ACC(1)
0000 0000
CCON
00X0 0000
CMOD
00XX X000
CCAPM0
X000 0000
CCAPM1
X000 0000
CCAPM2
X000 0000
CCAPM3
X000 0000
CCAPM4
X000 0000
PSW(1)
0000 0000
PSW1(1)
0000 0000
T2CON
0000 0000
T2MOD
XXXX XX00
RCAP2L
0000 0000
RCAP2H
0000 0000
TL2
0000 0000
TH2
0000 0000
IPL0
X000 0000
SADEN
0000 0000
SPH(1)
0000 0000
P3
1111 1111
IE1
IPL1
IPH1
XX0X XXX0
IPH0
X000 0000
XX0X XXX0 XX0X XXX0
IE0
0000 0000
SADDR
0000 0000
P2
1111 1111
WDTRST
1111 1111
WCON
XXXX XX00
SCON
0000 0000
SBUF
XXXX XXXX
BRL
0000 0000
BDRCON
XXX0 0000
P1LS
0000 0000
P1IE
0000 0000
P1F
0000 0000
P1
1111 1111
SSBR
0000 0000
SSDAT
0000 0000
SSADR
0000 0000
SSCON(2)
SSCS(3)
TCON
0000 0000
TMOD
0000 0000
TL0
0000 0000
TL1
0000 0000
TH0
0000 0000
TH1
0000 0000
CKRL
0000 1000
POWM
0XXX XXXX
P0
1111 1111
SP(1)
0000 0111
DPL(1)
0000 0000
DPH(1)
0000 0000
DPXL(1)
0000 0001
PCON
0000 0000
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
Reserved
Notes: 1. These registers are described in the TSC80251 Programmer’s Guide (C251 core registers).
2. In TWI and SPI modes, SSCON is splitted in two separate registers. SSCON reset value is 0000 0000 in TWI mode and
0000 0100 in SPI mode.
3. In read and write modes, SSCS is splitted in two separate registers. SSCS reset value is 1111 1000 in read mode and 0000
0000 in write mode.
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Configuration Bytes
The TSC80251G2D derivatives provide user design flexibility by configuring certain
operating features at device reset. These features fall into the following categories:
•
external memory interface (Page mode, address bits, programmed wait states and
the address range for RD#, WR#, and PSEN#)
•
•
•
source mode/binary mode opcodes
selection of bytes stored on the stack by an interrupt
mapping of the upper portion of on-chip code memory to region 00:
Two user configuration bytes UCONFIG0 (see Table 11) and UCONFIG1 (see Table
12) provide the information.
When EA# is tied to a low level, the configuration bytes are fetched from the external
address space. The TSC80251G2D derivatives reserve the top eight bytes of the mem-
ory address space (FF:FFF8h-FF:FFFFh) for an external 8-byte configuration array.
Only two bytes are actually used: UCONFIG0 at FF:FFF8h and UCONFIG1 at
FF:FFF9h.
For the mask ROM devices, configuration information is stored in on-chip memory (see
ROM Verifying). When EA# is tied to a high level, the configuration information is
retrieved from the on-chip memory instead of the external address space and there is no
restriction in the usage of the external memory.
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Table 11. Configuration Byte 0
UCONFIG0
7
-
6
5
4
3
2
1
0
WSA1#
WSA0#
XALE#
RD1
RD0
PAGE#
SRC
Bit
Bit Number Mnemonic Description
Reserved
Set this bit when writing to UCONFIG0.
7
6
-
WSA1#
Wait State A bits
Select the number of wait states for RD#, WR# and PSEN# signals for external
memory accesses (all regions except 01:).
WSA1# WSA0#
Number of Wait States
0
0
1
1
0
1
0
1
3
2
1
0
5
WSA0#
Extend ALE bit
Clear to extend the duration of the ALE pulse from TOSC to 3·TOSC.
4
XALE#
Set to minimize the duration of the ALE pulse to 1·TOSC
.
3
2
RD1
RD0
Memory Signal Select bits
Specify a 18-bit, 17-bit or 16-bit external address bus and the usage of RD#,
WR# and PSEN# signals (see Table 13).
Page Mode Select bit(1)
Clear to select the faster Page mode with A15:8/D7:0 on Port 2 and A7:0 on
1
PAGE#
Port 0.
Set to select the non-Page mode(2) with A15:8 on Port 2 and A7:0/D7:0 on Port
0.
Source Mode/Binary Mode Select bit
Clear to select the binary mode.
Set to select the source mode.
0
SRC
Notes: 1. UCONFIG0 is fetched twice so it can be properly read both in Page or Non-Page
modes. If P2.1 is cleared during the first data fetch, a Page mode configuration is
used, otherwise the subsequent fetches are performed in Non-Page mode.
2. This selection provides compatibility with the standard 80C51 hardware which is mul-
tiplexing the address LSB and the data on Port 0.
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Table 12. Configuration Byte 1
UCONFIG1
7
6
-
5
-
4
3
2
1
0
CSIZE
INTR
WSB
WSB1#
WSB0#
EMAP#
Bit
Number
Bit Mnemonic
Description
On-Chip Code Memory Size bit(1)
CSIZE
TSC87251G2D
Clear to select 16 KB of on-chip code memory (TSC87251G1D
product).
7
Set to select 32 KB of on-chip code memory (TSC87251G2D product).
TSC80251G2D
TSC83251G2D
Reserved
Set this bit when writing to UCONFIG1.
Reserved
Set this bit when writing to UCONFIG1.
6
5
-
-
Reserved
Set this bit when writing to UCONFIG1.
Interrupt Mode bit(2)
Clear so that the interrupts push two bytes onto the stack (the two lower
bytes of the PC register).
4
INTR
Set so that the interrupts push four bytes onto the stack (the three bytes
of the PC register and the PSW1 register).
Wait State B bit(3)
3
2
WSB
Clear to generate one wait state for memory region 01:.
Set for no wait states for memory region 01:.
WSB1#
Wait State B bits
Select the number of wait states for RD#, WR# and PSEN# signals for
external memory accesses (only region 01:).
WSB1# WSB0#
Number of Wait States
0
0
1
1
0
1
0
1
3
2
1
0
1
WSB0#
On-Chip Code Memory Map bit
Clear to map the upper 16 KB of on-chip code memory (at FF:4000h-
FF:7FFFh) to the data space (at 00:C000h-00:FFFFh).
Set not to map the upper 16 KB of on-chip code memory (at FF:4000h-
FF:7FFFh) to the data space.
0
EMAP#
Notes: 1. The CSIZE is only available on EPROM/OTPROM products.
2. Two or four bytes are transparently popped according to INTR when using the RETI
instruction. INTR must be set if interrupts are used with code executing outside
region FF:.
3. Use only for Step A compatibility; set this bit when WSB1:0# are used.
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Configuration Byte 1
Table 13. Address Ranges and Usage of RD#, WR# and PSEN# Signals
External
Memory
RD1
RD0
P1.7
P3.7/RD# PSEN#
Read signal for all
WR#
Write signal for all
external memory
locations
0
0
A17
A16
external memory
locations
256 KB
128 KB
64 KB
Read signal for all
external memory
locations
Write signal for all
external memory
locations
0
1
1
0
I/O pin
I/O pin
A16
Read signal for all
external memory
locations
Write signal for all
external memory
locations
I/O pin
Read
signal for
regions 00: regions FE: and FF:
and 01:
Write signal for all
external memory
locations
Read signal for
1
1
I/O pin
2 × 64 KB(1)
Notes: 1. This selection provides compatibility with the standard 80C51 hardware which has
separate external memory spaces for data and code.
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Instruction Set
Summary
This section contains tables that summarize the instruction set. For each instruction
there is a short description, its length in bytes, and its execution time in states (one state
time is equal to two system clock cycles). There are two concurrent processes limiting
the effective instruction throughput:
•
•
Instruction Fetch
Instruction Execution
Table 20 to Table 32 assume code executing from on-chip memory, then the CPU is
fetching 16-bit at a time and this is never limiting the execution speed.
If the code is fetched from external memory, a pre-fetch queue will store instructions
ahead of execution to optimize the memory bandwidth usage when slower instructions
are executed. However, the effective speed may be limited depending on the average
size of instructions (for the considered section of the program flow). The maximum aver-
age instruction throughput is provided by Table 14 depending on the external memory
configuration (from Page Mode to Non-Page Mode and the maximum number of wait
states). If the average size of instructions is not an integer, the maximum effective
throughput is found by pondering the number of states for the neighbor integer values.
Table 14. Minimum Number of States per Instruction for given Average Sizes
Non-page Mode (states)
Average size
of Instructions
(bytes)
Page Mode
(states)
0 Wait
State
1 Wait
State
2 Wait States 3 Wait States 4 Wait States
1
2
3
4
5
1
2
3
4
5
2
4
3
6
4
5
6
8
10
15
20
25
12
18
24
30
6
9
12
16
20
8
12
15
10
If the average execution time of the considered instructions is larger than the number of
states given by Table 14, this larger value will prevail as the limiting factor. Otherwise,
the value from Table 14 must be taken. This is providing a fair estimation of the execu-
tion speed but only the actual code execution can provide the final value.
Notation for Instruction
Operands
Table 15 to Table 19 provide notation for Instruction Operands.
Table 15. Notation for Direct Addressing
Direct
Address
Description
C251
C51
A direct 8-bit address. This can be a memory address (00h-7Fh) or a
SFR address (80h-FFh). It is a byte (default), word or double word
depending on the other operand.
dir8
3
3
A 16-bit memory address (00:0000h-00:FFFFh) used in direct
addressing.
dir16
3
–
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Table 16. Notation for Immediate Addressing
Immediate
Address
Description
C251
C51
3
#data
An 8-bit constant that is immediately addressed in an instruction
A 16-bit constant that is immediately addressed in an instruction
3
3
#data16
–
#0data16
#1data16
A 32-bit constant that is immediately addressed in an instruction. The
upper word is filled with zeros (#0data16) or ones (#1data16).
3
3
–
–
A constant, equal to 1, 2, or 4, that is immediately addressed in an
instruction.
#short
Table 17. Notation for Bit Addressing
Direct
Address
Description
C251
C51
A directly addressed bit (bit number = 00h-FFh) in memory or an
SFR. Bits 00h-7Fh are the 128 bits in byte locations 20h-2Fh in the
on-chip RAM. Bits 80h-FFh are the 128 bits in the 16 SFRs with
addresses that end in 0h or 8h, S:80h, S:88h, S:90h,..., S:F0h,
S:F8h.
bit51
–
3
A directly addressed bit in memory locations 00:0020h-00:007Fh or
in any defined SFR.
bit
3
Table 18. Notation for Destination in Control Instructions
Direct
Address
Description
C251
C51
A signed (two’s complement) 8-bit relative address. The destination
is -128 to +127 bytes relative to the next instruction’s first byte.
rel
3
3
An 11-bit target address. The target is in the same 2-Kbyte block of
memory as the next instruction’s first byte.
addr11
addr16
addr24
–
–
3
3
3
–
A 16-bit target address. The target can be anywhere within the same
64-Kbyte region as the next instruction’s first byte.
A 24-bit target address. The target can be anywhere within the 16-
Mbyte address space.
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Table 19. Notation for Register Operands
Register
Description
C251
C51
A memory location (00h-FFh) addressed indirectly via byte registers
R0 or R1
at Ri
–
3
Rn
n
Byte register R0-R7 of the currently selected register bank
Byte register index: n = 0-7
–
3
3
–
Rm
Byte register R0-R15 of the currently selected register file
Destination register
Rmd
Rms
Source register
m, md, ms
Byte register index: m, md, ms = 0-15
Word register WR0, WR2, ..., WR30 of the currently selected register
file
WRj
Destination register
Source register
WRjd
WRjs
at WRj
A memory location (00:0000h-00:FFFFh) addressed indirectly
through word register WR0-WR30, is the target address for jump
instructions.
–
at WRj +dis16
j, jd, js
3
A memory location (00:0000h-00:FFFFh) addressed indirectly
through word register (WR0-WR30) + 16-bit signed (two’s
complement) displacement value
Word register index: j, jd, js = 0-30
Dword register DR0, DR4, ..., DR28, DR56, DR60 of the currently
selected register file
DRk
Destination register
Source register
DRkd
DRks
at DRk
A memory location (00:0000h-FF:FFFFh) addressed indirectly
through dword register DR0-DR28, DR56 and DR60, is the target
address for jump instruction
–
at DRk +dis16
k, kd, ks
3
A memory location (00:0000h-FF:FFFFh) addressed indirectly
through dword register (DR0-DR28, DR56, DR60) + 16-bit (two’s
complement) signed displacement value
Dword register index: k, kd, ks = 0, 4, 8..., 28, 56, 60
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Size and Execution Time Table 20. Summary of Add and Subtract Instructions
for Instruction Families
AddADD <dest>, <src>dest opnd ← dest opnd + src opnd
SubtractSUB <dest>, <src>dest opnd ← dest opnd - src opnd
Add with CarryADDC <dest>, <src>(A) ← (A) + src opnd + (CY)
Subtract with BorrowSUBB <dest>, <src>(A) ← (A) - src opnd - (CY)
Binary Mode
Source Mode
<dest>,
Mnemonic <src>(1)
Comments
Bytes
States Bytes States
A, Rn
Register to ACC
1
2
1
2
3
3
3
1
1(2)
2
2
2
2
2
2
2
2
2
1(2)
3
A, dir8
ADD
Direct address to ACC
A, at Ri
Indirect address to ACC
Immediate data to ACC
Byte register to/from byte register
Word register to/from word register
Dword register to/from dword register
A, #data
1
1
Rmd, Rms
WRjd, WRjs
DRkd, DRks
2
1
3
2
5
4
Immediate 8-bit data to/from byte
register
Rm, #data
4
5
5
4
4
5
5
4
3
4
3
4
4
3
3
4
4
3
2
3
Immediate 16-bit data to/from word
register
WRj, #data16
DRk,
#0data16
16-bit unsigned immediate data
to/from dword register
6
5
Direct address (on-chip RAM or SFR)
to/from byte register
Rm, dir8
3(2)
2(2)
ADD/SUB
Direct address (on-chip RAM or SFR)
to/from word register
WRj, dir8
4
3
Direct address (64K) to/from byte
register
Rm, dir16
WRj, dir16
Rm, at WRj
3(3)
4(4)
3(3)
2(3)
3(4)
2(3)
Direct address (64K) to/from word
register
Indirect address (64K) to/from byte
register
Indirect address (16M) to/from byte
register
Rm, at DRk
A, Rn
4
1
2
4(3)
1
3
2
2
3(3)
2
Register to/from ACC with carry
Direct address (on-chip RAM or SFR)
to/from ACC with carry
A, dir8
1(2)
1(2)
ADDC/SU
Indirect address to/from ACC with
carry
BB
A, at Ri
1
2
2
1
2
2
3
1
Immediate data to/from ACC with
carry
A, #data
Notes: 1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states.
Add 2 if it addresses a Peripheral SFR.
3. If this instruction addresses external memory location, add N+2 to the number of
states (N: number of wait states).
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4. If this instruction addresses external memory location, add 2(N+2) to the number of
states (N: number of wait states).
Table 21. Summary of Increment and Decrement Instructions
IncrementINC <dest>dest opnd ← dest opnd + 1
IncrementINC <dest>, <src>dest opnd ← dest opnd + src opnd
DecrementDEC <dest>dest opnd ← dest opnd - 1
DecrementDEC <dest>, <src>dest opnd ← dest opnd - src opnd
Binary Mode
Source Mode
<dest>,
<src>(1)
Mnemonic
Comments
ACC by 1
Bytes
States Bytes States
A
1
1
1
1
1
2
1
2
Rn
Register by 1
INC
Direct address (on-chip RAM or
SFR) by 1
DEC
dir8
2
2(2)
2
2(2)
at Ri
Indirect address by 1
1
3
3
3
3
1
3
2
2
4
5
1
2
2
2
2
2
1
4
1
1
3
4
1
Rm, #short
WRj, #short
DRk, #short
DRk, #short
DPTR
Byte register by 1, 2, or 4
Word register by 1, 2, or 4
Double word register by 1, 2, or 4
Double word register by 1, 2, or 4
Data pointer by 1
INC
DEC
INC
DEC
INC
Notes: 1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x = 0-3), add 2 to the number of states.
Add 3 if it addresses a Peripheral SFR.
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Table 22. Summary of Compare Instructions
CompareCMP <dest>, <src>dest opnd - src opnd
Binary Mode
Source Mode
<dest>,
Mnemonic <src>(2)
Comments
Bytes
States Bytes States
Rmd, Rms Register with register
3
2
3
2
2
1
2
WRjd,
Word register with word register
3
WRjs
DRkd,
DRks
Dword register with dword register
3
4
5
5
3
4
2
3
4
4
2
3
Rm, #data Register with immediate data
WRj,
#data16
Word register with immediate 16-bit data
DRk,
#0data16
Dword register with zero-extended 16-bit
immediate data
5
5
4
4
6
6
4
4
3
3
5
5
CMP
DRk,
#1data16
Dword register with one-extended 16-bit
immediate data
Direct address (on-chip RAM or SFR) with
byte register
Rm, dir8
3(1)
2(1)
Direct address (on-chip RAM or SFR) with
word register
WRj, dir8
Rm, dir16
4
3
Direct address (64K) with byte register
5
5
4
4
3(2)
4(3)
3(2)
4(2)
4
4
3
3
2(2)
3(3)
2(2)
3(2)
WRj, dir16 Direct address (64K) with word register
Rm, at WRj Indirect address (64K) with byte register
Rm, at DRk Indirect address (16M) with byte register
Notes: 1. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states.
Add 2 if it addresses a Peripheral SFR.
2. If this instruction addresses external memory location, add N+2 to the number of
states (N: number of wait states).
3. If this instruction addresses external memory location, add 2(N+2) to the number of
states (N: number of wait states).
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Logical AND(1)ANL <dest>, <src>dest opnd ← dest opnd Λ src opnd
Logical OR(1)ORL <dest>, <src>dest opnd ← dest opnd ς src opnd
Logical Exclusive OR(1)XRL <dest>, <src>dest opnd ← dest opnd ∀ src opnd
Clear(1)CLR A(A) ← 0
Complement(1)CPL A(A) ← ∅ (A)
Rotate LeftRL A(A)n+1 ← (A)n, n = 0..6
(A)0 ← (A)7
Rotate Left CarryRLC A(A)n+1 ← (A)n, n = 0..6
(CY) ← (A)7
(A)0 ← (CY)
Rotate RightRR A(A)n-1 ← (A)n, n = 7..1
(A)7 ← (A)0
Rotate Right CarryRRC A(A)n-1 ← (A)n, n = 7..1
(CY) ← (A)0
(A)7 ← (CY)
Binary Mode
Source Mode
Bytes States
Mnemonic
<dest>, <src>(1)
A, Rn
Comments
Bytes
States
register to ACC
1
2
1
2
2
3
3
3
4
5
1
1(3)
2
2
2
2
2
2
3
2
2
3
4
2
1(3)
3
A, dir8
Direct address (on-chip RAM or SFR) to ACC
Indirect address to ACC
A, at Ri
A, #data
Immediate data to ACC
1
1
dir8, A
ACC to direct address
2(4)
3(4)
2
2(4)
3(4)
1
dir8, #data
Rmd, Rms
WRjd, WRjs
Rm, #data
WRj, #data16
Immediate 8-bit data to direct address
Byte register to byte register
Word register to word register
Immediate 8-bit data to byte register
Immediate 16-bit data to word register
3
2
ANL
ORL
XRL
3
2
4
3
Direct address (on-chip RAM or SFR) to byte
register
Rm, dir8
WRj, dir8
4
4
3(3)
3
3
2(3)
Direct address (on-chip RAM or SFR) to word
register
4
3
Rm, dir16
Direct address (64K) to byte register
Direct address (64K) to word register
Indirect address (64K) to byte register
Indirect address (16M) to byte register
Clear ACC
5
5
4
4
1
1
1
1
1
1
3(5)
4(6)
3(5)
4(5)
1
4
4
3
3
1
1
1
1
1
1
2(5)
3(6)
2(5)
3(5)
1
WRj, dir16
Rm, at WRj
Rm, at DRk
CLR
CPL
RL
A
A
A
A
A
A
Complement ACC
1
1
Rotate ACC left
1
1
RLC
RR
Rotate ACC left through CY
Rotate ACC right
1
1
1
1
RRC
Rotate ACC right through CY
1
1
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Notes: 1. Logical instructions that affect a bit are in Table 27.
2. A shaded cell denotes an instruction in the C51 Architecture.
3. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. If this instruction addresses an I/O Port (Px, x = 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
5. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
6. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).
Table 23. Summary of Logical Instructions (2/2)
Shift Left LogicalSLL <dest><dest>0 ← 0
<dest>n+1 ← <dest>n, n = 0..msb-1
(CY) ← <dest>msb
Shift Right ArithmeticSRA <dest><dest>msb ← <dest>msb
<dest>n-1 ← <dest>n, n = msb..1
(CY) ← <dest>0
Shift Right LogicalSRL <dest><dest>msb ← 0
<dest>n-1 ← <dest>n, n = msb..1
(CY) ← <dest>0
SwapSWAP AA3:0 A7:4
Binary Mode
Source Mode
<dest>,
<src>(1)
Mnemonic
Comments
Bytes
States Bytes States
Shift byte register left through the
MSB
Rm
3
2
2
2
2
1
1
SLL
Shift word register left through the
MSB
WRj
3
Rm
WRj
Rm
WRj
A
Shift byte register right
Shift word register right
Shift byte register left
Shift word register left
Swap nibbles within ACC
3
3
3
3
1
2
2
2
2
2
2
2
2
2
1
1
1
1
1
2
SRA
SRL
SWAP
Note:
1. A shaded cell denotes an instruction in the C51 Architecture.
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Table 24. Summary of Multiply, Divide and Decimal-adjust Instructions
MultiplyMUL AB(B:A) ← (A)×(B)
MUL <dest>, <src>extended dest opnd ← dest opnd × src opnd
DivideDIV AB(A) ← Quotient ((A) ⁄ (B))
(B) ← Remainder ((A) ⁄ (B))
DivideDIV <dest>, <src>ext. dest opnd high ← Quotient (dest opnd ⁄ src opnd)
ext. dest opnd low ← Remainder (dest opnd ⁄ src opnd)
Decimal-adjust ACCDA AIF [[(A)3:0 > 9] ∨ [(AC) = 1]]
for Addition (BCD)
THEN (A)3:0 ← (A)3:0 + 6 !affects CY;
IF [[(A)7:4 > 9] ∨ [(CY) = 1]]
THEN (A)7:4 ← (A)7:4 + 6
Binary Mode
Source Mode
<dest>,
Mnemonic
<src>(1)
Comments
Bytes States Bytes States
AB
Rmd, Rms
Multiply A and B
1
3
3
1
3
3
1
5
6
1
2
2
1
2
2
1
5
5
MUL
DIV
Multiply byte register and byte register
WRjd, WRjs Multiply word register and word register
12
10
11
21
1
11
10
10
20
1
AB
Divide A and B
Rmd, Rms
Divide byte register and byte register
WRjd, WRjs Divide word register and word register
Decimal adjust ACC
DA
A
Note:
1. A shaded cell denotes an instruction in the C51 Architecture.
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Table 25. Summary of Move Instructions (1/3)
Move to High wordMOVH <dest>, <src>dest opnd31:16 ← src opnd
Move with Sign extensionMOVS <dest>, <src>dest opnd ← src opnd with sign extend
Move with Zero extensionMOVZ <dest>, <src>dest opnd ← src opnd with zero extend
Move CodeMOVC A, <src>(A) ← src opnd
Move eXtendedMOVX <dest>, <src>dest opnd ← src opnd
Binary Mode
Source Mode
<dest>,
Mnemonic
<src>(2)
Comments
Bytes
States Bytes States
16-bit immediate data into upper
word of dword register
MOVH
DRk, #data16
5
3
2
2
4
2
2
2
1
1
Byte register to word register with
sign extension
MOVS
MOVZ
WRj, Rm
WRj, Rm
3
3
Byte register to word register with
zeros extension
Code byte relative to DPTR to
ACC
A, at A +DPTR
A, at A +PC
A, at Ri
1
1
1
6(3)
6(3)
4
1
1
1
6(3)
6(3)
5
MOVC
Code byte relative to PC to ACC
Extended memory (8-bit address)
to ACC(2)
Extended memory (16-bit
address) to ACC(2)
A, at DPTR
at Ri, A
1
1
1
3(4)
1
1
1
3(4)
MOVX
ACC to extended memory (8-bit
address)(2)
4
4
ACC to extended memory (16-bit
address)(2)
at DPTR, A
4(3)
4(3)
Notes: 1. A shaded cell denotes an instruction in the C51 Architecture.
2. Extended memory addressed is in the region specified by DPXL (reset value = 01h).
3. If this instruction addresses external memory location, add N+1 to the number of
states (N: number of wait states).
4. If this instruction addresses external memory location, add N+2 to the number of
states (N: number of wait states).
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Table 26. Summary of Move Instructions (2/3)
Move(1)MOV <dest>, <src>dest opnd ← src opnd
Binary Mode
Source Mode
<dest>,
Mnemonic <src>(2)
Comments
Bytes
States
Bytes
States
A, Rn
Register to ACC
1
1
2
2
Direct address (on-chip RAM or SFR)
to ACC
A, dir8
2
1(3)
2
1(3)
A, at Ri
A, #data
Rn, A
Indirect address to ACC
Immediate data to ACC
ACC to register
1
2
1
2
1
1
2
2
2
3
1
2
Direct address (on-chip RAM or SFR)
to register
Rn, dir8
Rn, #data
dir8, A
2
2
2
1(3)
1
3
3
2
2(3)
2
Immediate data to register
ACC to direct address (on-chip RAM or
SFR)
2(3)
2(3)
Register to direct address (on-chip
RAM or SFR)
dir8, Rn
MOV
2
3
2
2(3)
3(4)
3(3)
3
3
3
3(3)
3(4)
4(3)
Direct address to direct address (on-
chip RAM or SFR)
dir8, dir8
dir8, at Ri
Indirect address to direct address (on-
chip RAM or SFR)
Immediate data to direct address (on-
chip RAM or SFR)
dir8, #data
at Ri, A
3
1
2
2
3
3(3)
3
3
2
3
3
3
3(3)
4
ACC to indirect address
Direct address (on-chip RAM or SFR)
to indirect address
at Ri, dir8
3(3)
3
4(3)
4
at Ri, #data Immediate data to indirect address
DPTR,
#data16
Load Data Pointer with a 16-bit
constant
2
2
Notes: 1. Instructions that move bits are in Table 27.
2. Move instructions from the C51 Architecture.
3. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states.
Add 2 if it addresses a Peripheral SFR.
4. Apply note 3 for each dir8 operand.
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Move(1)MOV <dest>, <src>dest opnd ← src opnd
Binary Mode
Source Mode
Mnemonic <dest>, <src>(1) Comments
Bytes
States
2
Bytes
States
1
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
Rmd, Rms
WRjd, WRjs
DRkd, DRks
Rm, #data
WRj, #data16
DRk, #0data16
DRk, #1data16
Rm, dir8
Byte register to byte register
3
3
3
4
5
5
5
4
4
4
5
5
5
4
4
4
4
4
4
4
5
5
5
4
4
4
4
2
2
2
3
4
4
4
3
3
3
4
4
4
3
3
3
3
3
3
3
4
4
4
3
3
3
3
Word register to word register
2
1
Dword register to dword register
3
2
Immediate 8-bit data to byte register
3
2
Immediate 16-bit data to word register
zero-ext 16bit immediate data to dword register
one-ext 16bit immediate data to dword register
Direct address (on-chip RAM or SFR) to byte register
Direct address (on-chip RAM or SFR) to word register
Direct address (on-chip RAM or SFR) to dword register
Direct address (64K) to byte register
3
2
5
4
5
4
3(3)
4
2(3)
3
WRj, dir8
DRk, dir8
6
5
Rm, dir16
3(4)
4(5)
6(6)
3(4)
4(4)
4(5)
5(5)
4(3)
5
2(4)
3(5)
5(6)
2(4)
3(4)
3(5)
4(5)
3(3)
4
WRj, dir16
DRk, dir16
Rm, at WRj
Rm, at DRk
WRjd, at WRjs
WRj, at DRk
dir8, Rm
Direct address (64K) to word register
Direct address (64K) to dword register
Indirect address (64K) to byte register
Indirect address (16M) to byte register
Indirect address (64K) to word register
Indirect address (16M) to word register
Byte register to direct address (on-chip RAM or SFR)
Word register to direct address (on-chip RAM or SFR)
Dword register to direct address (on-chip RAM or SFR)
Byte register to direct address (64K)
dir8, WRj
dir8, DRk
7
6
dir16, Rm
4(4)
5(5)
7(6)
4(4)
5(4)
5(5)
6(5)
3(4)
4(5)
6(6)
3(4)
4(4)
4(5)
5(5)
dir16, WRj
dir16, DRk
at WRj, Rm
at DRk, Rm
at WRjd, WRjs
at DRk, WRj
Word register to direct address (64K)
Dword register to direct address (64K)
Byte register to indirect address (64K)
Byte register to indirect address (16M)
Word register to indirect address (64K)
Word register to indirect address (16M)
Rm, at WRj
+dis16
MOV
MOV
MOV
Indirect with 16-bit displacement (64K) to byte register
Indirect with 16-bit displacement (64K) to word register
Indirect with 16-bit displacement (16M) to byte register
5
5
5
6(4)
7(5)
7(4)
4
4
4
5(4)
6(5)
6(4)
WRj, at WRj
+dis16
Rm, at DRk
+dis24
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WRj, at WRj
+dis24
MOV
MOV
MOV
MOV
MOV
Indirect with 16-bit displacement (16M) to word register
Byte register to indirect with 16-bit displacement (64K)
Word register to indirect with 16-bit displacement (64K)
Byte register to indirect with 16-bit displacement (16M)
Word register to indirect with 16-bit displacement (16M)
5
5
5
5
5
8(5)
6(4)
7(5)
7(4)
8(5)
4
4
4
4
4
7(5)
5(4)
6(5)
6(4)
7(5)
at WRj +dis16,
Rm
at WRj +dis16,
WRj
at DRk +dis24,
Rm
at DRk +dis24,
WRj
Notes: 1. Instructions that move bits are in Table 27.
2. Move instructions unique to the C251 Architecture.
3. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
5. If this instruction addresses external memory location, add 2(N+1) to the number of states (N: number of wait states).
6. If this instruction addresses external memory location, add 4(N+2) to the number of states (N: number of wait states).
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4135D–8051–08/05
Table 27. Summary of Bit Instructions
Clear BitCLR <dest>dest opnd ← 0
Set BitSETB <dest>dest opnd ← 1
Complement BitCPL <dest>dest opnd ← ∅ bit
AND Carry with BitANL CY, <src>(CY) ← (CY) ∧ src opnd
AND Carry with Complement of BitANL CY, /<src>(CY) ← (CY) ∧ ∅ src opnd
OR Carry with BitORL CY, <src>(CY) ← (CY) ∨ src opnd
OR Carry with Complement of BitORL CY, /<src>(CY) ← (CY) ∨ ∅ src opnd
Move Bit to CarryMOV CY, <src>(CY) ← src opnd
Move Bit from CarryMOV <dest>, CYdest opnd ← (CY)
Binary Mode
Source Mode
<dest>,
<src>(1)
Mnemonic
Comments
Bytes
States
1
Bytes
States
1
CY
Clear carry
1
2
4
1
2
4
1
2
4
2
4
1
2
3
1
2
3
1
2
3
2
3
CLR
bit51
bit
Clear direct bit
Clear direct bit
Set carry
2(3)
4(3)
1
2(3)
3(3)
1
CY
SETB
CPL
bit51
bit
Set direct bit
2(3)
4(3)
1
2(3)
3(3)
1
Set direct bit
CY
Complement carry
Complement direct bit
Complement direct bit
And direct bit to carry
And direct bit to carry
bit51
bit
2(3)
4(3)
1(2)
3(2)
2(3)
3(3)
1(2)
2(2)
CY, bit51
CY, bit
And complemented direct bit to
carry
ANL
CY, /bit51
CY, /bit
2
4
1(2)
3(2)
2
3
1(2)
2(2)
And complemented direct bit to
carry
CY, bit51
CY, bit
Or direct bit to carry
Or direct bit to carry
2
4
1(2)
3(2)
2
3
1(2)
2(2)
Or complemented direct bit to
carry
ORL
CY, /bit51
CY, /bit
2
4
1(2)
3(2)
2
3
1(2)
2(2)
Or complemented direct bit to
carry
CY, bit51
CY, bit
Move direct bit to carry
Move direct bit to carry
Move carry to direct bit
Move carry to direct bit
2
4
2
4
1(2)
3(2)
2(3)
4(3)
2
3
2
3
1(2)
2(2)
2(3)
3(3)
MOV
bit51, CY
bit, CY
Notes: 1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states.
Add 2 if it addresses a Peripheral SFR.
3. If this instruction addresses an I/O Port (Px, x = 0-3), add 2 to the number of states.
Add 3 if it addresses a Peripheral SFR.
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Table 28. Summary of Exchange, Push and Pop Instructions
Exchange bytesXCH A, <src>(A) ↔ src opnd
Exchange DigitXCHD A, <src>(A)3:0 ↔ src opnd3:0
PushPUSH <src>(SP) ← (SP) +1; ((SP)) ← src opnd;
(SP) ← (SP) + size (src opnd) - 1
PopPOP <dest>(SP) ← (SP) - size (dest opnd) + 1;
dest opnd ← ((SP)); (SP) ← (SP) -1
Binary Mode
Source Mode
<dest>,
Mnemonic
<src>(1)
Comments
Bytes States Bytes States
A, Rn
ACC and register
1
2
1
1
3
3(3)
4
2
2
2
2
4
3(3)
5
ACC and direct address (on-chip
RAM or SFR)
XCH
A, dir8
A, at Ri
A, at Ri
ACC and indirect address
ACC low nibble and indirect address
(256 bytes)
XCHD
PUSH
4
5
dir8
Push direct address onto stack
Push immediate data onto stack
2
4
2(2)
4
2
3
2(2)
3
#data
Push 16-bit immediate data onto
stack
#data16
5
5
4
5
Rm
Push byte register onto stack
Push word register onto stack
3
3
4
5
2
2
3
4
WRj
Push double word register onto
stack
DRk
dir8
3
2
9
2
2
8
Pop direct address (on-chip RAM or
SFR) from stack
3(2)
3(2)
Rm
Pop byte register from stack
3
3
3
3
5
9
2
2
2
2
4
8
POP
WRj
DRk
Pop word register from stack
Pop double word register from stack
Notes: 1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states.
Add 2 if it addresses a Peripheral SFR.
3. If this instruction addresses an I/O Port (Px, x = 0-3), add 2 to the number of states.
Add 3 if it addresses a Peripheral SFR.
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4135D–8051–08/05
Table 29. Summary of Conditional Jump Instructions (1/2)
Jump conditional on statusJcc rel(PC) ← (PC) + size (instr);
IF [cc] THEN (PC) ← (PC) + rel
Binary Mode
Source Mode
<dest>,
Mnemonic
JC
<src>(1)
Comments
Bytes
States
1/4(3)
1/4(3)
2/5(3)
2/5(3)
2/5(3)
2/5(3)
2/5(3)
2/5(3)
2/5(3)
2/5(3)
Bytes
States
1/4(3)
1/4(3)
1/4(3)
1/4(3)
1/4(3)
1/4(3)
1/4(3)
1/4(3)
1/4(3)
1/4(3)
rel
Jump if carry
2
2
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
JNC
JE
rel
Jump if not carry
rel
Jump if equal
JNE
JG
rel
Jump if not equal
rel
Jump if greater than
JLE
rel
Jump if less than, or equal
Jump if less than (signed)
Jump if less than, or equal (signed)
Jump if greater than (signed)
Jump if greater than or equal (signed)
JSL
rel
JSLE
JSG
JSGE
rel
rel
rel
Notes: 1. A shaded cell denotes an instruction in the C51 Architecture.
2. States are given as jump not-taken/taken.
3. In internal execution only, add 1 to the number of states of the ‘jump taken’ if the des-
tination address is internal and odd.
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Table 30. Summary of Conditional Jump Instructions (2/2)
Jump if bitJB <src>, rel(PC) ← (PC) + size (instr);
IF [src opnd = 1] THEN (PC) ← (PC) + rel
Jump if not bitJNB <src>, rel(PC) ← (PC) + size (instr);
IF [src opnd = 0] THEN (PC) ← (PC) + rel
Jump if bit and clearJBC <dest>, rel(PC) ← (PC) + size (instr);
IF [dest opnd = 1] THEN
dest opnd ← 0
(PC) ← (PC) + rel
Jump if accumulator is zeroJZ rel(PC) ← (PC) + size (instr);
IF [(A) = 0] THEN (PC) ← (PC) + rel
Jump if accumulator is not zeroJNZ rel(PC) ← (PC) + size (instr);
IF [(A) ≠ 0] THEN (PC) ← (PC) + rel
Compare and jump if not equalCJNE <src1>, <src2>, rel(PC) ← (PC) + size (instr);
IF [src opnd1 < src opnd2] THEN (CY) ← 1
IF [src opnd1 ≥ src opnd2] THEN (CY) ← 0
IF [src opnd1 ≠ src opnd2] THEN (PC) ← (PC) + rel
Decrement and jump if not zeroDJNZ <dest>, rel(PC) ← (PC) + size (instr); dest opnd ← dest opnd -1;
IF [ϕ (Z)] THEN (PC) ← (PC) + rel
Binary Mode(2)
Source Mode(2)
Mnemonic <dest>, <src>(1) Comments
Bytes
States Bytes States
bit51, rel
bit, rel
Jump if direct bit is set
3
2/5(3)(6)
4/7(3)(6)
2/5(3)(6)
4/7(3)(6)
4/7(5)(6)
3
4
3
4
3
4
2/5(3)(6)
3/6(3)(6)
2/5(3)(6)
3/6(3)
JB
Jump if direct bit of 8-bit address
location is set
5
3
5
3
5
bit51, rel
bit, rel
Jump if direct bit is not set
JNB
JBC
Jump if direct bit of 8-bit address
location is not set
bit51, rel
bit, rel
Jump if direct bit is set & clear bit
4/7(5)(6)
6/9(5)(6)
Jump if direct bit of 8-bit address
location is set and clear
7/10(5)(
6)
JZ
rel
rel
Jump if ACC is zero
2
2
2/5(6)
2/5(6)
2
2
2/5(6)
2/5(6)
JNZ
Jump if ACC is not zero
Compare direct address to ACC and
jump if not equal
A, dir8, rel
A, #data, rel
Rn, #data, rel
at Ri, #data, rel
Rn, rel
3
3
3
3
2
3
2/5(3)(6)
2/5(6)
3
3
4
4
3
3
2/5(3)(6)
2/5(6)
Compare immediate to ACC and
jump if not equal
CJNE
Compare immediate to register and
jump if not equal
2/5(6)
3/6(6)
Compare immediate to indirect and
jump if not equal
3/6(6)
4/7(6)
Decrement register and jump if not
zero
2/5(6)
3/6(6)
DJNZ
Decrement direct address and jump
if not zero
dir8, rel
3/6(4)(6)
3/6(4)(6)
Notes: 1. A shaded cell denotes an instruction in the C51 Architecture.
2. States are given as jump not-taken/taken.
3. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states.
Add 2 if it addresses a Peripheral SFR.
4. If this instruction addresses an I/O Port (Px, x = 0-3), add 2 to the number of states.
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4135D–8051–08/05
Add 3 if it addresses a Peripheral SFR.
5. If this instruction addresses an I/O Port (Px, x = 0-3), add 3 to the number of states.
Add 5 if it addresses a Peripheral SFR.
6. In internal execution only, add 1 to the number of states of the ‘jump taken’ if the des-
tination address is internal and odd.
Table 31. Summary of Unconditional Jump Instructions
Absolute jumpAJMP <src>(PC) ← (PC) +2; (PC)10:0 ← src opnd
Extended jumpEJMP <src>(PC) ← (PC) + size (instr); (PC)23:0 ← src opnd
Long jumpLJMP <src>(PC) ← (PC) + size (instr); (PC)15:0 ← src opnd
Short jumpSJMP rel(PC) ← (PC) +2; (PC) ← (PC) +rel
Jump indirectJMP at A +DPTR(PC)23:16 ← FFh; (PC)15:0 ← (A) + (DPTR)
No operationNOP(PC) ← (PC) +1
Binary Mode
Source Mode
<dest>,
<src>(1)
Mnemonic
Comments
Bytes
States
Bytes
States
3(2)(3)
5(2)(4)
6(2)(4)
5(2)(4)
5(2)(4)
4(2)(4)
5(2)(4)
1
AJMP
addr11
addr24
at DRk
at WRj
addr16
rel
Absolute jump
2
5
3
3
3
2
1
1
3(2)(3)
6(2)(4)
7(2)(4)
6(2)(4)
5(2)(4)
4(2)(4)
5(2)(4)
1
2
4
2
2
3
2
1
1
Extended jump
EJMP
LJMP
Extended jump (indirect)
Long jump (indirect)
Long jump (direct address)
Short jump (relative address)
SJMP
JMP
at A +DPTR Jump indirect relative to the DPTR
No operation (Jump never)
NOP
Notes: 1. A shaded cell denotes an instruction in the C51 Architecture.
2. In internal execution only, add 1 to the number of states if the destination address is
internal and odd.
3. Add 2 to the number of states if the destination address is external.
4. Add 3 to the number of states if the destination address is external.
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AT/TSC8x251G2D
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AT/TSC8x251G2D
Table 32. Summary of Call and Return Instructions
Absolute callACALL <src>(PC) ← (PC) +2; push (PC)15:0
(PC)10:0 ← src opnd
;
Extended callECALL <src>(PC) ← (PC) + size (instr); push (PC)23:0
(PC)23:0 ← src opnd
;
Long callLCALL <src>(PC) ← (PC) + size (instr); push (PC)15:0
;
(PC)15:0 ← src opnd
Return from subroutineRETpop(PC)15:0
Extended return from subroutineERETpop(PC)23:0
Return from interruptRETIIF [INTR = 0] THEN pop (PC)15:0
IF [INTR = 1] THEN pop (PC)23:0; pop (PSW1)
Trap interruptTRAP(PC) ← (PC) + size (instr);
IF [INTR = 0] THEN push (PC)15:0
IF [INTR = 1] THEN push (PSW1); push (PC)23:0
Binary Mode
Bytes States
Source Mode
<dest>,
Mnemonic
<src>(1)
addr11
at DRk
addr24
at WRj
addr16
Comments
Bytes
States
9(2)(3)
13(2)(3)
13(2)(3)
9(2)(3)
9(2)(3)
7(2)
ACALL
Absolute subroutine call
Extended subroutine call (indirect)
Extended subroutine call
Long subroutine call (indirect)
Long subroutine call
2
3
5
3
3
1
3
1
2
9(2)(3)
14(2)(3)
14(2)(3)
10(2)(3)
9(2)(3)
7(2)
2
2
4
2
3
1
2
1
1
ECALL
LCALL
RET
Return from subroutine
Extended subroutine return
Return from interrupt
ERET
RETI
TRAP
9(2)
8(2)
7(2)(4)
12(4)
7(2)(4)
11(4)
Jump to the trap interrupt vector
Notes: 1. A shaded cell denotes an instruction in the C51 Architecture.
2. In internal execution only, add 1 to the number of states if the destination/return
address is internal and odd.
3. Add 2 to the number of states if the destination address is external.
4. Add 5 to the number of states if INTR = 1.
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4135D–8051–08/05
Programming and Verifying Non-volatile Memory
Internal Features
The internal non-volatile memory of the TSC80251G2D derivatives contains five differ-
ent areas:
•
•
•
•
•
Code Memory
Configuration Bytes
Lock Bits
Encryption Array
Signature Bytes
EPROM/OTPROM Devices
All the internal non-volatile memory but the Signature Bytes of the TSC87251G2D prod-
ucts is made of EPROM cells. The Signature Bytes of the TSC87251G2D products are
made of Mask ROM.
The TSC87251G2D products are programmed and verified in the same manner as
Atmel’s TSC87251G1A, using a SINGLE-PULSE algorithm, which programs at
V
PP = 12.75V using only one 100µs pulse per byte. This results in a programming time
of less than 10 seconds for the 32 kilobytes on-chip code memory.
The EPROM of the TSC87251G2D products in Window package is erasable by Ultra-
Violet radiation(1) (UV). UV erasure set all the EPROM memory cells to one and allows
reprogramming. The quartz window must be covered with an opaque label(2) when the
device is in operation. This is not so much to protect the EPROM array from inadvertent
erasure, as to protect the RAM and other on-chip logic. Allowing light to impinge on the
silicon die during device operation may cause a logical malfunction.
The TSC87251G2D products in plastic packages are One Time Programmable (OTP).
An EPROM cell cannot be reset by UV once programmed to zero.
Notes: 1. The recommended erasure procedure is exposure to ultra-violet light (at 2537 Å) to
an integrated dose of at least 20 W-sec/cm2. Exposing the EPROM to an ultra-violet
lamp of 12000 µW/cm2 rating for 30 minutes should be sufficient.
2. Erasure of the EPROM begins to occur when the chip is exposed to light wavelength
shorter than 4000 Å. Since sunlight and fluorescent light have wavelength in this
range, exposure to these light sources over an extended time (1 week in sunlight or 3
years in room-level fluorescent lighting) could cause inadvertent erasure.
Mask ROM Devices
ROMless Devices
All the internal non-volatile memory of TSC83251G2D products is made of Mask ROM
cells. They can only be verified by the user, using the same algorithm as the
EPROM/OTPROM devices.
The TSC80251G2D products do not include on-chip Configuration Bytes, Code Memory
and Encryption Array. They only include Signature Bytes made of Mask ROM cells
which can be read using the same algorithm as the EPROM/OTPROM devices.
Security Features
In some microcontroller applications, it is desirable that the user’s program code be
secured from unauthorized access. The TSC83251G2D and TSC87251G2D offer two
kinds of protection for program code stored in the on-chip array:
•
Program code in the on-chip Code Memory is encrypted when read out for
verification if the Encryption Array isprogrammed.
•
A three-level lock bit system restricts external access to the on-chip code memory.
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AT/TSC8x251G2D
4135D–8051–08/05
AT/TSC8x251G2D
Lock Bit System
The TSC87251G2D products implement 3 levels of security for User’s program as
described in Table 33. The TSC83251G2D products implement only the first level of
security.
Level 0 is the level of an erased part and does not enable any security features.
Level 1 locks the programming of the User’s internal Code Memory, the Configuration
Bytes and the Encryption Array.
Level 2 locks the verifying of the User’s internal Code Memory. It is always possible to
verify the Configuration Bytes and the Lock Bits. It is not possible to verify the Encryp-
tion Array.
Level 3 locks the external execution.
Table 33. Lock Bits Programming
External
Lock bits
LB[2:0]
Internal
Execution
External
Execution
PROM read
(MOVC)
Level
Verification Programming
0
1
2
3
000
001
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Disable
Enable(1)
Enable(1)
Disable
Disable
Enable
Disable
Disable
Disable
Enable(2)
Disable
Disable
Disable
01x(3)
1xx(3)
Notes: 1. Returns encrypted data if Encryption Array is programmed.
2. Returns non encrypted data.
3. x means don’t care. Level 2 always enables level 1, and level 3 always enables levels
1 and 2.
The security level may be verified according to Table 34.
Table 34. Lock Bits Verifying
Level
Lock bits Data(1)
xxxxx000
0
1
xxxxx001
2
xxxxx01x
3
xxxxx1xx
Note:
1. x means don’t care.
Encryption Array
The TSC83251G2D and TSC87251G2D products include a 128-byte Encryption Array
located in non-volatile memory outside the memory address space. During verification
of the on-chip code memory, the seven low-order address bits also address the Encryp-
tion Array. As the byte of the code memory is read, it is exclusive-NOR’ed (XNOR) with
the key byte from the Encryption Array. If the Encryption Array is not programmed (still
all 1s), the user program code is placed on the data bus in its original, unencrypted form.
If the Encryption Array is programmed with key bytes, the user program code is
encrypted and cannot be used without knowledge of the key byte sequence.
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4135D–8051–08/05
To preserve the secrecy of the encryption key byte sequence, the Encryption Array can
not be verified.
Notes: 1. When a MOVC instruction is executed, the content of the ROM is not encrypted. In
order to fully protect the user program code, the lock bit level 1 (see Table 33) must
always be set when encryption is used.
2. If the encryption feature is implemented, the portion of the on-chip code memory that
does not contain program code should be filled with “random” byte values to prevent
the encryption key sequence from being revealed.
Signature Bytes
The TSC80251G2D derivatives contain factory-programmed Signature Bytes. These
bytes are located in non-volatile memory outside the memory address space at 30h,
31h, 60h and 61h. To read the Signature Bytes, perform the procedure described in sec-
tion Verify Algorithm, using the verify signature mode (see Table 37). Signature byte
values are listed in Table 35.
Table 35. Signature Bytes (Electronic ID)
Signature Address
Signature Data
Vendor
Atmel
C251
30h
31h
58h
40h
Architecture
32 kilobytes EPROM or
OTPROM
F7h
77h
FDh
Memory
Revision
60h
61h
32 kilobytes MaskROM
or ROMless
TSC80251G2D
derivative
Programming Algorithm Figure 6 shows the hardware setup needed to program the TSC87251G2D
EPROM/OTPROM areas:
•
The chip has to be put under reset and maintained in this state until completion of
the programming sequence.
•
•
PSEN# and the other control signals (ALE and Port 0) have to be set to a high level.
Then PSEN# has to be to forced to a low level after two clock cycles or more and it
has to be maintained in this state until the completion of the programming sequence
(see below).
•
•
The voltage on the EA# pin must be set to VDD.
The programming mode is selected according to the code applied on Port 0 (see
Table 36). It has to be applied until the completion of this programming operation.
•
The programming address is applied on Ports 1 and 3 which are respectively the
Most Significant Byte (MSB) and the Least Significant Byte (LSB) of the address.
•
•
The programming data are applied on Port 2.
The EPROM Programming is done by raising the voltage on the EA# pin to VPP,
then by generating a low level pulse on ALE/PROG# pin.
•
•
The voltage on the EA# pin must be lowered to VDD before completing the
programming operation.
It is possible to alternate programming and verifying operation (See Paragraph
Verify Algorithm). Please make sure the voltage on the EA# pin has actually been
lowered to VDD before performing the verifying operation.
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AT/TSC8x251G2D
4135D–8051–08/05
AT/TSC8x251G2D
•
PSEN# and the other control signals have to be released to complete a sequence of
programming operations or a sequence of programming and verifying operations.
Figure 6. Setup for Programming
VDD
VDD
RST
VDD
VPP
EA#/VPP
ALE/PROG#
PSEN#
100 ms pulses
TSC87251G2D
Mode
A[7:0]
A[14:8]
Data
P0[7:0]
P3[7:0]
P1[7:0]
P2[7:0]
4 to 12 MHz
XTAL1
VSS/VSS1/VSS2
Table 36. Programming Modes
PSEN
#
ROM Area(1)
RST EA#/VPP
ALE/PROG#(2)
P0
P2
P1(MSB) P3(LSB)
16-bit Address
On-chip Code
Memory
1
1
VPP
0
0
1 Pulse
68h
69h
Data 0000h-7FFFh (32
kilobytes)
Configuration
Bytes
CONFIG0: FFF8h
Data
VPP
1 Pulse
CONFIG1: FFF9h
LB0: 0001h
Lock Bits
1
1
VPP
VPP
0
0
1 Pulse
1 Pulse
6Bh
6Ch
X
LB1: 0002h
LB2: 0003h
Encryption Array
Data 0000h-007Fh
Notes: 1. Signature Bytes are not user-programmable.
2. The ALE/PROG# pulse waveform is shown in Figure 23 page 59.
Verify Algorithm
Figure 7 shows the hardware setup needed to verify the TSC87251G2D
EPROM/OTPROM or TSC83251G2D ROM areas:
•
The chip has to be put under reset and maintained in this state until the completion
of the verifying sequence.
•
•
PSEN# and the other control signals (ALE and Port 0) have to be set to a high level.
Then PSEN# has to be to forced to a low level after two clock cycles or more and it
has to be maintained in this state until the completion of the verifying sequence (see
below).
•
•
The voltage on the EA# pin must be set to VDD and ALE must be set to a high level.
The Verifying Mode is selected according to the code applied on Port 0. It has to be
applied until the completion of this verifying operation.
•
The verifying address is applied on Ports 1 and 3 which are respectively the MSB
and the LSB of the address.
43
4135D–8051–08/05
•
•
Then device is driving the data on Port 2.
It is possible to alternate programming and verification operation (see Paragraph
Programming Algorithm). Please make sure the voltage on the EA# pin has actually
been lowered to VDD before performing the verifying operation.
•
PSEN# and the other control signals have to be released to complete a sequence of
verifying operations or a sequence of programming and verifying operations.
Table 37. Verifying Modes
ROM Area(1)
RST EA#/VPP PSEN# ALE/PROG#
P0
P2
P1(MSB) P3(LSB)
16-bit Address
Data 0000h-7FFFh (32
kilobytes)
On-chip code
memory
1
1
0
1
28h
CONFIG0: FFF8h
Data
Configuration Bytes
Lock Bits
1
1
1
1
1
1
0
0
0
1
1
1
29h
CONFIG1: FFF9h
2Bh Data 0000h
0030h, 0031h, 0060h,
0061h
Signature Bytes
29h
Data
Notes: 1. To preserve the secrecy of on-chip code memory when encrypted, the Encryption
Array can not be verified.
Figure 7. Setup for Verifying
VDD
VDD
RST
VDD
EA#/VPP
ALE/PROG#
PSEN#
TSC8x251G2D
Mode
A[7:0]
P0[7:0]
P3[7:0]
P1[7:0]
P2[7:0]
Data
XTAL1
4 to 12 MHz
A[14:8]
VSS/VSS1/VSS2
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AT/TSC8x251G2D
AC Characteristics - Commercial & Industrial
AC Characteristics - External Bus Cycles
Definition of Symbols
Table 38. External Bus Cycles Timing Symbol Definitions
Signals
Conditions
A
D
L
Address
Data In
ALE
H
L
High
Low
V
X
Z
Valid
Q
R
W
Data Out
No Longer Valid
Floating
RD#/PSEN#
WR#
Timings
Test conditions: capacitive load on all pins = 50 pF.
Table 39 and Table 40 list the AC timing parameters for the TSC80251G2D derivatives
with no wait states. External wait states can be added by extending PSEN#/RD#/WR#
and or by extending ALE. In these tables, Note 2 marks parameters affected by one ALE
wait state, and Note 3 marks parameters affected by PSEN#/RD#/WR# wait states.
Figure 8 to Figure 13 show the bus cycles with the timing parameters.
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4135D–8051–08/05
Table 39. Bus Cycles AC Timings; VDD = 4.5 to 5.5 V, TA = -40 to 85°C
12 MHz
16 MHz
24 MHz
Symbol Parameter
Min
Max
Min
Max
Min
Max
Unit
ns
TOSC
TLHLL
TAVLL
TLLAX
1/FOSC
83
78
62
58
41
38
37
3
ALE Pulse Width
ns(2)
ns(2)
ns
Address Valid to ALE Low
Address hold after ALE Low
RD#/PSEN# Pulse Width
78
58
19
11
(1)
TRLRH
162
165
22
121
124
14
78
81
6
ns(3)
ns(3)
ns
TWLWH WR# Pulse Width
(1)
TLLRL
ALE Low to RD#/PSEN# Low
TLHAX ALE High to Address Hold
99
70
40
ns(2)
ns(3)
ns
(1)
TRLDV
RD#/PSEN# Low to Valid Data
146
104
61
(1)
TRHDX
Data Hold After RD#/PSEN# High
0
0
0
0
0
0
Address Hold After RD#/PSEN#
High
(1)
TRHAX
ns
ns
ns
ns
ns
(1)
TRLAZ
TRHDZ1
RD#/PSEN# Low to Address Float
0
0
0
Instruction Float After RD#/PSEN#
High
45
40
30
TRHDZ2 Data Float After RD#/PSEN# High
215
165
115
RD#/PSEN# high to ALE High
(Instruction)
TRHLH1
49
43
31
RD#/PSEN# high to ALE High
TRHLH2
(Data)
215
215
169
169
115
115
ns
TWHLH WR# High to ALE High
ns
TAVDV1 Address (P0) Valid to Valid Data In
TAVDV2 Address (P2) Valid to Valid Data In
250
306
175
223
105
140
ns(2)(3)
ns(2)(3)
Address (P0) Valid to Valid
Instruction In
TAVDV3
150
109
68
ns(3)
TAXDX Data Hold after Address Hold
0
0
0
ns
ns(2)
ns(2)
ns(2)
ns
(1)
TAVRL
Address Valid to RD# Low
100
100
158
90
70
40
40
74
32
72
84
TAVWL1 Address (P0) Valid to WR# Low
TAVWL2 Address (P2) Valid to WR# Low
TWHQX Data Hold after WR# High
TQVWH Data Valid to WR# High
70
115
69
133
167
102
125
ns(3)
ns
TWHAX WR# High to Address Hold
Notes: 1. Specification for PSEN# are identical to those for RD#.
2. If a wait state is added by extending ALE, add 2·TOSC.
3. If wait states are added by extending RD#/PSEN#/WR#, add 2N·TOSC (N = 1..3).
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AT/TSC8x251G2D
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AT/TSC8x251G2D
Table 40. Bus Cycles AC Timings; VDD = 2.7 to 5.5 V, TA = -40 to 85°C
12 MHz
16 MHz
Symbol Parameter
Min
Max
Min
Max
Unit
ns
TOSC
TLHLL
TAVLL
TLLAX
1/FOSC
83
72
62
52
51
6
ALE Pulse Width
ns(2)
ns(2)
ns
Address Valid to ALE Low
Address hold after ALE Low
RD#/PSEN# Pulse Width
71
14
(1)
TRLRH
163
165
17
121
124
11
ns(3)
ns(3)
ns
TWLWH WR# Pulse Width
(1)
TLLRL
ALE Low to RD#/PSEN# Low
TLHAX ALE High to Address Hold
90
57
ns(2)
ns(3)
ns
(1)
TRLDV
TRHDX
TRHAX
RD#/PSEN# Low to Valid Data
133
92
(1)
(1)
Data Hold After RD#/PSEN# High
Address Hold After RD#/PSEN# High
RD#/PSEN# Low to Address Float
0
0
0
0
ns
(1)
TRLAZ
0
0
ns
TRHDZ1 Instruction Float After RD#/PSEN# High
TRHDZ2 Data Float After RD#/PSEN# High
TRHLH1 RD#/PSEN# high to ALE High (Instruction)
TRHLH2 RD#/PSEN# high to ALE High (Data)
TWHLH WR# High to ALE High
59
48
ns
225
175
ns
60
47
ns
226
226
172
172
ns
ns
TAVDV1 Address (P0) Valid to Valid Data In
TAVDV2 Address (P2) Valid to Valid Data In
TAVDV3 Address (P0) Valid to Valid Instruction In
289
296
144
160
211
98
ns(2)(3)
ns(2)(3)
ns(3)
ns
TAXDX Data Hold after Address Hold
0
0
(1)
TAVRL
Address Valid to RD# Low
111
111
158
82
64
ns(2)
ns(2)
ns(2)
ns
TAVWL1 Address (P0) Valid to WR# Low
TAVWL2 Address (P2) Valid to WR# Low
TWHQX Data Hold after WR# High
TQVWH Data Valid to WR# High
64
116
66
135
168
103
125
ns(3)
ns
TWHAX WR# High to Address Hold
Notes: 1. Specification for PSEN# are identical to those for RD#.
2. If a wait state is added by extending ALE, add 2·TOSC.
3. If wait states are added by extending RD#/PSEN#/WR#, add 2N·TOSC (N = 1..3).
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4135D–8051–08/05
Waveforms in Non-Page Mode Figure 8. External Bus Cycle: Code Fetch (Non-Page Mode)
ALE
TLHLL(1)
TLLRL(1) TRLRH(1) TRHLH1
PSEN#
TRLDV(1)
TRLAZ
(1)
TLHAX
TRHDZ1
TRHDX
(1)
TAVLL
TLLAX
P0
A7:0
D7:0
(1)
Instruction In
TAVRL
(1)
TAVDV1
TRHAX
(1)
TAVDV2
P2/A16/A17
A15:8/A16/A17
Note:
1. The value of this parameter depends on wait states. See Table 39 and Table 40.
Figure 9. External Bus Cycle: Data Read (Non-Page Mode)
ALE
TLHLL(1)
TLLRL(1) TRLRH(1)
TRHLH2
RD#/PSEN#
TRLDV(1)
TRLAZ
(1)
TLHAX
TRHDZ2
TRHDX
(1)
TAVLL
TLLAX
P0
A7:0
D7:0
(1)
Data In
TAVRL
(1)
TAVDV1
TRHAX
(1)
TAVDV2
P2/A16/A17
A15:8/A16/A17
Note:
1. The value of this parameter depends on wait states. See Table 39 and Table 40.
48
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AT/TSC8x251G2D
Figure 10. External Bus Cycle: Data Write (Non-Page Mode)
ALE
TLHLL(1)
TWLWH(1)
TWHLH
WR#
(1)
TLHAX
TAVLL(1)
TQVWH
TWHQX
TLLAX
P0
A7:0
D7:0
(1)
Data Out
TAVWL1
(1)
TAVWL2
TWHAX
P2/A16/A17
A15:8/A16/A17
Note:
1. The value of this parameter depends on wait states. See Table 39 and Table 40.
Waveforms in Page Mode
Figure 11. External Bus Cycle: Code Fetch (Page Mode)
ALE
TLHLL(1)
TLLRL(1)
PSEN#(3)
TRLDV(1)
TRLAZ
(1)
TLHAX
TRHDZ1
TRHDX
TAVLL(1)
TLLAX
P2
A15:8
D7:0
D7:0
Instruction In
(1)
Instruction In
TAVRL
(1)
TAVDV1
TAXDX
(1)
(1)
TAVDV3
TAVDV2
TRHAX
P0/A16/A17
A7:0/A16/A17
Page Miss(2)
A7:0/A16/A17
Page Hit(2)
Note:
1. The value of this parameter depends on wait states. See Table 39 and Table 40.
2. A page hit (i.e., a code fetch to the same 256-byte “page” as the previous code fetch)
requires one state (2·TOSC);
a page miss requires two states (4·TOSC).
3. During a sequence of page hits, PSEN# remains low until the end of the last page-hit
cycle.
49
4135D–8051–08/05
Figure 12. External Bus Cycle: Data Read (Page Mode)
ALE
TLHLL(1)
TLLRL(1) TRLRH(1)
TRHLH2
RD#/PSEN#
TRLDV(1)
TRLAZ
(1)
TLHAX
TRHDZ2
TRHDX
(1)
TAVLL
TLLAX
P2
A15:8
TAVRL(1)
D7:0
Data In
(1)
TAVDV1
TRHAX
(1)
TAVDV2
P0/A16/A17
A7:0/A16/A17
Note:
1. The value of this parameter depends on wait states. See Table 39 and Table 40.
Figure 13. External Bus Cycle: Data Write (Page Mode)
ALE
TLHLL(1)
TWLWH(1)
TWHLH
WR#
(1)
TLHAX
TQVWH
TWHQX
TAVLL(1)
TLLAX
P2
A15:8
D7:0
(1)
Data Out
TAVWL1
(1)
TAVWL2
TWHAX
P0/A16/A17
A7:0/A16/A17
Note:
1. The value of this parameter depends on wait states. See Table 39 and Table 40.
AC Characteristics - Real-Time Synchronous Wait State
Definition of Symbols
Table 41. Real-Time Synchronous Wait Timing Symbol Definitions
Signals
Conditions
C
R
W
Y
WCLK
L
V
X
Low
RD#/PSEN#
WR#
Valid
No Longer Valid
WAIT#
50
AT/TSC8x251G2D
4135D–8051–08/05
AT/TSC8x251G2D
Timings
Table 42. Real-Time Synchronous Wait AC Timings; VDD = 2.7 to 5.5 V, TA = -40 to
85°C
Symbol Parameter
Min
Max
Unit
ns
TCLYV
TCLYX
TRLYV
TRLYX
TWLYV
TWLYX
Wait Clock Low to Wait Set-up
0
TOSC - 20
Wait Hold after Wait Clock Low
PSEN#/RD# Low to Wait Set-up
Wait Hold after PSEN#/RD# Low
WR# Low to Wait Set-up
2W·TOSC + 5
(1+2W)·TOSC - 20
TOSC - 20
ns
0
ns
2W·TOSC + 5
0
(1+2W)·TOSC - 20
TOSC - 20
ns
ns
Wait Hold after WR# Low
2W·TOSC + 5
(1+2W)·TOSC - 20
ns
Waveforms
Figure 14. Real-time Synchronous Wait State: Code Fetch/Data Read
State 1
State 2
State 3
State 1 (next cycle)
WCLK
ALE
TCLYXmin
TCLYXmax
TCLYV
RD#/PSEN# stretched
RD#/PSEN#
TRLYXmax
TRLYXmin
TRLYV
WAIT#
P0
A7:0
D7:0
stretched
stretched
A7:0
P2
A15:8
A15:8
Figure 15. Real-time Synchronous Wait State: Data Write
State 1
State 2
State 3
State 1 (next cycle)
WCLK
ALE
TCLYXmin
TCLYXmax
TCLYV
RD#/PSEN#
WR# stretched
TWLYXmax
TWLYXmin
TWLYV
WAIT#
P0
A7:0
D7:0
stretched
stretched
P2
A15:8
51
4135D–8051–08/05
AC Characteristics - Real-Time Asynchronous Wait State
Definition of Symbols
Table 43. Real-Time Asynchronous Wait Timing Symbol Definitions
Signals
Conditions
Low
S
Y
PSEN#/RD#/WR#
AWAIT#
L
V
X
Valid
No Longer Valid
Timings
Table 44. Real-Time Asynchronous Wait AC Timings; VDD = 2.7 to 5.5 V, TA = -40 to
85°C
Symbol Parameter
TSLYV PSEN#/RD#/WR# Low to Wait Set-up
TSLYX Wait Hold after PSEN#/RD#/WR# Low
Min
Max
Unit
ns
TOSC - 10
(2N-1)·TOSC + 10
ns(1)
Note:
1. N is the number of wait states added (N≥ 1).
Waveforms
Figure 16. Real-time Asynchronous Wait State Timings
RD#/PSEN#/WR#
TSLYX
TSLYV
AWAIT#
AC Characteristics - Serial Port in Shift Register Mode
Definition of Symbols
Table 45. Serial Port Timing Symbol Definitions
Signals
Conditions
D
Q
X
Data In
Data Out
Clock
H
L
High
Low
V
X
Valid
No Longer Valid
52
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AT/TSC8x251G2D
Timings
Table 46. Serial Port AC Timing -Shift Register Mode; VDD = 2.7 to 5.5 V, TA = -40 to
85°C
12 MHz
16 MHz
24 MHz(1)
Symbol Parameter
Min
Max
Min
Max
Min Max
Unit
TXLXL
Serial Port Clock Cycle Time
998
833
749
625
500
417
ns
Output Data Setup to Clock Rising
Edge
TQVXH
ns
ns
ns
ns
Output Data hold after Clock Rising
Edge
TXHQX
TXHDX
TXHDV
165
0
124
0
82
0
Input Data Hold after Clock Rising
Edge
Clock Rising Edge to Input Data
Valid
974
732
482
Note:
1. For high speed versions only.
Waveforms
Figure 17. Serial Port Waveforms - Shift Register Mode
TXLXL
TXD
TQVXH
TXHQX
Set TI(1)
RXD (Out)
RXD (In)
0
1
2
3
4
5
6
7
Set RI(1)
TXHDX
TXHDV
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Note:
1. TI and RI are set during S1P1 of the peripheral cycle following the shift of the eight bit.
53
4135D–8051–08/05
AC Characteristics - SSLC: TWI Interface
Timings
Table 47. TWI Interface AC Timing; VDD = 2.7 to 5.5 V, TA = -40 to 85°C
INPUT
OUTPUT
Symbol
THD; STA
TLOW
Parameter
Min
Max
Min
Max
(4)
(4)
(4)
Start condition hold time
SCL low time
14·TCLCL
16·TCLCL
14·TCLCL
1 μs
4.0 μs(1)
4.7 μs(1)
4.0 μs(1)
THIGH
TRC
SCL high time
SCL rise time
SCL fall time
(2)
-
TFC
0.3 μs
0.3 μs(3)
TSU; DAT1 Data set-up time
250 ns
20·TCLCL(4)- TRD
SDA set-up time (before repeated START
condition)
TSU; DAT2
250 ns
1 μs(1)
(4)
TSU; DAT3 SDA set-up time (before STOP condition)
250 ns
0 ns
8·TCLCL
THD; DAT
TSU; STA
TSU; STO
TBUF
Data hold time
8·TCLCL(4) - TFC
4.7 μs(1)
(4)
(4)
(4)
Repeated START set-up time
STOP condition set-up time
Bus free time
14·TCLCL
14·TCLCL
14·TCLCL
1 μs
4.0 μs(1)
4.7 μs(1)
(2)
TRD
SDA rise time
-
TFD
SDA fall time
0.3 μs
0.3 μs(3)
Notes: 1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of
100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-up
resistor, this must be < 1 μs.
3. Spikes on the SDA and SCL lines with a duration of less than 3·TCLCL will be filtered
out. Maximum capacitance on bus-lines SDA and
SCL = 400 pF.
4. TCLCL = TOSC = one oscillator clock period.
Waveforms
Figure 18. TWI Waveforms
Repeated START condition
START or Repeated START condition
START condition
STOP condition
TSU;STA
TRD
0.7 VDD
0.3 VDD
SDA
(INPUT/OUTPUT)
TFD
TSU;STO
TBUF
TSU;DAT3
TRC
TFC
0.7 VDD
0.3 VDD
SCL
(INPUT/OUTPUT)
THD;STA
TLOW
THIGH
TSU;DAT1
THD;DAT
TSU;DAT2
54
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AT/TSC8x251G2D
AC Characteristics - SSLC: SPI Interface
Definition of Symbols
Table 48. SPI Interface Timing Symbol Definitions
Signals
Conditions
C
I
Clock
Data In
Data Out
SS#
H
L
High
Low
O
S
V
X
Z
Valid
No Longer Valid
Floating
55
4135D–8051–08/05
Timings
Table 49. SPI Interface AC Timing; VDD = 2.7 to 5.5 V, TA = -40 to 85°C
Symbol
Parameter
Min
Max
Unit
Slave Mode(1)
TCHCH
Clock Period
8
TOSC
TOSC
TOSC
ns
TCHCX
Clock High Time
3.2
3.2
200
100
100
TCLCX
Clock Low Time
TSLCH, TSLCL
SS# Low to Clock edge
Input Data Valid to Clock Edge
T
T
T
T
T
T
T
IVCL, TIVCH
CLIX, TCHIX
CLOV, TCHOV
ns
Input Data Hold after Clock Edge
Output Data Valid after Clock Edge
ns
100
ns
CLOX, TCHOX Output Data Hold Time after Clock Edge
CLSH, TCHSH SS# High after Clock Edge
0
ns
0
ns
IVCL, TIVCH
CLIX, TCHIX
Input Data Valid to Clock Edge
Input Data Hold after Clock Edge
SS# Low to Output Data Valid
Output Data Hold after SS# High
SS# High to SS# Low
Input Rise Time
100
100
ns
ns
TSLOV
TSHOX
TSHSL
TILIH
130
130
ns
ns
(2)
2
μs
μs
ns
ns
TIHIL
Input Fall Time
2
TOLOH
TOHOL
Output Rise time
100
100
Output Fall Time
Master Mode(3)
TCHCH
Clock Period
4
TOSC
TOSC
TOSC
ns
TCHCX
Clock High Time
1.6
1.6
50
50
TCLCX
Clock Low Time
TIVCL, TIVCH
Input Data Valid to Clock Edge
Input Data Hold after Clock Edge
Output Data Valid after Clock Edge
TCLIX, TCHIX
ns
TCLOV, TCHOV
65
ns
TCLOX, TCHOX Output Data Hold Time after Clock Edge
0
ns
TILIH
Input Data Rise Time
Input Data Fall Time
Output Data Rise time
Output Data Fall Time
2
2
μs
TIHIL
μs
TOLOH
TOHOL
50
50
ns
ns
Notes: 1. Capacitive load on all pins = 200 pF in slave mode.
2. The value of this parameter depends on software.
3. Capacitive load on all pins = 100 pF in master mode.
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AT/TSC8x251G2D
Waveforms
Figure 19. SPI Master Waveforms (SSCPHA = 0)
SS#(1)
(output)
TCHCH
TCLCH
SCK
(SSCPOL = 0)
(output)
TCHCX
TCLCX
TCHCL
SCK
(SSCPOL = 1)
(output)
TIVCH TCHIX
TIVCL TCLIX
MISO
(input)
MSB IN
BIT 6
LSB IN
TCLOV
TCHOV
TCLOX
TCHOX
MOSI
(output)
Port Data
MSB OUT
BIT 6
LSB OUT
Port Data
Note:
1. SS# handled by software.
Figure 20. SPI Master Waveforms (SSCPHA = 1)
SS#(1)
(output)
TCHCH
TCLCH
SCK
(SSCPOL = 0)
(output)
TCHCX
TCLCX
TCHCL
SCK
(SSCPOL = 1)
(output)
TIVCH TCHIX
TIVCL TCLIX
MISO
(input)
MSB IN
BIT 6
LSB IN
TCLOV
TCHOV
TCLOX
TCHOX
MOSI
(output)
Port Data
MSB OUT
BIT 6
LSB OUT
Port Data
Note:
1. Not Defined but normally MSB of character just received.
57
4135D–8051–08/05
Figure 21. SPI Slave Waveforms (SSCPHA = 0)
SS#
(input)
TSLCH
TSLCL
TCLSH
TCHSH
TCHCH
TSHSL
TCLCH
SCK
(SSCPOL = 0)
(input)
TCHCX
TCLCX
TCHCL
SCK
(SSCPOL = 1)
(input)
TCLOV
TCHOV
TCLOX
TCHOX
TSLOV
TSHOX
MISO
(output)
SLAVE MSB OUT
BIT 6
SLAVE LSB OUT
(1)
TIVCH TCHIX
TIVCL TCLIX
MOSI
(input)
MSB IN
BIT 6
LSB IN
Note:
1. Not Defined but generally the LSB of the character which has just been received.
Figure 22. SPI Slave Waveforms (SSCPHA = 1)
SS#
(input)
TSLCH
TSLCL
TCLSH
TCHSH
TCHCH
TSHSL
TCLCH
SCK
(SSCPOL = 0)
(input)
TCHCX
TCLCX
TCHCL
SCK
(SSCPOL = 1)
(input)
TCHOV
TCLOV
TCHOX
TCLOX
TSLOV
TSHOX
MISO
(output)
SLAVE MSB OUT
BIT 6
SLAVE LSB OUT
(1)
TIVCH TCHIX
TIVCL TCLIX
MOSI
(input)
MSB IN
BIT 6
LSB IN
AC Characteristics - EPROM Programming and Verifying
Definition of Symbols
Table 50. EPROM Programming and Verifying Timing Symbol Definitions
Signals
Conditions
A
E
G
Q
S
Address
H
L
High
Low
Enable: mode set on Port 0
Program
V
X
Z
Valid
Data Out
No Longer Valid
Floating
Supply (VPP
)
58
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AT/TSC8x251G2D
Timings
Table 51. EPROM Programming AC timings; VDD = 4.5 to 5.5 V, TA = 0 to 40°C
Symbol
TOSC
Parameter
XTAL1 Period
Min
83.5
48
48
48
48
48
10
10
0
Max
Unit
ns
250
TAVGL
TGHAX
TDVGL
TGHDX
TELSH
TSHGL
TGHSL
TSLEH
TGLGH
Address Setup to PROG# low
Address Hold after PROG# low
Data Setup to PROG# low
Data Hold after PROG#
ENABLE High to VPP
TOSC
TOSC
TOSC
TOSC
TOSC
μs
VPP Setup to PROG# low
VPP Hold after PROG#
ENABLE Hold after VPP
PROG# Width
μs
ns
90
110
μs
Table 52. EPROM Verifying AC timings; VDD = 4.5 to 5.5 V, VDD = 2.7 to 5.5 V, TA = 0 to
40°C
Symbol
TOSC
Parameter
Min
Max
250
48
Unit
ns
XTAL1 Period
83.5
TAVQV
TAXQX
TELQV
TEHQZ
Address to Data Valid
Address to Data Invalid
ENABLE low to Data Valid
Data Float after ENABLE
TOSC
ns
0
0
0
48
48
TOSC
TOSC
Waveforms
Figure 23. EPROM Programming Waveforms
P1 = A15:8
P3 = A7:0
Address
Data
TAVGL
TGHAX
P2 = D7:0
TDVGL
TGHDX
VPP
VDD
TSHGL
TGLGH
TGHSL
EA#/VPP
VSS
ALE/PROG#
TELSH
TSLEH
P0
Mode = 68h, 69h, 6Bh or 6Ch
59
4135D–8051–08/05
Figure 24. EPROM Verifying Waveforms
P1 = A15:8
P3 = A7:0
Address
TAVQV
TAXQX
P2 = D7:0
Data
TELQV
Mode = 28h, 29h or 2Bh
TEHQZ
P0
AC Characteristics - External Clock Drive and Logic Level References
Definition of Symbols
Table 53. External Clock Timing Symbol Definitions
Signals
Conditions
C
Clock
H
L
High
Low
X
No Longer Valid
Timings
Table 54. External Clock AC Timings; VDD = 4.5 to 5.5 V, TA = -40 to +85°C
Symbol
FOSC
Parameter
Oscillator Frequency
Min
Max
Unit
MHz
ns
24
TCHCX
TCLCX
TCLCH
TCHCL
High Time
Low Time
Rise Time
Fall Time
10
10
3
ns
ns
3
ns
Waveforms
Figure 25. External Clock Waveform
TCLCH
TCLCX
TCHCX
VDD - 0.5
VIH1
VIL
0.45 V
TCHCL
TCLCL
Notes: 1. During AC testing, all inputs are driven at VDD -0.5 V for a logic 1 and 0.45 V for a
logic 0.
2. Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for
a logic 0.
60
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AT/TSC8x251G2D
Figure 26. AC Testing Input/Output Waveforms
INPUTS
OUTPUTS
VDD - 0.5
0.2 VDD + 0.9
VIH min
0.2 VDD - 0.1
0.45 V
VIL max
Note:
For timing purposes, a port pin is no longer floating when a 100 mV change from load
voltage occurs and begins to float when a 100 mV change from the loading VOH/VOL level
occurs with IOL/IOH = ±20 mA.
Figure 27. Float Waveforms
V
LOAD + 0.1 V
VOH - 0.1 V
VOL + 0.1 V
VLOAD
Timing Reference Points
VLOAD - 0.1 V
61
4135D–8051–08/05
Absolute Maximum Rating and Operating Conditions
Absolute Maximum Ratings
*NOTICE:
Stressing the device beyond the “Absolute Maxi-
Storage Temperature......................................... -65 to +150°C
Voltage on any other Pin to VSS ........................ -0.5 to +6.5 V
IOL per I/O Pin ................................................................ 15 mA
Power Dissipation........................................................... 1.5 W
mum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond
the “operating conditions” is not recommended
and extended exposure beyond the “Operating
Conditions” may affect device reliability.
Ambient Temperature Under Bias
Commercial..............................................................0 to +70°C
Industrial.............................................................. -40 to +85°C
VDD
High Speed versions.............................................. 4.5 to 5.5 V
Low Voltage versions............................................. 2.7 to 5.5 V
62
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AT/TSC8x251G2D
DC Characteristics
High Speed Versions - Commercial & Industrial
Table 55. DC Characteristics; VDD = 4.5 to 5.5 V, TA = -40 to +85°C
Symbol Parameter
Min
Typical(4)
Max
Units Test Conditions
Input Low Voltage
(except EA#, SCL, SDA)
VIL
-0.5
0.2·VDD - 0.1
0.3·VDD
V
Input Low Voltage
(SCL, SDA)
(5)
VIL1
-0.5
0
V
V
V
V
Input Low Voltage
(EA#)
VIL2
0.2·VDD - 0.3
VDD + 0.5
VDD + 0.5
Input high Voltage
(except XTAL1, RST, SCL, SDA)
VIH
0.2·VDD + 0.9
0.7·VDD
Input high Voltage
(XTAL1, RST, SCL, SDA)
(5)
VIH1
0.3
0.45
1.0
I
OL = 100 μA(1)(2)
Output Low Voltage
(Ports 1, 2, 3)
VOL
V
V
V
V
IOL = 1.6 mA(1)(2)
IOL = 3.5 mA(1)(2)
Output Low Voltage
(Ports 0, ALE, PSEN#, Port 2 in Page Mode during
External Address)
0.3
0.45
1.0
I
OL = 200 μA(1)(2)
VOL1
IOL = 3.2 mA(1)(2)
IOL = 7.0 mA(1)(2)
V
V
V
DD - 0.3
DD - 0.7
DD - 1.5
IOH = -10 μA(3)
IOH = -30 μA(3)
IOH = -60 μA(3)
Output high Voltage
(Ports 1, 2, 3, ALE, PSEN#)
VOH
V
V
V
DD - 0.3
DD - 0.7
DD - 1.5
IOH = -200 μA
Output high Voltage
(Port 0, Port 2 in Page Mode during External Address)
VOH1
I
OH = -3.2 mA
I
OH = -7.0 mA
VRET
IIL0
VDD data retention limit
1.8
V
Logical 0 Input Current
(Ports 1, 2, 3)
- 50
μA
VIN = 0.45 V
VIN = VDD
Logical 1 Input Current
(NMI)
+ 50
IIL1
μA
μA
μA
Input Leakage Current
(Port 0)
ILI
± 10
0.45 V < VIN < VDD
Logical 1-to-0 Transition Current
(Ports 1, 2, 3 - AWAIT#)
ITL
- 650
225
VIN = 2.0 V
RRST
CIO
RST Pull-Down Resistor
Pin Capacitance
40
110
10
kΩ
pF
TA = 25°C
20
25
35
25
30
40
F
F
F
OSC = 12 MHz
OSC = 16 MHz
OSC = 24 MHz
IDD
Operating Current
Idle Mode Current
mA
mA
5
6.5
9.5
6
8
12
F
F
F
OSC = 12 MHz
OSC = 16 MHz
OSC = 24 MHz
IDL
IPD
VPP
IPP
Power-Down Current
2
20
13
75
μA
V
VRET < VDD < 5.5 V
TA = 0 to +40°C
TA = 0 to +40°C
Programming supply voltage
Programming supply current
12.5
mA
63
4135D–8051–08/05
Notes: 1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:Port 0 26 mA
Ports 1-3 15 mA
Maximum Total IOL for all: Output Pins 71 mA
If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test
conditions.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and Ports
1, 2, and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change
from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed
0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger or CMOS-level input logic.
3. Capacitive loading on Ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specification when the address
lines are stabilizing.
4. Typical values are obtained using VDD = 5 V and TA = 25°C. They are not tested and there is not guarantee on these values.
5. The input threshold voltage of SCL and SDA meets the TWI specification, so an input voltage below 0.3·VDD will be recog-
nized as a logic 0 while an input voltage above 0.7·VDD will be recognized as a logic 1.
Figure 28. IDD/IDL Versus Frequency; VDD = 4.5 to 5.5 V
40
30
20
10
0
2
4
6
8
10
12
14
16
18
20
22
24
max Active mode (mA)
typ Active mode (mA)
max Idle mode (mA)
typ Idle mode (mA)
Frequency at XTAL(1) (MHz)
Note:
1. The clock prescaler is not used: FOSC = FXTAL.
64
AT/TSC8x251G2D
4135D–8051–08/05
AT/TSC8x251G2D
Low Voltage Versions - Commercial & Industrial
Table 56. DC Characteristics; VDD = 2.7 to 5.5 V, TA = -40 to +85°C
Symbol Parameter
Min
Typical(4)
Max
Units
Test Conditions
Input Low Voltage
(except EA#, SCL, SDA)
VIL
-0.5
0.2·VDD - 0.1
V
Input Low Voltage
(SCL, SDA)
(5)
VIL1
-0.5
0
0.3·VDD
0.2·VDD - 0.3
VDD + 0.5
VDD + 0.5
0.45
V
V
V
V
V
Input Low Voltage
(EA#)
VIL2
Input high Voltage
(except XTAL1, RST, SCL, SDA)
VIH
0.2·VDD + 0.9
0.7·VDD
Input high Voltage
(XTAL1, RST, SCL, SDA)
(5)
VIH1
Output Low Voltage
(Ports 1, 2, 3)
VOL
I
I
OL = 0.8 mA(1)(2)
OL = 1.6 mA(1)(2)
Output Low Voltage
(Ports 0, ALE, PSEN#, Port 2 in Page
Mode during External Address)
VOL1
0.45
V
V
V
Output high Voltage
(Ports 1, 2, 3, ALE, PSEN#)
VOH
0.9·VDD
0.9·VDD
IOH = -10 μA(3)
IOH = -40 μA
Output high Voltage
(Port 0, Port 2 in Page Mode during
External Address)
VOH1
VRET
IIL0
VDD data retention limit
1.8
V
Logical 0 Input Current
(Ports 1, 2, 3 - AWAIT#)
- 50
μA
VIN = 0.45 V
VIN = VDD
Logical 1 Input Current
(NMI)
+ 50
IIL1
μA
μA
μA
Input Leakage Current
(Port 0)
ILI
± 10
0.45 V < VIN < VDD
Logical 1-to-0 Transition Current
(Ports 1, 2, 3)
ITL
- 650
225
VIN = 2.0 V
RRST
CIO
RST Pull-Down Resistor
Pin Capacitance
40
110
10
kΩ
pF
TA = 25°C
4
8
9
8
5 MHz, VDD < 3.6 V
10 MHz, VDD < 3.6 V
12 MHz, VDD < 3.6 V
16 MHz, VDD < 3.6 V
11
12
14
IDD
Operating Current
mA
11
0.5
1.5
2
1
4
5
7
5 MHz, VDD < 3.6 V
10 MHz, VDD < 3.6 V
12 MHz, VDD < 3.6 V
16 MHz, VDD < 3.6 V
IDL
Idle Mode Current
mA
3
IPD
Power-Down Current
1
10
μA
VRET < VDD < 3.6 V
Notes: 1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port: Port 0 26 mA
Ports 1-315 mA
65
4135D–8051–08/05
Maximum Total IOL for all:Output Pins71 mA
If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test
conditions.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and Ports
1, 2, and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change
from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed
0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger or CMOS-level input logic.
3. Capacitive loading on Ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specification when the address
lines are stabilizing.
4. Typical values are obtained using VDD = 3 V and TA = 25°C. They are not tested and there is not guarantee on these values.
5. The input threshold voltage of SCL and SDA meets the TWI specification, so an input voltage below 0.3·VDD will be recog-
nized as a logic 0 while an input voltage above 0.7·VDD will be recognized as a logic 1.
Figure 29. IDD/IDL Versus XTAL Frequency; VDD = 2.7 to 3.6 V
15
10
5
0
2
4
6
8
10
12
14
16
max Active mode (mA)
typ Active mode (mA)
max Idle mode (mA)
typ Idle mode (mA)
Frequency at XTAL(1) (MHz)
Note: 1.The clock prescaler is not used: FOSC = FXTAL
.
IDD, DL and IPD Test Conditions
I
Figure 30. IDD Test Condition, Active Mode
VDD
VDD
IDD
RST
VDD
VDD
TSC80251G2D
P0
(NC)
Clock Signal
XTAL2
EA#
XTAL1
VSS
All other pins are unconnected
66
AT/TSC8x251G2D
4135D–8051–08/05
AT/TSC8x251G2D
Figure 31. IDL Test Condition, Idle Mode
VDD
IDL
RST
VDD
VDD
TSC80251G2D
P0
(NC)
Clock Signal
XTAL2
EA#
XTAL1
VSS
All other pins are unconnected
Figure 32. IPD Test Condition, Power-Down Mode
VDD
IPD
RST
VDD
VDD
TSC80251G2D
P0
(NC)
XTAL2
XTAL1
EA#
VSS
All other pins are unconnected
67
4135D–8051–08/05
Packages
List of Packages
•
•
•
•
•
PDIL 40
CDIL 40 with window
PLCC 44
CQPJ 44 with window
VQFP 44 (10x10)
PDIL 40 - Mechanical
Outline
Figure 33. Plastic Dual In Line
Table 57. PDIL Package Size
MM
Inch
Min
Max
5.08
-
Min
-
Max
.200
-
A
A1
A2
B
-
0.38
3.18
0.36
0.76
0.20
50.29
15.24
12.32
.015
.125
.014
.030
.008
1.980
.600
.485
4.95
0.56
1.78
0.38
53.21
15.87
14.73
.195
.022
.070
.015
2.095
.625
.580
B1
C
D
E
E1
e
2.54 B.S.C.
.100 B.S.C.
.600 B.S.C.
eA
eB
L
15.24 B.S.C.
-
17.78
3.81
-
-
.700
.150
-
2.93
0.13
.115
.005
D1
68
AT/TSC8x251G2D
4135D–8051–08/05
AT/TSC8x251G2D
CDIL 40 with Window -
Mechanical Outline
Figure 34. Ceramic Dual In Line
Table 58. CDIL Package Size
MM
Inch
Min
Max
5.71
0.58
1.65
0.38
53.47
15.37
Min
-
Max
.225
.023
.065
.015
2.105
.605
A
b
-
0.36
1.14
0.20
-
.014
.045
.008
-
b2
c
D
E
13.06
.514
e
2.54 B.S.C.
.100 B.S.C.
.600 B.S.C.
eA
L
15.24 B.S.C.
3.18
0.38
0.13
5.08
1.40
-
.125
.015
.005
.200
.055
-
Q
S1
a
0 - 15
0 - 15
N
40
69
4135D–8051–08/05
PLCC 44 - Mechanical
Outline
Figure 35. Plastic Lead Chip Carrier
Table 59. PLCC Package Size
MM
Inch
Min
Max
Min
Max
.180
.120
.695
.656
.630
.695
.656
.630
A
A1
D
4.20
2.29
4.57
.165
.090
.685
.647
.590
.685
.647
.590
3.04
17.40
16.44
14.99
17.40
16.44
14.99
17.65
16.66
16.00
17.65
16.66
16.00
D1
D2
E
E1
E2
e
1.27 BSC
.050 BSC
G
1.07
1.07
0.51
0.33
1.22
1.42
-
.042
.042
.020
.013
.048
.056
-
H
J
K
0.53
.021
Nd
Ne
11
11
11
11
70
AT/TSC8x251G2D
4135D–8051–08/05
AT/TSC8x251G2D
CQPJ 44 with Window -
Mechanical Outline
Figure 36. Ceramic Quad Pack J
Table 60. CQPJ Package Size
MM
Inch
Min
-
Max
4.90
Min
-
Max
.193
.010
.691
.656
A
C
0.15
17.40
16.36
0.25
.006
.685
.644
D - E
17.55
16.66
D1 - E1
e
f
1.27 TYP
.050 TYP
0.43
0.86
0.53
1.12
.017
.034
.610
.021
.044
.630
J
Q
R
15.49
16.00
0.86 TYP
.034 TYP
N1
N2
11
11
11
11
71
4135D–8051–08/05
VQFP 44 (10x10) -
Mechanical Outline
Figure 37. Shrink Quad Flat Pack (Plastic)
Table 61. VQFP Package Size
MM
Inch
Min
Max
Min
Max
A
A1
A2
A3
D
-
1.60
-
.063
0.64 REF
0.64 REF
.025 REF
.025REF
1.35
11.90
9.90
11.90
9.90
0.05
0.45
1.45
12.10
10.10
12.10
10.10
-
.053
.468
.390
.468
.390
.002
.018
.057
.476
.398
.476
.398
6
D1
E
E1
J
L
0.75
.030
e
0.80 BSC
0.35 BSC
.0315 BSC
.014 BSC
f
72
AT/TSC8x251G2D
4135D–8051–08/05
AT/TSC8x251G2D
Ordering Information
AT/TSC80251G2D
ROMless
Part Number
ROM
Description
High Speed Versions 4.5 to 5.5 V, Commercial and Industrial
TSC80251G2D-16CB
TSC80251G2D-24CB
TSC80251G2D-24CE
TSC80251G2D-24IA
TSC80251G2D-24IB
AT80251G2D-SLSUM
AT80251G2D-3CSUM
AT80251G2D-RLTUM
ROMless
ROMless
ROMless
ROMless
ROMless
ROMless
ROMless
ROMless
16 MHz, Commercial 0° to 70°C, PLCC 44
24 MHz, Commercial 0° to 70°C, PLCC 44
24 MHz, Commercial 0° to 70°C, VQFP 44
24 MHz, Industrial -40° to 85°C, PDIL 40
24 MHz, Industrial -40° to 85°C, PLCC 44
24 MHz, Industrial & Green -40° to 85°C, PLCC 44
24 MHz, Industrial & Green -40° to 85°C, PDIL 40
24 MHz, Industrial & Green -40° to 85°C, VQFP 44
Low Voltage Versions 2.7 to 5.5 V
TSC80251G2D-L16CB
TSC80251G2D-L16CE
AT80251G2D-SLSUL
AT80251G2D-RLTUL
ROMless
ROMless
ROMless
ROMless
16 MHz, Commercial, PLCC 44
16 MHz, Commercial, VQFP 44
16 MHz, Industrial & Green, PLCC 44
16 MHz, Industrial & Green, VQFP 44
AT/TSC83251G2D
32 kilobytes
MaskROM
Part Number(1)
ROM
Description
High Speed Versions 4.5 to 5.5 V, Commercial and Industrial
32K MaskROM 16 MHz, Commercial 0° to 70°C, PLCC 44
32K MaskROM 24 MHz, Commercial 0° to 70°C, PLCC 44
32K MaskROM 24 MHz, Commercial 0° to 70°C, VQFP 44
32K MaskROM 24 MHz, Industrial -40° to 85°C, PDIL 40
32K MaskROM 24 MHz, Industrial -40° to 85°C, PLCC 44
TSC251G2Dxxx-16CB
TSC251G2Dxxx-24CB
TSC251G2Dxxx-24CE
TSC251G2Dxxx-24IA
TSC251G2Dxxx-24IB
AT251G2Dxxx-SLSUM
AT251G2Dxxx-3CSUM
AT251G2Dxxx-RLTUM
32K MaskROM 24 MHz, Industrial & Green -40° to 85°C, PLCC 44
32K MaskROM 24 MHz, Industrial & Green -40° to 85°C, PDIL 40
32K MaskROM 24 MHz, Industrial & Green -40° to 85°C, VQFP 44
Low Voltage Versions 2.7 to 5.5 V
TSC251G2Dxxx-L16CB
TSC251G2Dxxx-L16CE
AT251G2Dxxx-SLSUL
AT251G2Dxxx-RLTUL
32K MaskROM 16 MHz, Commercial 0° to 70°C, PLCC 44
32K MaskROM 16 MHz, Commercial 0° to 70°C, VQFP 44
32K MaskROM 16 MHz, Industrial & Green, PLCC 44
32K MaskROM 16 MHz, Industrial & Green, VQFP 44
Note:
1. xxx: means ROM code, is Cxxx in case of encrypted code.
73
4135D–8051–08/05
AT/TSC87251G2D
OTPROM
Part Number
ROM
Description
High Speed Versions 4.5 to 5.5 V, Commercial and Industrial
32K OTPROM 16 MHz, Commercial 0° to 70°C, PLCC 44
32K OTPROM 24 MHz, Commercial 0° to 70°C, PLCC 44
TSC87251G2D-16CB
TSC87251G2D-24CB
TSC87251G2D-24CED
TSC87251G2D-24IA
TSC87251G2D-24IB
AT87251G2D-SLSUM
AT87251G2D-3CSUM
AT87251G2D-RLTUM
32K OTPROM 24 MHz, Commercial 0° to 70°C, VQFP 44
32K OTPROM 24 MHz, Industrial -40° to 85°C, PDIL 40
32K OTPROM 24 MHz, Industrial -40° to 85°C, PLCC 44
32K OTPROM 24 MHz, Industrial & Green -40° to 85°C, PLCC 44
32K OTPROM 24 MHz, Industrial & Green -40° to 85°C, PDIL 40
32K OTPROM 24 MHz, Industrial & Green -40° to 85°C, VQFP 44
Low Voltage Versions 2.7 to 5.5 V
TSC87251G2D-L16CB
TSC87251G2D-L16CED
AT87251G2D-SLSUL
AT87251G2D-RLTUL
32K OTPROM 16 MHz, Commercial 0° to 70°C, PLCC 44
32K OTPROM 16 MHz, Commercial 0° to 70°C, VQFP 44
32K OTPROM 16 MHz, Industrial & Green, 0° to 70°C, PLCC 44
32K OTPROM 16 MHz, Industrial & Green, 0° to 70°C, VQFP 44
74
AT/TSC8x251G2D
4135D–8051–08/05
AT/TSC8x251G2D
Options (Please
consult Atmel sales)
•
•
•
•
ROM code encryption
Tape & Reel or Dry Pack
Known good dice
Extended temperature range: -55°C to +125°C
Product Markings
ROMless versions
Mask ROM versions
OTP versions
ATMEL
ATMEL
ATMEL
Part number
Customer Part number
Part number
Part Number
YYWW . Lot Number
YYWW . Lot Number
YYWW . Lot Number
75
4135D–8051–08/05
Atmel Corporation
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