TSX83102G0BGS [ATMEL]

ADC, Proprietary Method, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, CBGA152, HERMATIC, CI-CGA-152;


型号：	TSX83102G0BGS
厂家：	ATMEL
描述：	ADC, Proprietary Method, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, CBGA152, HERMATIC, CI-CGA-152 转换器
文件：	总13页 (文件大小：403K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Features

•

Up to 2 Gsps Sampling Rate

Power Consumption: 4.6W

500 mVpp Differential 100Ω or Single-ended 50Ω (±2 %) Analog Inputs

Differential 100Ω or Single-ended 50Ω Clock Inputs

ECL or LVDS Output Compatibility

50Ω Differential Outputs with Common Mode not Dependent on Temperature

ADC Gain Adjust

Sampling Delay Adjust

Offset Control Capability

Data Ready Output with Asynchronous Reset

Out-of-range Output Bit

Selectable Decimation by 32-function

Gray or Binary Selectable Output Data; NRZ Output Mode

Pattern Generator Output (for Acquisition System Monitoring)

Radiation Tolerance Oriented Design (More Than 100 Krad (Si) Expected)

CI-CGA152 Cavity Down Hermetic Package

CBGA 152 Package Evaluation Board TSEV83102G0BGL

Companion Device: DMUX 8-/10-bit 1:4/1:8 2 Gsps TS81102G0

10-bit 2 Gsps

ADC MIL

TS83102G0BMGS

Summary

Performance

•

3.3 GHz Full Power Input Bandwidth (-3 dB)

Gain Flatness: ± 0.2 dB (from DC up to 1.5 GHz)

For more information, please

contact

hotline-bdc@gfo.atmel.com

Low Input VSWR: 1.2 Max from DC to 2.5 GHz

SFDR = -59 dBc; 7.6 Effective Bits at F_S= 1.4 Gsps, F_IN= 700 MHz [-1 dBFS]

SFDR = -53 dBc; 7.1 Effective Bits at Fs = 1.4 Gsps, F_IN= 1950 MHz [-1 dBFS]

SFDR = -54 dBc; 6.5 Effective Bits at F_S= 2 Gsps, F_IN= 2 GHz [-1 dBFS]

Low Bit Error Rate (10^-12) at 2 Gsps

Application

•

Direct RF Down Conversion

Wide Band Satellite Receiver

High-speed Instrumentation

High-speed Acquisition Systems

High-energy Physics

Automatic Test Equipment

Radar

Screening

•

Temperature Range for Packaged Device:

“M” Grade: -40°C < T_C; T_J< 125° C

Standard Die Flow (upon Request)

–

•

Description

The TS83102G0BMGS is a monolithic 10-bit analog-to-digital converter, designed for

digitizing wide bandwidth analog signals at very high sampling rates of up to 2 Gsps. It

uses an innovative architecture, including an on-chip Sample and Hold (S/H). The

3.3 GHz full power input bandwidth and band flatness performances enable the digitiz-

ing of high IF and large bandwidth signals.

5360AS–BDC–08/04

This is a summary document only. A complete document is not avail-

able at this time. For more information, please contact your local

Atmel sales office.

Figure 1. Simplified Block Diagram

PGEB B/GB

Sample &Hold

ORB

VIN

D9B

VINB

Logic block

D0B

DRB

CLK

Clock generation

SDA

CLKB

DECB/

DIODE

DRRB

Functional Description

The TS83102G0BMGS is a 10-bit 2 Gsps ADC. The device includes a front-end master/slave

Track and Hold stage (Sample and Hold), followed by an analog encoding stage (Analog

Quantizer), which outputs analog residues resulting from analog quantization. Successive

banks of latches regenerate the analog residues into logical levels before entering an error

correction circuit and resynchronization stage, followed by 50Ω differential output buffers.

The TS83102G0BMGS works in a fully differential mode from analog inputs to digital outputs.

A differential Data Ready output (DR/DRB) is available to indicate when the outputs are valid

and an Asynchronous Data Ready Reset ensures that the first digitized data corresponds to

the first acquisition.

The control pin B/GB (A11 of the CI-CGA package) is provided to select either a binary or gray

data output format. The gain control pin GA (R9 of the CI-CGA package) is provided to adjust

the ADC gain transfer function.

A Sampling Delay Adjust function (SDA) may be used to ease the interleaving of ADCs.

A pattern generator is integrated on the chip for debug or acquisition setup. This function is

activated through the PGEB pin (A9 of the CI-CGA package).

An Out-of-range bit (OR/ORB) indicates when the input overrides 0.5 Vpp.

A selectable decimation by 32 functions is also available for enhanced testability coverage

(A10 of the CI-CGA package), along with the die junction temperature monitoring function.

The TS83102G0BMGS uses only vertical isolated NPN transistors together with oxide isolated

polysilicon resistors, which provides enhanced radiation tolerance (over 100 kRad (Si) total

dose expected tolerance).

TS83102G0BMGS

5360AS–BDC–08/04

TS83102G0BMGS

TS83102G0BMGS Package Description

Table 1. Pin Description (CI-CGA 152)

Symbol

Pin Number

Function

Power Supplies

5V analog supply (connected to same power supply

plane)

V_CC, V_CCTH

K1, K2, J3, K3, B6, C6, A7, B7, C7, P8, Q8, R8

B1, C1, D1, G1, M1, Q1, B2, C2, D2, E2, F2,

G2, N2, P2, Q2, A3, B3, D3, E3, F3, G3, N3, P4,

Q4, R4, A5, P5, Q5, P6, Q6, P7, Q7, R7, B9,

B10, B11, R11, P12, A14, B14, C14, G14, K14,

P14, Q14, R14, B15, Q15, B16, Q16

GND

Analog ground

H1, J1, L1, H2, J2, L2, M2, C3, H3, L3, M3, P3,

Q3, R3, A4, B4, C4, B5, C5, A8, B8, C8, C9, P9,

Q9, C10, Q10, R10

-5V analog supply (connected to same power supply

plane)

V_EE, V_EETH

P10, C11, P11, Q11, A12, B12, C12, Q12, R12,

D14, E14, F14, L14, M14, N14

V_PLUSD

Digital positive supply

-5V digital supply

DV_EE

A13, B13, C13, P13, Q13, R13, H14, J14

Analog Inputs

In-phase (+) analog input signal of the differential

Sample & Hold preamplifier

VIN

Inverted phase (-) analog input signal of the differential

Sample & Hold preamplifier

VINB

Clock Inputs

CLK

In-phase (+) clock input

CLKB

Inverted phase (-) clock input

Digital Outputs

D0, D1, D2, D3, D4,

D5, D6, D7, D8, D9

In-phase (+) digital outputs

D0 is the LSB, D7 is the MSB

D16, E16, F16, G16, J16, K16, L16, M16, N16,

P16

D0B, D1B, D2B, D3B,

D4B, D5B, D6B, D7B,

D8B, D9B

D15, E15, F15, G15, J15, K15, L15, M15, N15,

P15

Inverted phase (-) digital outputs

C16

C15

H16

H15

In-phase (+) out-of-range output

ORB

Inverted phase (-) out-of-range output

In-phase (+) data ready signal output

Inverted phase (-) data ready signal output

DRB

Additional Functions

Binary or gray select output format control

- Binary output format if B/GB is floating or

connected to GND

B/GB

A11

- Gray output format if B/GB is connected to V_EE

5360AS–BDC–08/04

Table 1. Pin Description (CI-CGA 152) (Continued)

Symbol

Pin Number

Function

Decimation function enable or die junction temperature

measurement:

- Decimation active when LOW (die junction

temperature monitoring is not possible)

DECB/DIODE

A10

- Normal mode when HIGH or left floating

- Die junction temperature monitoring when current

is applied

Active low pattern generator enable

- Digitized input delivered at outputs according to

B/GB if PGEB is floating or connected to GND

PGEB

DRRB

- Checker board pattern delivered at outputs if

PGEB is connected to V_EE

Asynchronous data ready reset function (active at ECL

low level)

Gain adjust

SDA

Sampling delay adjust

Sampling delay adjust enable

SDAEN

- Inactive if floating or connected to GND

- Active if connected to V_EE

TS83102G0BMGS

5360AS–BDC–08/04

TS83102G0BMGS

Figure 2. Pinout

ORB

DIODE

DECB/

TS83102G0BMGS

CI-CGA 152

PGEB

BOTTOM VIEW

Notes: 1. To simplify PCB routing, the 4 NC columns can be electrically connected to the GND

columns.

2. The pinout is shown from the bottom. The columns and rows are defined differently from the

JEDEC standard.

5360AS–BDC–08/04

Thermal and Moisture Characteristics

Dissipation by Conduction and Convection

The thermal resistance from junction to ambient RTH_JAis around 30° C/W. Therefore, to lower

RTH_JA, it is mandatory to use an external heat sink to improve dissipation by convection and

conduction. The heat sink should be fixed in contact with the top side of the package (AI203

electrical isolation over CuW heat spreader).

The heat sink does not need to be electrically isolated, because the top of the package is

already electrically isolated thanks to a 0.30 mm AI203 layer.

Example:

The thermal resistance from case to ambient RTH_CAis typically 4.0°C/W (0 m/s air flow or

still air) with the heat sink depicted in Figure 3 on page 7, of dimensions 50 mm x 50 mm x

28 mm (respectively L x l x H).

The global junction to ambient thermal resistance RTH_JAis:

4.8° C/W RTH_JC+ 2.0° C/W thermal grease resistance + 4.0° C/W RTH_CA(case to ambi-

ent) = 10.8° C/W total (RTH_JA).

Assuming:

A typical thermal resistance from the junction to the top of the case RTH_JCof 4.8° C/W

(finite element method thermal simulation results): this value does not include the thermal

contact resistance between the package and the external heat sink (glue, paste, or ther-

mal foil interface, for example). As an example, use a 2.0° C/W value for a

50 µm thickness of thermal grease.

Note:

Example of the calculation of the ambient temperature T_Amax to ensure T_Jmax = 110°C:

assuming RTH_JA= 10.8° C/W and power dissipation = 4.6 W, T_Amax = T_J- (RTH_JAx 4.6 W) =

110 - (10.8 x 4.6) = 60.32°C. T_Amax can be increased by lowering RTH_JAwith an adequate air

flow ( 2 m/s, for example).

TS83102G0BMGS

5360AS–BDC–08/04

TS83102G0BMGS

Figure 3. Black Anodized Aluminium Heat Sink Glued on a Copper Base Screwed on Board (all dimensions in mm)

50 x 52

50 x 50

16 x 50

0.3

11.5 x 52

6.5

Board

Ø 18.50

Note:

The cooling system efficiency can be monitored using the temperature sensing diodes integrated in the device.

Thermal Dissipation by Conduction Only

When the external heat sink cannot be used, the relevant thermal resistance is the thermal

resistance from the junction to the bottom of the columns: RTH _{J-Bottom-of-columns}

The thermal path, in this case, is the junction, then the silicon, glue, CuW heat spreader, pack-

age Al2O3, and the columns (Sn10Pb90).

The Finite Element Method (FEM) with the thermal simulator leads to

RTH_{J-bottom-of-columns}= 7.4°C/W. This value assumes pure conduction from the junction to the

bottom of the columns (this is the worst case, no radiation and no convection is applied). With

such an assumption, RTH_{J- Bottom-of-columns}is user-independent.

To complete the thermal analysis, you must add the thermal resistance from the top of the

board (on which the device is soldered) to the ambient resistance, whose values are user-

dependent (the type of board, thermal, routing, area covered by copper in each board layer,

thickness, airflow or cold plate are all parameters to consider).

In the case of the CI-CGA 152 package, the thermal resistance from the junction to the top of

the package (via the CuW heat spreader covered by AI203) is

RTH_{J-top-of-package}= 4.8° C/W.

5360AS–BDC–08/04

Figure 4. Thermal Net

Silicon Junction

Silicon Die

14.4 mm2

0.80 ˚C/Watt

= 0.95 W/cm/˚C

Epoxy/Ag glue

3.0 ˚C/Watt

= 0.02 W/cm/˚C

CuW heatspreader

0.25 ˚C/Watt

= 2.3 W/cm/˚C

To external

heatsink if any

0.25 ˚C/Watt

1.7 ˚C/Watt

CuW heatspreader

= 2.3 W/cm/˚C

Ceramic package

= 0.17 W/cm/˚C

0.6 ˚C/Watt

0.5˚C/Watt

˚C/Watt

0.9

0.56

˚C/Watt

0.47

˚C/Watt

0.44

˚C/Watt

Ceramic

2.05

˚C/Watt

columns PbSn

= 0.40 W/cm/˚C

1.60

˚C/Watt

1.75

˚C/Watt

Bottom of 44

internal columns

Bottom

external columns

of 56

Bottom of 52

"between" columns

Assumptions:

Die 3.75x3.84=14.4 mm2

50 µm thick Epoxy/Ag glue

Pb90Sn 10 columns diameter 0.86 mm

2.1 mm length under bottom of LGA

21x21 mm CLGA

18.5x18.5 mm CuW on top

Bottom view

Silicon Junction

Case where all bottoms of columns

are connected to infinite heat sink at bottom

and no external heatsink on top

0.80

3.0

Reduction

(Result using SPICE, thermal to

electrical equivalent model)

0.25

1.7

Silicon

Junction

0.6

0.5

0.9

7.4 ˚C/Watt

2.61

2.22

2.04

Infinite heatsink

at bottom of columns

Infinite heatsink

at bottom of columns

TS83102G0BMGS

5360AS–BDC–08/04

TS83102G0BMGS

Package Description

Hermetic CI-CGA 152 Outline Dimensions

Figure 5. Mechanical Description Bottom View

Package Chamfer 0.4 (x4)

SCI Chamfer

1.8 (x4) 16

Pb90Sn10

columns

21.00 mm +/- 0.20

152 x O D = 0.89 +/- 0.10 mm

0.30 O T AO BO

Pin A1 Index

(no column)

Note: CuW Heat Spreader on Opposite Side of Package

Ceramic body size : 21 x 21 mm

Column pitch : 1.27 mm

Cofired : Al2O3

5360AS–BDC–08/04

Figure 6. Package Top View

R 7.00 mm

R 6.70 mm

Nickel gold finishing that

defines the external

heat sink footprint location

(electrically isolated from CuW)

Top surface is

AI203 ceramic

CuW vertical side is

apparent at peripheral

under AI203

Metalized area for

CuW brazing

Chamfer 0.5 (x4)

Pin A1 index

(no column)

CuW 18.5 mm sq. is

brazed on 20.3 mm sq.

metalization.

CuW side is electrically

connected to VEE

NI-Au plating

TS83102G0BMGS

5360AS–BDC–08/04

TS83102G0BMGS

Figure 7. Cross Section

High T^osolder coloumns

(Pb90Sn10)

152 columns in 3 external rows

minus 4 corners

Combo lid

soldered

9.27 mm sq

0.254 mm thick

CuW heat spreader

AI203 plate

brazed on CuW

This side has

no metalization

(0.300)

(0.500)

(0.150)

1.62 +/- 0.075

All units in mm

(0.30 +/- 0.05)

1.55 +/- 0.16

0.80 +/- 0.09

4.42 +/- 0.40

5360AS–BDC–08/04

Ordering Information

Part Number

Package

CI-CGA152

CI-CGA 152

Temperature Range

Ambient

Screening Level

Prototype

Comments

Please contact your

local Atmel sales office

TSX83102G0BGS

TS83102G0BMGS

-40°C < T_c; T_J< 125°C

Standard product

Evaluation Board

(delivered with a heat

sink)

TSEV83102G0BGL

CBGA 152

Ambient

Prototype

TS83102G0BMGS

5360AS–BDC–08/04

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Printed on recycled paper.

5360AS–BDC–08/04

TSX83102G0BGS [ATMEL]

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