U2794B-NFSH [ATMEL]
1000-MHz Quadrature Demodulator; 1000 MHz的正交解调器
| 型号： | U2794B-NFSH |
| 厂家： | 
ATMEL |
| 描述： | 1000-MHz Quadrature Demodulator |
| 文件： | 总15页 (文件大小：911K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Supply Voltage 5V
• Very Low Power Consumption 125 mW
• Very Good Image Rejection By Means of Phase Control Loop for Precise 90° Phase
Shifting
• Duty-cycle Regeneration for Single-ended LO Input Signal
• Low LO Input Level –10 dBm
• LO Frequency from 70 MHz to 1 GHz
• Power-down Mode
1000-MHz
• 25 dB Gain Control
• Very Low I/Q Output DC Offset Voltage Typically < 5 mV
Quadrature
Demodulator
Benefits
• Low Current Consumption
• Easy to Implement
• Perfect Performance for Large Variety of Wireless Applications
U2794B
1. Description
The silicon monolithic integrated circuit U2794B is a quadrature demodulator manu-
factured using Atmel®’s advanced UHF technology. This demodulator features a
frequency range from 70 MHz to 1000 MHz, low current consumption, selectable gain,
power-down mode, and adjustment-free handling. The IC is suitable for direct conver-
sion and image rejection applications in digital radio systems up to 1 GHz such as
cellular radios, cordless telephones, cable TV, and satellite TV systems.
Figure 1-1. Block Diagram
VS
IIX
II
PU
5,6 14
4
3
IX
Power
down
1
2
OUTPUT
I
0°
15
90°Control
loop
Frequency
doubler
Duty cycle
regenerator
7
LO
RFin
90°
17
PC
8
13
PCX
12
19
20
Q
OUTPUT
QX
10
9
11
16,18
GC
GND
QQ
QQX
4653F–CELL–11/08
2. Pin Configuration
Figure 2-1. Pinning SSO20
1
2
20
19
18
17
16
15
14
13
12
11
IX
QX
Q
I
3
II
GND
LOin
4
IIX
5
V
S
GND
6
LOXin
V
S
7
RFin
PU
RFXin
8
PC
9
PCX
GC
QQ
10
QQX
Table 2-1.
Pin Description
Pin
1
Symbol
IX
Function
IX output
2
I
I output
3
II
II lowpass filter I
IIX lowpass filter I
Supply voltage
Supply voltage
RF input
4
IIX
5
VS
6
VS
7
RFin
RFXin
QQ
QQX
GC
PCX
PC
8
RFX input
9
QQ lowpass filter Q
QQX lowpass filter Q
GC gain control
PCX phase control
PC phase control
PU power up
LOX input
10
11
12
13
14
15
16
17
18
19
20
PU
LOXin
GND
LOin
GND
Q
Ground
LO input
Ground
Q output
QX
QX output
2
U2794B
4653F–CELL–11/08
U2794B
3. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Value
6
Unit
V
Supply voltage
VS
Vi
Input voltage
0 to VS
+125
V
Junction temperature
Storage-temperature range
Tj
°C
°C
Tstg
–55 to +125
4. Thermal Resistance
Parameters
Symbol
Value
Unit
Junction ambient SSO20
RthJA
140
K/W
5. Operating Range
Parameters
Symbol
VS
Value
Unit
V
Supply-voltage range
Ambient-temperature range
4.75 to 5.25
–40 to +85
Tamb
°C
3
4653F–CELL–11/08
6. Electrical Characteristics
Test conditions (unless otherwise specified); VS = 5V, Tamb = 25°C, referred to test circuit
System impedance ZO = 50Ω, fiLO = 950 MHz, PiLO = –10 dBm
No.
1.1
1.2
2
Parameters
Test Conditions
Pin
5, 6
5, 6
Symbol
Min.
4.75
22
Typ.
Max.
5.25
35
Unit
V
Type*
Supply-voltage range
Supply current
VS
IS
A
A
30
mA
Power-down Mode
“OFF” mode supply
current
V
PU ≤ 0.5V
14, 5
6
≤ 1
20
µA
µA
B
D
2.1
ISPU
VPU = 1.0 V(1)
3
Switch Voltage
“Power ON”
3.1
3.2
4
14
14
VPON
4
V
V
D
D
“Power DOWN”
LO Input, LOin
Frequency range
Input level
VPOFF
1
4.1
4.2
4.3
17
17
17
fiLO
PiLO
ZiLO
70
1000
–5
MHz
dBm
Ω
D
D
D
(2)
–12
–10
50
Input impedance
See Figure 6-10
Voltage standing
wave ratio
4.4
See Figure 6-3
17
17
VSWRLO
DCRLO
1.2
2
D
D
4.5
Duty-cycle range
0.4
40
0.6
5
RF Input, RFin
Noise figure (DSB)
symmetrical output
at 950 MHz(3)
at 100 MHz
12
10
5.1
5.2
5.3
5.4
5.5
7, 8
7, 8
7, 8
7, 8
7, 8
NF
fiRF
dB
D
D
D
D
D
Frequency range
fiRF = fiLO ±BWYQ
1030
MHz
dBm
dBm
dBm
–1 dB input
compression point
High gain
Low gain
(4)
P1dBHG
P1dBLG
–8
+3.5
Second order IIP
IIP2HG
35
High gain
Low gain
IIP3HG
IIP3LG
+3
+13
Third order IIP
Symmetric input
Asymmetric input
≤ –60
≤ –55
5.6
5.7
LO leakage
7, 8
7, 8
LOL
dBm
D
D
Input impedance
see Figure 6-10
ZiRF
500II0.8
ΩIIpF
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. During power-down status a load circuitry with DC-isolation to GND is assumed, otherwise a current of I ≈ (VS –0.8V)/RI
has to be added to the above power-down current for each output I, IX, Q, QX.
2. The required LO-Level is a function of the LO frequency (see Figure 6-6).
3. Measured with input matching. For 950 MHz, the optional transmission line T3 at the RF input may be used for this pur-
pose. Noise figure measurements without using the differential output signal result in a worse noise figure.
4. Using pins 7 and 8 as a symmetric RF input, the second-order IIP can be improved.
5. Due to test board parasitics, this bandwidth may be reduced and not be equal for I, IX, Q, QX. If symmetry and full band-
width is required, the lowpass pins 3, 4 and 9, 10 should be isolated from the board. the bandwidth of the I/Q outputs can
be increased further by using a resistor between pins 3, 4, 9 and 10. These resistors shunt the internal loads of
RI ~ 5.4 kΩ. The decrease in gain here has to be considered.
6. The internal current of the output emitter followers is 0.6 mA. This reduces the undistorted output voltage swing at a 50Ω
load to approximately 30 mV. For low signal distortion the load impedance should be RI ≥ 5 kΩ.
7. Referred to the level of the output vector I2 + Q2
8. The low-gain status is achieved with an open or high-ohmic pin 11. A recommended application circuit for switching
between high and low gain status is shown in Figure 6-1.
4
U2794B
4653F–CELL–11/08
U2794B
6. Electrical Characteristics (Continued)
Test conditions (unless otherwise specified); VS = 5V, Tamb = 25°C, referred to test circuit
System impedance ZO = 50Ω, fiLO = 950 MHz, PiLO = –10 dBm
No.
6
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
I/Q Outputs (I, IX, Q, QX) Emitter Follower I = 0.6 mA
3-dB bandwidth
w/o external C
1, 2, 19,
20
6.1
6.2
6.3
6.4
6.5
6.6
BWI/Q
Ae
≥ 30
–0.5
–3
MHz
dB
D
B
B
D
A
1, 2, 19,
20
I/Q amplitude error
I/Q phase error
≤ ±0.2
+0.5
+3
1, 2, 19,
20
Pe
≤ ±1.5
Deg
I/Q maximum output
swing
Symm. output
RL > 5 kΩ
1, 2, 19,
20
VPP
2
1, 2, 19,
20
DC output voltage
VOUT
Voffset
Zout
2.5
2.8
< 5
50
3.1
V
mV
Ω
DC output offset
voltage
1, 2, 19,
20
Test
spec.
(6)
1, 2, 19,
20
6.7
Output impedance
see Figure 6-10
D
7
Gain Control, GC
Control range power
Gain high
Gain low
GCR
GH
GL
25
23
–2
dB
dB
dB
D
B
D
(7)
(8)
7.1
11
7.2
7.3
7.4
Switch Voltage
“Gain high”
11
1
V
“Gain low”
11 < open
7.5
Settling Time, ST
Power “OFF” - “ON”
Power “ON” - “OFF”
7.6
7.7
TSON
< 4
< 4
µs
µs
D
D
TSOFF
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. During power-down status a load circuitry with DC-isolation to GND is assumed, otherwise a current of I ≈ (VS –0.8V)/RI
has to be added to the above power-down current for each output I, IX, Q, QX.
2. The required LO-Level is a function of the LO frequency (see Figure 6-6).
3. Measured with input matching. For 950 MHz, the optional transmission line T3 at the RF input may be used for this pur-
pose. Noise figure measurements without using the differential output signal result in a worse noise figure.
4. Using pins 7 and 8 as a symmetric RF input, the second-order IIP can be improved.
5. Due to test board parasitics, this bandwidth may be reduced and not be equal for I, IX, Q, QX. If symmetry and full band-
width is required, the lowpass pins 3, 4 and 9, 10 should be isolated from the board. the bandwidth of the I/Q outputs can
be increased further by using a resistor between pins 3, 4, 9 and 10. These resistors shunt the internal loads of
RI ~ 5.4 kΩ. The decrease in gain here has to be considered.
6. The internal current of the output emitter followers is 0.6 mA. This reduces the undistorted output voltage swing at a 50Ω
load to approximately 30 mV. For low signal distortion the load impedance should be RI ≥ 5 kΩ.
7. Referred to the level of the output vector I2 + Q2
8. The low-gain status is achieved with an open or high-ohmic pin 11. A recommended application circuit for switching
between high and low gain status is shown in Figure 6-1.
5
4653F–CELL–11/08
Figure 6-1. Test Circuit
* optional for single-ended tests (notice 3 dB bandwidth of AD620)
T1, T2 = transmission line ZO = 50Ω.
If no GC function is required, connect Pin 11 to GND.
For high and low gain status GC´ is to be switched to GND respectively to VS.
Figure 6-2. I and Q phase for fRF > fLO. For fRF < fLO the phase is inverted.
1.5
1.0
Q
I
0.5
0.0
0
5
10
15
20
25
30
-0.5
-1.0
-1.5
Time (Arbitrary Units)
6
U2794B
4653F–CELL–11/08
U2794B
Figure 6-3. Typical VSWR Frequency Response of the LO Input
6
5
4
3
2
1
1050
50
250
450
650
850
LO Frequency ( MHz )
Figure 6-4. Noise Figure versus LO Frequency; o: Value at 950 MHz with RF Input Matching
with T3
18
16
14
12
10
8
0
200
400
600
800
1000
LO Frequency (MHz)
Figure 6-5. Typical Suitable LO Power Range versus Frequency
0
PLOmax
-10
-20
-30
-40
-50
PLOmin
30
40
50
60
70
80
90
LO Frequency (MHz)
7
4653F–CELL–11/08
Figure 6-6. Gain versus LO Frequency; x: Value at 950 MHz with RF Input Matching with T3
30
26
22
18
14
10
0
200
400
600
800
1000
LO Frequency (MHz)
Figure 6-7. Typical Output Signal versus LO Frequency for PRF = –15 dBm and
PLO = –15 dBm
1600
1500
1400
1300
1200
1100
1000
900
800
0
200
400
600
800
1000
LO Frequency (MHz)
Figure 6-8. Typical Suitable LO Power Range versus Frequency
10
0
-10
-20
-30
-40
-50
0
200
400
600
800
1000
LO Frequency (MHz)
8
U2794B
4653F–CELL–11/08
U2794B
Figure 6-9. Typical Output Voltage (Single Ended) versus PRF at Tamb = 25°C and
PLO = –15 dBm
1800
1600
1400
1200
1000
800
600
400
200
0
-40
-35
-30
-25
-20
-15
-10
PRF (dBm)
Figure 6-10. Typical S11 Frequency Response
j
0.5j
2j
0.2j
5j
c
a
0
0.2
0.5
1
2
5
1
b
-0.2j
-5j
-0.5j
-2j
-j
a: LO input, LO frequency from 100 MHz to 1100 MHz, marker: 950 MHz
b: RF input, RF frequency from 100 MHz to 1100 MHz, marker: 950 MHz
c: I/Q Outputs, Baseband Frequency from 5 MHz to 55 MHz, marker: 25 MHz
9
4653F–CELL–11/08
Figure 6-11. Evaluation Board Layout
Figure 6-12. Evaluation Board
10
U2794B
4653F–CELL–11/08
U2794B
6.1
External Components
CUCC
CRFX
CLO
100 nF
1 nF
100 pF
1 nF
CNLO
CRF
100 pF
CII, CQQ
T3
optional external lowpass filters
transmission line for RF-input matching, to connect optionally
optional for AC-coupling at
CI, CIX
CQ, CQX
CPDN
CGC
baseband outputs
100 pF
100 pF
100 pF
100 pF
not connected
CPC
not connected
not connected
gain switch
CNPC
GSW
6.2
6.3
Calibration Part
CO, CS, CL 100 pF
RL 50Ω
Conversion to Single Ended Output
(see datasheet of AD620)
OP1, OP2
RG1, RG2
AD620
prog. gain, see datasheet, for 5.6 kΩ a gain of 1 at 50Ω is
achieved together with RD1 and RD2.
RD1, RD2
CS1, CS2
CS3, CS4
450Ω
100 nF
100 nF
11
4653F–CELL–11/08
7. Description of the Evaluation Board
Board material: epoxy; εr = 4.8, thickness = 0.5 mm, transmission lines: ZO = 50Ω
The board offers the following functions:
• Test circuit for the U2794B:
– The supply voltage and the control inputs GC, PC, and PU are connected via a plug
strip. The control input voltages can be generated via external potentiometers; then
the inputs should be AC-grounded (time requirements in burst mode for power up
have to be considered).
– The outputs I, IX, Q, QX are DC coupled via an plug strip or can be AC-connected
via SMB plugs for high frequency tests e.g. noise figure or s-parameter
measurement. The Pins II, IIX, QQ, QQX allow user-definable filtering with 2
external capacitors CII, CQQ.
– The offsets of both channels can be adjusted with two potentiometers or resistors.
– The LO and the RF-inputs are AC-coupled and connected via SMB plugs. If
transmission line T3 is connected to the RF-input and AC-grounded at the other end,
gain and noise performance can be improved (input matching to 50Ω).
– The complementary RF-input is AC-coupled to GND (CRFX = 1 nF), the same
appears to the complementary LO input (CNLO = 1 nF).
• A calibration part which allows to calibrate an s-parameter analyzer directly to the in- and
output- signal ports of the U2794B.
• For single-ended measurements at the demodulator outputs, two OPs (e.g., AD620 or other)
can be configured with programmable gain; together with an output-divider network
RD = 450Ω to RL = 50Ω, direct measurements with 50Ω load impedances are possible at
frequencies t < 100 kHz.
12
U2794B
4653F–CELL–11/08
U2794B
8. Ordering Information
Extended Type Number
Package
SSO20
SSO20
Remarks
U2794B-NFSH
Tube, MOQ 830 pcs, Pb-free
U2794B-NFSG3H
Taped and reeled, MOQ 4000 pcs, Pb-free
9. Package Information
5.4±0.2
4.4±0.1
6.75-0.25
6.45±0.15
0.25±0.05
0.65±0.05
5.85±0.05
20
11
Package: SSO20
Dimensions in mm
technical drawings
according to DIN
specifications
1
10
Drawing-No.: 6.543-5056.01-4
Issue: 1; 10.03.04
13
4653F–CELL–11/08
10. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
• Put datasheet in the newest template
4653F-CELL-11/08
• ESD logo on page 1 deleted
• Section 6 “Electrical Characteristics” number 7.1 on page 6 changed
• Put datasheet in the newest template
4653E-CELL-07/06
• Section 3 “Absolute Maximum Ratings”: Storage temperature values on
page 4 changed.
14
U2794B
4653F–CELL–11/08
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4653F–CELL–11/08
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