U6224B-MFPG3_技术文档

U6224B

Frequency Synthesizer for TV and VCR Tuner with

Universal Bus

Description

The U6224B is a single chip frequency synthesizer with mable divider ratios, a crystal oscillator, a phase/

2

bi-directional I C-bus control and an unidirectional frequency detector together with a charge pump and a

3-wire bus control, developed for TV-tuner applications. tuning amplifier. It perform also a EASY LINK interface

This IC contains an integrated preamplifier, a high to MOSMIC and Mixer IC.

frequency prescaler, a reference divider with program-

F_De₁a_.3tu_Gr_He_zs_{divide-by-8 prescaler integrated}

2

D I C-bus mode:

(can be bridged)

3 bidirectional ports (open collector)

5 level ADC or unidirectional

D Easy-link interface to MOSMIC and

port (open collector)

3 addresses selectable at Pin 10 and

1 address fixed for multituner application

MIXER-IC

2

D Universal bus:

I C-bus or 3-wire-bus

D Low-power consumption (typ. 5 V / 35 mA)

D Electrostatic protection according to MIL-STD 883

D SO16 small package

D 3-wire-bus mode:

3 unidirectional output ports (open collector)

lock output (open collector)

Block Diagram

6 P1

7 P2

I/O

Ports

4–bit Latch

AS / ENA

10

5

4

UNI–BUS

Control

8 P0

SCL

SDA

9 P6 / ADC / Lock

11 MS

ADC

T1

7–bit Latch

8–bit Latch

7–bit Latch

Power–on

reset

POR

Vs 12

GND 15

Sync

LOCK

15–bit Latch

PSC T0

5I

RD1,2

FPRD

OS

SET

14

RFi

div. by 8

Prescaler

15–bit counter

13

Phase

detector

Charge

pump

RDS 3

16VD

1 PD

FRFD

XTAL 2

Oscillator

divide by 512 / 640 / 1024

Figure 1. Block diagram

Ordering Information

Extended Type Number

U6224B-MFP

Package

Remarks

SO16

U6224B-MFPG3

Taped and reeled

Rev. A3, 08-Mar-01

1 (15)

U6224B

Pin Description

1

2

3

4

5

6

7

8

Symbol

PD

Q1

RDS

SDA

SCL

P1

Function

Charge pump output

XTAL

Reference divider select input

Data input / output

Clock input

Input / output port

1

2

3

4

5

6

7

8

PD

16

15

14

13

12

11

10

9

VD

Q1

GND

RFi

RDS

SDA

SCL

P1

P2

P0

RFi

9

P6/ADC/ Port output / ADC-input / Lock

Lock output

AS/ENA Address select / Enable input

MS

Vs

RFi

GND

VD

V

S

10

11

12

13

14

15

16

MS

Mixer switch output

Supply voltage

RF input

Ground

P2

AS/ENA

P0

P6/ADC

/Lock

Active filter output

Figure 2. Pinning

2

In I C-bus mode, an Analog-to-Digital Converter is

available for digital AFC control applications and the

ports P0-2 can be used as inputs.

Description

The U6224B is a single chip-PLL designed for TV and

VCR receiver systems. It consists of a bridgeable

divide-by-8 prescaler with an integrated preamplifier, a

15-bit programmable divider, a crystal oscillator and a

reference divider with three selectable divider ratios

(ꢀ512/ꢀ640/ꢀ1024), and phase/ frequency detector

with a charge-pump which is driving the tuning amplifier.

Only one external transistor is required for varactor line

Functional Description

2

The U6224B is programmed via the 2-wire I C-bus or the

3-wire-bus depending on the received data format. The

three bus inputs Pins 4, 5 and 10 are used as SDA, SCL

and address select inputs in I C-bus mode or as data,

clock and enable inputs in 3-wire-bus mode. The data

includes the scaling factor SF and switching output

2

driving. The device can be controlled via the I C-bus or

the 3-wire-bus format. It detects automatically which bus

format is received, therefore, there is no need for a bus

2

information. In I C-bus mode, are some additional

functions are available (ADC, bidirectional ports, etc.).

2

selection pin. In I C-bus mode, the device has one fixed

2

I C-bus address and three programmable addresses. Pro-

Oscillator frequency calculation:

gramming is carried out by applying a specific input

voltage to the address select input, enabling the use of up

to three synthesizers in a system. This pin serves in

3-wire-bus mode as the enable signal input. Four open-

collector outputs are available for switching functions. In

3-wire-bus mode, there are three open-collector outputs.

One of them serves as Lock signal output. The logic of the

output ports P0-2 is inverted in order to drive gate 1 of

MOSMIC prestages directly without change in software.

This feature removes the formerly external pnp switching

transistors. All open collector outputs are capable of

sinking at least 10 mA. The MS output is provided to

control directly a mixer-oscillator IC in combination with

the output port P0-2 state.

f

= PSF SPF f

/SRF

VCO

refosc

f

:

Locked frequency of voltage controlled

oscillator

VCO

PSF: Scaling factor of prescaler

2

(ꢀ1 or ꢀ8 in I C-/ꢀ8 in 3-wire-bus mode)

SPF: Scaling factor of programmable divider

2

(15 bit in I C-/14 bit in 3-wire-bus mode)

SRF: Scaling

factor

(ꢀ512/ꢀ640/ꢀ1024)

of

reference

divider

f

: Reference oscillator frequency: 3.2/4 MHz

crystal or external reference frequency

refosc

2 (15)

Rev. A3, 08-Mar-01

U6224B

The input amplifier together and the divide-by-8 comparison frequency is 7.8125 kHz, resulting in

prescaler enable an excellent sensitivity (see figures 7

62.5-kHz steps for the VCO. Using a 3.2-MHz crystal

and 8). The input impedance is shown in the figure 16. results in 6.25 kHz comparison frequency and 50-kHz

2

When a new divider ratio according to the requested f

VCO step size. In I C-bus mode, the division ratio may

VCO

is entered, the phase detector and charge pump together be set via two bits, in 3-wire-bus mode via a voltage at Pin

with the tuning amplifier adjust the control voltage of the 3. In addition, port outputs for band switching and other

VCO until the output signals of the programmable divider purposes are available.

and the reference divider are in frequency and phase

locked. The reference frequency may be provided by an

external source capacitively coupled into Pin 2, or by

Application

using an on-board crystal with an 18-pF capacitor in A typical application is shown on page 14. All

series. The crystal operates in series resonance mode. The input/output interface circuits are shown on pages 12 and

reference divider division ratio is selectable to 13. Some special features related to test- and alignment

ꢀ512/ꢀ640/ꢀ1024. Using a 4-MHz crystal and the procedures for tuner production are explained in the

nominal division ratio of 512 of the reference divider, the following bus-mode description.

Absolute Maximum Ratings

All voltages are referred to GND (Pin 15).

Parameters

Supply voltage

RF input voltage

Xtal input voltage

Charge pump output volt-

age

Test Conditions / Pins

Pin 12

Symbol

Vs

RFi

Q1

Min.

–0.3

Typ.

Max.

6

Vs+0.3

Unit

V

Pin 13, 14

Pin 2

Pin 1

PD

Active filter output voltage

Bus input/output voltage

SDA output current

Address select/ENA input

Port output current

Total port output current

Port input/output voltage

Port output voltage

Junction temperature

Storage temperature

Pin 16

Pin 4, 5

open collector Pin 4

Pin 10

open collector Pin 6-9

VD

VSDA, VSCL

ISDA

VAS/ENA

P0-2, P6

Tjmax

–0.3

–1

–0.3

–1

Vs+0.3

V

mA

V

mA

V

6

5

Vs+0.3

15

50

15

6

–1

in off-state

in on-state

Pin 6-9

–0.3

–40

V

125

°C

Tstg

°C

Operating Range

All voltages are referred to GND (Pin 15).

Parameters

Supply voltage

Ambient temperature

Input frequency

Test Conditions / Pins

Pin 12

Symbol

Vs

Tamb

RFi

SF

Min.

4.5

0

80

1

256

3

Typ.

5

Max.

5.5

70

1300

220

32767

16383

4.48

Unit

V

°C

PSC = 1

PSC = 0

Pin 13, 14

MHz

Input frequency

2

Programmable divider

Xtal oscillator

I C-bus mode

3-wire-bus mode

SF

fXtal

Pin 2

4

MHz

Rev. A3, 08-Mar-01

3 (15)

U6224B

Thermal Resistance

All voltages are referred to GND (Pin 15).

Parameters

Thermal resistance

Test Conditions / Pins

SO16 small

Symbol

RthJA

Min.

Typ.

Max.

110

Unit

K/W

Electrical Characteristics

Test conditions (unless otherwise specified): Vs = 5 V, Tamb = 25 °C

Parameters

Test Conditions / Pins

Symbol Min.

Typ.

35

Max.

Unit

mA

Supply current (prescaler on)

P0-2 = 1; P6 = 0; PSC =1

Pin 12

Is

Supply current (prescaler off)

P0-2 = 1; P6 = 0; PSC =0

Pin 12

Is

21

mA

Input sensitivity

1)

f

= 80-1000 MHz

= 1300 MHz

= 10-220 MHz

PSC =1

PSC =0

Pin 13

Vi

10

40

10

315

mVrms

RFi

1)

Crystal oscillator

Recommended crystal series

resistance

10

200

W

Crystal oscillator drive level

Pin 2

50

mVrms

Crystal oscillator source im-

pedance

Nominal spread ±15 %

–650

W

Pin 2

External reference input fre-

quency

AC-coupled sinewave

Pin 2

3

4.5

MHz

External reference input ampli- AC-coupled sinewave

tude Pin 2

Port outputs/lock output (open collector), Lock condition: low, P0-2, P6, Lock

70

200

mVrms

Leakage current

Saturation voltage

Port inputs (P0-2)

Input voltage high

Input voltage low

Input current high

Input current low

ADC input (ADC), see page 7 for ADC-levels

Input current high

Input current low

VH = 13.5 V

IL = 10 mA

Pins 6-9

IL

VSL

10

0.5

mA

V

2)

Pins 6-8

Vi‘H’

Vi‘L’

Ii‘H’

Ii‘L’

2.7

–10

V

mA

0.8

10

Vi‘H’ = 13.5 V Pins 6-8

Vi‘L’ = 0 V

Pins 6-8

Vi‘H’ = 13.5 V Pin 9

Vi‘L’ = 0 V

Ii‘H’

Ii‘L’

10

mA

Pin 9

Charge pump output (PD)

Charge pump current ‘H’

5I = 1, VPD = 1.7 V

Pin 1

5I = 0, VPD = 1.7 V

Pin 1

TO = 1, VPD = 1.7 V

Pin 1

IPDH

IPDL

±180

±50

±5

mA

nA

Charge pump current ‘L’

Charge pump leakage current

Charge pump amplifier gain

IPDTRI

Pins 1, 16

6400

Notes: 1) RMS-voltage calculated from the available power measured at 50 W.

2) Tested with one port active. The collector voltage of an active port may not exceed 6 V.

4 (15)

Rev. A3, 08-Mar-01

U6224B

Parameters

Bus inputs (SDA, SCL)

Input voltage high

Input voltage low

Input current high

Input current low

Output voltage SDA (open ISDA‘L’ = 3 mA Pin 4

collector)

Address selection/Enable input (AS/ENA)

Test Conditions / Pins

Symbol

Min.

3

Typ.

Max.

Unit

Pin 4, 5

Vi‘H’

Vi‘L’

Ii‘H’

Ii‘L’

VSDA

‘L’

5.5

1.5

10

V

mA

V

Vi‘H’ = Vs

Vi‘L’ = 0 V

Pin 4, 5

–20

–10

0.4

10

Input current high

Input current low

Vi‘H’ = Vs

Vi‘L’ = 0 V

Pin 10

Ii‘H’

Ii‘L’

mA

Mixer switch output (MS)

Output voltage band A

Output voltage band B

Output voltage band C

I MS = –20 mA Pin 11

V MSA

V MSB

V MSC

0

1.6

Vs–1

0.25

0.4*Vs

Vs–.75

1

2.4

Vs

V

I²C-Bus Description

Functional Description

th

divider. They are loaded in a 15 bit latch after the 8 clock

pulse of the second divider byte PDB2, the control and the

2

th

When the U6224B is controlled via the 2-wire I C-bus

format, then data and clock signals are fed into the SDA

and SCL lines respectively. Depending on the LSB of the

address byte, the device can either accept new data (write

mode: LSB = 0) or send data (read mode: LSB = 1). The

port register latches are loaded after the 8 clock pulse of

the control byte CB1 resp. port byte CB2.

The control byte CB1 allows to control the following

special functions:

2

device has one fixed and three programmable I C-bus ad-

D 5I-bit switches between low and high charge pump

2

dresses. The tables ‘I C-BUS WRITE DATA FORMAT’

current

2

and ‘I C-BUS READ DATA FORMAT’ describe the for-

D T1-bit enables divider test mode when it is set to

mat of the data and show how to select the device address

by applying a voltage at Pin 10.

logic 1

D T0-bit allows to disable the charge pump when it is

Write Mode (Address byte LSB = 0)

set to logic 1

When write mode is activated and the correct address is

received, the SDA line is pulled low by the device during

the acknowledge period, and then also during the ac-

knowledge periods, when additional data bytes are

programmed. After the address transmission (first byte),

data bytes can be sent to the device. There are four data

bytes requested to fully program the device. Once the cor-

rect address is received and acknowledged, the first bit of

the following byte determines whether that byte is inter-

preted as byte 2 or 4; a logic 0 for divider information and

a logic 1 for control and port output information. When

byte 2 was received the device always expects byte 3 next.

Likewise when byte 4 was received, byte 5 is expected.

Additional data bytes can be entered without the need to

D PSC-bit switches prescaler off when it is set to logic 0

D RD1 and RD2-bit allow to select the reference divider

ratio

D OS-bit disables the charge pump drive amplifier out-

put when it is set to logic 1.

2

The charge pump current can be controlled in I C-bus

mode only.

The OS-bit function disables the complete PLL function.

This allows the tuner alignment by supplying the tuning

voltage directly through the 30 V supply voltage of the

tuner.

The control byte CB2 programs the port outputs P0-2 and

P6; for the MOSMIC ports P0-2 a logic 1 for high imped-

ance output (off) or a logic 0 for low impedance output

and for the standard port P6 a logic 0 for high impedance

output (off) or a logic 1 for low impedance output (on). At

power-on the MOSMIC ports P0-2 are set to low imped-

2

re-address the device to the device until an I C-bus stop

condition is recognized. This allows a smooth frequency

2

sweep for fine tuning AFC purposes. The table ‘I C-BUS

PULSE DIAGRAM’ shows some possible data transfer

examples.

The programmable divider bytes PDB1 and PDB2 are ance state and the standard port P6 to high impedance

controlling the division ratio of the 15 bit programmable state.

Rev. A3, 08-Mar-01

5 (15)

U6224B

2

Description

I C Bus Write Data Format

MSB

1

0

n7

1

X

LSB

0

n8

n0

OS

P0

Address byte

1

n14

n6

5I

0

n13

n5

T1

X

0

n12

n4

T0

X

0

n11

n3

PSC

X

AS1

n10

n2

RD2 RD1

P2 P1

AS2

n9

n1

A

Progr. divider byte 1

Progr. divider byte 2

Control byte 1

Control byte 2

P6

A = Acknowledged; X = not used; unused bits of control byte 2 should be 0 for lowest power consumption

n0 ... n14:

PSC:

Scaling factor (SF)

Prescaler on/off

SF = 16384 n14 + 8192 n13 + ... + 2 n1 + n0

PSC = 1: prescaler on

PSC = 0: prescaler off

T0, T1:

Test mode selection

T1 = 1: divider test mode on fPRD at Pin 6, fRFD at Pin 7

T1 = 0: divide test mode off

T0 = 1: charge pump disable

T0 = 0: charge pump enable

P0-2:

P6:

Port outputs (for MOSMIC’S)

Port outputs

P0, 1, 2 = 0: open collector active for MOSMIC gate 1 logic

P6 = 1: open collector active

5I:

Charge pump current switch

Output switch

5I = 1: high current

5I = 0: low current

OS:

OS = 1: varicap drive disable

OS = 0: varicap drive enable

RD1, RD2: Reference Divider Selection

AS1, AS2: Address Selection Pin 10

RD2 RD1

Reference Divider Ratio

X

0

1

0

1

640

1024

512

AS1

AS2 Address Dec. Value

Voltage at

Pin 10

0

1

0

1

2

3

4

194

192

196

198

always valid

0 to 10 % Vs

40 to 60 % Vs

90 % Vs to 13.5

V

Mixer-Switch Output Levels

P2

P1

P0

MS Output Band Selection

Voltage

0

1

0

1

0

1

< 0.25 V

Band A

Band B

Band C

0.4 Vs

Vs –

0.75 V

6 (15)

Rev. A3, 08-Mar-01

U6224B

tion is lost and the port outputs are all set to high

impedance state.

Read Mode (Address byte LSB = 1)

After the address transmission (first byte), the status byte

can be read from the device on the SDA line (MSB first).

Data is valid on the SDA line during logic high of the SCL

signal. The controller accepting the data has to pull the

SDA line to low-level during all status byte acknowledge

periods to read another status byte. If the controller fails

to pull the SDA line to low-level during this period, the

device will release the SDA line to allow the controller to

generate a STOP condition.

The FL-bit indicates whether the loop is in phase lock

condition (logic 1) or not (logic 0).

If the ADC or the ports are to be used as inputs, the corre-

sponding outputs must be programmed to a high

impedance state (logic 1).

The bits I2, I1 and I0 show the status of the I/O ports P0,

P1 and P2 respectively. A logic 0 indicates a LOW level

and a logic 1 a HIGH level (TTL levels).

The POR-bit (power-on-reset) is set to a logic 1 when the

supply voltage Vs of the device has dropped below 3 V (at The bits A2, A1 and A0 represent the digital information

25 °C) and also when the device is initially turned on. The of the 5-level ADC. This converter can be used to feed

POR-bit is reset to a logic 0 when the read sequence is ter- AFC information to the controller from the IF section of

minated by a STOP condition. When POR-bit is set high the receiver, as shown in the typical application circuit on

(at low Vs) it is indicated that all programmed informa- page 14.

2

Description

I C Bus Read Data Format

MSB

1

POR

LSB

1

A0

Address byte

Status byte

1

FL

0

I2

0

I1

0

I0

AS1

A2

AS2

A1

A

–

POR: Power-on-reset flag:

FL: in-lock flag:

POR = 1 on power on

FL = 1, when loop is phase locked

I2, I1, I0: digital information of I/O-ports P0, P1 and P2 respectively

A2, A1, A0: digital data of the 5-level ADC.

see next table

A/D Converter Levels

A2

1

0

A1

0

1

A0

0

1

Input Voltage to ADC Pin 9

60 % Vs to 13.5 V

45 % to 60 % Vs

0

1

0

30 % to 45 % Vs

0

1

15 % to 30 % Vs

0

0 V to 15 % Vs

Rev. A3, 08-Mar-01

7 (15)

U6224B

I²C-Bus Pulse Diagram

ADDRESS BYTE

/ A / 1.BYTE

/ A / 2.BYTE / A / 3.BYTE / A /

4.BYTE / A /

SDA

SCL

1...

1

2

3

4

5

6

7

8

9

8

9

1...

8

9

8

9

1...

8

9

STOP

START

Figure 3. Pulse diagram

Data transfer examples

Description

START – ADR – PDB1 – PDB2 – CB1 – CB2 – STOP

START – ADR – CB1 – CB2 – PDB1 – PDB2 – STOP

START – ADR – PDB1 – PDB2 – CB1 – STOP

START – ADR –PDB1 – PDB2 –STOP

START =

ADR =

PDB1 =

PDB2 =

CB1 =

Start condition

Address byte

Progr. divider byte 1

Progr. divider byte 2

Control byte 1

START –ADR – CB1 – CB2 – STOP

START – ADR – CB1 –STOP

CB2 =

Control byte 2

STOP =

Stop condition

I²C-Bus Timing

t

W STT

SDA

t _{S STT}

t _LOW

t _HIGH

t _R

t _F

t _{S STP}

SCL

t _{H STT}

t _{S DAT}

t _{H DAT}

START

CLOCK

DATACHANGE

STOP

Figure 4. Bus timing

Parameters

Test Conditions / Pins

Symbol

tR

tF

fSCL

tHIGH

tLOW

tH STT

tW STT

tS STT

tS STP

tS DAT

tH DAT

Min.

Max.

15

Unit

ms

kHz

ms

Rise time SDA, SCL

Fall time SDA, SCL

Clock frequency SCL

Clock ‘H’ pulse

Clock ‘L’ pulse

0

4

0.3

0

100

Hold time start

Waiting time start

Setup time start

Setup time stop

Setup time data

Hold time data

ms

8 (15)

Rev. A3, 08-Mar-01

U6224B

In 3-wire-bus mode, the following conditions are set in-

ternally:

3-Wire-Bus Description

When the U6224B is controlled via 3-wire-bus format,

then data, clock and enable signals are fed into the SDA,

SCL and AS/ENA lines respectively. Figure 5 shows the

data format. The data consists of a single word which

contains the programmable divider (14 bit) and port

information. Bit no. 15 of the programmable divider is

always zero when 3-wire-bus mode is active. Only during

the enable high period, the data is clocked into the internal

data shift register on the negative clock transition. During

enable low periods, the clock input is disabled. New data

words are only accepted by the internal data latches from

the shift register on a negative transition of the enable

signal when exactly eighteen clock pulses were sent

during the high period of the enable. The data sequence

and the timing is described in the following diagrams.

D 5I = 1:

always high, charge pump current ac-

tive

D T1 = 0:

D T0 = 0:

divider test mode off

charge pump enable

D RD1, 2 = X: reference divider ratio is selected

through RDS input

D PSC = 1:

D OS = 0:

prescaler on

varicap enable

In 3-wire-bus mode, the division ratio of the reference

divider may be selected by applying an appropriate

voltage at the RDS input Pin 3.

In 3-wire-bus mode, Pin 9 becomes automatically the The complete PLL function can be disabled by

Lock signal output. An improved lock detect circuit gen- programming a normally not used division ratio of zero.

erates a flag when the loop has attained lock. ‘In lock’ is This allows the tuner alignment by supplying the tuning

indicated by a low impedance at on state of the open voltage directly through the 30-V supply voltage of the

collector output.

tuner.

RDS: Reference Divider Selection Pin 3

Reference Divider Ratio

Voltage at Pin 3

0% to 10% Vs

open or 40% to 60% Vs

90% to 100% Vs

1024

512

640

Rev. A3, 08-Mar-01

9 (15)

U6224B

3-Wire-Bus Pulse Diagram

3 Bit

Ports

14 Bit scaling factor SF

MSB

P0

X

LSB

P1 P2

SDA

SCL

AS / ENA

Figure 5. Pulse diagram

3-Wire-Bus Timing

SDA

LSB

SCL

AS / ENA

TL

TS TC TH TSL

TT

Figure 6. Bus timing

Parameters

Setup time

Test Conditions / Pins

Symbol

TS

Min.

2

Typ.

Max.

Unit

ms

Enable hold time

Clock width

TSL

TC

2

ms

Enable setup time

Enable between two trans-

missions

TL

TT

10

ms

Data hold time

TH

2

ms

10 (15)

Rev. A3, 08-Mar-01

U6224B

Typical Prescaler Input Sensitivity (Prescaler on: PSC = 1)

Vi (mV RMS on 50 Ohm)

1000

100

OPERATING WINDOW

10

1

0,1

0

200

400

600

800

1000

1200

1400

1600

1800

2000

Frequency (MHz)

Figure 7.

Typical Prescaler Input Sensitivity (Prescaler off: PSC = 0)

Vi (mV RMS on 50 Ohm)

1000

100

OPERATING WINDOW

10

1

0,1

0

50

100

150

200

250

300

350

400

Frequency (MHz)

Figure 8.

Rev. A3, 08-Mar-01

11 (15)

U6224B

Input/Output Interface Circuits

Vref

Vs

Port

Vref

1.5K

RF1

RF2

Figure 9. RF Input

Figure 12. Ports

Vs

2K

60

PD

Vref

AS / ENA

VD

OS

(O/P Disable)

45K

Figure 13. Address select/ Enable input

Figure 10. Loop amplifier

Vs

25k

RDS

25k

SDA / SCL

SDA only

ACK

Figure 11. SCL and SDA input

Figure 14. Reference divider select input

12 (15)

Rev. A3, 08-Mar-01

U6224B

Vs

XTAL Q1

Figure 15. Reference oscillator

Typical Input Impedance

j

0.5j

2j

0.2j

5j

0

0.2

0.5

1

2

5

1

100 MHz

–0.2j

–5j

500 MHz

1 GHz

1.5 GHz

–0.5j

–2j

Z = 50 W

0

–j

Figure 16.

Rev. A3, 08-Mar-01

13 (15)

U6224B

Application Circuit

MOSMIC MX / OSC

f

IF

AGC

ANT

10k

IF–Section

AFC

f

VCO

OSC

4n7

30 V

RDS

4 MHz

18 p

39 n

22 k

1 n

14

RFi

ADC

13

3

2

9

12

Vs

PD

180 n

VD

1

15

GND

16

U6224B

10

5

4

AS / ENA

m

from/to

C

SCL

SDA

11

6

MS

7

8

P1 P2 P0

Figure 17. Application circuit

Package Information

Package SO16

Dimensions in mm

5.2

4.8

10.0

9.85

3.7

1.4

0.2

0.25

0.10

0.4

3.8

1.27

6.15

5.85

8.89

16

9

technical drawings

according to DIN

specifications

1

8

14 (15)

Rev. A3, 08-Mar-01

U6224B

Ozone Depleting Substances Policy Statement

It is the policy of Atmel Germany GmbH to

1. Meet all present and future national and international statutory requirements.

2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems

with respect to their impact on the health and safety of our employees and the public, as well as their impact on

the environment.

It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as

ozone depleting substances (ODSs).

The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid

their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these

substances.

Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed

in the following documents.

1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively

2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental

Protection Agency (EPA) in the USA

3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.

Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances

and do not contain such substances.

We reserve the right to make changes to improve technical design and may do so without further notice.

Parameters can vary in different applications. All operating parameters must be validated for each customer

application by the customer. Should the buyer use Atmel Wireless & Microcontrollers products for any unintended

or unauthorized application, the buyer shall indemnify Atmel Wireless & Microcontrollers against all claims,

costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death

associated with such unintended or unauthorized use.

Data sheets can also be retrieved from the Internet:

http://www.atmel–wm.com

Atmel Germany GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany

Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423

Rev. A3, 08-Mar-01

15 (15)


型号：	U6224B-MFPG3
厂家：	ATMEL
描述：	PLL Frequency Synthesizer, PDSO16, SO-16 光电二极管
文件：	总15页 (文件大小：109K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

U6224B-MFPG3 [ATMEL]

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