U6815BM-NFLY [ATMEL]
Dual Hex DMOS Output Driver with Serial Input Control; 带串行输入控制的双六角DMOS输出驱动器
| 型号： | U6815BM-NFLY |
| 厂家： | 
ATMEL |
| 描述： | Dual Hex DMOS Output Driver with Serial Input Control |
| 文件： | 总14页 (文件大小：314K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
•
•
•
Six High-side and Six Low-side Drivers
Outputs Freely Configurable as Switch, Half Bridge or H-bridge
Capable to Switch All Kinds of Loads Such as DC Motors, Bulbs, Resistors, Capacitors
and Inductors
•
•
•
•
•
•
•
•
0.6A Continuous Current Per Switch
Low-side: RDSon < 1.5ΩVersus Total Temperature Range
High-side: RDSon < 2.0Ω Versus Total Temperature Range
Very Low Quiescent Current IS < 20 µA in Standby Mode
Outputs Short-circuit Protected
Dual Hex DMOS
Output Driver
with Serial Input
Control
Overtemperature Prewarning and Protection
Under- and Overvoltage Protection
Various Diagnosis Functions Such as Shorted Output, Open Load, Overtemperature
and Power Supply Fail
•
•
•
Serial Data Interface
Daisy Chaining Possible
U6815BM
SO28 Power Package
1. Description
The U6815BM is a fully protected driver interface designed in 0.8-µm BCDMOS tech-
nology. It is used to control up to 12 different loads by a microcontroller in automotive
and industrial applications.
Each of the 6 high-side and 6 low-side drivers is capable to drive currents up to
600 mA. The drivers are freely configurable and can be controlled separately from a
standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors,
capacitors and inductors can be combined. The IC design especially supports the
applications of H-bridges to drive DC motors.
Protection is guaranteed in terms of short-circuit conditions, overtemperature, under-
and overvoltage. Various diagnostic functions and a very low quiescent current in
standby mode enable a wide range of applications. Automotive qualification referring
to conducted interferences, EMC protection and 2-kV ESD protection gives added
value and enhanced quality for the strict automotive requirements.
Rev. 4545C–BCD–09/05
Figure 1-1. Block Diagram
HS3
HS5
HS6
HS2
HS1
HS4
15
2
13
12
3
28
5
VS
Fault
Fault
Detect
Fault
Fault
Fault
Fault
Detect
Detect
Detect
Detect
Detect
10
VS
26
DI
6
7
V
OV -
protection
S
GND
Osc
25
S
C
T
O
L
H
S
6
H
S
5
H
S
4
H
L
S
2
H
L
S
6
L
L
S
4
H
S
3
L
S
3
L
S
1
S
GND
GND
CLK
S
S
R
R
S
S
5
I
D
2
1
V
S
8
Control
logic
UV -
protection
24
Input Register
Output Register
CS
9
GND
GND
GND
GND
Thermal
protection
17
18
L
S
6
P
S
F
S
C
D
H
S
6
H
L
H
L
H
S
3
L
H
L
S
2
H
L
S
1
T
P
I
INH
20
21
22
23
19
N
H
S
S
S
S
S
S
S
5
4
5
4
3
2
1
P - ON -
Reset
DO
Vcc
Fault
Fault
Detect
Fault
Fault
Fault
Detect
Fault
Detect
GND
Vcc
Detect
Detect
Detect
Vcc
16
LS1
14
LS2
11
LS3
4
1
27
LS6
LS4
LS5
2
U6815BM
4545C–BCD–09/05
U6815BM
2. Pin Configuration
Figure 2-1. Pinning SO28
HS6 LS6
DI
CLK CS GND GND GND GND VCC
INH LS1 HS1
17 16 15
DO
18
28
27
26
25
24
23
22
21
20
19
U6815BM
Lead frame
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LS5 HS5 HS4 LS4 VS GND GND GND GND VS LS3 HS3 HS2 LS2
Table 2-1.
Pin
Pin Description
Symbol
Function
Low-side driver output 5, power-MOS open drain with internal reverse diode, overvoltage protection by
active zenering, short-circuit protection, diagnosis for short and open load
1
2
LS5
High-side driver output 5, power-MOS open drain with internal reverse diode, overvoltage protection by
active zenering, short-circuit protection, diagnosis for short and open load
HS5
3
4
HS4
LS4
VS
High-side driver output 4 (see pin 2)
Low-side driver output 4 (see pin 1)
5
Power supply output stages HS4, HS5, HS6, internal supply; external connection to pin 10 necessary
Ground, reference potential, internal connection to pin 20 to 23, cooling tab
Power supply output stages HS1, HS2 and HS3
Low-side driver output 3 (see pin 1)
6, 7, 8, 9
10
GND
VS
11
LS3
HS3
HS2
LS2
HS1
LS1
INH
12
High-side driver output 3 (see pin 2)
13
High-side driver output 2 (see pin 2)
14
Low-side driver output 2 (see pin 1)
15
High-side driver output 1 (see pin 2)
16
Low-side driver output 1 (see pin 1)
17
Inhibit input, 5-V logic input with internal pull down, low = standby, high = normal operating
Serial data output, 5-V CMOS logic level tristate output for output (status) register data, sends 16-bit
status information to the microcontroller (LSB is transferred first). Output will remain tristated unless
device is selected by CS = low, therefore, several ICs can operate on one data output line only.
18
DO
19
VCC
GND
Logic supply voltage (5V)
Ground (see pins 6 to 9)
20, 21, 22, 23
Chip select input, 5-V CMOS logic level input with internal pull up, low = serial communication is
enabled, high = disabled
24
25
26
CS
CLK
DI
Serial clock input, 5-V CMOS logic level input with internal pull down, controls serial data input
interface and internal shift register (fmax = 2 MHz)
Serial data input, 5-V CMOS logic level input with internal pull down, receives serial data from the
control device, DI expects a 16-bit control word with LSB being transferred first
27
28
LS6
HS6
Low-side driver output 6 (see pin 1)
High-side driver output 6 (see pin 2)
3
4545C–BCD–09/05
3. Functional Description
3.1
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized
to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be trans-
ferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS
is high, Pin DO is in tristate condition. This output is enabled on the falling edge of CS. Output
data will change their state with the rising edge of CLK and stay stable until the next rising edge
of CLK appears. LSB (bit 0, TP) is transferred first.
Figure 3-1. Data Transfer
CS
DI
SRR
0
LS1
HS1
LS2
HS2
LS3
HS3
LS4
HS4
LS5
HS5
10
LS6
11
HS6 OLD SCT
12 13 14
SI
1
2
3
4
5
6
7
8
9
15
CLK
DO
TP
SLS1 SHS1 SLS2 SHS2 SLS3 SHS3 SLS4 SHS4 SLS5 SHS5 SLS6 SHS6 SCD
INH
PSF
Table 3-1.
Input Data Protocol
Bit
Input Register
Function
Status register reset (high = reset; the bits PSF, SCD and overtemperature shutdown in the output
data register are set to low)
0
SRR
1
2
LS1
HS1
LS2
HS2
LS3
HS3
LS4
HS4
LS5
HS5
LS6
HS6
OLD
Controls output LS1 (high = switch output LS1 on)
Controls output HS1 (high = switch output HS1 on)
3
See LS1
4
See HS1
5
See LS1
6
See HS1
7
See LS1
8
See HS1
9
See LS1
10
11
12
13
See HS1
See LS1
See HS1
Open load detection (low = on)
Programmable time delay for short circuit and overvoltage shutdown (short circuit shutdown delay
high/low = 100 ms/12.5 ms, overvoltage shutdown delay high/low = 15 ms/3.5 ms
14
15
SCT
SI
Software inhibit; low = standby, high = normal operation
(data transfer is not affected by standby function because the digital part is still powered)
4
U6815BM
4545C–BCD–09/05
U6815BM
After power-on reset, the input register has the following status:
Bit 15
(SI)
Bit 14
(SCT)
Bit 13
(OLD)
Bit 12
(HS6)
Bit 11
(LS6)
Bit 10
(HS5)
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LS5)
(HS4)
(LS4)
(HS3)
(LS3)
(HS2)
(LS2)
(HS1)
(LS1)
(SRR)
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
Table 3-2.
Output Data Protocol
Output (Status) Register
TP
Bit
Function
0
Temperature prewarning: high = warning (overtemperature shut down)(1)
Normal operation: high = output is on, low = output is off
1
2
Status LS1
Status HS1
Open-load detection: high = open load, low = no open load (correct load condition is detected
if the corresponding output is switched off)
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load (correct load condition is detected
if the corresponding output is switched off)
3
4
Status LS2
Status HS2
Status LS3
Status HS3
Status LS4
Status HS4
Status LS5
Status HS5
Status LS6
Status HS6
Description see LS1
Description see HS1
Description see LS1
Description see HS1
Description see LS1
Description see HS1
Description see LS1
Description see HS1
Description see LS1
Description see HS1
5
6
7
8
9
10
11
12
Short circuit detected: set high, when at least one output is switched off by a short circuit
condition
13
SCD
Inhibit: this bit is controlled by software (bit SI in input register) and hardware inhibit (pin 17).
High = standby, low = normal operation
14
15
INH
PSF
Power supply fail: over- or undervoltage at pin VS detected
Note:
1. Bit 0 to 15 = high: overtemperature shutdown
5
4545C–BCD–09/05
4. Power Supply Fail
In case of over-/undervoltage at pin VS, an internal timer is started. When the overvoltage delay
time (tdOV) programmed by the SCT Bit, or the undervoltage delay time (tdUV) is reached, the
power supply fail bit (PSF) in the output register is set and all outputs are disabled. When normal
voltage is present again, the outputs are enabled immediately. The PSF bit remains high until it
is reset by the SRR bit in the input register.
5. Open-load Detection
If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and
a pull-down current for each low-side switch is turned on (open-load detection current IHS1-6
LS1-6). If VVS – VHS1-6 or VLS1-6 is lower than the open-load detection threshold (open-load condi-
,
I
tion) the corresponding bit of the output in the output register is set to high. Switching on an
output stage with OLD bit set to low disables the open-load function for this output.
6. Overtemperature Protection
If the junction temperature exceeds the thermal prewarning threshold, TjPW set, the temperature
prewarning bit (TP) in the output register is set. When temperature falls below the thermal pre-
warning threshold TjPW reset, the bit TP is reset. The TP bit can be read without transferring a
complete 16-bit data word: with CS = high to low, the state of TP appears at Pin DO. After the
microcontroller has read this information, CS is set high and the data transfer is interrupted with-
out affecting the state of input and output registers.
If the junction temperature exceeds the thermal shutdown threshold Tj switch off, the outputs are
disabled and all bits in the output register are set high. The outputs can be enabled again when
the temperature falls below the thermal shutdown threshold, Tj switch on, and when a high has
been written to the SRR bit in the input register. Thermal prewarning and shutdown threshold
have hysteresis.
7. Short-circuit Protection
The output currents are limited by a current regulator. Current limitation takes place when the
over-current limitation and shutdown threshold (IHS1-6, ILS1-6) are reached. Simultaneously, an
internal timer is started. The shorted output is disabled when during a permanent short the delay
time (tdSd) programmed by the Short-Circuit Timer (SCT) bit is reached. Additionally, the Short-
Circuit Detection (SCD) bit is set. If the temperature prewarning bit TP in the output register is
set during a short, the shorted output is disabled immediately and SCD bit is set. By writing a
high to the SRR bit in the input register, the SCD bit is reset and the disabled outputs are
enabled.
7.1
Inhibit
There are two ways to inhibit the U6815BM:
1. Set bit SI in the input register to zero
2. Switch Pin 17 (INH) to 0V
In both cases, all output stages are turned off but the serial interface stays active. The output
stages can be activated again by bit SI = 1 or by pin 17 (INH) switched back to 5V.
6
U6815BM
4545C–BCD–09/05
U6815BM
8. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All values refer to GND pins.
Parameters
Pins
Symbol
VVS
Value
–0.3 to +40
–1
Unit
V
Supply voltage
5, 10
Supply voltage, t < 0.5s; IS > –2A
Supply voltage difference
Supply current
5, 10
VVS
V
|VS_Pin5 – VS_Pin10
|
∆VVS
150
mV
A
5, 10
5, 10
IVS
1.4
Supply current, t < 200 ms
Logic supply voltage
Input voltage
IVS
2.6
A
19
VVCC
–0.3 to +7
–0.3 to +17
–0.3 to VVCC + 0.3
–0.3 to VVCC + 0.3
–10 to +10
–10 to +10
V
17
VINH
V
Logic input voltage
Logic output voltage
Input current
24 to 26
18
VDI, VCLK, VCS
VDO
IINH, IDI, ICLK, ICS
IDO
ILS1 to ILS6
IHS1 to IHS6
V
V
17, 24 to 26
18
mA
mA
mA
mA
Output current
1 to 4, 11 to 16
27, 28
Internally limited (see
output specification)
Output current
2, 3, 12, 13, 15,
28 towards 5, 10
Reverse conducting current (tpulse = 150 µs)
IHS1 to IHS6
17
A
Junction temperature range
Storage temperature range
Tj
–40 to +150
–55 to +150
°C
°C
Tstg
9. Thermal Resistance
All values refer to GND pins
Parameters
Symbol
RthJP
Value
25
Unit
K/W
K/W
Junction - pin, measured to GND, Pins 6 to 9 and 20 to 23
Junction ambient
RthJA
65
10. Operating Range
All values refer to GND pins
Parameters
Pins
5, 10
19
Symbol
VVS
Min.
Typ.
Max.
40 (2)
5.5
Unit
V
(1)
Supply voltage
Logic supply voltage
VUV
VVCC
4.5
5
V
17, 24
to 26
V
INH, VDI,
Logic input voltage
–0.3
VVCC
V
VCLK, VCS
Serial interface clock frequency
Junction temperature
25
fCLK
Tj
2
MHz
°C
–40
+150
Notes: 1. Threshold for undervoltage detection
2. Output disabled for VVS > VOV (threshold for overvoltage detection)
7
4545C–BCD–09/05
11. Noise and Surge Immunity
Parameters
Test Conditions
Value
level 4 (1)
level 5
2 kV
Conducted interferences
Interference suppression
ESD (human body model)
ESD (machine model)
ISO 7637-1
VDE 0879 Part 2
MIL-STD-883D Method 3015.7
EOS/ESD - S 5.2
150V
Note:
1. Test pulse 5: VSmax = 40V
12. Electrical Characteristics
7.5V < VVS < 40V; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
Parameters
Test Conditions/Pins
Symbol
Min.
Typ.
Max.
Unit
Current Consumption
V
VS < 16V, INH or bit SI = low
Quiescent current (VS)
IVS
40
20
µA
µA
Pins 5, 10
4.5V < VVCC < 5.5V,
INH or bit SI = low, pin 19
Quiescent current (VCC
)
IVCC
VVS < 16V, pins 5, 10
all output stages off
Supply current (VS)
normal operating
IVS
IVS
0.8
1.2
10
mA
mA
All output stages on, no load
4.5V < VVCC < 5.5V,
normal operating, pin 19
Supply current (VCC
)
IVCC
150
µA
Internal Oscillator Frequency
Frequency
(time-base for delay timers)
fOSC
19
45
kHz
Over- and Undervoltage Detection, Power-on Reset
Power-on reset threshold
Pin 19
VVCC
tdPor
VUV
3.4
30
3.9
95
4.4
160
7.0
V
µs
V
Power-on reset delay time
After switching on VVCC
Pins 5, 10
Undervoltage detection threshold
Undervoltage detection hysteresis
Undervoltage detection delay
Overvoltage detection threshold
Overvoltage detection hysteresis
Overvoltage detection delay
Overvoltage detection delay
Thermal Prewarning and Shutdown
Thermal prewarning, set
5.5
Pins 5, 10
∆VUV
tdUV
0.4
1
V
7
21
ms
V
Pins 5, 10
VOV
18
22.5
Pins 5, 10
∆VOV
tdOV
V
Input register, Bit 14 (SCT) = high
Input register, Bit 14 (SCT) = low
7
21
ms
ms
tdOV
1.75
5.25
TjPWset
TjPWreset
∆TjPW
125
105
145
125
20
165
145
°C
°C
K
Thermal prewarning, reset
Thermal prewarning hysteresis
Thermal shutdown, off
Tj switch off
Tj switch on
∆Tj switch off
150
130
170
150
20
190
170
°C
°C
K
Thermal shutdown, on
Thermal shutdown hysteresis
Notes: 1. Only valid for version U6815BM-N.
2. Delay time between rising edge of CS after data transmission and switch-on output stages to 90% of final level.
8
U6815BM
4545C–BCD–09/05
U6815BM
12. Electrical Characteristics (Continued)
7.5V < VVS < 40V; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
Parameters
Test Conditions/Pins
Symbol
Min.
Typ.
Max.
Unit
Ratio thermal shutdown, off/thermal
prewarning, set
Tj switch off/
TjPW set
1.05
1.17
Ratio thermal shutdown, on/thermal
prewarning, reset
Tj switch on/
TjPW reset
1.05
1.2
Output Specification (LS1 to LS6, HS1 to HS6), 7.5V < VVS < VOV
IOut = 600 mA,
On resistance, low
Pins 1, 4, 11, 14, 16 and 27
RDS On L
RDS On H
VLS1–6
1.5
2.0
60
Ω
Ω
I
Out = –600 mA,
On resistance, high
Pins 2, 3, 12, 13, 15 and 28
ILS1–6 = 50 mA,
Pins 1, 4, 11, 14, 16, 27
Output clamping voltage
40
V
VLS1–6 = 40V, all output stages off,
Pins 1, 4, 11, 14, 16 and 27
ILS1–6
10
µA
Output leakage current
VHS1–6 = 0V, all output stages off,
Pins 2, 3, 12, 13, 15 and 28
IHS1–6
Woutx
–10
50
µA
mJ
Inductive shutdown energy(1)
Output voltage edge steepness
Pins 1-4, 11-16, 27 and 28
15
dVLS1–6/dt
dVHS1–6/dt
mV/µ
s
Pins 1-4, 11-16, 27 and 28
200
400
Pins 1, 4, 11, 14, 16 and 27
Pins 2, 3, 12, 13,15 and 28
ILS1–6
IHS1–6
tdSd
650
–1250
70
950
–950
100
1250
–650
140
mA
mA
ms
ms
Overcurrent limitation and shutdown
threshold
Input register, bit 14 (SCT) = high
Input register, bit 14 (SCT) = low
Overcurrent shutdown delay time
tdSd
8.75
17.5
Input register, bit 13 (OLD) = low,
output off, pins 1, 4, 11, 14, 16, 27
ILS1–6
IHS1–6
60
–150
1.2
200
–30
µA
µA
Open load detection current
Open load detection current ratio
Open load detection threshold
Input register, bit 13 (OLD) = low,
output off, pins 2, 3, 12, 13, 15, 28
ILS1–6/
IHS1–6
Input register, bit 13 (OLD) = low,
output off, pins 1, 4, 11, 14, 16, 27
VLS1–6
0.6
4
4
V
V
Input register, bit 13 (OLD) = low,
output off, pins 2, 3, 12, 13, 15, 28
VVS–
VHS1–6
0.6
RLoad = 1 kΩ
RLoad = 1 kΩ
tdon
tdoff
0.5
1
ms
ms
Output switch on delay (2)
Inhibit Input
0.3 ×
VVCC
Input voltage low level threshold
Pin 17
Pin 17
VIL
VIH
V
V
0.7×
VVCC
Input voltage high level threshold
Hysteresis of input voltage
Pull-down current
Pin 17
∆VI
100
10
700
80
mV
µA
VINH = VVCC, pin 17
IPD
Notes: 1. Only valid for version U6815BM-N.
2. Delay time between rising edge of CS after data transmission and switch-on output stages to 90% of final level.
9
4545C–BCD–09/05
12. Electrical Characteristics (Continued)
7.5V < VVS < 40V; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
Parameters
Test Conditions/Pins
Symbol
Min.
Typ.
Max.
Unit
Serial Interface - Logic Inputs (DI, CLK, CS)
0.3 ×
VVCC
Input voltage low level threshold
Input voltage high level threshold
Pins 24 to 26
VIL
VIH
V
V
0.7 ×
VVCC
Pins 24 to 26
Hysteresis of input voltage
Pull-down current, Pins DI and CLK
Pull-up current Pin CS
Pins 24 to 26
∆VI
IPDSI
IPUSI
50
2
500
50
mV
µA
µA
VDI, VCLK = VVCC, pins 25, 26
VCS= 0V, pin 24
–50
–2
Serial Interface - Logic Output (DO)
Output voltage low level
IOL = 3 mA, pin 18
VDOL
VDOH
IDO
0.5
10
V
V
VVCC
1V
–
Output voltage high level
IOL = –2 mA, pin 18
Leakage current (tristate)
VCS = VVCC, 0V < VDO < VVCC, pin 18
–10
mA
Notes: 1. Only valid for version U6815BM-N.
2. Delay time between rising edge of CS after data transmission and switch-on output stages to 90% of final level.
13. Serial Interface – Timing
Parameters
Test Conditions
Timing Chart No.(1)
Symbol
Min.
Typ.
Max.
Unit
DO enable after CS
falling edge
CDO = 100 pF
1
tENDO
200
ns
DO disable after CS
rising edge
C
DO = 100 pF
DO = 100 pF
2
tDISDO
200
ns
DO fall time
C
–
–
tDOf
tDOr
100
100
200
ns
ns
ns
ns
ns
DO rise time
DO valid time
CS setup time
CS setup time
CDO = 100 pF
CDO = 100 pF
10
4
tDOVal
tCSSethl
tCSSetlh
225
225
VDO < 0.2 × VVCC
8
Input register,
Bit 14 (SCT) = high
9
9
tCSh
tCSh
140
ns
ns
CS high time
Input register,
Bit 14 (SCT) = low
17.5
CLK high time
CLK low time
CLK period time
CLK setup time
CLK setup time
DI setup time
DI hold time
5
6
tCLKh
tCLKl
225
225
500
225
225
40
ns
ns
ns
ns
ns
ns
ns
–
tCLKp
7
tCLKSethl
tCLKSetlh
tDIset
3
11
12
tDIHold
40
Note:
1. see Figure 13-1 on page 11
10
U6815BM
4545C–BCD–09/05
U6815BM
Figure 13-1. Serial Interface Timing Diagram with Chart Numbers
1
2
CS
DO
9
CS
4
7
CLK
5
3
6
8
DI
11
CLK
10
12
DO
Inputs DI, CLK, CS: High level = 0.7 × VCC, Low level = 0.3 × VCC
Output DO: High level = 0.8 × VCC, Low level = 0.2 × VCC
For chart numbers, see Table “Serial Interface – Timing” on page 10.
11
4545C–BCD–09/05
Figure 13-2. Application Circuit
Vcc
U5021M
Enable
WATCHDOG
HS1
15
HS2
13
HS4
HS5
HS3
12
HS6
3
2
28
Vs
BYT41D
5
10
6
VS
VS
GND
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Fault
Fault
Detect
Detect
Detect
VBATT
13V
+
26
DI
VS
OV -
Osc
7 GND
8 GND
protection
25
S
O
L
H
S
6
L
S
6
H
S
5
L
S
5
H
S
4
L
S
4
H
S
3
L
H
S
2
L
S
2
H
L
S
1
S
CLK
S
C
S
S
1
R
R
I
T
D
3
VS
UV -
Control
logic
µC
24
Input Register
Output Register
CS
protection
9
GND
Thermal
protection
17
P
S
F
S
C
D
H
S
6
L
S
6
H
L
H
L
H
L
H
L
S
2
H
S
1
L
T
P
I
INH
20GND
21GND
22GND
23GND
N
H
S
S
S
S
S
3
S
S
2
S
1
5
5
4
4
3
P - ON -
Reset
18
DO
Vcc
Fault
Fault
Detect
Fault
Fault
Fault
Detect
Fault
Detect
Detect
Detect
Detect
Vcc
Vcc
+
19
Vcc
Vcc
Vcc
5V
16
LS1
14
LS2
11
LS3
4
1
27
LS6
LS4
LS5
Vs
Vs
14. Application Notes
It is strongly recommended to connect the blocking capacitors at VCC and VS as close as possi-
ble to the power supply and GND pins.
Recommended value for capacitors at VS:
Electrolythic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. Value for elec-
trolytic capacitor depends on external loads, conducted interferences and reverse conducting
current IHSx (see table Absolute Maximum Ratings).
Recommended value for capacitors at VCC
:
Electrolythic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF. To reduce ther-
mal resistance, it is recommended to place cooling areas on the PCB as close as possible to the
GND pins.
12
U6815BM
4545C–BCD–09/05
U6815BM
15. Ordering Information
Extended Type Number
Package
SO28
Remarks
U6815BM-NFLY
Tubed, Pb-free
U6815BM-NFLG3Y
SO28
Taped and reeled, Pb-free
16. Package Information
9.15
8.65
Package SO28
Dimensions in mm
18.05
17.80
7.5
7.3
2.35
0.25
0.25
0.10
0.4
10.50
10.20
1.27
16.51
28
15
technical drawings
according to DIN
specifications
1
14
17. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
• Put datasheet in a new template
• Pb-free logo on page 1 added
4545C-BCD-09/05
• New heading rows on Table “Absolute Maximum Ratings” on page 7added
• Table “Ordering Information” on page 13 changed
13
4545C–BCD–09/05
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