AS8E128K32N-300/XT [AUSTIN]
128K x 32 EEPROM EEPROM Memory Array; 128K ×32 EEPROM EEPROM存储器阵列
| 型号： | AS8E128K32N-300/XT |
| 厂家： | 
AUSTIN SEMICONDUCTOR |
| 描述： | 128K x 32 EEPROM EEPROM Memory Array |
| 文件： | 总13页 (文件大小：283K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EEPROM
AS8E128K32
Austin Semiconductor, Inc.
128K x 32 EEPROM
EEPROM Memory Array
AVAILABLE AS MILITARY
SPECIFICATIONS
PIN ASSIGNMENT
(Top View)
66 Lead PGA
(Pins 8, 21, 28, 39 are no connects on the PN package)
•
•
SMD 5962-94585
MIL-STD-883
FEATURES
•
•
•
Access times of 120, 140, 150, 200, 250, and 300 ns
Built in decoupling caps for low noise operation
Organized as 128K x32; User configurable
as 256K x16 or 512K x8
•
•
•
•
Operation with single 5 volt supply
Low power CMOS
TTL Compatible Inputs and Outputs
Operating Temperature Ranges:
Military: -55oC to +125oC
Industrial: -40oC to +85oC
66 Lead PGA
(Pins 8, 21, 28, 39 are grounds on the P package)
OPTIONS
MARKINGS
•
Timing
120 ns
-120
-140
-150
-200
-250
-300
140 ns
150 ns
200 ns
250 ns
300 ns
•
Package
68 Lead CQFP
Ceramic Quad Flat pack
Pin Grid Array- 8 Series
Pin Grid Array- 8 Series
Q
P
PN
No. 703
No. 904
No. 904
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. AS8E128K32 is a 4 Megabit
EEPROM Module organized as 128K x 32 bit. User configurable to
256K x16 or 512Kx 8. The module achieves high speed access, low
power consumption and high reliability by employing advanced CMOS
memory technology.
The military grade product is manufactured in compliance to the
SMD and MIL-STD 883, making the AS8E128K32 ideally suited for
military or space applications.
The module is offered in a 1.075 inch square ceramic pin grid
array substrate. This package design provides the optimum space
saving solution for boards that accept through hole packaging.
The module is also offered as a 68 lead 0.990 inch square ceramic
quad flat pack. It has a max. height of 0.200 inch. This package design
is targeted for those applications which require low profile SMT
Packaging.
For more products and information
please visit our web site at
www.austinsemiconductor.com
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8E128K32
Rev. 7.6 06/05
1
EEPROM
AS8E128K32
Austin Semiconductor, Inc.
of the last byte written will result in the complement of the written
data to be presented on I/O7. Once the write cycle has been com-
pleted, true data is valid on all outputs, and the next write cycle may
begin. DATA Polling may begin at anytime during the write cycle.
DEVICE IDENTIFICATION
An extra 128 bytes of EEPROM memory is available on each
die for user identification. By raising A9 to 12V + 0.5V and using
address locations 1FF80H to 1FFFFH the bytes may be written to
or read from in the same manner as the regular memory array.
TOGGLE BIT
In addition to DATAPolling the module provides another method
for determining the end of a write cycle. During the write operation,
successive attempts to read data from the device will result in I/O6 of
the accessed die toggling between one and zero. Once the write has
completed, I/O6 will stop toggling and valid data will be read. Reading
the toggle bit may begin at any time during the write cycle.
DEVICE OPERATION
The 128K x 32 EEPROM memory solution is an electrically
erasable and programmable memory module that is accessed like a
Static RAM for the read or write cycle without the need for external
components. The device contains a 128-byte-page register to allow
writing of up to 128 bytes of data simultaneously. During a write
cycle, the address and 1 to 128 bytes of data are internally latched,
freeing the address and data bus for other operations. Following the DATA PROTECTION
initiation of a write cycle, the device will automatically write the
latched data using an internal control timer. The end of a write cycle
can be detected by DATA polling of I/O7. Once the end of a write
cycle has been detected a new access for a read or write can begin.
If precautions are not taken, inadvertent writes may occur during
transitions of the host power supply. The E2 module has incorpo-
rated both hardware and software features that will protect the memory
against inadvertent writes.
READ
HARDWARE PROTECTION
The memory module is accessed like a Static RAM. When CE\
and OE\ are low and WE\ is High, the data stored at the memory
location determined by the address pins is asserted on the outputs.
The module can be read as a 32 bit, 16 bit or 8 bit device. The outputs
are put in the high impedance state when either CE\ or OE\ is high.
This dual-line control gives designers flexibility in preventing bus
contention in their system.
Hardware features protect against inadvertent writes to the mod-
ule in the following ways: (a) Vcc sense - if Vcc is below 3.8 V
(typical) the write function is inhibited; (b) Vcc power-on delay -
once Vcc has reached 3.8 V the device will automatically time out 5 ms
(typical) before allowing a write; (c) write inhibit - holding any one of
OE\ low, CE\ high or WE\ high inhibits write cycles; (d) noise filter -
pulses of less than 15 ns (typical) on the WE\ or CE\ inputs will not
initiate a write cycle.
BYTEWRITE
A low pulse on the WE\ or CE\ input with CE\ or WE\ low
(respectively) and OE\ high initiates a write cycle. The address is
latched on the falling edge of CE\ or WE\, whichever occurs last. The
data is latched by the first rising edge of CE\ or WE\. Once a BWDW
(byte, word or double word) write has been started it will automati-
cally time itself to completion.
SOFTWARE DATA PROTECTION
A software controlled data protection feature has been imple-
mented on the memory module. When enabled, the software data
protection (SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user and is shipped with SDP
disabled, SDP is enabled by the host system issuing a series of three
write commands; three specific bytes of data are written to three
specific addresses (refer to Software Data Protection Algorithm). After
writing the three byte command sequence and after tWC the entire
module will be protected from inadvertent write operations. It should
be noted, that once protected the host may still perform a byte of page
write to the module. This is done by preceding the data to be written
by the same three byte command sequence used to enable SDP. Once
set, SDP will remain active unless the disable command sequence is
issued. Power transitions do not disable SDP and SDP will protect
the 128K x 32 EEPROM during power-up and Power-down condi-
tions. All command sequences must conform to the page write timing
specifications. The data in the enable and disable command sequences
is not written to the device and the memory addresses used in the
sequence may be written with data in either a byte or page write
operation.
PAGEWRITE
The page write operation of the 128K x 32 EEPROM allows 1 to
128 BWDWs of data to be written into the device during a single
internal programming period. Each new BWDW must be written
within 150-µ sec (tBLC) of the previous BWDW. If the tBLC limit is
exceeded the memory module will cease accepting data and commence
the internal programming operation. For each WE high to low transi-
tion during the page write operation, A7-A16 must be the same.
The A0-A6 inputs are used to specify which bytes within the
page are to be written. The bytes may be loaded in any order and may
be altered within the same load period. Only bytes which are speci-
fied for writing will be written; unnecessary cycling of other bytes
within the page does not occur.
After setting SDP, any attempt to write to the device without the
three byte command sequence will start the internal write timers. No
DATA POLLING
This memory module features DATA Polling to indicate the end
of a write cycle. During a byte or page write cycle an attempted read
data will be written to the device; however, for the duration of tWC
read operations will effectively be polling operations.
,
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8E128K32
Rev. 7.6 06/05
2
EEPROM
AS8E128K32
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc Supply Relative to Vss
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
Vcc ..............................................................................-.5V to +7.0V a stress rating only and functional operation of the device at
Storage Temperature ....................... ....................-65°C to +150°C these or any other conditions above those indicated in the
Voltage on any Pin Relative to Vss.....................-.5V to Vcc+1 V operation section of this specification is not implied. Exposure
Max Junction Temperature**.............................................+150°C to absolute maximum rating conditions for extended periods
may affect reliability.
Thermal Resistance junction to case (θJC):
**Junction temperature depends upon package type, cycle time,
loading, ambient temperature and airflow, and humidity (plas-
tics).
Package Type Q...............................................11.3° C/W
Package Type P& PN.......................................2.8° C/W
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55oC<TA<125oC or -40oC to +85oC;Vcc = 5V + 10%)
µΑ
µΑ
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8E128K32
Rev. 7.6 06/05
3
EEPROM
AS8E128K32
Austin Semiconductor, Inc.
1
CAPACITANCE TABLE (VIN = 0V, f = 1 MHz, TA = 25oC)
SYMBOL
CADD
PARAMETER
A0 - A16 Capacitance
MAX
UNITS
40
pF
pF
pF
pF
COE
OE\ Capacitance
40
10
12
CWE, CCE
CIO
WE\ and CE\ Capacitance
I/O 0- I/O 31 Capacitance
NOTE: 1. This parameter is guaranteed but not tested.
TRUTH TABLE
MODE
CE
OE
WE
I/O
VIL
VIL
VIH
DOUT
DIN
Read
VIL
VIH
X
VIH
X (1)
X
VIL
X
Write (2)
Standby/Write
Write Inhibit
Write Inhibit
Output Disable
High Z
VIH
X
VIL
X
VIH
X
X
High Z
NOTES: 1. X can be VIL or VIH
2. Refer toAC Programming Waveforms
AC TEST CONDITIONS
I
OL
Current Source
TEST SPECIFICATIONS
Device
Under
Test
-
+
Vz = 1.5V
(Bipolar
Supply)
Input pulse levels...........................................VSS to 3V
Input rise and fall times...........................................5ns
Input timing reference levels.................................1.5V
Output reference levels.........................................1.5V
Output load................................................See Figure 1
+
Ceff = 50pf
I
Current Source
OH
Figure 1
NOTES:
Vz is programmable from -2V to + 7V.
IOL and IOH programmable from 0 to 16 mA.
Vz is typically the midpoint of VOH and VOL.
IOL and IOH are adjusted to simulate a typical resistive load
circuit.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8E128K32
Rev. 7.6 06/05
4
EEPROM
AS8E128K32
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(-55oC < TA < +125oC or -40oC to +85oC; Vcc = 5V +10%)
120
140
150
200
250
300
MAX UNITS
DESCRIPTION
Address to Output Delay
SYMBOL MIN MAX MIN MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
120
120
140
140
150
200
250
300
ns
tACC
tCE
tOE
tDF
150
55
200
55
250
55
300
ns
CE\ to Output Delay
0
0
50
55
0
0
55
55
0
0
0
0
0
0
0
0
55
55
ns
ns
OE\ to Output Delay
55
55
55
CE\ or OE\ to Output Float
Output Hold from OE\, CE\ or Address,
whichever comes first
ns
tOH
AC READ WAVEFORMS(1,2,3)
ADDRESS VALID
ADDRESS
CE/
t
t
CE
DF
tO
t
t
OH
E
OE\
t
ACC
OUTPUT VALID
DQ
NOTES:
1. CE\ may be delayed to tACC-tCE after the address transition without impact on tACC
2. OE\ may be delayed to tCE-tOE after the falling edge of CE\ without impact on tCE or by tACC-tOE after an address change
without inpact on tACC
.
.
3. tDF is specified from OE\ or CE\ whichever occurs first (CL = 5pF).
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8E128K32
Rev. 7.6 06/05
5
EEPROM
AS8E128K32
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC WRITE CHARACTERISTICS
(-55oC < TA < +125oC; Vcc = 5V +10%)
Symbol
Parameter
Min
Max
Units
Write Cyce Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
10
ms
ns
ns
ns
ns
ns
µs
ns
tWC
tAS
4
50
50
10
100
tAH
tDS
tDH
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
tWP
tBLC
tWPH
150
50
WRITE CYCLE NO 1.
(Chip Enable Controlled)
tOEH
t
OES
OE\
tWC
tAH
tAS
ADDRESS VALID
ADDRESS
tCH
t
CS
WE\
CE\
tWP
tWPH
tDS
tDH
DATA VALID
DQ
OE\
WRITE CYCLE NO 2.
(Write Enable Controlled)
t
t
tE
OES
tOEH
OEH
t
t
AH
t
tAASS
ADDRESS
CE\
tCS
t
tC
CH
ttWPH
t
WPH
WP
WE\
t
DS
t
tDH
DH
DATA VALID
DQ
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8E128K32
Rev. 7.6 06/05
6
EEPROM
AS8E128K32
Austin Semiconductor, Inc.
PAGE MODE CHARACTERISTICS
Symbol
tAS, tOES
tAH
Parameter
Address, OE\ Set-Up time
Address, Hold time
Min
4
Max
Unit
ns
50
0
ns
tCS
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE\ or CE\)
Data Set-up Time
ns
tCH
0
ns
tWP
100
50
10
ns
tDS
ns
tDH, tOEH
Data, OE\ Hold Time
ns
PAGE MODE WRITE WAVEFORMS(1,2)
OE
CE\
tWP
tWP
t
tBLC
BLC
tW
P
tW
P
H
H
WE\
A0 - A16
DATA
tAH
tAH
tAS
VA
VA
VA
VA
VA
VA
VA
tDH
tWC
tDS
VD
VD
VD
VD
VD
VD
VD
VD
BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE 126
BYTE127
NOTES: 1. A7 through A16 must specify the page address during each high to low transition of WE\ (or CE\).
2. OE\ must be high only when WE\ and CE\ are both low.
3. VD - Valid Data
4. VA - Valid Address
CHIP ERASE WAVEFORMS
VIH
CE\
VIL
VH
OE\
t
t
H
S
VIH
VIH
WE\
t = 5 msec (min.)
S
VIL
t
= tH = 10 msec (min.)
W
t
W
V = 12.0V+0.5V
H
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8E128K32
Rev. 7.6 06/05
7
EEPROM
AS8E128K32
Austin Semiconductor, Inc.
Software Data Protection Disable
Algorithm(1)
Software Data Protection Enable
Algorithm(1)
Load Data >AA
Address >5555
Load Data AA
to
Address 5555
Load Data >55
Load Data 55
to
Address >2AAA
Address 2AAA
Load Data >80
Address >5555
Load Data A0
to
Writes Enabled(2)
Address 5555
Load Data >AA
Address >5555
Load Data XX
to
Load Data >55
Address >2AAA
Any Address(4)
Load Last Byte
Load Data >20
Address >5555
to
Enter Data
Last Address
Protect State
Load Data XX
Any Address (4)
NOTES:
;Exit Data Protect State(3)
1. Byte Data Format: I/O7 - I/O0, I/
Address Format: A14 - A0 (Hex)
2. Write Protect state will be active at end of write even if no other
data is loaded.
3. Write Protect state will be deactivated at end of period even if no
other data is loaded.
Load Last Byte(s)
Last Address
4. 1 to 128 bytes of data are loaded.
SOFTWARE PROTECTED PROGRAM CYCLE WAVEFORM(1)(2)(3)
OE\
CE\
t
t
WPH
BLC
t
WP
WE\
t
AS
t
AH
A0-A6
A7-A16
BYTE ADDRESS
5555
2AAA
5555
PAGE ADDRESS
t
t
DS
DH
DATA
AA
A0
55
BYTE 0
BYTE 126
BYTE 127
t
WC
1. A0-A14 of the selected I/O bytes must conform to the addressing sequence for the first three bytes as shown above.
2. After the command sequence has been issued and a page write operation follows, the page address inputs (A7-A16) of the selected I/O bytes must be the same for each high to low transition
of WE\ (or CE\).
3. OE Must be high only when WE\ and CE\ are both low.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8E128K32
Rev. 7.6 06/05
8
EEPROM
AS8E128K32
Austin Semiconductor, Inc.
DATA POLLING CHARACTERISTICS(1)
Symbol Parameter
Min
10
Max
Units
ns
tDH
tOEH
tOE
Data Hold Time
OE\ Hold Time
OE\ to Output Delay (2)
Write Recovery Time
10
0
ns
ns
ns
tWR
NOTES: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
DATA POLLING WAVEFORMS
WE\
CE\
t
OEH
OE\
t
t
WR
DH
t
High-Z
An
OE
I/O7
An
An
An
An
A0 - A16
TOGGLE BIT CHARACTERISTICS(1)
Symbol
tDH
Parameter
Data Hold Time
Min
10
Max
Units
ns
tOEH
tOE
OE\ Hold Time
OE\ to Output Delay(2)
10
ns
ns
ns
ns
t
t
OE\ High Pulse
150
0
OEHP
t
I
Write Recovery Time
WR
NOTES: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
TOGGLE BIT WAVEFORMS(1,2,3)
WE\
CE\
tOEH
tOEHP
tOEH
OE\
tWR
tDH
t
tD
H
OE
HIGH Z
I/O 6
NOTES:
1. Toggling either OE or CE or Both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8E128K32
Rev. 7.6 06/05
9
EEPROM
AS8E128K32
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS*
ASI Case #703 (Package Designator Q)
SMD 5962-94585, Case Outline M
4 x D2
4 x D1
DETAILA
4 x D
R
Pin 1
A 2
B
0o - 7o
b
L 1
SEE DETAIL A
e
A 1
A
D 3
ASI PACKAGE SPECIFICATIONS
SYMBOL
MIN
MAX
0.200
0.186
0.020
0.017
A
A1
A2
b
0.123
0.118
0.005
0.013
B
0.010 REF
0.800 BSC
D
D1
D2
D3
e
0.870
0.980
0.936
0.890
1.000
0.956
0.050 BSC
R
0.005
0.035
---
L1
0.045
*All measurements are in inches.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8E128K32
Rev. 7.6 06/05
10
EEPROM
AS8E128K32
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS*
ASI Case #904 (Package Designator P & PN)
SMD 5962-94585, Case Outline 4 and 5
4 x D
A
D1
D2
A1
Pin 56
Pin 1
(identified by
φb1
0.060 square pad)
E1
e
φb
Pin 66
e
66 x φb2
Pin 11
L
SMD SPECIFICATIONS
SYMBOL
MIN
MAX
0.181
0.035
0.020
0.055
0.075
1.085
A
A1
φb
φb1
φb2
D
0.135
0.025
0.016
0.045
0.065
1.065
D1/E1
D2
e
1.000 BSC
0.600 BSC
0.100 BSC
L
0.132
0.155
*All measurements are in inches.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8E128K32
Rev. 7.6 06/05
11
EEPROM
AS8E128K32
Austin Semiconductor, Inc.
ORDERING INFORMATION
EXAMPLE: AS8E128K32Q-250/XT
Package
Type
Q
Speed
ns
Device Number
Process
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
-120
-140
-150
-200
-250
-300
/*
/*
/*
/*
/*
/*
Q
Q
Q
Q
Q
EXAMPLE: AS8E128K32P-200/883C
Package
Type
Speed
ns
Device Number
Process
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
AS8E128K32
P
PN
P
PN
P
PN
P
PN
P
-120
-120
-140
-140
-150
-150
-200
-200
-250
-250
-300
-300
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
PN
P
PN
*AVAILABLE PROCESSES
IT = IndustrialTemperature Range
XT = Extended Temperature Range
883C = Full Military Processing
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
PACKAGE NOTES
P = Pins 8, 21, 28, and 39 are grounds.
PN = Pins 8, 21, 28, and 39 are no connects.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8E128K32
Rev. 7.6 06/05
12
EEPROM
AS8E128K32
Austin Semiconductor, Inc.
ASITO DSCC PART NUMBER
CROSS REFERENCE*
ASI Package Designator Q
ASI Part #
SMD Part #
AS8E128K32Q-120/883C
AS8E128K32Q-120/883C
AS8E128K32Q-140/883C
AS8E128K32Q-140/883C
AS8E128K32Q-150/883C
AS8E128K32Q-150/883C
AS8E128K32Q-200/883C
AS8E128K32Q-200/883C
AS8E128K32Q-250/883C
AS8E128K32Q-250/883C
AS8E128K32Q-300/883C
AS8E128K32Q-300/883C
5962-9458506HMA
5962-9458506HMC
5962-9458505HMA
5962-9458505HMC
5962-9458504HMA
5962-9458504HMC
5962-9458503HMA
5962-9458503HMC
5962-9458502HMA
5962-9458502HMC
5962-9458501HMA
5962-9458501HMC
ASI Package Designator P & PN
ASI Part #
SMD Part #
AS8E128K32P-120/883C
AS8E128K32P-120/883C
AS8E128K32P-140/883C
AS8E128K32P-140/883C
AS8E128K32P-150/883C
AS8E128K32P-150/883C
AS8E128K32P-200/883C
AS8E128K32P-200/883C
AS8E128K32P-250/883C
AS8E128K32P-250/883C
AS8E128K32P-300/883C
AS8E128K32P-300/883C
5962-9458506H5A
5962-9458506H5C
5962-9458505H5A
5962-9458505H5C
5962-9458504H5A
5962-9458504H5C
5962-9458503H5A
5962-9458503H5C
5962-9458502H5A
5962-9458502H5C
5962-9458501H5A
5962-9458501H5C
AS8E128K32PN-120/883C
AS8E128K32PN-120/883C
AS8E128K32PN-140/883C
AS8E128K32PN-140/883C
AS8E128K32PN-150/883C
AS8E128K32PN-150/883C
AS8E128K32PN-200/883C
AS8E128K32PN-200/883C
AS8E128K32PN-250/883C
AS8E128K32PN-250/883C
AS8E128K32PN-300/883C
AS8E128K32PN-300/883C
5962-9458506H4A
5962-9458506H4C
5962-9458505H4A
5962-9458505H4C
5962-9458504H4A
5962-9458504H4C
5962-9458503H4A
5962-9458503H4C
5962-9458502H4A
5962-9458502H4C
5962-9458501H4A
5962-9458501H4C
* ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8E128K32
Rev. 7.6 06/05
13
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